`resetall
`timescale 1ns / 1ps
`default_nettype none

module delay_shift_register #(
  parameter DELAY_CYCLES = 4 
) (
  input  wire clk,
  input  wire reset, 
  input  wire data_in,
  output wire data_out
);

  // Declare a register to hold the shifted data
  reg [DELAY_CYCLES-1:0] shift_reg;

  always @ (posedge clk) begin
    if (reset) begin
      shift_reg <= '0;
    end else begin
      shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in};
    end
  end

  assign data_out = shift_reg[DELAY_CYCLES-1];

endmodule
`resetall