{
  "design": {
    "design_info": {
      "boundary_crc": "0x3EB2241EA722D10B",
      "device": "xcku040-ffva1156-2-i",
      "gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/bd/microblaze_bd",
      "name": "microblaze_bd",
      "rev_ctrl_bd_flag": "RevCtrlBdOff",
      "synth_flow_mode": "Singular",
      "tool_version": "2022.2",
      "validated": "true"
    },
    "design_tree": {
      "microblaze_0_local_memory": {
        "dlmb_bram_if_cntlr": "",
        "dlmb_v10": "",
        "ilmb_bram_if_cntlr": "",
        "ilmb_v10": "",
        "lmb_bram": ""
      },
      "jesd": {
        "jesd204_phy_0": "",
        "jesd204c_0": "",
        "jesd204c_1": "",
        "util_ds_buf_0": "",
        "util_ds_buf_1": ""
      },
      "axi_bram_ctrl_0": "",
      "axi_bram_ctrl_1": "",
      "axi_bram_ctrl_2": "",
      "axi_bram_ctrl_3": "",
      "axi_ethernet_0": "",
      "axi_ethernet_0_dma": "",
      "axi_fifo_mm_s_0": "",
      "axi_iic_0": "",
      "axi_interconnect_0": {
        "xbar": "",
        "s00_couplers": {
          "s00_data_fifo": "",
          "auto_us": ""
        },
        "s01_couplers": {
          "s01_data_fifo": "",
          "auto_us": ""
        },
        "s02_couplers": {
          "s02_data_fifo": "",
          "auto_us": ""
        },
        "s03_couplers": {
          "s03_data_fifo": "",
          "auto_cc": ""
        },
        "s04_couplers": {
          "s04_data_fifo": "",
          "auto_cc": ""
        },
        "m00_couplers": {
          "m00_data_fifo": ""
        }
      },
      "axi_interconnect_1": {
        "xbar": "",
        "s00_couplers": {},
        "m00_couplers": {},
        "m01_couplers": {},
        "m02_couplers": {},
        "m03_couplers": {},
        "m04_couplers": {},
        "m05_couplers": {},
        "m06_couplers": {},
        "m07_couplers": {},
        "m08_couplers": {},
        "m09_couplers": {},
        "m10_couplers": {},
        "m11_couplers": {},
        "m12_couplers": {},
        "m13_couplers": {}
      },
      "axi_quad_spi_0": "",
      "axi_quad_spi_1": "",
      "qspi_flash": "",
      "axi_timer_0": "",
      "axi_uartlite_0": "",
      "axis_dwidth_converter_0": "",
      "axis_dwidth_converter_1": "",
      "clk_wiz_0": "",
      "ddr4_0": "",
      "mdm_1": "",
      "microblaze_0": "",
      "microblaze_0_axi_intc": "",
      "microblaze_0_axi_periph": {
        "xbar": "",
        "s00_couplers": {},
        "m00_couplers": {},
        "m01_couplers": {},
        "m02_couplers": {},
        "m03_couplers": {},
        "m04_couplers": {},
        "m05_couplers": {},
        "m06_couplers": {},
        "m07_couplers": {
          "auto_cc": ""
        },
        "m08_couplers": {},
        "m09_couplers": {},
        "m10_couplers": {}
      },
      "microblaze_0_xlconcat": "",
      "rst_ddr": "",
      "rst_150": "",
      "system_management_wiz_0": ""
    },
    "interface_ports": {
      "clk_200_in": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "200000000"
          }
        },
        "port_maps": {
          "CLK_N": {
            "physical_name": "clk_200_in_clk_n",
            "direction": "I"
          },
          "CLK_P": {
            "physical_name": "clk_200_in_clk_p",
            "direction": "I"
          }
        }
      },
      "uart": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:uart:1.0",
        "vlnv": "xilinx.com:interface:uart_rtl:1.0",
        "port_maps": {
          "RxD": {
            "physical_name": "uart_rxd",
            "direction": "I"
          },
          "TxD": {
            "physical_name": "uart_txd",
            "direction": "O"
          }
        }
      },
      "mdio": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:mdio:1.0",
        "vlnv": "xilinx.com:interface:mdio_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          }
        },
        "port_maps": {
          "MDC": {
            "physical_name": "mdio_mdc",
            "direction": "O"
          },
          "MDIO_I": {
            "physical_name": "mdio_mdio_i",
            "direction": "I"
          },
          "MDIO_O": {
            "physical_name": "mdio_mdio_o",
            "direction": "O"
          },
          "MDIO_T": {
            "physical_name": "mdio_mdio_t",
            "direction": "O"
          }
        }
      },
      "rgmii": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:rgmii:1.0",
        "vlnv": "xilinx.com:interface:rgmii_rtl:1.0",
        "port_maps": {
          "RD": {
            "physical_name": "rgmii_rd",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "RX_CTL": {
            "physical_name": "rgmii_rx_ctl",
            "direction": "I"
          },
          "RXC": {
            "physical_name": "rgmii_rxc",
            "direction": "I"
          },
          "TD": {
            "physical_name": "rgmii_td",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "TX_CTL": {
            "physical_name": "rgmii_tx_ctl",
            "direction": "O"
          },
          "TXC": {
            "physical_name": "rgmii_txc",
            "direction": "O"
          }
        }
      },
      "ddr": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:ddr4:1.0",
        "vlnv": "xilinx.com:interface:ddr4_rtl:1.0",
        "parameters": {
          "AXI_ARBITRATION_SCHEME": {
            "value": "RD_PRI_REG",
            "value_src": "user_prop"
          },
          "BURST_LENGTH": {
            "value": "8",
            "value_src": "user_prop"
          },
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "CAS_LATENCY": {
            "value": "15",
            "value_src": "user_prop"
          },
          "CAS_WRITE_LATENCY": {
            "value": "11",
            "value_src": "user_prop"
          },
          "CS_ENABLED": {
            "value": "true",
            "value_src": "user_prop"
          },
          "CUSTOM_PARTS": {
            "value": "no_file_loaded",
            "value_src": "user_prop"
          },
          "DATA_MASK_ENABLED": {
            "value": "DM_NO_DBI",
            "value_src": "user_prop"
          },
          "DATA_WIDTH": {
            "value": "64",
            "value_src": "user_prop"
          },
          "MEMORY_PART": {
            "value": "MT40A512M16LY-075",
            "value_src": "user_prop"
          },
          "MEMORY_TYPE": {
            "value": "Components",
            "value_src": "user_prop"
          },
          "MEM_ADDR_MAP": {
            "value": "ROW_COLUMN_BANK",
            "value_src": "user_prop"
          },
          "SLOT": {
            "value": "Single",
            "value_src": "user_prop"
          },
          "TIMEPERIOD_PS": {
            "value": "1000",
            "value_src": "user_prop"
          }
        },
        "port_maps": {
          "ACT_N": {
            "physical_name": "ddr_act_n",
            "direction": "O"
          },
          "ADR": {
            "physical_name": "ddr_adr",
            "direction": "O",
            "left": "16",
            "right": "0"
          },
          "BA": {
            "physical_name": "ddr_ba",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "BG": {
            "physical_name": "ddr_bg",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "CK_C": {
            "physical_name": "ddr_ck_c",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "CK_T": {
            "physical_name": "ddr_ck_t",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "CKE": {
            "physical_name": "ddr_cke",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "CS_N": {
            "physical_name": "ddr_cs_n",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "DM_N": {
            "physical_name": "ddr_dm_n",
            "direction": "IO",
            "left": "7",
            "right": "0"
          },
          "DQ": {
            "physical_name": "ddr_dq",
            "direction": "IO",
            "left": "63",
            "right": "0"
          },
          "DQS_C": {
            "physical_name": "ddr_dqs_c",
            "direction": "IO",
            "left": "7",
            "right": "0"
          },
          "DQS_T": {
            "physical_name": "ddr_dqs_t",
            "direction": "IO",
            "left": "7",
            "right": "0"
          },
          "ODT": {
            "physical_name": "ddr_odt",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "RESET_N": {
            "physical_name": "ddr_reset_n",
            "direction": "O"
          }
        }
      },
      "util_reg_axil": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
            "value_src": "user_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "125000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0",
            "value_src": "default_prop"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "util_reg_axil",
        "port_maps": {
          "AWADDR": {
            "physical_name": "util_reg_axil_awaddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "util_reg_axil_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "util_reg_axil_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "util_reg_axil_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "util_reg_axil_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "util_reg_axil_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "util_reg_axil_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "util_reg_axil_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "util_reg_axil_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "util_reg_axil_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "util_reg_axil_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "util_reg_axil_araddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "util_reg_axil_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "util_reg_axil_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "util_reg_axil_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "util_reg_axil_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "util_reg_axil_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "util_reg_axil_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "util_reg_axil_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "jesd_axis_rx": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "microblaze_bd_core_clk",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "250000000"
          },
          "HAS_TKEEP": {
            "value": "0",
            "value_src": "const_prop"
          },
          "HAS_TLAST": {
            "value": "0",
            "value_src": "const_prop"
          },
          "HAS_TREADY": {
            "value": "0",
            "value_src": "const_prop"
          },
          "HAS_TSTRB": {
            "value": "0",
            "value_src": "const_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "LAYERED_METADATA": {
            "value": "undef",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "TDATA_NUM_BYTES": {
            "value": "64",
            "value_src": "auto_prop"
          },
          "TDEST_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "TID_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "TUSER_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          }
        },
        "port_maps": {
          "TDATA": {
            "physical_name": "jesd_axis_rx_tdata",
            "direction": "O",
            "left": "511",
            "right": "0"
          },
          "TVALID": {
            "physical_name": "jesd_axis_rx_tvalid",
            "direction": "O"
          }
        }
      },
      "jesd_axis_rx_cmd": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "microblaze_bd_core_clk",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "250000000"
          },
          "HAS_TKEEP": {
            "value": "0",
            "value_src": "const_prop"
          },
          "HAS_TLAST": {
            "value": "0",
            "value_src": "const_prop"
          },
          "HAS_TREADY": {
            "value": "1",
            "value_src": "auto_prop"
          },
          "HAS_TSTRB": {
            "value": "0",
            "value_src": "const_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "LAYERED_METADATA": {
            "value": "undef",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "TDATA_NUM_BYTES": {
            "value": "32",
            "value_src": "auto_prop"
          },
          "TDEST_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "TID_WIDTH": {
            "value": "0",
            "value_src": "const_prop"
          },
          "TUSER_WIDTH": {
            "value": "8",
            "value_src": "auto_prop"
          }
        },
        "port_maps": {
          "TDATA": {
            "physical_name": "jesd_axis_rx_cmd_tdata",
            "direction": "O",
            "left": "255",
            "right": "0"
          },
          "TREADY": {
            "physical_name": "jesd_axis_rx_cmd_tready",
            "direction": "I"
          },
          "TUSER": {
            "physical_name": "jesd_axis_rx_cmd_tuser",
            "direction": "O",
            "left": "7",
            "right": "0"
          },
          "TVALID": {
            "physical_name": "jesd_axis_rx_cmd_tvalid",
            "direction": "O"
          }
        }
      },
      "jesd_axis_tx": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "microblaze_bd_core_clk",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "250000000"
          },
          "HAS_TKEEP": {
            "value": "0"
          },
          "HAS_TLAST": {
            "value": "0"
          },
          "HAS_TREADY": {
            "value": "1"
          },
          "HAS_TSTRB": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "LAYERED_METADATA": {
            "value": "undef"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "TDATA_NUM_BYTES": {
            "value": "64"
          },
          "TDEST_WIDTH": {
            "value": "0"
          },
          "TID_WIDTH": {
            "value": "0"
          },
          "TUSER_WIDTH": {
            "value": "0"
          }
        },
        "port_maps": {
          "TDATA": {
            "physical_name": "jesd_axis_tx_tdata",
            "direction": "I",
            "left": "511",
            "right": "0"
          },
          "TREADY": {
            "physical_name": "jesd_axis_tx_tready",
            "direction": "O"
          }
        }
      },
      "jesd_axis_tx_cmd": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "microblaze_bd_core_clk",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "250000000"
          },
          "HAS_TKEEP": {
            "value": "0"
          },
          "HAS_TLAST": {
            "value": "0"
          },
          "HAS_TREADY": {
            "value": "1"
          },
          "HAS_TSTRB": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "LAYERED_METADATA": {
            "value": "undef"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "TDATA_NUM_BYTES": {
            "value": "32"
          },
          "TDEST_WIDTH": {
            "value": "0"
          },
          "TID_WIDTH": {
            "value": "0"
          },
          "TUSER_WIDTH": {
            "value": "0"
          }
        },
        "port_maps": {
          "TDATA": {
            "physical_name": "jesd_axis_tx_cmd_tdata",
            "direction": "I",
            "left": "255",
            "right": "0"
          },
          "TREADY": {
            "physical_name": "jesd_axis_tx_cmd_tready",
            "direction": "O"
          },
          "TVALID": {
            "physical_name": "jesd_axis_tx_cmd_tvalid",
            "direction": "I"
          }
        }
      },
      "fmc_spi0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:spi:1.0",
        "vlnv": "xilinx.com:interface:spi_rtl:1.0",
        "port_maps": {
          "IO0_I": {
            "physical_name": "fmc_spi0_io0_i",
            "direction": "I"
          },
          "IO0_O": {
            "physical_name": "fmc_spi0_io0_o",
            "direction": "O"
          },
          "IO0_T": {
            "physical_name": "fmc_spi0_io0_t",
            "direction": "O"
          },
          "IO1_I": {
            "physical_name": "fmc_spi0_io1_i",
            "direction": "I"
          },
          "IO1_O": {
            "physical_name": "fmc_spi0_io1_o",
            "direction": "O"
          },
          "IO1_T": {
            "physical_name": "fmc_spi0_io1_t",
            "direction": "O"
          },
          "SCK_I": {
            "physical_name": "fmc_spi0_sck_i",
            "direction": "I"
          },
          "SCK_O": {
            "physical_name": "fmc_spi0_sck_o",
            "direction": "O"
          },
          "SCK_T": {
            "physical_name": "fmc_spi0_sck_t",
            "direction": "O"
          },
          "SS_I": {
            "physical_name": "fmc_spi0_ss_i",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "SS_O": {
            "physical_name": "fmc_spi0_ss_o",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "SS_T": {
            "physical_name": "fmc_spi0_ss_t",
            "direction": "O"
          }
        }
      },
      "jesd_qpll0_refclk": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "187500000"
          }
        },
        "port_maps": {
          "CLK_P": {
            "physical_name": "jesd_qpll0_refclk_clk_p",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "CLK_N": {
            "physical_name": "jesd_qpll0_refclk_clk_n",
            "direction": "I",
            "left": "0",
            "right": "0"
          }
        }
      },
      "jesd_sysref": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "default"
          }
        },
        "port_maps": {
          "CLK_P": {
            "physical_name": "jesd_sysref_clk_p",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "CLK_N": {
            "physical_name": "jesd_sysref_clk_n",
            "direction": "I",
            "left": "0",
            "right": "0"
          }
        }
      },
      "fmc_spi1": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:spi:1.0",
        "vlnv": "xilinx.com:interface:spi_rtl:1.0",
        "port_maps": {
          "IO0_I": {
            "physical_name": "fmc_spi1_io0_i",
            "direction": "I"
          },
          "IO0_O": {
            "physical_name": "fmc_spi1_io0_o",
            "direction": "O"
          },
          "IO0_T": {
            "physical_name": "fmc_spi1_io0_t",
            "direction": "O"
          },
          "IO1_I": {
            "physical_name": "fmc_spi1_io1_i",
            "direction": "I"
          },
          "IO1_O": {
            "physical_name": "fmc_spi1_io1_o",
            "direction": "O"
          },
          "IO1_T": {
            "physical_name": "fmc_spi1_io1_t",
            "direction": "O"
          },
          "SCK_I": {
            "physical_name": "fmc_spi1_sck_i",
            "direction": "I"
          },
          "SCK_O": {
            "physical_name": "fmc_spi1_sck_o",
            "direction": "O"
          },
          "SCK_T": {
            "physical_name": "fmc_spi1_sck_t",
            "direction": "O"
          },
          "SS_I": {
            "physical_name": "fmc_spi1_ss_i",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "SS_O": {
            "physical_name": "fmc_spi1_ss_o",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "SS_T": {
            "physical_name": "fmc_spi1_ss_t",
            "direction": "O"
          }
        }
      },
      "dac0_wf_bram": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:bram:1.0",
        "vlnv": "xilinx.com:interface:bram_rtl:1.0",
        "parameters": {
          "MASTER_TYPE": {
            "value": "BRAM_CTRL"
          },
          "MEM_ECC": {
            "value": "NONE",
            "value_src": "user_prop"
          },
          "MEM_SIZE": {
            "value": "131072",
            "value_src": "ip_prop"
          },
          "MEM_WIDTH": {
            "value": "32",
            "value_src": "ip_prop"
          },
          "READ_LATENCY": {
            "value": "1",
            "value_src": "user_prop"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE"
          }
        },
        "port_maps": {
          "ADDR": {
            "physical_name": "dac0_wf_bram_addr",
            "direction": "O",
            "left": "16",
            "right": "0"
          },
          "CLK": {
            "physical_name": "dac0_wf_bram_clk",
            "direction": "O"
          },
          "DIN": {
            "physical_name": "dac0_wf_bram_din",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "DOUT": {
            "physical_name": "dac0_wf_bram_dout",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "EN": {
            "physical_name": "dac0_wf_bram_en",
            "direction": "O"
          },
          "RST": {
            "physical_name": "dac0_wf_bram_rst",
            "direction": "O"
          },
          "WE": {
            "physical_name": "dac0_wf_bram_we",
            "direction": "O",
            "left": "3",
            "right": "0"
          }
        }
      },
      "dac1_wf_bram": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:bram:1.0",
        "vlnv": "xilinx.com:interface:bram_rtl:1.0",
        "parameters": {
          "MASTER_TYPE": {
            "value": "BRAM_CTRL"
          },
          "MEM_ECC": {
            "value": "NONE",
            "value_src": "user_prop"
          },
          "MEM_SIZE": {
            "value": "131072",
            "value_src": "ip_prop"
          },
          "MEM_WIDTH": {
            "value": "32",
            "value_src": "ip_prop"
          },
          "READ_LATENCY": {
            "value": "1",
            "value_src": "user_prop"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE"
          }
        },
        "port_maps": {
          "ADDR": {
            "physical_name": "dac1_wf_bram_addr",
            "direction": "O",
            "left": "16",
            "right": "0"
          },
          "CLK": {
            "physical_name": "dac1_wf_bram_clk",
            "direction": "O"
          },
          "DIN": {
            "physical_name": "dac1_wf_bram_din",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "DOUT": {
            "physical_name": "dac1_wf_bram_dout",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "EN": {
            "physical_name": "dac1_wf_bram_en",
            "direction": "O"
          },
          "RST": {
            "physical_name": "dac1_wf_bram_rst",
            "direction": "O"
          },
          "WE": {
            "physical_name": "dac1_wf_bram_we",
            "direction": "O",
            "left": "3",
            "right": "0"
          }
        }
      },
      "dac2_wf_bram": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:bram:1.0",
        "vlnv": "xilinx.com:interface:bram_rtl:1.0",
        "parameters": {
          "MASTER_TYPE": {
            "value": "BRAM_CTRL"
          },
          "MEM_ECC": {
            "value": "NONE",
            "value_src": "user_prop"
          },
          "MEM_SIZE": {
            "value": "131072",
            "value_src": "ip_prop"
          },
          "MEM_WIDTH": {
            "value": "32",
            "value_src": "ip_prop"
          },
          "READ_LATENCY": {
            "value": "1",
            "value_src": "user_prop"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE"
          }
        },
        "port_maps": {
          "ADDR": {
            "physical_name": "dac2_wf_bram_addr",
            "direction": "O",
            "left": "16",
            "right": "0"
          },
          "CLK": {
            "physical_name": "dac2_wf_bram_clk",
            "direction": "O"
          },
          "DIN": {
            "physical_name": "dac2_wf_bram_din",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "DOUT": {
            "physical_name": "dac2_wf_bram_dout",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "EN": {
            "physical_name": "dac2_wf_bram_en",
            "direction": "O"
          },
          "RST": {
            "physical_name": "dac2_wf_bram_rst",
            "direction": "O"
          },
          "WE": {
            "physical_name": "dac2_wf_bram_we",
            "direction": "O",
            "left": "3",
            "right": "0"
          }
        }
      },
      "dac3_wf_bram": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:bram:1.0",
        "vlnv": "xilinx.com:interface:bram_rtl:1.0",
        "parameters": {
          "MASTER_TYPE": {
            "value": "BRAM_CTRL"
          },
          "MEM_ECC": {
            "value": "NONE",
            "value_src": "user_prop"
          },
          "MEM_SIZE": {
            "value": "131072",
            "value_src": "ip_prop"
          },
          "MEM_WIDTH": {
            "value": "32",
            "value_src": "ip_prop"
          },
          "READ_LATENCY": {
            "value": "1",
            "value_src": "user_prop"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE"
          }
        },
        "port_maps": {
          "ADDR": {
            "physical_name": "dac3_wf_bram_addr",
            "direction": "O",
            "left": "16",
            "right": "0"
          },
          "CLK": {
            "physical_name": "dac3_wf_bram_clk",
            "direction": "O"
          },
          "DIN": {
            "physical_name": "dac3_wf_bram_din",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "DOUT": {
            "physical_name": "dac3_wf_bram_dout",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "EN": {
            "physical_name": "dac3_wf_bram_en",
            "direction": "O"
          },
          "RST": {
            "physical_name": "dac3_wf_bram_rst",
            "direction": "O"
          },
          "WE": {
            "physical_name": "dac3_wf_bram_we",
            "direction": "O",
            "left": "3",
            "right": "0"
          }
        }
      },
      "timing_engine_axil": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
            "value_src": "user_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "125000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "timing_engine_axil",
        "port_maps": {
          "AWADDR": {
            "physical_name": "timing_engine_axil_awaddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "timing_engine_axil_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "timing_engine_axil_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "timing_engine_axil_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "timing_engine_axil_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "timing_engine_axil_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "timing_engine_axil_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "timing_engine_axil_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "timing_engine_axil_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "timing_engine_axil_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "timing_engine_axil_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "timing_engine_axil_araddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "timing_engine_axil_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "timing_engine_axil_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "timing_engine_axil_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "timing_engine_axil_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "timing_engine_axil_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "timing_engine_axil_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "timing_engine_axil_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "udp_rx": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "microblaze_bd_s_axi_aclk_0",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "156250000"
          },
          "HAS_TKEEP": {
            "value": "0"
          },
          "HAS_TLAST": {
            "value": "1"
          },
          "HAS_TREADY": {
            "value": "1"
          },
          "HAS_TSTRB": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "LAYERED_METADATA": {
            "value": "undef"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "TDATA_NUM_BYTES": {
            "value": "8"
          },
          "TDEST_WIDTH": {
            "value": "0"
          },
          "TID_WIDTH": {
            "value": "0"
          },
          "TUSER_WIDTH": {
            "value": "0"
          }
        },
        "port_maps": {
          "TVALID": {
            "physical_name": "udp_rx_tvalid",
            "direction": "I"
          },
          "TREADY": {
            "physical_name": "udp_rx_tready",
            "direction": "O"
          },
          "TDATA": {
            "physical_name": "udp_rx_tdata",
            "direction": "I",
            "left": "63",
            "right": "0"
          },
          "TLAST": {
            "physical_name": "udp_rx_tlast",
            "direction": "I"
          }
        }
      },
      "udp_tx": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "microblaze_bd_s_axi_aclk_0",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "156250000"
          },
          "HAS_TKEEP": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "HAS_TLAST": {
            "value": "1",
            "value_src": "default_prop"
          },
          "HAS_TREADY": {
            "value": "1",
            "value_src": "default"
          },
          "HAS_TSTRB": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "LAYERED_METADATA": {
            "value": "undef",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "TDATA_NUM_BYTES": {
            "value": "8",
            "value_src": "default_prop"
          },
          "TDEST_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "TID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "TUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "port_maps": {
          "TVALID": {
            "physical_name": "udp_tx_tvalid",
            "direction": "O"
          },
          "TREADY": {
            "physical_name": "udp_tx_tready",
            "direction": "I"
          },
          "TDATA": {
            "physical_name": "udp_tx_tdata",
            "direction": "O",
            "left": "63",
            "right": "0"
          },
          "TKEEP": {
            "physical_name": "udp_tx_tkeep",
            "direction": "O",
            "left": "7",
            "right": "0"
          },
          "TLAST": {
            "physical_name": "udp_tx_tlast",
            "direction": "O"
          }
        }
      },
      "dig_rx0_axil": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
            "value_src": "user_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "125000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0",
            "value_src": "default_prop"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "dig_rx0_axil",
        "port_maps": {
          "AWADDR": {
            "physical_name": "dig_rx0_axil_awaddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "dig_rx0_axil_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "dig_rx0_axil_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "dig_rx0_axil_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "dig_rx0_axil_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "dig_rx0_axil_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "dig_rx0_axil_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "dig_rx0_axil_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "dig_rx0_axil_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "dig_rx0_axil_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "dig_rx0_axil_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "dig_rx0_axil_araddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "dig_rx0_axil_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "dig_rx0_axil_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "dig_rx0_axil_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "dig_rx0_axil_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "dig_rx0_axil_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "dig_rx0_axil_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "dig_rx0_axil_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "wf_gen_axil": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
            "value_src": "user_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "125000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "wf_gen_axil",
        "port_maps": {
          "AWADDR": {
            "physical_name": "wf_gen_axil_awaddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "wf_gen_axil_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "wf_gen_axil_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "wf_gen_axil_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "wf_gen_axil_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "wf_gen_axil_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "wf_gen_axil_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "wf_gen_axil_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "wf_gen_axil_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "wf_gen_axil_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "wf_gen_axil_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "wf_gen_axil_araddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "wf_gen_axil_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "wf_gen_axil_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "wf_gen_axil_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "wf_gen_axil_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "wf_gen_axil_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "wf_gen_axil_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "wf_gen_axil_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "dig_rx1_axil": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
            "value_src": "user_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "125000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "dig_rx1_axil",
        "port_maps": {
          "AWADDR": {
            "physical_name": "dig_rx1_axil_awaddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "dig_rx1_axil_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "dig_rx1_axil_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "dig_rx1_axil_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "dig_rx1_axil_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "dig_rx1_axil_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "dig_rx1_axil_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "dig_rx1_axil_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "dig_rx1_axil_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "dig_rx1_axil_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "dig_rx1_axil_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "dig_rx1_axil_araddr",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "dig_rx1_axil_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "dig_rx1_axil_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "dig_rx1_axil_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "dig_rx1_axil_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "dig_rx1_axil_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "dig_rx1_axil_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "dig_rx1_axil_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "STARTUP_IO": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:startup:1.0",
        "vlnv": "xilinx.com:interface:startup_rtl:1.0",
        "port_maps": {
          "cfgclk": {
            "physical_name": "STARTUP_IO_cfgclk",
            "direction": "O"
          },
          "cfgmclk": {
            "physical_name": "STARTUP_IO_cfgmclk",
            "direction": "O"
          },
          "eos": {
            "physical_name": "STARTUP_IO_eos",
            "direction": "O"
          },
          "gsr": {
            "physical_name": "STARTUP_IO_gsr",
            "direction": "I"
          },
          "gts": {
            "physical_name": "STARTUP_IO_gts",
            "direction": "I"
          },
          "keyclearb": {
            "physical_name": "STARTUP_IO_keyclearb",
            "direction": "I"
          },
          "preq": {
            "physical_name": "STARTUP_IO_preq",
            "direction": "O"
          },
          "userdoneo": {
            "physical_name": "STARTUP_IO_userdoneo",
            "direction": "I"
          },
          "usrclkts": {
            "physical_name": "STARTUP_IO_usrclkts",
            "direction": "I"
          },
          "usrdonets": {
            "physical_name": "STARTUP_IO_usrdonets",
            "direction": "I"
          }
        }
      },
      "i2c": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:iic:1.0",
        "vlnv": "xilinx.com:interface:iic_rtl:1.0",
        "port_maps": {
          "SCL_I": {
            "physical_name": "i2c_scl_i",
            "direction": "I"
          },
          "SCL_O": {
            "physical_name": "i2c_scl_o",
            "direction": "O"
          },
          "SCL_T": {
            "physical_name": "i2c_scl_t",
            "direction": "O"
          },
          "SDA_I": {
            "physical_name": "i2c_sda_i",
            "direction": "I"
          },
          "SDA_O": {
            "physical_name": "i2c_sda_o",
            "direction": "O"
          },
          "SDA_T": {
            "physical_name": "i2c_sda_t",
            "direction": "O"
          }
        }
      }
    },
    "ports": {
      "ext_reset_in_200": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "default"
          }
        }
      },
      "phy_rst_n": {
        "type": "rst",
        "direction": "O",
        "left": "0",
        "right": "0",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW"
          }
        }
      },
      "ddr_init_calib_complete": {
        "direction": "O"
      },
      "mb_axi_clk": {
        "type": "clk",
        "direction": "O",
        "parameters": {
          "ASSOCIATED_BUSIF": {
            "value": "util_reg_axil:timing_engine_axil:dig_rx0_axil:wf_gen_axil:dig_rx1_axil"
          },
          "ASSOCIATED_RESET": {
            "value": "qspi_flash_aresetn"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
            "value_src": "user_prop"
          },
          "FREQ_HZ": {
            "value": "125000000",
            "value_src": "user_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0",
            "value_src": "default_prop"
          }
        }
      },
      "mb_axi_aresetn": {
        "type": "rst",
        "direction": "O",
        "left": "0",
        "right": "0",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "const_prop"
          }
        }
      },
      "jesd_rxp_in": {
        "direction": "I",
        "left": "7",
        "right": "0"
      },
      "jesd_rxn_in": {
        "direction": "I",
        "left": "7",
        "right": "0"
      },
      "jesd_txp_out": {
        "direction": "O",
        "left": "7",
        "right": "0"
      },
      "jesd_txn_out": {
        "direction": "O",
        "left": "7",
        "right": "0"
      },
      "jesd_axis_rx_aresetn": {
        "type": "rst",
        "direction": "O",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "const_prop"
          }
        }
      },
      "jesd_axis_tx_aresetn": {
        "type": "rst",
        "direction": "O",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "const_prop"
          }
        }
      },
      "jesd_tx_core_reset": {
        "direction": "I"
      },
      "jesd_rx_core_reset": {
        "direction": "I"
      },
      "common0_qpll1_lock_out": {
        "direction": "O"
      },
      "common1_qpll1_lock_out": {
        "direction": "O"
      },
      "jesd_tx_sys_reset": {
        "direction": "I"
      },
      "jesd_rx_sys_reset": {
        "direction": "I"
      },
      "jesd_core_clk": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "ASSOCIATED_BUSIF": {
            "value": "jesd_axis_rx:jesd_axis_rx_cmd:jesd_axis_tx:jesd_axis_tx_cmd"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_core_clk",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "250000000"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          }
        }
      },
      "eth_clk": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "ASSOCIATED_BUSIF": {
            "value": "udp_rx:udp_tx"
          },
          "ASSOCIATED_RESET": {
            "value": "eth_resetn"
          },
          "CLK_DOMAIN": {
            "value": "microblaze_bd_s_axi_aclk_0",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "156250000"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          }
        }
      },
      "eth_resetn": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "default"
          }
        }
      },
      "qspi_flash_aresetn": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "default"
          }
        }
      },
      "pps": {
        "direction": "I",
        "left": "0",
        "right": "0"
      },
      "jesd_tx_sync": {
        "direction": "I"
      },
      "jesd_rx_sync": {
        "direction": "O"
      }
    },
    "components": {
      "microblaze_0_local_memory": {
        "interface_ports": {
          "DLMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          },
          "ILMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          }
        },
        "ports": {
          "LMB_Clk": {
            "type": "clk",
            "direction": "I"
          },
          "SYS_Rst": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "dlmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "microblaze_bd_dlmb_bram_if_cntlr_0",
            "xci_path": "ip/microblaze_bd_dlmb_bram_if_cntlr_0/microblaze_bd_dlmb_bram_if_cntlr_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            },
            "hdl_attributes": {
              "BMM_INFO_ADDRESS_SPACE": {
                "value": "byte  0x00000000 32 > microblaze_bd microblaze_0_local_memory/lmb_bram",
                "value_src": "default"
              },
              "KEEP_HIERARCHY": {
                "value": "yes",
                "value_src": "default"
              }
            }
          },
          "dlmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "microblaze_bd_dlmb_v10_0",
            "xci_path": "ip/microblaze_bd_dlmb_v10_0/microblaze_bd_dlmb_v10_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "ilmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "microblaze_bd_ilmb_bram_if_cntlr_0",
            "xci_path": "ip/microblaze_bd_ilmb_bram_if_cntlr_0/microblaze_bd_ilmb_bram_if_cntlr_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            }
          },
          "ilmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "microblaze_bd_ilmb_v10_0",
            "xci_path": "ip/microblaze_bd_ilmb_v10_0/microblaze_bd_ilmb_v10_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "lmb_bram": {
            "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
            "xci_name": "microblaze_bd_lmb_bram_0",
            "xci_path": "ip/microblaze_bd_lmb_bram_0/microblaze_bd_lmb_bram_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/lmb_bram",
            "parameters": {
              "Enable_B": {
                "value": "Use_ENB_Pin"
              },
              "Memory_Type": {
                "value": "True_Dual_Port_RAM"
              },
              "Port_B_Clock": {
                "value": "100"
              },
              "Port_B_Enable_Rate": {
                "value": "100"
              },
              "Port_B_Write_Rate": {
                "value": "50"
              },
              "Use_RSTB_Pin": {
                "value": "true"
              },
              "use_bram_block": {
                "value": "BRAM_Controller"
              }
            }
          }
        },
        "interface_nets": {
          "microblaze_0_dlmb": {
            "interface_ports": [
              "DLMB",
              "dlmb_v10/LMB_M"
            ]
          },
          "microblaze_0_dlmb_bus": {
            "interface_ports": [
              "dlmb_v10/LMB_Sl_0",
              "dlmb_bram_if_cntlr/SLMB"
            ]
          },
          "microblaze_0_dlmb_cntlr": {
            "interface_ports": [
              "dlmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTA"
            ]
          },
          "microblaze_0_ilmb": {
            "interface_ports": [
              "ILMB",
              "ilmb_v10/LMB_M"
            ]
          },
          "microblaze_0_ilmb_bus": {
            "interface_ports": [
              "ilmb_v10/LMB_Sl_0",
              "ilmb_bram_if_cntlr/SLMB"
            ]
          },
          "microblaze_0_ilmb_cntlr": {
            "interface_ports": [
              "ilmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTB"
            ]
          }
        },
        "nets": {
          "SYS_Rst_1": {
            "ports": [
              "SYS_Rst",
              "dlmb_bram_if_cntlr/LMB_Rst",
              "dlmb_v10/SYS_Rst",
              "ilmb_bram_if_cntlr/LMB_Rst",
              "ilmb_v10/SYS_Rst"
            ]
          },
          "microblaze_0_Clk": {
            "ports": [
              "LMB_Clk",
              "dlmb_bram_if_cntlr/LMB_Clk",
              "dlmb_v10/LMB_Clk",
              "ilmb_bram_if_cntlr/LMB_Clk",
              "ilmb_v10/LMB_Clk"
            ]
          }
        }
      },
      "jesd": {
        "interface_ports": {
          "s_axi_tx": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "jesd_axis_tx": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "jesd_axis_tx_cmd": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "s_axi_rx": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "jesd_axis_rx": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "jesd_axis_rx_cmd": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "jesd_sysref": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
            "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0"
          },
          "jesd_qpll0_refclk": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
            "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0"
          },
          "s_axi_phy": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        },
        "ports": {
          "mb_axi_clk": {
            "type": "clk",
            "direction": "I"
          },
          "jesd_txp_out": {
            "direction": "O",
            "left": "7",
            "right": "0"
          },
          "jesd_txn_out": {
            "direction": "O",
            "left": "7",
            "right": "0"
          },
          "jesd_rxp_in": {
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "jesd_rxn_in": {
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "mb_axi_aresetn": {
            "type": "rst",
            "direction": "I"
          },
          "jesd_tx_core_reset": {
            "direction": "I"
          },
          "irq": {
            "direction": "O"
          },
          "jesd_axis_tx_aresetn": {
            "type": "rst",
            "direction": "O"
          },
          "jesd_rx_core_reset": {
            "direction": "I"
          },
          "irq1": {
            "direction": "O"
          },
          "jesd_axis_rx_aresetn": {
            "type": "rst",
            "direction": "O"
          },
          "common0_qpll1_lock_out": {
            "direction": "O"
          },
          "common1_qpll1_lock_out": {
            "direction": "O"
          },
          "jesd_core_clk": {
            "direction": "I"
          },
          "jesd_tx_sys_reset": {
            "direction": "I"
          },
          "jesd_rx_sys_reset": {
            "direction": "I"
          },
          "jesd_tx_sync": {
            "direction": "I"
          },
          "jesd_rx_sync": {
            "direction": "O"
          }
        },
        "components": {
          "jesd204_phy_0": {
            "vlnv": "xilinx.com:ip:jesd204_phy:4.0",
            "xci_name": "microblaze_bd_jesd204_phy_0_0",
            "xci_path": "ip/microblaze_bd_jesd204_phy_0_0/microblaze_bd_jesd204_phy_0_0.xci",
            "inst_hier_path": "jesd/jesd204_phy_0",
            "parameters": {
              "Axi_Lite": {
                "value": "true"
              },
              "C_LANES": {
                "value": "8"
              },
              "C_PLL_SELECTION": {
                "value": "1"
              },
              "DRPCLK_FREQ": {
                "value": "125.0"
              },
              "Equalization_Mode": {
                "value": "High_Loss"
              },
              "GT_Line_Rate": {
                "value": "12.375"
              },
              "GT_Location": {
                "value": "X0Y12"
              },
              "GT_REFCLK_FREQ": {
                "value": "187.5"
              },
              "Ins_Loss": {
                "value": "30"
              },
              "RX_GT_Line_Rate": {
                "value": "12.375"
              },
              "RX_GT_REFCLK_FREQ": {
                "value": "187.5"
              },
              "RX_PLL_SELECTION": {
                "value": "1"
              },
              "Rx_JesdVersion": {
                "value": "1"
              },
              "Rx_use_64b": {
                "value": "1"
              },
              "TransceiverControl": {
                "value": "false"
              },
              "Tx_JesdVersion": {
                "value": "1"
              },
              "Tx_use_64b": {
                "value": "1"
              }
            },
            "interface_ports": {
              "s_axi": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "memory_map_ref": "s_axi"
              }
            },
            "addressing": {
              "memory_maps": {
                "s_axi": {
                  "address_blocks": {
                    "Reg": {
                      "base_address": "0",
                      "range": "4K",
                      "width": "12",
                      "usage": "register"
                    }
                  }
                }
              }
            }
          },
          "jesd204c_0": {
            "vlnv": "xilinx.com:ip:jesd204c:4.2",
            "xci_name": "microblaze_bd_jesd204c_0_0",
            "xci_path": "ip/microblaze_bd_jesd204c_0_0/microblaze_bd_jesd204c_0_0.xci",
            "inst_hier_path": "jesd/jesd204c_0",
            "parameters": {
              "AXICLK_FREQ": {
                "value": "150.0"
              },
              "C_ENCODING": {
                "value": "1"
              },
              "C_LANES": {
                "value": "8"
              },
              "C_NODE_IS_TRANSMIT": {
                "value": "0"
              },
              "C_PLL_SELECTION": {
                "value": "1"
              },
              "C_USE_FEC": {
                "value": "true"
              },
              "DRPCLK_FREQ": {
                "value": "187.5"
              },
              "GT_Line_Rate": {
                "value": "12.375"
              },
              "GT_REFCLK_FREQ": {
                "value": "187.5"
              }
            },
            "interface_ports": {
              "s_axi": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "memory_map_ref": "s_axi"
              }
            },
            "addressing": {
              "memory_maps": {
                "s_axi": {
                  "address_blocks": {
                    "Reg": {
                      "base_address": "0",
                      "range": "4K",
                      "width": "12",
                      "usage": "register"
                    }
                  }
                }
              }
            }
          },
          "jesd204c_1": {
            "vlnv": "xilinx.com:ip:jesd204c:4.2",
            "xci_name": "microblaze_bd_jesd204c_1_0",
            "xci_path": "ip/microblaze_bd_jesd204c_1_0/microblaze_bd_jesd204c_1_0.xci",
            "inst_hier_path": "jesd/jesd204c_1",
            "parameters": {
              "AXICLK_FREQ": {
                "value": "150"
              },
              "C_ENCODING": {
                "value": "1"
              },
              "C_LANES": {
                "value": "8"
              },
              "C_PLL_SELECTION": {
                "value": "1"
              },
              "C_USE_FEC": {
                "value": "true"
              },
              "DRPCLK_FREQ": {
                "value": "187.5"
              },
              "GT_Line_Rate": {
                "value": "12.375"
              },
              "GT_REFCLK_FREQ": {
                "value": "187.5"
              }
            },
            "interface_ports": {
              "s_axi": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "memory_map_ref": "s_axi"
              }
            },
            "addressing": {
              "memory_maps": {
                "s_axi": {
                  "address_blocks": {
                    "Reg": {
                      "base_address": "0",
                      "range": "4K",
                      "width": "12",
                      "usage": "register"
                    }
                  }
                }
              }
            }
          },
          "util_ds_buf_0": {
            "vlnv": "xilinx.com:ip:util_ds_buf:2.2",
            "xci_name": "microblaze_bd_util_ds_buf_0_0",
            "xci_path": "ip/microblaze_bd_util_ds_buf_0_0/microblaze_bd_util_ds_buf_0_0.xci",
            "inst_hier_path": "jesd/util_ds_buf_0",
            "parameters": {
              "C_BUF_TYPE": {
                "value": "IBUFDSGTE"
              }
            }
          },
          "util_ds_buf_1": {
            "vlnv": "xilinx.com:ip:util_ds_buf:2.2",
            "xci_name": "microblaze_bd_util_ds_buf_1_0",
            "xci_path": "ip/microblaze_bd_util_ds_buf_1_0/microblaze_bd_util_ds_buf_1_0.xci",
            "inst_hier_path": "jesd/util_ds_buf_1",
            "parameters": {
              "C_BUF_TYPE": {
                "value": "IBUFDS"
              }
            }
          }
        },
        "interface_nets": {
          "Conn1": {
            "interface_ports": [
              "jesd_sysref",
              "util_ds_buf_1/CLK_IN_D"
            ]
          },
          "Conn2": {
            "interface_ports": [
              "jesd_qpll0_refclk",
              "util_ds_buf_0/CLK_IN_D"
            ]
          },
          "jesd204_phy_0_gt0_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt0_rx",
              "jesd204c_0/gt0_rx"
            ]
          },
          "jesd204_phy_0_gt1_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt1_rx",
              "jesd204c_0/gt1_rx"
            ]
          },
          "jesd204_phy_0_gt2_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt2_rx",
              "jesd204c_0/gt2_rx"
            ]
          },
          "jesd204_phy_0_gt3_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt3_rx",
              "jesd204c_0/gt3_rx"
            ]
          },
          "jesd204_phy_0_gt4_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt4_rx",
              "jesd204c_0/gt4_rx"
            ]
          },
          "jesd204_phy_0_gt5_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt5_rx",
              "jesd204c_0/gt5_rx"
            ]
          },
          "jesd204_phy_0_gt6_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt6_rx",
              "jesd204c_0/gt6_rx"
            ]
          },
          "jesd204_phy_0_gt7_rx": {
            "interface_ports": [
              "jesd204_phy_0/gt7_rx",
              "jesd204c_0/gt7_rx"
            ]
          },
          "jesd204c_0_m_axis_rx": {
            "interface_ports": [
              "jesd_axis_rx",
              "jesd204c_0/m_axis_rx"
            ]
          },
          "jesd204c_0_m_axis_rx_cmd": {
            "interface_ports": [
              "jesd_axis_rx_cmd",
              "jesd204c_0/m_axis_rx_cmd"
            ]
          },
          "jesd204c_1_gt0_tx": {
            "interface_ports": [
              "jesd204c_1/gt0_tx",
              "jesd204_phy_0/gt0_tx"
            ]
          },
          "jesd204c_1_gt1_tx": {
            "interface_ports": [
              "jesd204c_1/gt1_tx",
              "jesd204_phy_0/gt1_tx"
            ]
          },
          "jesd204c_1_gt2_tx": {
            "interface_ports": [
              "jesd204c_1/gt2_tx",
              "jesd204_phy_0/gt2_tx"
            ]
          },
          "jesd204c_1_gt3_tx": {
            "interface_ports": [
              "jesd204c_1/gt3_tx",
              "jesd204_phy_0/gt3_tx"
            ]
          },
          "jesd204c_1_gt4_tx": {
            "interface_ports": [
              "jesd204c_1/gt4_tx",
              "jesd204_phy_0/gt4_tx"
            ]
          },
          "jesd204c_1_gt5_tx": {
            "interface_ports": [
              "jesd204c_1/gt5_tx",
              "jesd204_phy_0/gt5_tx"
            ]
          },
          "jesd204c_1_gt6_tx": {
            "interface_ports": [
              "jesd204c_1/gt6_tx",
              "jesd204_phy_0/gt6_tx"
            ]
          },
          "jesd204c_1_gt7_tx": {
            "interface_ports": [
              "jesd204c_1/gt7_tx",
              "jesd204_phy_0/gt7_tx"
            ]
          },
          "jesd_axis_tx_cmd_1": {
            "interface_ports": [
              "jesd_axis_tx_cmd",
              "jesd204c_1/s_axis_tx_cmd"
            ]
          },
          "microblaze_0_axi_periph_M07_AXI": {
            "interface_ports": [
              "s_axi_rx",
              "jesd204c_0/s_axi"
            ]
          },
          "microblaze_0_axi_periph_M08_AXI": {
            "interface_ports": [
              "s_axi_tx",
              "jesd204c_1/s_axi"
            ]
          },
          "s_axi_phy_1": {
            "interface_ports": [
              "s_axi_phy",
              "jesd204_phy_0/s_axi"
            ]
          },
          "s_axis_tx_0_1": {
            "interface_ports": [
              "jesd_axis_tx",
              "jesd204c_1/s_axis_tx"
            ]
          }
        },
        "nets": {
          "jesd204_phy_0_common0_qpll0_lock_out": {
            "ports": [
              "jesd204_phy_0/common0_qpll0_lock_out",
              "common0_qpll1_lock_out"
            ]
          },
          "jesd204_phy_0_common1_qpll0_lock_out": {
            "ports": [
              "jesd204_phy_0/common1_qpll0_lock_out",
              "common1_qpll1_lock_out"
            ]
          },
          "jesd204_phy_0_rx_reset_done": {
            "ports": [
              "jesd204_phy_0/rx_reset_done",
              "jesd204c_0/rx_reset_done"
            ]
          },
          "jesd204_phy_0_tx_reset_done": {
            "ports": [
              "jesd204_phy_0/tx_reset_done",
              "jesd204c_1/tx_reset_done"
            ]
          },
          "jesd204_phy_0_txn_out": {
            "ports": [
              "jesd204_phy_0/txn_out",
              "jesd_txn_out"
            ]
          },
          "jesd204_phy_0_txoutclk": {
            "ports": [
              "jesd_core_clk",
              "jesd204_phy_0/tx_core_clk",
              "jesd204_phy_0/rx_core_clk",
              "jesd204c_0/rx_core_clk",
              "jesd204c_1/tx_core_clk"
            ]
          },
          "jesd204_phy_0_txp_out": {
            "ports": [
              "jesd204_phy_0/txp_out",
              "jesd_txp_out"
            ]
          },
          "jesd204c_0_irq": {
            "ports": [
              "jesd204c_0/irq",
              "irq1"
            ]
          },
          "jesd204c_0_rx_aresetn": {
            "ports": [
              "jesd204c_0/rx_aresetn",
              "jesd_axis_rx_aresetn"
            ]
          },
          "jesd204c_0_rx_reset_gt": {
            "ports": [
              "jesd204c_0/rx_reset_gt",
              "jesd204_phy_0/rx_reset_gt"
            ]
          },
          "jesd204c_1_irq": {
            "ports": [
              "jesd204c_1/irq",
              "irq"
            ]
          },
          "jesd204c_1_tx_aresetn": {
            "ports": [
              "jesd204c_1/tx_aresetn",
              "jesd_axis_tx_aresetn"
            ]
          },
          "jesd204c_1_tx_reset_gt": {
            "ports": [
              "jesd204c_1/tx_reset_gt",
              "jesd204_phy_0/tx_reset_gt"
            ]
          },
          "microblaze_0_Clk": {
            "ports": [
              "mb_axi_clk",
              "jesd204_phy_0/drpclk",
              "jesd204_phy_0/s_axi_aclk",
              "jesd204c_0/s_axi_aclk",
              "jesd204c_1/s_axi_aclk"
            ]
          },
          "rst_clk_wiz_1_100M_peripheral_aresetn": {
            "ports": [
              "mb_axi_aresetn",
              "jesd204_phy_0/s_axi_aresetn",
              "jesd204c_0/s_axi_aresetn",
              "jesd204c_1/s_axi_aresetn"
            ]
          },
          "rx_core_reset_0_1": {
            "ports": [
              "jesd_rx_core_reset",
              "jesd204c_0/rx_core_reset"
            ]
          },
          "rx_sys_reset_0_1": {
            "ports": [
              "jesd_rx_sys_reset",
              "jesd204_phy_0/rx_sys_reset"
            ]
          },
          "rxn_in_0_1": {
            "ports": [
              "jesd_rxn_in",
              "jesd204_phy_0/rxn_in"
            ]
          },
          "rxp_in_0_1": {
            "ports": [
              "jesd_rxp_in",
              "jesd204_phy_0/rxp_in"
            ]
          },
          "tx_core_reset_0_1": {
            "ports": [
              "jesd_tx_core_reset",
              "jesd204c_1/tx_core_reset"
            ]
          },
          "tx_sys_reset_0_1": {
            "ports": [
              "jesd_tx_sys_reset",
              "jesd204_phy_0/tx_sys_reset"
            ]
          },
          "util_ds_buf_0_IBUF_OUT": {
            "ports": [
              "util_ds_buf_0/IBUF_OUT",
              "jesd204_phy_0/cpll_refclk",
              "jesd204_phy_0/qpll0_refclk",
              "jesd204_phy_0/qpll1_refclk"
            ]
          },
          "util_ds_buf_1_IBUF_OUT": {
            "ports": [
              "util_ds_buf_1/IBUF_OUT",
              "jesd204c_0/rx_sysref",
              "jesd204c_1/tx_sysref"
            ]
          }
        }
      },
      "axi_bram_ctrl_0": {
        "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
        "xci_name": "microblaze_bd_axi_bram_ctrl_0_0",
        "xci_path": "ip/microblaze_bd_axi_bram_ctrl_0_0/microblaze_bd_axi_bram_ctrl_0_0.xci",
        "inst_hier_path": "axi_bram_ctrl_0",
        "parameters": {
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "SINGLE_PORT_BRAM": {
            "value": "1"
          }
        }
      },
      "axi_bram_ctrl_1": {
        "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
        "xci_name": "microblaze_bd_axi_bram_ctrl_0_1",
        "xci_path": "ip/microblaze_bd_axi_bram_ctrl_0_1/microblaze_bd_axi_bram_ctrl_0_1.xci",
        "inst_hier_path": "axi_bram_ctrl_1",
        "parameters": {
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "SINGLE_PORT_BRAM": {
            "value": "1"
          }
        }
      },
      "axi_bram_ctrl_2": {
        "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
        "xci_name": "microblaze_bd_axi_bram_ctrl_1_1",
        "xci_path": "ip/microblaze_bd_axi_bram_ctrl_1_1/microblaze_bd_axi_bram_ctrl_1_1.xci",
        "inst_hier_path": "axi_bram_ctrl_2",
        "parameters": {
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "SINGLE_PORT_BRAM": {
            "value": "1"
          }
        }
      },
      "axi_bram_ctrl_3": {
        "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
        "xci_name": "microblaze_bd_axi_bram_ctrl_1_2",
        "xci_path": "ip/microblaze_bd_axi_bram_ctrl_1_2/microblaze_bd_axi_bram_ctrl_1_2.xci",
        "inst_hier_path": "axi_bram_ctrl_3",
        "parameters": {
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "SINGLE_PORT_BRAM": {
            "value": "1"
          }
        }
      },
      "axi_ethernet_0": {
        "vlnv": "xilinx.com:ip:axi_ethernet:7.2",
        "xci_name": "microblaze_bd_axi_ethernet_0_2",
        "xci_path": "ip/microblaze_bd_axi_ethernet_0_2/microblaze_bd_axi_ethernet_0_2.xci",
        "inst_hier_path": "axi_ethernet_0",
        "parameters": {
          "Frame_Filter": {
            "value": "false"
          },
          "PHY_TYPE": {
            "value": "RGMII"
          },
          "RXCSUM": {
            "value": "Full"
          },
          "RXMEM": {
            "value": "4k"
          },
          "Statistics_Counters": {
            "value": "false"
          },
          "TXCSUM": {
            "value": "Full"
          },
          "TXMEM": {
            "value": "4k"
          },
          "axiliteclkrate": {
            "value": "150.0"
          },
          "axisclkrate": {
            "value": "300.0"
          }
        },
        "interface_ports": {
          "s_axi": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "ADDR_WIDTH": {
                "value": "18"
              },
              "PROTOCOL": {
                "value": "AXI4LITE"
              }
            },
            "memory_map_ref": "s_axi"
          },
          "s_axis_txd": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "s_axis_txc": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "m_axis_rxd": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "m_axis_rxs": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          },
          "mdio": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:mdio:1.0",
            "vlnv": "xilinx.com:interface:mdio_rtl:1.0"
          },
          "rgmii": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:rgmii:1.0",
            "vlnv": "xilinx.com:interface:rgmii_rtl:1.0"
          }
        },
        "addressing": {
          "memory_maps": {
            "s_axi": {
              "address_blocks": {
                "Reg0": {
                  "base_address": "0",
                  "range": "256K",
                  "width": "18",
                  "usage": "register",
                  "bank_blocks": {
                    "SEG_eth_buf_REG;/eth_buf/S_AXI/Reg;xilinx.com:ip:axi_ethernet_buffer:2.0;/eth_buf;S_AXI;NONE;NONE": {
                      "base_address": "0",
                      "range": "256K",
                      "width": "18",
                      "usage": "register"
                    }
                  }
                }
              }
            }
          }
        }
      },
      "axi_ethernet_0_dma": {
        "vlnv": "xilinx.com:ip:axi_dma:7.1",
        "xci_name": "microblaze_bd_axi_ethernet_0_dma_1",
        "xci_path": "ip/microblaze_bd_axi_ethernet_0_dma_1/microblaze_bd_axi_ethernet_0_dma_1.xci",
        "inst_hier_path": "axi_ethernet_0_dma",
        "parameters": {
          "c_include_mm2s_dre": {
            "value": "1"
          },
          "c_include_s2mm_dre": {
            "value": "1"
          },
          "c_mm2s_burst_size": {
            "value": "256"
          },
          "c_s2mm_burst_size": {
            "value": "256"
          },
          "c_sg_length_width": {
            "value": "16"
          },
          "c_sg_use_stsapp_length": {
            "value": "1"
          }
        },
        "interface_ports": {
          "M_AXI_SG": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data_SG",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "M_AXI_MM2S": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data_MM2S",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "M_AXI_S2MM": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data_S2MM",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          }
        },
        "addressing": {
          "address_spaces": {
            "Data_SG": {
              "range": "4G",
              "width": "32"
            },
            "Data_MM2S": {
              "range": "4G",
              "width": "32"
            },
            "Data_S2MM": {
              "range": "4G",
              "width": "32"
            }
          }
        }
      },
      "axi_fifo_mm_s_0": {
        "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2",
        "xci_name": "microblaze_bd_axi_fifo_mm_s_0_0",
        "xci_path": "ip/microblaze_bd_axi_fifo_mm_s_0_0/microblaze_bd_axi_fifo_mm_s_0_0.xci",
        "inst_hier_path": "axi_fifo_mm_s_0",
        "parameters": {
          "C_AXIS_TUSER_WIDTH": {
            "value": "4"
          },
          "C_DATA_INTERFACE_TYPE": {
            "value": "0"
          },
          "C_S_AXI4_DATA_WIDTH": {
            "value": "32"
          },
          "C_USE_TX_CTRL": {
            "value": "0"
          },
          "C_USE_TX_DATA": {
            "value": "1"
          }
        }
      },
      "axi_iic_0": {
        "vlnv": "xilinx.com:ip:axi_iic:2.1",
        "xci_name": "microblaze_bd_axi_iic_0_0",
        "xci_path": "ip/microblaze_bd_axi_iic_0_0/microblaze_bd_axi_iic_0_0.xci",
        "inst_hier_path": "axi_iic_0",
        "parameters": {
          "IIC_FREQ_KHZ": {
            "value": "50"
          }
        }
      },
      "axi_interconnect_0": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/microblaze_bd_axi_interconnect_0_0/microblaze_bd_axi_interconnect_0_0.xci",
        "inst_hier_path": "axi_interconnect_0",
        "xci_name": "microblaze_bd_axi_interconnect_0_0",
        "parameters": {
          "M00_HAS_DATA_FIFO": {
            "value": "1"
          },
          "NUM_MI": {
            "value": "1"
          },
          "NUM_SI": {
            "value": "5"
          },
          "S00_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S01_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S02_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S03_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S04_HAS_DATA_FIFO": {
            "value": "1"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "S01_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "S02_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "S03_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "S04_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S01_ARESETN"
              }
            }
          },
          "S01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S02_ARESETN"
              }
            }
          },
          "S02_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S03_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S03_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S03_ARESETN"
              }
            }
          },
          "S03_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S04_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S04_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S04_ARESETN"
              }
            }
          },
          "S04_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "microblaze_bd_xbar_6",
            "xci_path": "ip/microblaze_bd_xbar_6/microblaze_bd_xbar_6.xci",
            "inst_hier_path": "axi_interconnect_0/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "1"
              },
              "NUM_SI": {
                "value": "5"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S01_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S02_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S03_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S04_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s00_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "microblaze_bd_s00_data_fifo_0",
                "xci_path": "ip/microblaze_bd_s00_data_fifo_0/microblaze_bd_s00_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_0/s00_couplers/s00_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_us": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "microblaze_bd_auto_us_0",
                "xci_path": "ip/microblaze_bd_auto_us_0/microblaze_bd_auto_us_0.xci",
                "inst_hier_path": "axi_interconnect_0/s00_couplers/auto_us",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "512"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "32"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_us_to_s00_data_fifo": {
                "interface_ports": [
                  "s00_data_fifo/S_AXI",
                  "auto_us/M_AXI"
                ]
              },
              "s00_couplers_to_auto_us": {
                "interface_ports": [
                  "S_AXI",
                  "auto_us/S_AXI"
                ]
              },
              "s00_data_fifo_to_s00_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s00_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s00_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s00_data_fifo/aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_us/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_us/s_axi_aresetn"
                ]
              }
            }
          },
          "s01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s01_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "microblaze_bd_s01_data_fifo_0",
                "xci_path": "ip/microblaze_bd_s01_data_fifo_0/microblaze_bd_s01_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_0/s01_couplers/s01_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_us": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "microblaze_bd_auto_us_1",
                "xci_path": "ip/microblaze_bd_auto_us_1/microblaze_bd_auto_us_1.xci",
                "inst_hier_path": "axi_interconnect_0/s01_couplers/auto_us",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "512"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "32"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_us_to_s01_data_fifo": {
                "interface_ports": [
                  "s01_data_fifo/S_AXI",
                  "auto_us/M_AXI"
                ]
              },
              "s01_couplers_to_auto_us": {
                "interface_ports": [
                  "S_AXI",
                  "auto_us/S_AXI"
                ]
              },
              "s01_data_fifo_to_s01_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s01_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s01_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s01_data_fifo/aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_us/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_us/s_axi_aresetn"
                ]
              }
            }
          },
          "s02_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s02_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "microblaze_bd_s02_data_fifo_0",
                "xci_path": "ip/microblaze_bd_s02_data_fifo_0/microblaze_bd_s02_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_0/s02_couplers/s02_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_us": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "microblaze_bd_auto_us_2",
                "xci_path": "ip/microblaze_bd_auto_us_2/microblaze_bd_auto_us_2.xci",
                "inst_hier_path": "axi_interconnect_0/s02_couplers/auto_us",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "512"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "32"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_us_to_s02_data_fifo": {
                "interface_ports": [
                  "s02_data_fifo/S_AXI",
                  "auto_us/M_AXI"
                ]
              },
              "s02_couplers_to_auto_us": {
                "interface_ports": [
                  "S_AXI",
                  "auto_us/S_AXI"
                ]
              },
              "s02_data_fifo_to_s02_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s02_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s02_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s02_data_fifo/aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_us/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_us/s_axi_aresetn"
                ]
              }
            }
          },
          "s03_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s03_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "microblaze_bd_s03_data_fifo_0",
                "xci_path": "ip/microblaze_bd_s03_data_fifo_0/microblaze_bd_s03_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_0/s03_couplers/s03_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_cc": {
                "vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
                "xci_name": "microblaze_bd_auto_cc_0",
                "xci_path": "ip/microblaze_bd_auto_cc_0/microblaze_bd_auto_cc_0.xci",
                "inst_hier_path": "axi_interconnect_0/s03_couplers/auto_cc",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_cc_to_s03_data_fifo": {
                "interface_ports": [
                  "s03_data_fifo/S_AXI",
                  "auto_cc/M_AXI"
                ]
              },
              "s03_couplers_to_auto_cc": {
                "interface_ports": [
                  "S_AXI",
                  "auto_cc/S_AXI"
                ]
              },
              "s03_data_fifo_to_s03_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s03_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s03_data_fifo/aclk",
                  "auto_cc/m_axi_aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s03_data_fifo/aresetn",
                  "auto_cc/m_axi_aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_cc/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_cc/s_axi_aresetn"
                ]
              }
            }
          },
          "s04_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s04_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "microblaze_bd_s04_data_fifo_0",
                "xci_path": "ip/microblaze_bd_s04_data_fifo_0/microblaze_bd_s04_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_0/s04_couplers/s04_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_cc": {
                "vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
                "xci_name": "microblaze_bd_auto_cc_1",
                "xci_path": "ip/microblaze_bd_auto_cc_1/microblaze_bd_auto_cc_1.xci",
                "inst_hier_path": "axi_interconnect_0/s04_couplers/auto_cc",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_cc_to_s04_data_fifo": {
                "interface_ports": [
                  "s04_data_fifo/S_AXI",
                  "auto_cc/M_AXI"
                ]
              },
              "s04_couplers_to_auto_cc": {
                "interface_ports": [
                  "S_AXI",
                  "auto_cc/S_AXI"
                ]
              },
              "s04_data_fifo_to_s04_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s04_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s04_data_fifo/aclk",
                  "auto_cc/m_axi_aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s04_data_fifo/aresetn",
                  "auto_cc/m_axi_aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_cc/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_cc/s_axi_aresetn"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "m00_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "microblaze_bd_m00_data_fifo_0",
                "xci_path": "ip/microblaze_bd_m00_data_fifo_0/microblaze_bd_m00_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_0/m00_couplers/m00_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_data_fifo": {
                "interface_ports": [
                  "S_AXI",
                  "m00_data_fifo/S_AXI"
                ]
              },
              "m00_data_fifo_to_m00_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "m00_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "m00_data_fifo/aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "m00_data_fifo/aresetn"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "axi_interconnect_0_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "axi_interconnect_0_to_s01_couplers": {
            "interface_ports": [
              "S01_AXI",
              "s01_couplers/S_AXI"
            ]
          },
          "axi_interconnect_0_to_s02_couplers": {
            "interface_ports": [
              "S02_AXI",
              "s02_couplers/S_AXI"
            ]
          },
          "axi_interconnect_0_to_s03_couplers": {
            "interface_ports": [
              "S03_AXI",
              "s03_couplers/S_AXI"
            ]
          },
          "axi_interconnect_0_to_s04_couplers": {
            "interface_ports": [
              "S04_AXI",
              "s04_couplers/S_AXI"
            ]
          },
          "m00_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "s01_couplers_to_xbar": {
            "interface_ports": [
              "s01_couplers/M_AXI",
              "xbar/S01_AXI"
            ]
          },
          "s02_couplers_to_xbar": {
            "interface_ports": [
              "s02_couplers/M_AXI",
              "xbar/S02_AXI"
            ]
          },
          "s03_couplers_to_xbar": {
            "interface_ports": [
              "s03_couplers/M_AXI",
              "xbar/S03_AXI"
            ]
          },
          "s04_couplers_to_xbar": {
            "interface_ports": [
              "s04_couplers/M_AXI",
              "xbar/S04_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "M00_ACLK_1": {
            "ports": [
              "M00_ACLK",
              "m00_couplers/M_ACLK"
            ]
          },
          "M00_ARESETN_1": {
            "ports": [
              "M00_ARESETN",
              "m00_couplers/M_ARESETN"
            ]
          },
          "S00_ACLK_1": {
            "ports": [
              "S00_ACLK",
              "s00_couplers/S_ACLK"
            ]
          },
          "S00_ARESETN_1": {
            "ports": [
              "S00_ARESETN",
              "s00_couplers/S_ARESETN"
            ]
          },
          "S01_ACLK_1": {
            "ports": [
              "S01_ACLK",
              "s01_couplers/S_ACLK"
            ]
          },
          "S01_ARESETN_1": {
            "ports": [
              "S01_ARESETN",
              "s01_couplers/S_ARESETN"
            ]
          },
          "S02_ACLK_1": {
            "ports": [
              "S02_ACLK",
              "s02_couplers/S_ACLK"
            ]
          },
          "S02_ARESETN_1": {
            "ports": [
              "S02_ARESETN",
              "s02_couplers/S_ARESETN"
            ]
          },
          "S03_ACLK_1": {
            "ports": [
              "S03_ACLK",
              "s03_couplers/S_ACLK"
            ]
          },
          "S03_ARESETN_1": {
            "ports": [
              "S03_ARESETN",
              "s03_couplers/S_ARESETN"
            ]
          },
          "S04_ACLK_1": {
            "ports": [
              "S04_ACLK",
              "s04_couplers/S_ACLK"
            ]
          },
          "S04_ARESETN_1": {
            "ports": [
              "S04_ARESETN",
              "s04_couplers/S_ARESETN"
            ]
          },
          "axi_interconnect_0_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/M_ACLK",
              "s01_couplers/M_ACLK",
              "s02_couplers/M_ACLK",
              "s03_couplers/M_ACLK",
              "s04_couplers/M_ACLK",
              "m00_couplers/S_ACLK"
            ]
          },
          "axi_interconnect_0_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/M_ARESETN",
              "s01_couplers/M_ARESETN",
              "s02_couplers/M_ARESETN",
              "s03_couplers/M_ARESETN",
              "s04_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN"
            ]
          }
        }
      },
      "axi_interconnect_1": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/microblaze_bd_axi_interconnect_1_0/microblaze_bd_axi_interconnect_1_0.xci",
        "inst_hier_path": "axi_interconnect_1",
        "xci_name": "microblaze_bd_axi_interconnect_1_0",
        "parameters": {
          "NUM_MI": {
            "value": "14"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M02_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M03_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M04_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M05_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M06_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M07_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M08_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M09_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M10_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M11_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M12_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M13_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M01_ARESETN"
              }
            }
          },
          "M01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M02_ARESETN"
              }
            }
          },
          "M02_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M03_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M03_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M03_ARESETN"
              }
            }
          },
          "M03_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M04_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M04_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M04_ARESETN"
              }
            }
          },
          "M04_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M05_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M05_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M05_ARESETN"
              }
            }
          },
          "M05_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M06_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M06_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M06_ARESETN"
              }
            }
          },
          "M06_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M07_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M07_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M07_ARESETN"
              }
            }
          },
          "M07_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M08_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M08_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M08_ARESETN"
              }
            }
          },
          "M08_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M09_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M09_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M09_ARESETN"
              }
            }
          },
          "M09_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M10_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M10_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M10_ARESETN"
              }
            }
          },
          "M10_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M11_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M11_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M11_ARESETN"
              }
            }
          },
          "M11_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M12_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M12_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M12_ARESETN"
              }
            }
          },
          "M12_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M13_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M13_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M13_ARESETN"
              }
            }
          },
          "M13_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "microblaze_bd_xbar_7",
            "xci_path": "ip/microblaze_bd_xbar_7/microblaze_bd_xbar_7.xci",
            "inst_hier_path": "axi_interconnect_1/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "14"
              },
              "NUM_SI": {
                "value": "1"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI",
                  "M01_AXI",
                  "M02_AXI",
                  "M03_AXI",
                  "M04_AXI",
                  "M05_AXI",
                  "M06_AXI",
                  "M07_AXI",
                  "M08_AXI",
                  "M09_AXI",
                  "M10_AXI",
                  "M11_AXI",
                  "M12_AXI",
                  "M13_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "s00_couplers_to_s00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m01_couplers_to_m01_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m02_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m02_couplers_to_m02_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m03_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m03_couplers_to_m03_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m04_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m04_couplers_to_m04_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m05_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m05_couplers_to_m05_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m06_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m06_couplers_to_m06_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m07_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m07_couplers_to_m07_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m08_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m08_couplers_to_m08_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m09_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m09_couplers_to_m09_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m10_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m10_couplers_to_m10_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m11_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m11_couplers_to_m11_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m12_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m12_couplers_to_m12_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m13_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m13_couplers_to_m13_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "axi_interconnect_1_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "m00_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "m01_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M01_AXI",
              "m01_couplers/M_AXI"
            ]
          },
          "m02_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M02_AXI",
              "m02_couplers/M_AXI"
            ]
          },
          "m03_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M03_AXI",
              "m03_couplers/M_AXI"
            ]
          },
          "m04_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M04_AXI",
              "m04_couplers/M_AXI"
            ]
          },
          "m05_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M05_AXI",
              "m05_couplers/M_AXI"
            ]
          },
          "m06_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M06_AXI",
              "m06_couplers/M_AXI"
            ]
          },
          "m07_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M07_AXI",
              "m07_couplers/M_AXI"
            ]
          },
          "m08_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M08_AXI",
              "m08_couplers/M_AXI"
            ]
          },
          "m09_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M09_AXI",
              "m09_couplers/M_AXI"
            ]
          },
          "m10_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M10_AXI",
              "m10_couplers/M_AXI"
            ]
          },
          "m11_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M11_AXI",
              "m11_couplers/M_AXI"
            ]
          },
          "m12_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M12_AXI",
              "m12_couplers/M_AXI"
            ]
          },
          "m13_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M13_AXI",
              "m13_couplers/M_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "xbar_to_m01_couplers": {
            "interface_ports": [
              "xbar/M01_AXI",
              "m01_couplers/S_AXI"
            ]
          },
          "xbar_to_m02_couplers": {
            "interface_ports": [
              "xbar/M02_AXI",
              "m02_couplers/S_AXI"
            ]
          },
          "xbar_to_m03_couplers": {
            "interface_ports": [
              "xbar/M03_AXI",
              "m03_couplers/S_AXI"
            ]
          },
          "xbar_to_m04_couplers": {
            "interface_ports": [
              "xbar/M04_AXI",
              "m04_couplers/S_AXI"
            ]
          },
          "xbar_to_m05_couplers": {
            "interface_ports": [
              "xbar/M05_AXI",
              "m05_couplers/S_AXI"
            ]
          },
          "xbar_to_m06_couplers": {
            "interface_ports": [
              "xbar/M06_AXI",
              "m06_couplers/S_AXI"
            ]
          },
          "xbar_to_m07_couplers": {
            "interface_ports": [
              "xbar/M07_AXI",
              "m07_couplers/S_AXI"
            ]
          },
          "xbar_to_m08_couplers": {
            "interface_ports": [
              "xbar/M08_AXI",
              "m08_couplers/S_AXI"
            ]
          },
          "xbar_to_m09_couplers": {
            "interface_ports": [
              "xbar/M09_AXI",
              "m09_couplers/S_AXI"
            ]
          },
          "xbar_to_m10_couplers": {
            "interface_ports": [
              "xbar/M10_AXI",
              "m10_couplers/S_AXI"
            ]
          },
          "xbar_to_m11_couplers": {
            "interface_ports": [
              "xbar/M11_AXI",
              "m11_couplers/S_AXI"
            ]
          },
          "xbar_to_m12_couplers": {
            "interface_ports": [
              "xbar/M12_AXI",
              "m12_couplers/S_AXI"
            ]
          },
          "xbar_to_m13_couplers": {
            "interface_ports": [
              "xbar/M13_AXI",
              "m13_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "axi_interconnect_1_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/S_ACLK",
              "s00_couplers/M_ACLK",
              "m00_couplers/M_ACLK",
              "m01_couplers/M_ACLK",
              "m02_couplers/M_ACLK",
              "m03_couplers/M_ACLK",
              "m04_couplers/M_ACLK",
              "m05_couplers/M_ACLK",
              "m06_couplers/M_ACLK",
              "m07_couplers/M_ACLK",
              "m08_couplers/M_ACLK",
              "m09_couplers/M_ACLK",
              "m10_couplers/M_ACLK",
              "m11_couplers/M_ACLK",
              "m12_couplers/M_ACLK",
              "m13_couplers/M_ACLK",
              "m00_couplers/S_ACLK",
              "m01_couplers/S_ACLK",
              "m02_couplers/S_ACLK",
              "m03_couplers/S_ACLK",
              "m04_couplers/S_ACLK",
              "m05_couplers/S_ACLK",
              "m06_couplers/S_ACLK",
              "m07_couplers/S_ACLK",
              "m08_couplers/S_ACLK",
              "m09_couplers/S_ACLK",
              "m10_couplers/S_ACLK",
              "m11_couplers/S_ACLK",
              "m12_couplers/S_ACLK",
              "m13_couplers/S_ACLK"
            ]
          },
          "axi_interconnect_1_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/S_ARESETN",
              "s00_couplers/M_ARESETN",
              "m00_couplers/M_ARESETN",
              "m01_couplers/M_ARESETN",
              "m02_couplers/M_ARESETN",
              "m03_couplers/M_ARESETN",
              "m04_couplers/M_ARESETN",
              "m05_couplers/M_ARESETN",
              "m06_couplers/M_ARESETN",
              "m07_couplers/M_ARESETN",
              "m08_couplers/M_ARESETN",
              "m09_couplers/M_ARESETN",
              "m10_couplers/M_ARESETN",
              "m11_couplers/M_ARESETN",
              "m12_couplers/M_ARESETN",
              "m13_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN",
              "m01_couplers/S_ARESETN",
              "m02_couplers/S_ARESETN",
              "m03_couplers/S_ARESETN",
              "m04_couplers/S_ARESETN",
              "m05_couplers/S_ARESETN",
              "m06_couplers/S_ARESETN",
              "m07_couplers/S_ARESETN",
              "m08_couplers/S_ARESETN",
              "m09_couplers/S_ARESETN",
              "m10_couplers/S_ARESETN",
              "m11_couplers/S_ARESETN",
              "m12_couplers/S_ARESETN",
              "m13_couplers/S_ARESETN"
            ]
          }
        }
      },
      "axi_quad_spi_0": {
        "vlnv": "xilinx.com:ip:axi_quad_spi:3.2",
        "xci_name": "microblaze_bd_axi_quad_spi_0_0",
        "xci_path": "ip/microblaze_bd_axi_quad_spi_0_0/microblaze_bd_axi_quad_spi_0_0.xci",
        "inst_hier_path": "axi_quad_spi_0",
        "parameters": {
          "C_NUM_SS_BITS": {
            "value": "1"
          },
          "Multiples16": {
            "value": "2"
          }
        }
      },
      "axi_quad_spi_1": {
        "vlnv": "xilinx.com:ip:axi_quad_spi:3.2",
        "xci_name": "microblaze_bd_axi_quad_spi_1_0",
        "xci_path": "ip/microblaze_bd_axi_quad_spi_1_0/microblaze_bd_axi_quad_spi_1_0.xci",
        "inst_hier_path": "axi_quad_spi_1",
        "parameters": {
          "C_NUM_SS_BITS": {
            "value": "2"
          },
          "Multiples16": {
            "value": "2"
          }
        }
      },
      "qspi_flash": {
        "vlnv": "xilinx.com:ip:axi_quad_spi:3.2",
        "xci_name": "microblaze_bd_axi_quad_spi_2_0",
        "xci_path": "ip/microblaze_bd_axi_quad_spi_2_0/microblaze_bd_axi_quad_spi_2_0.xci",
        "inst_hier_path": "qspi_flash",
        "parameters": {
          "C_SPI_MEMORY": {
            "value": "2"
          },
          "C_SPI_MODE": {
            "value": "2"
          },
          "C_USE_STARTUP": {
            "value": "1"
          },
          "C_USE_STARTUP_INT": {
            "value": "1"
          }
        }
      },
      "axi_timer_0": {
        "vlnv": "xilinx.com:ip:axi_timer:2.0",
        "xci_name": "microblaze_bd_axi_timer_0_0",
        "xci_path": "ip/microblaze_bd_axi_timer_0_0/microblaze_bd_axi_timer_0_0.xci",
        "inst_hier_path": "axi_timer_0"
      },
      "axi_uartlite_0": {
        "vlnv": "xilinx.com:ip:axi_uartlite:2.0",
        "xci_name": "microblaze_bd_axi_uartlite_0_0",
        "xci_path": "ip/microblaze_bd_axi_uartlite_0_0/microblaze_bd_axi_uartlite_0_0.xci",
        "inst_hier_path": "axi_uartlite_0",
        "parameters": {
          "C_BAUDRATE": {
            "value": "115200"
          },
          "C_S_AXI_ACLK_FREQ_HZ": {
            "value": "125000000"
          }
        }
      },
      "axis_dwidth_converter_0": {
        "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1",
        "xci_name": "microblaze_bd_axis_dwidth_converter_0_0",
        "xci_path": "ip/microblaze_bd_axis_dwidth_converter_0_0/microblaze_bd_axis_dwidth_converter_0_0.xci",
        "inst_hier_path": "axis_dwidth_converter_0",
        "parameters": {
          "M_TDATA_NUM_BYTES": {
            "value": "4"
          }
        }
      },
      "axis_dwidth_converter_1": {
        "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1",
        "xci_name": "microblaze_bd_axis_dwidth_converter_1_0",
        "xci_path": "ip/microblaze_bd_axis_dwidth_converter_1_0/microblaze_bd_axis_dwidth_converter_1_0.xci",
        "inst_hier_path": "axis_dwidth_converter_1",
        "parameters": {
          "HAS_MI_TKEEP": {
            "value": "1"
          },
          "M_TDATA_NUM_BYTES": {
            "value": "8"
          }
        }
      },
      "clk_wiz_0": {
        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
        "xci_name": "microblaze_bd_clk_wiz_0_1",
        "xci_path": "ip/microblaze_bd_clk_wiz_0_1/microblaze_bd_clk_wiz_0_1.xci",
        "inst_hier_path": "clk_wiz_0",
        "parameters": {
          "CLKIN1_JITTER_PS": {
            "value": "80.0"
          },
          "CLKOUT1_JITTER": {
            "value": "119.348"
          },
          "CLKOUT1_PHASE_ERROR": {
            "value": "96.948"
          },
          "CLKOUT1_REQUESTED_OUT_FREQ": {
            "value": "125"
          },
          "CLKOUT2_JITTER": {
            "value": "99.263"
          },
          "CLKOUT2_PHASE_ERROR": {
            "value": "96.948"
          },
          "CLKOUT2_REQUESTED_OUT_FREQ": {
            "value": "333.33333"
          },
          "CLKOUT2_USED": {
            "value": "true"
          },
          "CLKOUT3_JITTER": {
            "value": "165.419"
          },
          "CLKOUT3_PHASE_ERROR": {
            "value": "96.948"
          },
          "CLKOUT3_REQUESTED_OUT_FREQ": {
            "value": "25"
          },
          "CLKOUT3_USED": {
            "value": "true"
          },
          "MMCM_CLKFBOUT_MULT_F": {
            "value": "8.000"
          },
          "MMCM_CLKIN1_PERIOD": {
            "value": "8.000"
          },
          "MMCM_CLKOUT0_DIVIDE_F": {
            "value": "8.000"
          },
          "MMCM_CLKOUT1_DIVIDE": {
            "value": "3"
          },
          "MMCM_CLKOUT2_DIVIDE": {
            "value": "40"
          },
          "MMCM_DIVCLK_DIVIDE": {
            "value": "1"
          },
          "NUM_OUT_CLKS": {
            "value": "3"
          },
          "PRIM_SOURCE": {
            "value": "Global_buffer"
          },
          "USE_LOCKED": {
            "value": "false"
          },
          "USE_RESET": {
            "value": "false"
          }
        }
      },
      "ddr4_0": {
        "vlnv": "xilinx.com:ip:ddr4:2.2",
        "xci_name": "microblaze_bd_ddr4_0_0",
        "xci_path": "ip/microblaze_bd_ddr4_0_0/microblaze_bd_ddr4_0_0.xci",
        "inst_hier_path": "ddr4_0",
        "parameters": {
          "ADDN_UI_CLKOUT1_FREQ_HZ": {
            "value": "125"
          },
          "ADDN_UI_CLKOUT2_FREQ_HZ": {
            "value": "None"
          },
          "C0.BANK_GROUP_WIDTH": {
            "value": "1"
          },
          "C0.DDR4_AxiAddressWidth": {
            "value": "32"
          },
          "C0.DDR4_AxiDataWidth": {
            "value": "512"
          },
          "C0.DDR4_CasLatency": {
            "value": "15"
          },
          "C0.DDR4_CasWriteLatency": {
            "value": "11"
          },
          "C0.DDR4_DataWidth": {
            "value": "64"
          },
          "C0.DDR4_InputClockPeriod": {
            "value": "5000"
          },
          "C0.DDR4_MemoryPart": {
            "value": "MT40A512M16LY-075"
          },
          "C0.DDR4_TimePeriod": {
            "value": "1000"
          }
        },
        "interface_ports": {
          "C0_DDR4_S_AXI": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Slave",
            "memory_map_ref": "C0_DDR4_MEMORY_MAP"
          }
        },
        "addressing": {
          "memory_maps": {
            "C0_DDR4_MEMORY_MAP": {
              "address_blocks": {
                "C0_DDR4_ADDRESS_BLOCK": {
                  "base_address": "0",
                  "range": "4G",
                  "width": "32",
                  "usage": "memory",
                  "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR",
                  "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR"
                }
              }
            }
          }
        }
      },
      "mdm_1": {
        "vlnv": "xilinx.com:ip:mdm:3.2",
        "xci_name": "microblaze_bd_mdm_1_0",
        "xci_path": "ip/microblaze_bd_mdm_1_0/microblaze_bd_mdm_1_0.xci",
        "inst_hier_path": "mdm_1",
        "parameters": {
          "C_ADDR_SIZE": {
            "value": "32"
          },
          "C_M_AXI_ADDR_WIDTH": {
            "value": "32"
          },
          "C_USE_UART": {
            "value": "1"
          }
        }
      },
      "microblaze_0": {
        "vlnv": "xilinx.com:ip:microblaze:11.0",
        "xci_name": "microblaze_bd_microblaze_0_0",
        "xci_path": "ip/microblaze_bd_microblaze_0_0/microblaze_bd_microblaze_0_0.xci",
        "inst_hier_path": "microblaze_0",
        "parameters": {
          "C_ADDR_TAG_BITS": {
            "value": "16"
          },
          "C_BRANCH_TARGET_CACHE_SIZE": {
            "value": "0"
          },
          "C_CACHE_BYTE_SIZE": {
            "value": "32768"
          },
          "C_DCACHE_ADDR_TAG": {
            "value": "16"
          },
          "C_DCACHE_BYTE_SIZE": {
            "value": "32768"
          },
          "C_DCACHE_DATA_WIDTH": {
            "value": "1"
          },
          "C_DCACHE_LINE_LEN": {
            "value": "16"
          },
          "C_DCACHE_USE_WRITEBACK": {
            "value": "1"
          },
          "C_DCACHE_VICTIMS": {
            "value": "8"
          },
          "C_DEBUG_ENABLED": {
            "value": "1"
          },
          "C_DIV_ZERO_EXCEPTION": {
            "value": "1"
          },
          "C_D_AXI": {
            "value": "1"
          },
          "C_D_LMB": {
            "value": "1"
          },
          "C_FPU_EXCEPTION": {
            "value": "1"
          },
          "C_ICACHE_DATA_WIDTH": {
            "value": "1"
          },
          "C_ICACHE_LINE_LEN": {
            "value": "16"
          },
          "C_ICACHE_STREAMS": {
            "value": "1"
          },
          "C_ICACHE_VICTIMS": {
            "value": "8"
          },
          "C_ILL_OPCODE_EXCEPTION": {
            "value": "1"
          },
          "C_I_LMB": {
            "value": "1"
          },
          "C_M_AXI_D_BUS_EXCEPTION": {
            "value": "1"
          },
          "C_M_AXI_I_BUS_EXCEPTION": {
            "value": "1"
          },
          "C_NUMBER_OF_PC_BRK": {
            "value": "2"
          },
          "C_OPCODE_0x0_ILLEGAL": {
            "value": "1"
          },
          "C_UNALIGNED_EXCEPTIONS": {
            "value": "1"
          },
          "C_USE_BARREL": {
            "value": "1"
          },
          "C_USE_BRANCH_TARGET_CACHE": {
            "value": "0"
          },
          "C_USE_DCACHE": {
            "value": "1"
          },
          "C_USE_DIV": {
            "value": "1"
          },
          "C_USE_FPU": {
            "value": "1"
          },
          "C_USE_HW_MUL": {
            "value": "1"
          },
          "C_USE_ICACHE": {
            "value": "1"
          },
          "C_USE_MSR_INSTR": {
            "value": "1"
          },
          "C_USE_PCMP_INSTR": {
            "value": "1"
          },
          "C_USE_STACK_PROTECTION": {
            "value": "1"
          },
          "G_TEMPLATE_LIST": {
            "value": "9"
          },
          "G_USE_EXCEPTIONS": {
            "value": "1"
          }
        },
        "interface_ports": {
          "DLMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "ILMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Instruction",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "M_AXI_DP": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "M_AXI_DC": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "M_AXI_IC": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Instruction",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          }
        },
        "addressing": {
          "address_spaces": {
            "Data": {
              "range": "4G",
              "width": "32"
            },
            "Instruction": {
              "range": "4G",
              "width": "32"
            }
          }
        },
        "hdl_attributes": {
          "BMM_INFO_PROCESSOR": {
            "value": "microblaze-le > microblaze_bd microblaze_0_local_memory/dlmb_bram_if_cntlr",
            "value_src": "default"
          },
          "KEEP_HIERARCHY": {
            "value": "yes",
            "value_src": "default"
          }
        }
      },
      "microblaze_0_axi_intc": {
        "vlnv": "xilinx.com:ip:axi_intc:4.1",
        "xci_name": "microblaze_bd_microblaze_0_axi_intc_0",
        "xci_path": "ip/microblaze_bd_microblaze_0_axi_intc_0/microblaze_bd_microblaze_0_axi_intc_0.xci",
        "inst_hier_path": "microblaze_0_axi_intc",
        "parameters": {
          "C_HAS_FAST": {
            "value": "1"
          }
        }
      },
      "microblaze_0_axi_periph": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/microblaze_bd_microblaze_0_axi_periph_0/microblaze_bd_microblaze_0_axi_periph_0.xci",
        "inst_hier_path": "microblaze_0_axi_periph",
        "xci_name": "microblaze_bd_microblaze_0_axi_periph_0",
        "parameters": {
          "NUM_MI": {
            "value": "11"
          },
          "NUM_SI": {
            "value": "1"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M02_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M03_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M04_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M05_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
                "value_src": "undefined"
              }
            }
          },
          "M06_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
                "value_src": "undefined"
              }
            }
          },
          "M07_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M08_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
                "value_src": "undefined"
              }
            }
          },
          "M09_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
                "value_src": "undefined"
              }
            }
          },
          "M10_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk",
                "value_src": "undefined"
              }
            }
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M01_ARESETN"
              }
            }
          },
          "M01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M02_ARESETN"
              }
            }
          },
          "M02_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M03_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M03_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M03_ARESETN"
              }
            }
          },
          "M03_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M04_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M04_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M04_ARESETN"
              }
            }
          },
          "M04_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M05_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M05_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M05_ARESETN"
              }
            }
          },
          "M05_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M06_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M06_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M06_ARESETN"
              }
            }
          },
          "M06_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M07_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M07_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M07_ARESETN"
              }
            }
          },
          "M07_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M08_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M08_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M08_ARESETN"
              }
            }
          },
          "M08_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M09_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M09_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M09_ARESETN"
              }
            }
          },
          "M09_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M10_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M10_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M10_ARESETN"
              }
            }
          },
          "M10_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
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            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "microblaze_bd_xbar_8",
            "xci_path": "ip/microblaze_bd_xbar_8/microblaze_bd_xbar_8.xci",
            "inst_hier_path": "microblaze_0_axi_periph/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "11"
              },
              "NUM_SI": {
                "value": "1"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI",
                  "M01_AXI",
                  "M02_AXI",
                  "M03_AXI",
                  "M04_AXI",
                  "M05_AXI",
                  "M06_AXI",
                  "M07_AXI",
                  "M08_AXI",
                  "M09_AXI",
                  "M10_AXI"
                ]
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              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
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                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
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          },
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              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
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                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
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                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
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                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
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              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
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                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m02_couplers_to_m02_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m03_couplers": {
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              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m03_couplers_to_m03_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m04_couplers": {
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                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
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                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m04_couplers_to_m04_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m05_couplers": {
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              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m05_couplers_to_m05_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m06_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m06_couplers_to_m06_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m07_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
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                "vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
                "xci_name": "microblaze_bd_auto_cc_2",
                "xci_path": "ip/microblaze_bd_auto_cc_2/microblaze_bd_auto_cc_2.xci",
                "inst_hier_path": "microblaze_0_axi_periph/m07_couplers/auto_cc",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_cc_to_m07_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "auto_cc/M_AXI"
                ]
              },
              "m07_couplers_to_auto_cc": {
                "interface_ports": [
                  "S_AXI",
                  "auto_cc/S_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "auto_cc/m_axi_aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "auto_cc/m_axi_aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_cc/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_cc/s_axi_aresetn"
                ]
              }
            }
          },
          "m08_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m08_couplers_to_m08_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m09_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m09_couplers_to_m09_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m10_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m10_couplers_to_m10_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "m00_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "m01_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M01_AXI",
              "m01_couplers/M_AXI"
            ]
          },
          "m02_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M02_AXI",
              "m02_couplers/M_AXI"
            ]
          },
          "m03_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M03_AXI",
              "m03_couplers/M_AXI"
            ]
          },
          "m04_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M04_AXI",
              "m04_couplers/M_AXI"
            ]
          },
          "m05_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M05_AXI",
              "m05_couplers/M_AXI"
            ]
          },
          "m06_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M06_AXI",
              "m06_couplers/M_AXI"
            ]
          },
          "m07_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M07_AXI",
              "m07_couplers/M_AXI"
            ]
          },
          "m08_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M08_AXI",
              "m08_couplers/M_AXI"
            ]
          },
          "m09_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M09_AXI",
              "m09_couplers/M_AXI"
            ]
          },
          "m10_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M10_AXI",
              "m10_couplers/M_AXI"
            ]
          },
          "microblaze_0_axi_periph_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "xbar_to_m01_couplers": {
            "interface_ports": [
              "xbar/M01_AXI",
              "m01_couplers/S_AXI"
            ]
          },
          "xbar_to_m02_couplers": {
            "interface_ports": [
              "xbar/M02_AXI",
              "m02_couplers/S_AXI"
            ]
          },
          "xbar_to_m03_couplers": {
            "interface_ports": [
              "xbar/M03_AXI",
              "m03_couplers/S_AXI"
            ]
          },
          "xbar_to_m04_couplers": {
            "interface_ports": [
              "xbar/M04_AXI",
              "m04_couplers/S_AXI"
            ]
          },
          "xbar_to_m05_couplers": {
            "interface_ports": [
              "xbar/M05_AXI",
              "m05_couplers/S_AXI"
            ]
          },
          "xbar_to_m06_couplers": {
            "interface_ports": [
              "xbar/M06_AXI",
              "m06_couplers/S_AXI"
            ]
          },
          "xbar_to_m07_couplers": {
            "interface_ports": [
              "xbar/M07_AXI",
              "m07_couplers/S_AXI"
            ]
          },
          "xbar_to_m08_couplers": {
            "interface_ports": [
              "xbar/M08_AXI",
              "m08_couplers/S_AXI"
            ]
          },
          "xbar_to_m09_couplers": {
            "interface_ports": [
              "xbar/M09_AXI",
              "m09_couplers/S_AXI"
            ]
          },
          "xbar_to_m10_couplers": {
            "interface_ports": [
              "xbar/M10_AXI",
              "m10_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "M00_ACLK_1": {
            "ports": [
              "M00_ACLK",
              "m00_couplers/M_ACLK"
            ]
          },
          "M00_ARESETN_1": {
            "ports": [
              "M00_ARESETN",
              "m00_couplers/M_ARESETN"
            ]
          },
          "M01_ACLK_1": {
            "ports": [
              "M01_ACLK",
              "m01_couplers/M_ACLK"
            ]
          },
          "M01_ARESETN_1": {
            "ports": [
              "M01_ARESETN",
              "m01_couplers/M_ARESETN"
            ]
          },
          "M02_ACLK_1": {
            "ports": [
              "M02_ACLK",
              "m02_couplers/M_ACLK"
            ]
          },
          "M02_ARESETN_1": {
            "ports": [
              "M02_ARESETN",
              "m02_couplers/M_ARESETN"
            ]
          },
          "M03_ACLK_1": {
            "ports": [
              "M03_ACLK",
              "m03_couplers/M_ACLK"
            ]
          },
          "M03_ARESETN_1": {
            "ports": [
              "M03_ARESETN",
              "m03_couplers/M_ARESETN"
            ]
          },
          "M04_ACLK_1": {
            "ports": [
              "M04_ACLK",
              "m04_couplers/M_ACLK"
            ]
          },
          "M04_ARESETN_1": {
            "ports": [
              "M04_ARESETN",
              "m04_couplers/M_ARESETN"
            ]
          },
          "M05_ACLK_1": {
            "ports": [
              "M05_ACLK",
              "m05_couplers/M_ACLK"
            ]
          },
          "M05_ARESETN_1": {
            "ports": [
              "M05_ARESETN",
              "m05_couplers/M_ARESETN"
            ]
          },
          "M06_ACLK_1": {
            "ports": [
              "M06_ACLK",
              "m06_couplers/M_ACLK"
            ]
          },
          "M06_ARESETN_1": {
            "ports": [
              "M06_ARESETN",
              "m06_couplers/M_ARESETN"
            ]
          },
          "M07_ACLK_1": {
            "ports": [
              "M07_ACLK",
              "m07_couplers/M_ACLK"
            ]
          },
          "M07_ARESETN_1": {
            "ports": [
              "M07_ARESETN",
              "m07_couplers/M_ARESETN"
            ]
          },
          "M08_ACLK_1": {
            "ports": [
              "M08_ACLK",
              "m08_couplers/M_ACLK"
            ]
          },
          "M08_ARESETN_1": {
            "ports": [
              "M08_ARESETN",
              "m08_couplers/M_ARESETN"
            ]
          },
          "M09_ACLK_1": {
            "ports": [
              "M09_ACLK",
              "m09_couplers/M_ACLK"
            ]
          },
          "M09_ARESETN_1": {
            "ports": [
              "M09_ARESETN",
              "m09_couplers/M_ARESETN"
            ]
          },
          "M10_ACLK_1": {
            "ports": [
              "M10_ACLK",
              "m10_couplers/M_ACLK"
            ]
          },
          "M10_ARESETN_1": {
            "ports": [
              "M10_ARESETN",
              "m10_couplers/M_ARESETN"
            ]
          },
          "S00_ACLK_1": {
            "ports": [
              "S00_ACLK",
              "s00_couplers/S_ACLK"
            ]
          },
          "S00_ARESETN_1": {
            "ports": [
              "S00_ARESETN",
              "s00_couplers/S_ARESETN"
            ]
          },
          "microblaze_0_axi_periph_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/M_ACLK",
              "m00_couplers/S_ACLK",
              "m01_couplers/S_ACLK",
              "m02_couplers/S_ACLK",
              "m03_couplers/S_ACLK",
              "m04_couplers/S_ACLK",
              "m05_couplers/S_ACLK",
              "m06_couplers/S_ACLK",
              "m07_couplers/S_ACLK",
              "m08_couplers/S_ACLK",
              "m09_couplers/S_ACLK",
              "m10_couplers/S_ACLK"
            ]
          },
          "microblaze_0_axi_periph_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN",
              "m01_couplers/S_ARESETN",
              "m02_couplers/S_ARESETN",
              "m03_couplers/S_ARESETN",
              "m04_couplers/S_ARESETN",
              "m05_couplers/S_ARESETN",
              "m06_couplers/S_ARESETN",
              "m07_couplers/S_ARESETN",
              "m08_couplers/S_ARESETN",
              "m09_couplers/S_ARESETN",
              "m10_couplers/S_ARESETN"
            ]
          }
        }
      },
      "microblaze_0_xlconcat": {
        "vlnv": "xilinx.com:ip:xlconcat:2.1",
        "xci_name": "microblaze_bd_microblaze_0_xlconcat_0",
        "xci_path": "ip/microblaze_bd_microblaze_0_xlconcat_0/microblaze_bd_microblaze_0_xlconcat_0.xci",
        "inst_hier_path": "microblaze_0_xlconcat",
        "parameters": {
          "NUM_PORTS": {
            "value": "14"
          },
          "dout_width": {
            "value": "14"
          }
        }
      },
      "rst_ddr": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "microblaze_bd_proc_sys_reset_0_0",
        "xci_path": "ip/microblaze_bd_proc_sys_reset_0_0/microblaze_bd_proc_sys_reset_0_0.xci",
        "inst_hier_path": "rst_ddr"
      },
      "rst_150": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "microblaze_bd_rst_clk_wiz_1_100M_0",
        "xci_path": "ip/microblaze_bd_rst_clk_wiz_1_100M_0/microblaze_bd_rst_clk_wiz_1_100M_0.xci",
        "inst_hier_path": "rst_150"
      },
      "system_management_wiz_0": {
        "vlnv": "xilinx.com:ip:system_management_wiz:1.3",
        "xci_name": "microblaze_bd_system_management_wiz_0_0",
        "xci_path": "ip/microblaze_bd_system_management_wiz_0_0/microblaze_bd_system_management_wiz_0_0.xci",
        "inst_hier_path": "system_management_wiz_0",
        "parameters": {
          "CHANNEL_ENABLE_VBRAM": {
            "value": "false"
          },
          "CHANNEL_ENABLE_VCCAUX": {
            "value": "false"
          },
          "CHANNEL_ENABLE_VCCINT": {
            "value": "false"
          },
          "CHANNEL_ENABLE_VP_VN": {
            "value": "false"
          },
          "ENABLE_TEMP_BUS": {
            "value": "false"
          },
          "INTERFACE_SELECTION": {
            "value": "Enable_AXI"
          },
          "OT_ALARM": {
            "value": "false"
          },
          "USER_TEMP_ALARM": {
            "value": "false"
          },
          "VCCAUX_ALARM": {
            "value": "false"
          },
          "VCCINT_ALARM": {
            "value": "false"
          }
        }
      }
    },
    "interface_nets": {
      "S00_AXI_1": {
        "interface_ports": [
          "axi_interconnect_1/S00_AXI",
          "microblaze_0_axi_periph/M01_AXI"
        ]
      },
      "S_AXIS_0_1": {
        "interface_ports": [
          "udp_rx",
          "axis_dwidth_converter_0/S_AXIS"
        ]
      },
      "axi_bram_ctrl_0_BRAM_PORTA": {
        "interface_ports": [
          "dac0_wf_bram",
          "axi_bram_ctrl_0/BRAM_PORTA"
        ]
      },
      "axi_bram_ctrl_1_BRAM_PORTA": {
        "interface_ports": [
          "dac1_wf_bram",
          "axi_bram_ctrl_1/BRAM_PORTA"
        ]
      },
      "axi_bram_ctrl_2_BRAM_PORTA": {
        "interface_ports": [
          "dac2_wf_bram",
          "axi_bram_ctrl_2/BRAM_PORTA"
        ]
      },
      "axi_bram_ctrl_3_BRAM_PORTA": {
        "interface_ports": [
          "dac3_wf_bram",
          "axi_bram_ctrl_3/BRAM_PORTA"
        ]
      },
      "axi_ethernet_0_dma_M_AXIS_CNTRL": {
        "interface_ports": [
          "axi_ethernet_0_dma/M_AXIS_CNTRL",
          "axi_ethernet_0/s_axis_txc"
        ]
      },
      "axi_ethernet_0_dma_M_AXIS_MM2S": {
        "interface_ports": [
          "axi_ethernet_0_dma/M_AXIS_MM2S",
          "axi_ethernet_0/s_axis_txd"
        ]
      },
      "axi_ethernet_0_dma_M_AXI_MM2S": {
        "interface_ports": [
          "axi_ethernet_0_dma/M_AXI_MM2S",
          "axi_interconnect_0/S00_AXI"
        ]
      },
      "axi_ethernet_0_dma_M_AXI_S2MM": {
        "interface_ports": [
          "axi_ethernet_0_dma/M_AXI_S2MM",
          "axi_interconnect_0/S01_AXI"
        ]
      },
      "axi_ethernet_0_dma_M_AXI_SG": {
        "interface_ports": [
          "axi_ethernet_0_dma/M_AXI_SG",
          "axi_interconnect_0/S02_AXI"
        ]
      },
      "axi_ethernet_0_m_axis_rxd": {
        "interface_ports": [
          "axi_ethernet_0_dma/S_AXIS_S2MM",
          "axi_ethernet_0/m_axis_rxd"
        ]
      },
      "axi_ethernet_0_m_axis_rxs": {
        "interface_ports": [
          "axi_ethernet_0_dma/S_AXIS_STS",
          "axi_ethernet_0/m_axis_rxs"
        ]
      },
      "axi_ethernet_0_mdio": {
        "interface_ports": [
          "mdio",
          "axi_ethernet_0/mdio"
        ]
      },
      "axi_ethernet_0_rgmii": {
        "interface_ports": [
          "rgmii",
          "axi_ethernet_0/rgmii"
        ]
      },
      "axi_fifo_mm_s_0_AXI_STR_TXD": {
        "interface_ports": [
          "axis_dwidth_converter_1/S_AXIS",
          "axi_fifo_mm_s_0/AXI_STR_TXD"
        ]
      },
      "axi_iic_0_IIC": {
        "interface_ports": [
          "i2c",
          "axi_iic_0/IIC"
        ]
      },
      "axi_interconnect_0_M00_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M00_AXI",
          "ddr4_0/C0_DDR4_S_AXI"
        ]
      },
      "axi_interconnect_1_M00_AXI": {
        "interface_ports": [
          "axi_bram_ctrl_0/S_AXI",
          "axi_interconnect_1/M00_AXI"
        ]
      },
      "axi_interconnect_1_M01_AXI": {
        "interface_ports": [
          "axi_bram_ctrl_1/S_AXI",
          "axi_interconnect_1/M01_AXI"
        ]
      },
      "axi_interconnect_1_M02_AXI": {
        "interface_ports": [
          "axi_bram_ctrl_2/S_AXI",
          "axi_interconnect_1/M02_AXI"
        ]
      },
      "axi_interconnect_1_M03_AXI": {
        "interface_ports": [
          "axi_bram_ctrl_3/S_AXI",
          "axi_interconnect_1/M03_AXI"
        ]
      },
      "axi_interconnect_1_M04_AXI": {
        "interface_ports": [
          "axi_quad_spi_1/AXI_LITE",
          "axi_interconnect_1/M04_AXI"
        ]
      },
      "axi_interconnect_1_M05_AXI": {
        "interface_ports": [
          "axi_quad_spi_0/AXI_LITE",
          "axi_interconnect_1/M05_AXI"
        ]
      },
      "axi_interconnect_1_M06_AXI": {
        "interface_ports": [
          "axi_uartlite_0/S_AXI",
          "axi_interconnect_1/M06_AXI"
        ]
      },
      "axi_interconnect_1_M08_AXI": {
        "interface_ports": [
          "axi_interconnect_1/M08_AXI",
          "jesd/s_axi_phy"
        ]
      },
      "axi_interconnect_1_M10_AXI": {
        "interface_ports": [
          "system_management_wiz_0/S_AXI_LITE",
          "axi_interconnect_1/M10_AXI"
        ]
      },
      "axi_interconnect_1_M11_AXI": {
        "interface_ports": [
          "axi_interconnect_1/M11_AXI",
          "qspi_flash/AXI_LITE"
        ]
      },
      "axi_interconnect_1_M12_AXI": {
        "interface_ports": [
          "axi_interconnect_1/M12_AXI",
          "axi_iic_0/S_AXI"
        ]
      },
      "axi_interconnect_1_M13_AXI": {
        "interface_ports": [
          "axi_interconnect_1/M13_AXI",
          "mdm_1/S_AXI"
        ]
      },
      "axi_quad_spi_0_SPI_0": {
        "interface_ports": [
          "fmc_spi0",
          "axi_quad_spi_0/SPI_0"
        ]
      },
      "axi_quad_spi_1_SPI_0": {
        "interface_ports": [
          "fmc_spi1",
          "axi_quad_spi_1/SPI_0"
        ]
      },
      "axi_uartlite_0_UART": {
        "interface_ports": [
          "uart",
          "axi_uartlite_0/UART"
        ]
      },
      "axis_dwidth_converter_0_M_AXIS": {
        "interface_ports": [
          "axis_dwidth_converter_0/M_AXIS",
          "axi_fifo_mm_s_0/AXI_STR_RXD"
        ]
      },
      "axis_dwidth_converter_1_M_AXIS": {
        "interface_ports": [
          "udp_tx",
          "axis_dwidth_converter_1/M_AXIS"
        ]
      },
      "clk_200_in_1": {
        "interface_ports": [
          "clk_200_in",
          "ddr4_0/C0_SYS_CLK"
        ]
      },
      "ddr4_0_C0_DDR4": {
        "interface_ports": [
          "ddr",
          "ddr4_0/C0_DDR4"
        ]
      },
      "jesd204c_0_m_axis_rx": {
        "interface_ports": [
          "jesd_axis_rx",
          "jesd/jesd_axis_rx"
        ]
      },
      "jesd204c_0_m_axis_rx_cmd": {
        "interface_ports": [
          "jesd_axis_rx_cmd",
          "jesd/jesd_axis_rx_cmd"
        ]
      },
      "jesd_qpll0_refclk_1": {
        "interface_ports": [
          "jesd_qpll0_refclk",
          "jesd/jesd_qpll0_refclk"
        ]
      },
      "jesd_sysref_1": {
        "interface_ports": [
          "jesd_sysref",
          "jesd/jesd_sysref"
        ]
      },
      "microblaze_0_M_AXI_DC": {
        "interface_ports": [
          "microblaze_0/M_AXI_DC",
          "axi_interconnect_0/S03_AXI"
        ]
      },
      "microblaze_0_M_AXI_IC": {
        "interface_ports": [
          "microblaze_0/M_AXI_IC",
          "axi_interconnect_0/S04_AXI"
        ]
      },
      "microblaze_0_axi_dp": {
        "interface_ports": [
          "microblaze_0_axi_periph/S00_AXI",
          "microblaze_0/M_AXI_DP"
        ]
      },
      "microblaze_0_axi_periph_M02_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M02_AXI",
          "axi_ethernet_0/s_axi"
        ]
      },
      "microblaze_0_axi_periph_M03_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M03_AXI",
          "axi_timer_0/S_AXI"
        ]
      },
      "microblaze_0_axi_periph_M04_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M04_AXI",
          "axi_ethernet_0_dma/S_AXI_LITE"
        ]
      },
      "microblaze_0_axi_periph_M05_AXI": {
        "interface_ports": [
          "timing_engine_axil",
          "microblaze_0_axi_periph/M05_AXI"
        ]
      },
      "microblaze_0_axi_periph_M06_AXI": {
        "interface_ports": [
          "util_reg_axil",
          "microblaze_0_axi_periph/M06_AXI"
        ]
      },
      "microblaze_0_axi_periph_M07_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M07_AXI",
          "axi_fifo_mm_s_0/S_AXI"
        ]
      },
      "microblaze_0_axi_periph_M08_AXI": {
        "interface_ports": [
          "dig_rx0_axil",
          "microblaze_0_axi_periph/M08_AXI"
        ]
      },
      "microblaze_0_axi_periph_M09_AXI": {
        "interface_ports": [
          "wf_gen_axil",
          "microblaze_0_axi_periph/M09_AXI"
        ]
      },
      "microblaze_0_axi_periph_M10_AXI": {
        "interface_ports": [
          "dig_rx1_axil",
          "microblaze_0_axi_periph/M10_AXI"
        ]
      },
      "microblaze_0_debug": {
        "interface_ports": [
          "mdm_1/MBDEBUG_0",
          "microblaze_0/DEBUG"
        ]
      },
      "microblaze_0_dlmb_1": {
        "interface_ports": [
          "microblaze_0/DLMB",
          "microblaze_0_local_memory/DLMB"
        ]
      },
      "microblaze_0_ilmb_1": {
        "interface_ports": [
          "microblaze_0/ILMB",
          "microblaze_0_local_memory/ILMB"
        ]
      },
      "microblaze_0_intc_axi": {
        "interface_ports": [
          "microblaze_0_axi_periph/M00_AXI",
          "microblaze_0_axi_intc/s_axi"
        ]
      },
      "microblaze_0_interrupt": {
        "interface_ports": [
          "microblaze_0_axi_intc/interrupt",
          "microblaze_0/INTERRUPT"
        ]
      },
      "qspi_flash_STARTUP_IO_S": {
        "interface_ports": [
          "STARTUP_IO",
          "qspi_flash/STARTUP_IO_S"
        ]
      },
      "s_axi_rx_1": {
        "interface_ports": [
          "jesd/s_axi_rx",
          "axi_interconnect_1/M07_AXI"
        ]
      },
      "s_axi_tx_1": {
        "interface_ports": [
          "jesd/s_axi_tx",
          "axi_interconnect_1/M09_AXI"
        ]
      },
      "s_axis_tx_0_1": {
        "interface_ports": [
          "jesd_axis_tx",
          "jesd/jesd_axis_tx"
        ]
      },
      "s_axis_tx_cmd_0_1": {
        "interface_ports": [
          "jesd_axis_tx_cmd",
          "jesd/jesd_axis_tx_cmd"
        ]
      }
    },
    "nets": {
      "In12_0_1": {
        "ports": [
          "pps",
          "microblaze_0_xlconcat/In12"
        ]
      },
      "axi_ethernet_0_dma_mm2s_cntrl_reset_out_n": {
        "ports": [
          "axi_ethernet_0_dma/mm2s_cntrl_reset_out_n",
          "axi_ethernet_0/axi_txc_arstn"
        ]
      },
      "axi_ethernet_0_dma_mm2s_introut": {
        "ports": [
          "axi_ethernet_0_dma/mm2s_introut",
          "microblaze_0_xlconcat/In4"
        ]
      },
      "axi_ethernet_0_dma_mm2s_prmry_reset_out_n": {
        "ports": [
          "axi_ethernet_0_dma/mm2s_prmry_reset_out_n",
          "axi_ethernet_0/axi_txd_arstn"
        ]
      },
      "axi_ethernet_0_dma_s2mm_introut": {
        "ports": [
          "axi_ethernet_0_dma/s2mm_introut",
          "microblaze_0_xlconcat/In5"
        ]
      },
      "axi_ethernet_0_dma_s2mm_sts_reset_out_n": {
        "ports": [
          "axi_ethernet_0_dma/s2mm_sts_reset_out_n",
          "axi_ethernet_0/axi_rxs_arstn"
        ]
      },
      "axi_ethernet_0_fifo_s2mm_prmry_reset_out_n": {
        "ports": [
          "axi_ethernet_0_dma/s2mm_prmry_reset_out_n",
          "axi_ethernet_0/axi_rxd_arstn"
        ]
      },
      "axi_ethernet_0_interrupt": {
        "ports": [
          "axi_ethernet_0/interrupt",
          "microblaze_0_xlconcat/In1"
        ]
      },
      "axi_ethernet_0_mac_irq": {
        "ports": [
          "axi_ethernet_0/mac_irq",
          "microblaze_0_xlconcat/In3"
        ]
      },
      "axi_ethernet_0_phy_rst_n": {
        "ports": [
          "axi_ethernet_0/phy_rst_n",
          "phy_rst_n"
        ]
      },
      "axi_fifo_mm_s_0_interrupt": {
        "ports": [
          "axi_fifo_mm_s_0/interrupt",
          "microblaze_0_xlconcat/In10"
        ]
      },
      "axi_iic_0_iic2intc_irpt": {
        "ports": [
          "axi_iic_0/iic2intc_irpt",
          "microblaze_0_xlconcat/In13"
        ]
      },
      "axi_quad_spi_0_ip2intc_irpt": {
        "ports": [
          "axi_quad_spi_0/ip2intc_irpt",
          "microblaze_0_xlconcat/In8"
        ]
      },
      "axi_quad_spi_1_ip2intc_irpt": {
        "ports": [
          "axi_quad_spi_1/ip2intc_irpt",
          "microblaze_0_xlconcat/In9"
        ]
      },
      "axi_timer_0_interrupt": {
        "ports": [
          "axi_timer_0/interrupt",
          "microblaze_0_xlconcat/In2"
        ]
      },
      "axi_uartlite_0_interrupt": {
        "ports": [
          "axi_uartlite_0/interrupt",
          "microblaze_0_xlconcat/In0"
        ]
      },
      "clk_wiz_0_clk_out1": {
        "ports": [
          "clk_wiz_0/clk_out1",
          "axi_ethernet_0/gtx_clk"
        ]
      },
      "clk_wiz_0_clk_out2": {
        "ports": [
          "clk_wiz_0/clk_out2",
          "axi_ethernet_0/ref_clk"
        ]
      },
      "clk_wiz_0_clk_out3": {
        "ports": [
          "clk_wiz_0/clk_out3",
          "qspi_flash/ext_spi_clk"
        ]
      },
      "core_clk_1": {
        "ports": [
          "jesd_core_clk",
          "jesd/jesd_core_clk"
        ]
      },
      "ddr4_0_c0_ddr4_ui_clk": {
        "ports": [
          "ddr4_0/c0_ddr4_ui_clk",
          "axi_ethernet_0/axis_clk",
          "axi_ethernet_0_dma/m_axi_sg_aclk",
          "axi_ethernet_0_dma/m_axi_mm2s_aclk",
          "axi_ethernet_0_dma/m_axi_s2mm_aclk",
          "axi_interconnect_0/ACLK",
          "axi_interconnect_0/S00_ACLK",
          "axi_interconnect_0/S01_ACLK",
          "axi_interconnect_0/S02_ACLK",
          "axi_interconnect_0/M00_ACLK",
          "rst_ddr/slowest_sync_clk"
        ]
      },
      "ddr4_0_c0_init_calib_complete": {
        "ports": [
          "ddr4_0/c0_init_calib_complete",
          "ddr_init_calib_complete"
        ]
      },
      "ext_reset_in_0_1": {
        "ports": [
          "ext_reset_in_200",
          "rst_ddr/ext_reset_in",
          "rst_150/ext_reset_in"
        ]
      },
      "jesd204_phy_0_txn_out": {
        "ports": [
          "jesd/jesd_txn_out",
          "jesd_txn_out"
        ]
      },
      "jesd204_phy_0_txp_out": {
        "ports": [
          "jesd/jesd_txp_out",
          "jesd_txp_out"
        ]
      },
      "jesd204c_0_irq": {
        "ports": [
          "jesd/irq1",
          "microblaze_0_xlconcat/In6"
        ]
      },
      "jesd204c_0_rx_aresetn": {
        "ports": [
          "jesd/jesd_axis_rx_aresetn",
          "jesd_axis_rx_aresetn"
        ]
      },
      "jesd204c_1_irq": {
        "ports": [
          "jesd/irq",
          "microblaze_0_xlconcat/In7"
        ]
      },
      "jesd204c_1_tx_aresetn": {
        "ports": [
          "jesd/jesd_axis_tx_aresetn",
          "jesd_axis_tx_aresetn"
        ]
      },
      "jesd_common0_qpll1_lock_out_0": {
        "ports": [
          "jesd/common0_qpll1_lock_out",
          "common0_qpll1_lock_out"
        ]
      },
      "jesd_common1_qpll1_lock_out_0": {
        "ports": [
          "jesd/common1_qpll1_lock_out",
          "common1_qpll1_lock_out"
        ]
      },
      "jesd_rx_sync_0": {
        "ports": [
          "jesd/jesd_rx_sync",
          "jesd_rx_sync"
        ]
      },
      "mdm_1_debug_sys_rst": {
        "ports": [
          "mdm_1/Debug_SYS_Rst",
          "rst_150/mb_debug_sys_rst"
        ]
      },
      "microblaze_0_Clk": {
        "ports": [
          "ddr4_0/addn_ui_clkout1",
          "microblaze_0_local_memory/LMB_Clk",
          "mb_axi_clk",
          "jesd/mb_axi_clk",
          "axi_bram_ctrl_0/s_axi_aclk",
          "axi_bram_ctrl_1/s_axi_aclk",
          "axi_bram_ctrl_2/s_axi_aclk",
          "axi_bram_ctrl_3/s_axi_aclk",
          "axi_ethernet_0/s_axi_lite_clk",
          "axi_ethernet_0_dma/s_axi_lite_aclk",
          "axi_iic_0/s_axi_aclk",
          "axi_interconnect_0/S03_ACLK",
          "axi_interconnect_0/S04_ACLK",
          "axi_interconnect_1/ACLK",
          "axi_interconnect_1/S00_ACLK",
          "axi_interconnect_1/M00_ACLK",
          "axi_interconnect_1/M01_ACLK",
          "axi_interconnect_1/M02_ACLK",
          "axi_interconnect_1/M03_ACLK",
          "axi_interconnect_1/M04_ACLK",
          "axi_interconnect_1/M05_ACLK",
          "axi_interconnect_1/M06_ACLK",
          "axi_interconnect_1/M07_ACLK",
          "axi_interconnect_1/M08_ACLK",
          "axi_interconnect_1/M09_ACLK",
          "axi_interconnect_1/M10_ACLK",
          "axi_interconnect_1/M11_ACLK",
          "axi_interconnect_1/M12_ACLK",
          "axi_quad_spi_0/ext_spi_clk",
          "axi_quad_spi_0/s_axi_aclk",
          "axi_quad_spi_1/ext_spi_clk",
          "axi_quad_spi_1/s_axi_aclk",
          "qspi_flash/s_axi_aclk",
          "axi_timer_0/s_axi_aclk",
          "axi_uartlite_0/s_axi_aclk",
          "clk_wiz_0/clk_in1",
          "microblaze_0/Clk",
          "microblaze_0_axi_intc/s_axi_aclk",
          "microblaze_0_axi_intc/processor_clk",
          "microblaze_0_axi_periph/ACLK",
          "microblaze_0_axi_periph/S00_ACLK",
          "microblaze_0_axi_periph/M00_ACLK",
          "microblaze_0_axi_periph/M01_ACLK",
          "microblaze_0_axi_periph/M02_ACLK",
          "microblaze_0_axi_periph/M03_ACLK",
          "microblaze_0_axi_periph/M04_ACLK",
          "microblaze_0_axi_periph/M05_ACLK",
          "microblaze_0_axi_periph/M06_ACLK",
          "microblaze_0_axi_periph/M08_ACLK",
          "microblaze_0_axi_periph/M09_ACLK",
          "microblaze_0_axi_periph/M10_ACLK",
          "rst_150/slowest_sync_clk",
          "system_management_wiz_0/s_axi_aclk",
          "axi_interconnect_1/M13_ACLK",
          "mdm_1/S_AXI_ACLK"
        ]
      },
      "microblaze_0_intr": {
        "ports": [
          "microblaze_0_xlconcat/dout",
          "microblaze_0_axi_intc/intr"
        ]
      },
      "qspi_flash_ip2intc_irpt": {
        "ports": [
          "qspi_flash/ip2intc_irpt",
          "microblaze_0_xlconcat/In11"
        ]
      },
      "rst_clk_wiz_1_100M_bus_struct_reset": {
        "ports": [
          "rst_150/bus_struct_reset",
          "microblaze_0_local_memory/SYS_Rst"
        ]
      },
      "rst_clk_wiz_1_100M_mb_reset": {
        "ports": [
          "rst_150/mb_reset",
          "microblaze_0/Reset",
          "microblaze_0_axi_intc/processor_rst"
        ]
      },
      "rst_clk_wiz_1_100M_peripheral_aresetn": {
        "ports": [
          "rst_150/peripheral_aresetn",
          "mb_axi_aresetn",
          "jesd/mb_axi_aresetn",
          "axi_bram_ctrl_0/s_axi_aresetn",
          "axi_bram_ctrl_1/s_axi_aresetn",
          "axi_bram_ctrl_2/s_axi_aresetn",
          "axi_bram_ctrl_3/s_axi_aresetn",
          "axi_ethernet_0/s_axi_lite_resetn",
          "axi_ethernet_0_dma/axi_resetn",
          "axi_iic_0/s_axi_aresetn",
          "axi_interconnect_0/S03_ARESETN",
          "axi_interconnect_0/S04_ARESETN",
          "axi_interconnect_1/ARESETN",
          "axi_interconnect_1/S00_ARESETN",
          "axi_interconnect_1/M00_ARESETN",
          "axi_interconnect_1/M01_ARESETN",
          "axi_interconnect_1/M02_ARESETN",
          "axi_interconnect_1/M03_ARESETN",
          "axi_interconnect_1/M04_ARESETN",
          "axi_interconnect_1/M05_ARESETN",
          "axi_interconnect_1/M06_ARESETN",
          "axi_interconnect_1/M07_ARESETN",
          "axi_interconnect_1/M08_ARESETN",
          "axi_interconnect_1/M09_ARESETN",
          "axi_interconnect_1/M10_ARESETN",
          "axi_interconnect_1/M11_ARESETN",
          "axi_interconnect_1/M12_ARESETN",
          "axi_quad_spi_0/s_axi_aresetn",
          "axi_quad_spi_1/s_axi_aresetn",
          "axi_timer_0/s_axi_aresetn",
          "axi_uartlite_0/s_axi_aresetn",
          "microblaze_0_axi_intc/s_axi_aresetn",
          "microblaze_0_axi_periph/ARESETN",
          "microblaze_0_axi_periph/S00_ARESETN",
          "microblaze_0_axi_periph/M00_ARESETN",
          "microblaze_0_axi_periph/M01_ARESETN",
          "microblaze_0_axi_periph/M02_ARESETN",
          "microblaze_0_axi_periph/M03_ARESETN",
          "microblaze_0_axi_periph/M04_ARESETN",
          "microblaze_0_axi_periph/M05_ARESETN",
          "microblaze_0_axi_periph/M06_ARESETN",
          "microblaze_0_axi_periph/M08_ARESETN",
          "microblaze_0_axi_periph/M09_ARESETN",
          "microblaze_0_axi_periph/M10_ARESETN",
          "system_management_wiz_0/s_axi_aresetn",
          "axi_interconnect_1/M13_ARESETN",
          "mdm_1/S_AXI_ARESETN"
        ]
      },
      "rst_ddr_mb_reset": {
        "ports": [
          "rst_ddr/mb_reset",
          "ddr4_0/sys_rst"
        ]
      },
      "rst_ddr_peripheral_aresetn": {
        "ports": [
          "rst_ddr/peripheral_aresetn",
          "axi_interconnect_0/ARESETN",
          "axi_interconnect_0/S00_ARESETN",
          "axi_interconnect_0/S01_ARESETN",
          "axi_interconnect_0/S02_ARESETN",
          "axi_interconnect_0/M00_ARESETN",
          "ddr4_0/c0_ddr4_aresetn"
        ]
      },
      "rx_core_reset_0_1": {
        "ports": [
          "jesd_rx_core_reset",
          "jesd/jesd_rx_core_reset"
        ]
      },
      "rx_sys_reset_0_1": {
        "ports": [
          "jesd_rx_sys_reset",
          "jesd/jesd_rx_sys_reset"
        ]
      },
      "rxn_in_0_1": {
        "ports": [
          "jesd_rxn_in",
          "jesd/jesd_rxn_in"
        ]
      },
      "rxp_in_0_1": {
        "ports": [
          "jesd_rxp_in",
          "jesd/jesd_rxp_in"
        ]
      },
      "s_axi_aclk_0_1": {
        "ports": [
          "eth_clk",
          "axi_fifo_mm_s_0/s_axi_aclk",
          "axis_dwidth_converter_0/aclk",
          "axis_dwidth_converter_1/aclk",
          "microblaze_0_axi_periph/M07_ACLK"
        ]
      },
      "s_axi_aresetn_0_1": {
        "ports": [
          "eth_resetn",
          "axi_fifo_mm_s_0/s_axi_aresetn",
          "axis_dwidth_converter_0/aresetn",
          "axis_dwidth_converter_1/aresetn",
          "microblaze_0_axi_periph/M07_ARESETN"
        ]
      },
      "s_axi_aresetn_0_2": {
        "ports": [
          "qspi_flash_aresetn",
          "qspi_flash/s_axi_aresetn"
        ]
      },
      "tx_core_reset_0_1": {
        "ports": [
          "jesd_tx_core_reset",
          "jesd/jesd_tx_core_reset"
        ]
      },
      "tx_sync_0_1": {
        "ports": [
          "jesd_tx_sync",
          "jesd/jesd_tx_sync"
        ]
      },
      "tx_sys_reset_0_1": {
        "ports": [
          "jesd_tx_sys_reset",
          "jesd/jesd_tx_sys_reset"
        ]
      }
    },
    "addressing": {
      "/": {
        "memory_maps": {
          "dig_rx0_axil": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "dig_rx1_axil": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "timing_engine_axil": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "util_reg_axil": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "wf_gen_axil": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          }
        }
      },
      "/axi_ethernet_0_dma": {
        "address_spaces": {
          "Data_SG": {
            "segments": {
              "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": {
                "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK",
                "offset": "0x80000000",
                "range": "2G",
                "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR",
                "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR"
              }
            }
          },
          "Data_MM2S": {
            "segments": {
              "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": {
                "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK",
                "offset": "0x80000000",
                "range": "2G",
                "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR",
                "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR"
              }
            }
          },
          "Data_S2MM": {
            "segments": {
              "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": {
                "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK",
                "offset": "0x80000000",
                "range": "2G",
                "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR",
                "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR"
              }
            }
          }
        }
      },
      "/microblaze_0": {
        "address_spaces": {
          "Data": {
            "segments": {
              "SEG_axi_bram_ctrl_0_Mem0": {
                "address_block": "/axi_bram_ctrl_0/S_AXI/Mem0",
                "offset": "0x00020000",
                "range": "128K"
              },
              "SEG_axi_bram_ctrl_1_Mem0": {
                "address_block": "/axi_bram_ctrl_1/S_AXI/Mem0",
                "offset": "0x00040000",
                "range": "128K"
              },
              "SEG_axi_bram_ctrl_2_Mem0": {
                "address_block": "/axi_bram_ctrl_2/S_AXI/Mem0",
                "offset": "0x00060000",
                "range": "128K"
              },
              "SEG_axi_bram_ctrl_3_Mem0": {
                "address_block": "/axi_bram_ctrl_3/S_AXI/Mem0",
                "offset": "0x00080000",
                "range": "128K"
              },
              "SEG_axi_ethernet_0_Reg0": {
                "address_block": "/axi_ethernet_0/s_axi/Reg0",
                "offset": "0x40080000",
                "range": "256K"
              },
              "SEG_axi_ethernet_0_dma_Reg": {
                "address_block": "/axi_ethernet_0_dma/S_AXI_LITE/Reg",
                "offset": "0x40040000",
                "range": "64K"
              },
              "SEG_axi_fifo_mm_s_0_Mem0": {
                "address_block": "/axi_fifo_mm_s_0/S_AXI/Mem0",
                "offset": "0x400F0000",
                "range": "64K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_axi_iic_0_Reg": {
                "address_block": "/axi_iic_0/S_AXI/Reg",
                "offset": "0x40110000",
                "range": "64K"
              },
              "SEG_axi_quad_spi_0_Reg": {
                "address_block": "/axi_quad_spi_0/AXI_LITE/Reg",
                "offset": "0x400C0000",
                "range": "64K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_axi_quad_spi_1_Reg": {
                "address_block": "/axi_quad_spi_1/AXI_LITE/Reg",
                "offset": "0x400D0000",
                "range": "64K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_axi_timer_0_Reg": {
                "address_block": "/axi_timer_0/S_AXI/Reg",
                "offset": "0x40030000",
                "range": "64K"
              },
              "SEG_axi_uartlite_0_Reg": {
                "address_block": "/axi_uartlite_0/S_AXI/Reg",
                "offset": "0x40000000",
                "range": "64K"
              },
              "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": {
                "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK",
                "offset": "0x80000000",
                "range": "2G",
                "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR",
                "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR"
              },
              "SEG_dig_rx1_axil_Reg": {
                "address_block": "/dig_rx1_axil/Reg",
                "offset": "0x20010000",
                "range": "4K"
              },
              "SEG_dig_rx_axil_Reg": {
                "address_block": "/dig_rx0_axil/Reg",
                "offset": "0x20000000",
                "range": "4K"
              },
              "SEG_dlmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x00000000",
                "range": "32K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_jesd204_phy_0_Reg": {
                "address_block": "/jesd/jesd204_phy_0/s_axi/Reg",
                "offset": "0x400E0000",
                "range": "64K"
              },
              "SEG_jesd204c_0_Reg": {
                "address_block": "/jesd/jesd204c_0/s_axi/Reg",
                "offset": "0x40060000",
                "range": "64K"
              },
              "SEG_jesd204c_1_Reg": {
                "address_block": "/jesd/jesd204c_1/s_axi/Reg",
                "offset": "0x40070000",
                "range": "64K"
              },
              "SEG_mdm_1_Reg": {
                "address_block": "/mdm_1/S_AXI/Reg",
                "offset": "0x41400000",
                "range": "4K"
              },
              "SEG_microblaze_0_axi_intc_Reg": {
                "address_block": "/microblaze_0_axi_intc/S_AXI/Reg",
                "offset": "0x40010000",
                "range": "64K"
              },
              "SEG_qspi_flash_Reg": {
                "address_block": "/qspi_flash/AXI_LITE/Reg",
                "offset": "0x40100000",
                "range": "64K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_system_management_wiz_0_Reg": {
                "address_block": "/system_management_wiz_0/S_AXI_LITE/Reg",
                "offset": "0x40020000",
                "range": "64K"
              },
              "SEG_timing_engine_axil_Reg": {
                "address_block": "/timing_engine_axil/Reg",
                "offset": "0x40051000",
                "range": "4K"
              },
              "SEG_util_reg_axil_Reg": {
                "address_block": "/util_reg_axil/Reg",
                "offset": "0x40050000",
                "range": "4K"
              },
              "SEG_wf_gen_axil_Reg": {
                "address_block": "/wf_gen_axil/Reg",
                "offset": "0x40053000",
                "range": "4K"
              }
            }
          },
          "Instruction": {
            "segments": {
              "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": {
                "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK",
                "offset": "0x80000000",
                "range": "2G",
                "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR",
                "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR"
              },
              "SEG_ilmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x00000000",
                "range": "32K",
                "offset_high_param": "C_HIGHADDR"
              }
            }
          }
        }
      }
    }
  }
}