#ifndef __REGISTERS_H__
#define __REGISTERS_H__


#define UTIL_ADDR 			0x40050000
#define GPO_REG 			(UTIL_ADDR + 0x08)
#define ETH_10G_RST			0x8000
#define JESD_CORE_CLK_SEL	0x0800
#define QSPI_FLASH_RST		0x0400
#define JESD_TX_SYS_RST		0x0200
#define JESD_RX_SYS_RST		0x0100
#define JESD_TX_CORE_RST	0x0080
#define JESD_RX_CORE_RST	0x0040
#define RESETB				0x0020
#define FMC_PWR_EN			0x0010
#define ALL_JESD_RST		(JESD_TX_SYS_RST | JESD_RX_SYS_RST | JESD_TX_CORE_RST | JESD_RX_CORE_RST)
#define GPI_REG				(UTIL_ADDR + 0x0C)



#define TIMING_ENGINE_ADDR 	0x40051000
#define DIG_RX_ADDR 		0x20000000
#define DIG_RX_STRIDE 		0x10000
#define WAVEFORM_GEN_ADDR 	0x40053000





#endif
