/*!
 * @brief     Use Case Settings
 *
 * @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
 *            This software is proprietary to Analog Devices, Inc. and its
 *            licensor. By using this software you agree to the terms of the
 *            associated analog devices software license agreement.
 */

/*!
 * @addtogroup __ADI_AD9081_APP__
 * @{
 */
/******************************************************
The AD9081/AD9082/AD9988/AD9986 standalone application use-case Settings holds the AD9081/AD9082/AD9988/AD9986 configuration parameters of a number of modes of operation or "usecase" for the ad9081.
Currently the Standalone App is QA'd with 20+ usecases that. These are usecases that the AD9081/AD9082/AD9988/AD9986 ADI evaluation platforms can support and can be used as a reference to�
build a usecase parameters for a custom application.
*/

/*============= I N C L U D E S ============*/
#include <stdio.h>
#include <unistd.h>
#include "adi_ad9081.h"

/*============= D A T A ====================*/
/* Usecase Frequency Scheme Settings
*   This array list the desired clocks required for the usecase.
*   For each usecase an array of depth 4 provides the frequecy in Hz for the following clocks
*   As this application targets the Txfe/MxFE evaluation board, that my have various XTAL as reference to the HMC7044.
*   The comments following the usecase entry will indicate if the scheme can be used with the target hardware.
*   The Comments also provide the expected lane rate of the usecase.
*          clk_hz["usecase"][0]  Txfe/MxFE Device reference Clock (dev_ref), if not using on chip pll, this should be equal to the dac_clk
*          clk_hz["usecase"][1]  The value of the reference clock to the ADS9 FPGA JESD Blocks, This is not used by MxFE/TxFE API. (204C lane rate/66) or (204B lane rate/20)
*          clk_hz["usecase"][2]  The MxFE TX data path DAC sampling clock (dac_clk) as per the desired usecase
*          clk_hz["usecase"][3]  The MxFE Rx data path ADC aampling clock (adc_clk) as per the desired usecase
*   Notes:
*         The Example Application will use adi_ad9081_device_clk_config_set to configure the MxFE/TxFE based on th dev_ref, dac_clk, and adc_clk.
*         If the on-chip PLL feature of MxFe/Txfe is not required dev_ref and dac_clk should be set to the same value.
*         If on chip PLL is required, then based on the applied dev_ref clock and the desired dac_clk the API will configure the onchip -pll appropriately
*         The API will also configure the chip to generate the desired adc_clk based on the dac_clk.
*
*/
uint64_t clk_hz[][4] = {
    /*dev_ref,  fpga_ref, dac_clk,    adc_clk */
	{ 93.75e6,    187.5e6,    9000e6,    3000e6    },
	{ 112.5e6,    225e6,    10800e6,    3600e6    },
	{ 125e6,    250e6,    6000e6,    3000e6    },
//	{ 125e6,    250e6,    12000e6,    4000e6    },
	{ 93.75e6,    187.5e6,    9000e6,    3000e6    },
//	{ 100e6,    250e6,    12000e6,    4000e6    },

};  // 204B

#if !defined(AD9207_ID) && !defined(AD9209_ID)
/* TX DataPath Configuration Settings*/
/*  DAC Crossbar Configuration
*   Use this parameter to define Mapping from Map JRx Samples to DAC Channelizer to MAIN DAC Datapath
*   For Modes that support Use Channel Interpolation > 1
*       JRX Converter Samples are mapped to Channels Datapaths as follows:
*       Note each AD9081_DAC_CH_X is made up of an IQ pair sample
*       DUAL LINK  | M  |  Default Channel Datapth Mapping (0-7)
*        0         | 2  |  AD9081_DAC_CH_0
*        0         | 4  |  AD9081_DAC_CH_0 , AD9081_DAC_CH_1
*        0         | 6  |  AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2
*        0         | 8  |  AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3 
*        0         | 12 |  AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5 
*        0         | 16 |  AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
*        1         | 2  |  Link 0: AD9081_DAC_CH_0 , Link1: AD9081_DAC_CH_4 
*        1         | 4  |  Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5
*        1         | 6  |  Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1, AD9081_DAC_CH_3 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6
*        1         | 8  |  Link 0:AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
*       Each Main DAC Datapath may be a summation of the Channel datapaths. Use tx_dac_chan_xbar as follows to achieve that as described below.

*       uint8_t tx_dac_chan_xbar[usecase][ORed List Channel (0-7) to be summed and mapped to DAC Datapath(0-3)]
*       Each usecase has an Array of depth 4, each member value is the list of Channels to be mapped a Main DAC Datapath,
*       where index 0 = DAC0, index 1 = DAC1 etc
*       OR adi_ad9082_dac_channel_select_e enumerations to create the list
*       For example: ad9081_dac_chan_xbar[0][0] =AD9081_DAC_CH_0 |AD9081_DAC_CH_1
*       Map Channlizer 0 and Channelizer 1 to DAC 0
*       
*  For Modes that bypass Channel ie Channel Interpolation = 1 and Main DAC Interpolation > 1
*      JRX Converter Samples are mapped by default to DAC Main Data apths as follows
*       DUAL LINK  | M  |  Default Main DAC Datapath  Mapping (0-3)                                    | DAC DP to DAC Mapping (0-3)           
*        0         | 2  |  AD9081_DAC_DP_0                                                               | AD9081_DAC_DP_0 ->DAC 0
*        0         | 4  |  AD9081_DAC_DP_0 , AD9081_DAC_DP_1                                               | AD9081_DAC_DP_0 ->DAC 0,  AD9081_DAC_DP_1 ->DAC 1
*        0         | 6  |  AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2                               | AD9081_DAC_DP_0 ->DAC 0,  AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2
*        0         | 8  |  AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2, AD9081_DAC_DP_3                | AD9081_DAC_DP_0 ->DAC 0,  AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
*        1         | 2  |  Link 0: AD9081_DAC_DP_0 , Link1: AD9081_DAC_DP_2                                | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_2 ->DAC 2
*        1         | 4  |  Link 0: AD9081_DAC_DP_0,AD9081_DAC_DP_1 , Link1: AD9081_DAC_DP_2, AD9081_DAC_DP_3   | AD9081_DAC_DP_0 ->DAC 0,  AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
*      Each converter sample pair may be routed to an alternative Datapath.  Use tx_dac_chan_xbar as follows to achieve that as described below.
*      
*      uint8_t tx_dac_chan_xbar[usecase][DAC Datapath(0-3) to be mapped to DAC (0-3)]
*      Each usecase has an Array of depth 4, each member value is the DAC MAIN DP to be routed
*      where index 0 = DAC0  index 1 = DAC1 etc

*      For example: ad9081_dac_chan_xbar[0][1] =AD9081_DAC_DP _3
*      DAC Datapath 3 is routed to DAC 1
*      
*    
*      
*/

#define tx_if_freq 1010e6
#define rx_if_freq 1000e6
//#define if_freq 10e6

uint8_t tx_dac_chan_xbar[][4] = { /* dac0, dac1, dac2, dac3 */
    { AD9081_DAC_CH_0,  AD9081_DAC_CH_1, AD9081_DAC_CH_2,  AD9081_DAC_CH_3 },
	{ AD9081_DAC_CH_0,  AD9081_DAC_CH_1, AD9081_DAC_CH_2,  AD9081_DAC_CH_3 },
	{ AD9081_DAC_CH_0,  AD9081_DAC_CH_1, AD9081_DAC_CH_2,  AD9081_DAC_CH_3 },
	{ AD9081_DAC_CH_0,  AD9081_DAC_CH_1, AD9081_DAC_CH_2,  AD9081_DAC_CH_3 },
};

int64_t tx_main_shift[][4] = { /* dac0, dac1, dac2, dac3 */
    { tx_if_freq,    tx_if_freq,    tx_if_freq,    tx_if_freq    }, /* uc13*/
    { tx_if_freq,    tx_if_freq,    tx_if_freq,    tx_if_freq    }, /* uc13*/
	{ tx_if_freq,    tx_if_freq,    tx_if_freq,    tx_if_freq    }, /* uc13*/
	{ tx_if_freq,    tx_if_freq,    tx_if_freq,    tx_if_freq    }, /* uc13*/
};

int64_t tx_chan_shift[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
    { 0,         0,        0,         0,        0,         0,        0,         0        }, /* uc13*/
    { 0,         0,        0,         0,        0,         0,        0,         0        }, /* uc13*/
	{ 0,         0,        0,         0,        0,         0,        0,         0        }, /* uc13*/
	{ 0,         0,        0,         0,        0,         0,        0,         0        }, /* uc13*/
};
int8_t  tx_chan_gain[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
    {  0,   0,   0,   0,   0,   0,   0,   0 }, /* uc13*/
    {  0,   0,   0,   0,   0,   0,   0,   0 }, /* uc13*/
	{  0,   0,   0,   0,   0,   0,   0,   0 }, /* uc13*/
	{  0,   0,   0,   0,   0,   0,   0,   0 }, /* uc13*/
};
uint8_t tx_interp[][2] = {
/* {main DUC Interpolation, Channelizer DUC Interpolation} */
    {  12,    1   }, /* uc13*/
    {  12,    1   }, /* uc13*/
	{  8,     3   }, /* uc13*/
	{  12,    2   }, /* uc13*/
};
#endif

/* RX Main Path DDC Enable Configuration */
/* MUX 0 & MUX 1 Settings
 * List the ADC_Coarse DDCs to be mapped to logical ADCs
 * OR�adi_ad9082_adc_coarse_ddc_select_e enumerations to create the list
 * Note all DDC are enabled for all use cases that configure main datapath.
 * Deselect CDDCs and FDDCs to override default Mux3 settings and enable full bandwidth mode
 */
uint8_t rx_cddc_select[] = {
  AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
  AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
  AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
  AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
}; 

/* RX Main Path DDC  NCO Frequency Configuration
 * List the ADC_Coarse DDCs desired Frequency Shift
 * Each usecase has an Array of depth 4, each member value is the desired frequency shift (MHz)of a Coarse DDC Datapath,
 * where index 0 = Frequency Shift for� Coarse DDC 0, index 1 = Frequency Shift for�Coarse DDC 1 etc
 *
 *   For example: rx_cddc_shift[0][0] = 1842.5e6,
 *   For Use case 0, Frequency Shift for Coarse DDC0 is 1842.5e6MHz
 */
int64_t rx_cddc_shift[][4] = {
 /* {cddc0, cddc1, cddc2, cddc3 }*/
    { rx_if_freq,   rx_if_freq,   rx_if_freq, rx_if_freq}, /* uc13*/
    { rx_if_freq,   rx_if_freq,   rx_if_freq, rx_if_freq}, /* uc13*/
	{ rx_if_freq,   rx_if_freq,   rx_if_freq, rx_if_freq}, /* uc13*/
	{ rx_if_freq,   rx_if_freq,   rx_if_freq, rx_if_freq}, /* uc13*/
};
/* RX Main Path DDC Data Decimation
 * List the ADC_Coarse DDCs desired data decimation
 * Each usecase has an Array of depth 4, each member value is the desired decimation of a Coarse DDC Datapath,
 * where index 0 = Decimation Factor for� Coarse DDC 0, index 1 = decimation Factor for�Coarse DDC 1 etc
 *
 *   For example: rx_cddc_dcm[1][0] =AD9081_CDDC_DCM_2,
 *   For Use case 1, Frequency Factor for Coarse DDC0 is 1
 *   Use adi_ad9082_adc_coarse_ddc_dcm_e to set the decimation setting
 */
uint8_t rx_cddc_dcm[][4] = {
  /*{cddc0, cddc1, cddc2, cddc3} */
		{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
		{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
		{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc13*/
		{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
};
/* RX Main Path DDC Has Optional Complex to Real Convertor
 * rx_cddc_c2r sets the enable for Complex to Real Converter per Main/Coarse DDC
 * Each usecase has an Array of depth 4, each member value is the enable of a Coarse DDC Datapath Complex to Real Converter
 * where index 0 = Enable Complex to Real Convertor for Coarse DDC 0,
 *       index 1 = Enable Complex to Real Convertor for Coarse DDC 1
 *
 *   For example: rx_cddc_c2r[1][0] = 0,
 *   For Use case 1, Complex to Real Converter for Coarse DDC 0 is Disabled
 *
 */
uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
    { 0, 0, 0, 0 }, /* uc13*/
    { 0, 0, 0, 0 }, /* uc13*/
	{ 0, 0, 0, 0 }, /* uc13*/
	{ 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer/Fine DDC Datapath Selection
 * List the ADC Fine DDCs data path for routing Data from Main/ Coarse DDC Datapth to the JESD Tx
 * Each usecase has an Array of depth 1, each member value is the masked list of Fine DDCs to be selected
 * Note Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC0- Fine DDC3 datapaths and
 *      Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC4- Fine DDC6 datapaths
 * For example: rx_fddc_select[3] = AD9081_ADC_FDDC_0 |AD9081_ADC_FDDC_1,
 *   For Use case 3,  Fine DDC 0 and Fine DDC 1 are enabled
 * Use adi_ad9082_adc_fine_ddc_select_e to create the list of fine DDCs to be enabled
 * Note: Based on the input from the user, will apply a recommended muxing from CDDC to FDDC,
 *         An Error will be returned if the muxing is not supported for that devices,
 * Note: If Fine DDC Decimation Factor is set to 1, Fine DDC in the Channel will be disabled
 *
 */
uint8_t rx_fddc_select[] = {
    AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
    AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
	AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
	AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
};
/* RX Channelizer Path DDC  NCO Frequency Configuration
 * List the ADC_Fine DDCs desired Frequency Shift
 * Each usecase has an Array of depth 8, each member value is the desired frequency shift (MHz)of a Fine DDC Datapath,
 * where index 0 = Frequency Shift for� Fine DDC 0, index 1 = Frequency Shift for�Fine DDC 1 etc
 *
 *   For example: rx_fddc_shift[0][0] = 1842.5e6,
 *   For Use case 0, Frequency Shift for Fine DDC0 is 1842.5e6MHz
 */
int64_t rx_fddc_shift[][8] = {
/* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
    { 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
    { 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
	{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
	{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer Data Decimation
 * List the ADC Fine DDCs desired data decimation
 * Each usecase has an Array of depth 8, each member value is the desired decimation of a Fine DDC Datapath,
 * where index 0 = Decimation factor for� Fine DDC 0, index 1 = decimation factor for�Fine DDC 1 etc
 * Note where No Fine DDC Decimation is required (bypassed), Decimation factor is set to 1,AD9081_FDDC_DCM_1
 *
 *   For example: rx_fddc_dcm[1][0] =AD9081_FDDC_DCM_4,
 *   For Use case 1, Decimation Factor for FineDDC0 is 4
 *   Use adi_ad9082_adc_fine_ddc_dcm_e to set the decimation setting
 */
uint8_t rx_fddc_dcm[][8] = { /* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
    { AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
    { AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
	{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
	{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0 }, /* uc13*/
};
uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */

/* Link Settings */
/* Rx Channelizer Virtual Converter Mapping
*  Maps the output of a Fine DDC Data Format O/P to a JESD TX virtual converter
*  Refer to Mux 4 in the Rx Digital Datapath section of the System Developer Userguide
*
*  adi_ad9082_adc_fine_ddc_converter_e enerates the Fine DCC I & Q Outputs
*  Each virtual converter in the JESD TX link must be assigned a source data,  Fine DDC X I or Q
*  Note this should be set carefully and reflect the Fine DDC selected in rx_fddc_select and also JESD TX Configuration
*
*  Each usecase has an Array of depth 2, each member a list of the source of data for the virtual converter for the JESD TX Link
*  where index 0 = Sources of Data for JESD TX Link 0
*   where index 1 = Sources of Data for JESD TX Link 1
*
*   For example: For Use Case 29 with is a Dual link JESD Mode with M =4, we specify the I & Q source for each virtual Converter
*    jtx_conv_sel[28][0]={AD9081_FDDC_0_I,AD9081_FDDC_0_Q,AD9081_FDDC_1_I,AD9081_FDDC_1_Q }
*    jtx_conv_sel[28][1]={AD9081_FDDC_4_I,AD9081_FDDC_4_Q,AD9081_FDDC_5_I,AD9081_FDDC_5_Q }
*/
adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
    { { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
    { { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
	{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
	{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
};

/* Total Decimation Settings */
/* The total decimation is used to calculate lane rate for each link which in
*  turn is used to determine FPGA clock sources and line rates for JESD204B
*
*  Each usecase has an Array of depth 2,
*   where index 0 = Total decimation for link 0
*   where index 1 = Total decimation for link 1
*
*  For example: For Use Case 3 with is a Dual link JESD Mode, total decimation for each link
*   jtx_chip_dcm[3][0]= 8
*   jtx_chip_dcm[3][1]= 8
*/
uint8_t jtx_chip_dcm[][2] = {
    { 4 }, /* uc13.link0 */
	{ 4 }, /* uc13.link0 */
	{ 6 }, /* uc13.link0 */
	{ 8 }, /* uc13.link0 */
};

adi_cms_jesd_param_t jrx_param[] = {
        /*L   F   M   S   HD  K    N    N'   CF  CS DID BID LID  SC SCR Dual V  Mode */
		{ 8,  2,  8,  1,  0,  128, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  2,  15 }, /* uc13: txmode = 378 */
		{ 8,  2,  8,  1,  0,  128, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  2,  15 }, /* uc13: txmode = 378 */
		{ 8,  2,  8,  1,  0,   32, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  1,  15 }, // 204B
		{ 8,  2,  8,  1,  0,   32, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  1,  15 }, // 204B
};
adi_cms_jesd_param_t jtx_param[][2] = {
      /*L   F   M   S   HD  K    N    N'   CF  CS DID BID LID  SC SCR Dual V  Mode C2R ModeS */
    { { 8,  2,  8,  1,  0,  128, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  2,  16,  0,  0 } }, /* uc13: rxmode = 227, link0 */
    { { 8,  2,  8,  1,  0,  128, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  2,  16,  0,  0 } }, /* uc13: rxmode = 227, link0 */
	{ { 8,  2,  8,  1,  0,   32, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  1,  16,  0,  0 } }, // 204B
	{ { 8,  2,  8,  1,  0,   32, 16,  16,  0,  0,  0,  0,  0,  1,  1,  0,  1,  16,  0,  0 } }, // 204B
//	{ { 8,  4,  8,  2,  0,   32, 16,  16,  0,  0,  0,  0,  0,  0,  1,  0,  1,  16,  0,  1 } }, // 204B
};

