#-------------------------------------------
# Config
#-------------------------------------------
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

#-------------------------------------------
# Register False Paths
#-------------------------------------------
set_false_path -from [get_cells util_reg_i/reg_*]
set_false_path -from [get_cells timing_engine_i/reg_*]
set_false_path -from [get_cells timing_engine_i/genblk1*reg_*]
set_false_path -from [get_cells timing_engine_i/system_time_start_of_cpi*]
set_false_path -from [get_cells *digital_rx_chain_i/reg_*]
set_false_path -from [get_cells waveform_gen_i/reg_*]

#-------------------------------------------
# Clocks
#-------------------------------------------
set_property PACKAGE_PIN AK17 [get_ports clk_200_p]
set_property PACKAGE_PIN AK16 [get_ports clk_200_n]
#create_clock -period 5.000 -name clk_200 [get_ports clk_200_p]

set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_n]

#set_property PACKAGE_PIN AF6 [get_ports clk_125_p]
#set_property PACKAGE_PIN AF5 [get_ports clk_125_n]
#create_clock -period 8.000 -name clk_125 [get_ports clk_125_p]

# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_p]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_n]

#-------------------------------------------
# I2C
#-------------------------------------------
set_property PACKAGE_PIN P24 [get_ports i2c_scl]
set_property PACKAGE_PIN P25 [get_ports i2c_sda]

set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda]

#-------------------------------------------
# RF Attenautors
#-------------------------------------------
# FMC2
#set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
#set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
#set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
#set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
#set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
#set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
#set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]

#set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
#set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
#set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
#set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
#set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
#set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
#set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]

#set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
#set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
#set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
#set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
#set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
#set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
#set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]

# FMC1
set_property PACKAGE_PIN AE28 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN AB34 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN AA34 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN AC34 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN AF34 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN AE33 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN AD34 [get_ports txlo_drv_en]

set_property PACKAGE_PIN AF33 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN AG30 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN AF30 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN U21 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AB20 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AA20 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN U22 [get_ports rx0_lna_en]

set_property PACKAGE_PIN AC28 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN AE30 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN AD29 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN AC33 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN AF32 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN AE32 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN AD33 [get_ports rx1_lna_en]

set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports tx1_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports tx1_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports tx1_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports txlo_drv_en]

set_property IOSTANDARD LVCMOS18 [get_ports rx0_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_if_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_if_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_if_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_lna_en]

set_property IOSTANDARD LVCMOS18 [get_ports rx1_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_if_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_if_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_if_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_lna_en]

#-------------------------------------------
# PPS
#-------------------------------------------
# FMC2
#set_property PACKAGE_PIN H24 [get_ports pps]  
# FMC1
set_property PACKAGE_PIN AF27 [get_ports pps]  
set_property IOSTANDARD LVCMOS18 [get_ports pps]

#-------------------------------------------
# FAN PWM
#-------------------------------------------
set_property PACKAGE_PIN P20 [get_ports fan_pwm]

set_property IOSTANDARD LVCMOS18 [get_ports fan_pwm]

set_property PACKAGE_PIN L17 [get_ports fmc_power_en]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_power_en]

#-------------------------------------------
# LEDs
#-------------------------------------------
set_property PACKAGE_PIN L20 [get_ports {leds[0]}]
set_property PACKAGE_PIN M20 [get_ports {leds[1]}]
set_property PACKAGE_PIN M21 [get_ports {leds[2]}]
set_property PACKAGE_PIN N21 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[*]}]

#-------------------------------------------
# UART
#-------------------------------------------
set_property PACKAGE_PIN N27 [get_ports uart_rxd]
set_property PACKAGE_PIN K22 [get_ports uart_txd]

set_property IOSTANDARD LVCMOS18 [get_ports uart_rxd]
set_property IOSTANDARD LVCMOS18 [get_ports uart_txd]


#-------------------------------------------
# SFP
#-------------------------------------------
set_property PACKAGE_PIN AP2 [get_ports sfp0_rx_p]
set_property PACKAGE_PIN AP1 [get_ports sfp0_rx_n]
set_property PACKAGE_PIN AN4 [get_ports sfp0_tx_p]
set_property PACKAGE_PIN AN3 [get_ports sfp0_tx_n]
set_property PACKAGE_PIN AM2 [get_ports sfp1_rx_p]
set_property PACKAGE_PIN AM1 [get_ports sfp1_rx_n]
set_property PACKAGE_PIN AM6 [get_ports sfp1_tx_p]
set_property PACKAGE_PIN AM5 [get_ports sfp1_tx_n]
set_property PACKAGE_PIN AK2 [get_ports sfp2_rx_p]
set_property PACKAGE_PIN AK1 [get_ports sfp2_rx_n]
set_property PACKAGE_PIN AL4 [get_ports sfp2_tx_p]
set_property PACKAGE_PIN AL3 [get_ports sfp2_tx_n]
set_property PACKAGE_PIN AJ4 [get_ports sfp3_rx_p]
set_property PACKAGE_PIN AJ3 [get_ports sfp3_rx_n]
set_property PACKAGE_PIN AK6 [get_ports sfp3_tx_p]
set_property PACKAGE_PIN AK5 [get_ports sfp3_tx_n]
set_property PACKAGE_PIN AF5 [get_ports sfp_mgt_refclk_0_n]
set_property PACKAGE_PIN AF6 [get_ports sfp_mgt_refclk_0_p]

set_property PACKAGE_PIN AM10 [get_ports sfp0_tx_disable_b]
set_property PACKAGE_PIN AL10 [get_ports sfp1_tx_disable_b]
set_property PACKAGE_PIN AP9 [get_ports sfp2_tx_disable_b]
set_property PACKAGE_PIN AN9 [get_ports sfp3_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp0_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp1_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp2_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp3_tx_disable_b]

set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]
set_output_delay 0.000 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]

#-------------------------------------------
# 1 Gb Ethernet (PHY 2)
#-------------------------------------------
set_property PACKAGE_PIN A23 [get_ports mdc]
set_property PACKAGE_PIN A22 [get_ports mdio]
set_property PACKAGE_PIN H22 [get_ports phy_rst_n]
set_property PACKAGE_PIN D23 [get_ports rgmii_rxc]
set_property PACKAGE_PIN A29 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN B29 [get_ports {rgmii_rd[0]}]
set_property PACKAGE_PIN A28 [get_ports {rgmii_rd[1]}]
set_property PACKAGE_PIN A27 [get_ports {rgmii_rd[2]}]
set_property PACKAGE_PIN C23 [get_ports {rgmii_rd[3]}]
set_property PACKAGE_PIN B24 [get_ports rgmii_txc]
set_property PACKAGE_PIN A24 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN B20 [get_ports {rgmii_td[0]}]
set_property PACKAGE_PIN A20 [get_ports {rgmii_td[1]}]
set_property PACKAGE_PIN B21 [get_ports {rgmii_td[2]}]
set_property PACKAGE_PIN B22 [get_ports {rgmii_td[3]}]

set_property IOSTANDARD LVCMOS18 [get_ports mdc]
set_property IOSTANDARD LVCMOS18 [get_ports mdio]
set_property IOSTANDARD LVCMOS18 [get_ports phy_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_txc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[3]}]

#-------------------------------------------
# FMC (HPC)
#-------------------------------------------
set_property PACKAGE_PIN C27 [get_ports fmc_spi0_mosi]
set_property PACKAGE_PIN A25 [get_ports fmc_spi0_miso]
set_property PACKAGE_PIN B27 [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN B25 [get_ports fmc_spi0_ss]

set_property PULLUP TRUE [get_ports fmc_spi0_mosi]
set_property PULLUP TRUE [get_ports fmc_spi0_miso]
set_property PULLUP TRUE [get_ports fmc_spi0_sck]

set_property PACKAGE_PIN C22 [get_ports fmc_spi1_mosi]
set_property PACKAGE_PIN D20 [get_ports fmc_spi1_sck]
set_property PACKAGE_PIN C21 [get_ports fmc_spi1_ss]
set_property PACKAGE_PIN F27 [get_ports resetb]

set_property PULLUP TRUE [get_ports fmc_spi1_mosi]
set_property PULLUP TRUE [get_ports fmc_spi1_sck]

set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_miso]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_sck]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_ss]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi1_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi1_sck]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi1_ss]
set_property IOSTANDARD LVCMOS18 [get_ports resetb]

set_property PACKAGE_PIN E25 [get_ports jesd_sysref_p]
set_property PACKAGE_PIN D25 [get_ports jesd_sysref_n]

set_property IOSTANDARD LVDS [get_ports jesd_sysref_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_p]
set_property DQS_BIAS TRUE [get_ports jesd_sysref_n]
create_clock -period 64.000 -name jesd_sysref [get_ports jesd_sysref_p]


set_property PACKAGE_PIN E28 [get_ports jesd_sync_in_p]
set_property PACKAGE_PIN D29 [get_ports jesd_sync_in_n]
set_property IOSTANDARD LVDS [get_ports jesd_sync_in_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sync_in_p]

set_property PACKAGE_PIN E22 [get_ports jesd_sync_out_p]
set_property PACKAGE_PIN E23 [get_ports jesd_sync_out_n]
set_property IOSTANDARD LVDS [get_ports jesd_sync_out_p]

set_property PACKAGE_PIN K5 [get_ports jesd_qpll0_refclk_n]
set_property PACKAGE_PIN K6 [get_ports jesd_qpll0_refclk_p]
create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p]
#create_clock -period 4.0 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p]

#set_property PACKAGE_PIN P5 [get_ports jesd_qpll0_refclk_n]
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]

# Works with the board at my house
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
# Works with the board Chris has (broken USB UART)
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]

set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
#create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]

#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
#set_property PACKAGE_PIN H2 [get_ports {jesd_rxp_in[1]}]
#set_property PACKAGE_PIN K2 [get_ports {jesd_rxp_in[2]}]
#set_property PACKAGE_PIN M2 [get_ports {jesd_rxp_in[3]}]
#set_property PACKAGE_PIN A4 [get_ports {jesd_rxp_in[4]}]
#set_property PACKAGE_PIN B2 [get_ports {jesd_rxp_in[5]}]
#set_property PACKAGE_PIN D2 [get_ports {jesd_rxp_in[6]}]
#set_property PACKAGE_PIN E4 [get_ports {jesd_rxp_in[7]}]


#set_property PACKAGE_PIN G4 [get_ports {jesd_txp_out[0]}]
#set_property PACKAGE_PIN J4 [get_ports {jesd_txp_out[1]}]
#set_property PACKAGE_PIN L4 [get_ports {jesd_txp_out[2]}]
#set_property PACKAGE_PIN N4 [get_ports {jesd_txp_out[3]}]
#set_property PACKAGE_PIN B6 [get_ports {jesd_txp_out[4]}]
#set_property PACKAGE_PIN C4 [get_ports {jesd_txp_out[5]}]
#set_property PACKAGE_PIN D6 [get_ports {jesd_txp_out[6]}]
#set_property PACKAGE_PIN F6 [get_ports {jesd_txp_out[7]}]


#-------------------------------------------
# DDR
#-------------------------------------------
set_property PACKAGE_PIN AG14 [get_ports {ddr_adr[0]}]
set_property PACKAGE_PIN AF17 [get_ports {ddr_adr[1]}]
set_property PACKAGE_PIN AF15 [get_ports {ddr_adr[2]}]
set_property PACKAGE_PIN AJ14 [get_ports {ddr_adr[3]}]
set_property PACKAGE_PIN AD18 [get_ports {ddr_adr[4]}]
set_property PACKAGE_PIN AG17 [get_ports {ddr_adr[5]}]
set_property PACKAGE_PIN AE17 [get_ports {ddr_adr[6]}]
set_property PACKAGE_PIN AK18 [get_ports {ddr_adr[7]}]
set_property PACKAGE_PIN AD16 [get_ports {ddr_adr[8]}]
set_property PACKAGE_PIN AH18 [get_ports {ddr_adr[9]}]
set_property PACKAGE_PIN AD19 [get_ports {ddr_adr[10]}]
set_property PACKAGE_PIN AD15 [get_ports {ddr_adr[11]}]
set_property PACKAGE_PIN AH16 [get_ports {ddr_adr[12]}]
set_property PACKAGE_PIN AL17 [get_ports {ddr_adr[13]}]
set_property PACKAGE_PIN AL15 [get_ports {ddr_adr[14]}]
set_property PACKAGE_PIN AL19 [get_ports {ddr_adr[15]}]
set_property PACKAGE_PIN AM19 [get_ports {ddr_adr[16]}]

set_property PACKAGE_PIN AG15 [get_ports {ddr_ba[0]}]
set_property PACKAGE_PIN AL18 [get_ports {ddr_ba[1]}]
set_property PACKAGE_PIN AJ15 [get_ports {ddr_bg[0]}]

set_property PACKAGE_PIN AE16 [get_ports {ddr_ck_t[0]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr_ck_c[0]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr_cs_n[0]}]

set_property PACKAGE_PIN AJ16 [get_ports {ddr_cke[0]}]
set_property PACKAGE_PIN AG19 [get_ports {ddr_odt[0]}]
set_property PACKAGE_PIN AF18 [get_ports ddr_act_n]

set_property PACKAGE_PIN AG16 [get_ports ddr_reset_n]

set_property PACKAGE_PIN AN34 [get_ports {ddr_dqs_t[7]}]
set_property PACKAGE_PIN AP34 [get_ports {ddr_dqs_c[7]}]
set_property PACKAGE_PIN AL32 [get_ports {ddr_dm_n[7]}]
set_property PACKAGE_PIN AN31 [get_ports {ddr_dq[56]}]
set_property PACKAGE_PIN AL34 [get_ports {ddr_dq[57]}]
set_property PACKAGE_PIN AN32 [get_ports {ddr_dq[58]}]
set_property PACKAGE_PIN AN33 [get_ports {ddr_dq[59]}]
set_property PACKAGE_PIN AM32 [get_ports {ddr_dq[60]}]
set_property PACKAGE_PIN AM34 [get_ports {ddr_dq[61]}]
set_property PACKAGE_PIN AP31 [get_ports {ddr_dq[62]}]
set_property PACKAGE_PIN AP33 [get_ports {ddr_dq[63]}]

set_property PACKAGE_PIN AH33 [get_ports {ddr_dqs_t[6]}]
set_property PACKAGE_PIN AJ33 [get_ports {ddr_dqs_c[6]}]
set_property PACKAGE_PIN AJ29 [get_ports {ddr_dm_n[6]}]
set_property PACKAGE_PIN AK31 [get_ports {ddr_dq[48]}]
set_property PACKAGE_PIN AH34 [get_ports {ddr_dq[49]}]
set_property PACKAGE_PIN AK32 [get_ports {ddr_dq[50]}]
set_property PACKAGE_PIN AJ31 [get_ports {ddr_dq[51]}]
set_property PACKAGE_PIN AJ30 [get_ports {ddr_dq[52]}]
set_property PACKAGE_PIN AH31 [get_ports {ddr_dq[53]}]
set_property PACKAGE_PIN AJ34 [get_ports {ddr_dq[54]}]
set_property PACKAGE_PIN AH32 [get_ports {ddr_dq[55]}]

set_property PACKAGE_PIN AN29 [get_ports {ddr_dqs_t[5]}]
set_property PACKAGE_PIN AP30 [get_ports {ddr_dqs_c[5]}]
set_property PACKAGE_PIN AN26 [get_ports {ddr_dm_n[5]}]
set_property PACKAGE_PIN AN28 [get_ports {ddr_dq[40]}]
set_property PACKAGE_PIN AM30 [get_ports {ddr_dq[41]}]
set_property PACKAGE_PIN AP28 [get_ports {ddr_dq[42]}]
set_property PACKAGE_PIN AM29 [get_ports {ddr_dq[43]}]
set_property PACKAGE_PIN AN27 [get_ports {ddr_dq[44]}]
set_property PACKAGE_PIN AL30 [get_ports {ddr_dq[45]}]
set_property PACKAGE_PIN AL29 [get_ports {ddr_dq[46]}]
set_property PACKAGE_PIN AP29 [get_ports {ddr_dq[47]}]

set_property PACKAGE_PIN AL27 [get_ports {ddr_dqs_t[4]}]
set_property PACKAGE_PIN AL28 [get_ports {ddr_dqs_c[4]}]
set_property PACKAGE_PIN AH26 [get_ports {ddr_dm_n[4]}]
set_property PACKAGE_PIN AM26 [get_ports {ddr_dq[32]}]
set_property PACKAGE_PIN AJ28 [get_ports {ddr_dq[33]}]
set_property PACKAGE_PIN AM27 [get_ports {ddr_dq[34]}]
set_property PACKAGE_PIN AK28 [get_ports {ddr_dq[35]}]
set_property PACKAGE_PIN AH27 [get_ports {ddr_dq[36]}]
set_property PACKAGE_PIN AH28 [get_ports {ddr_dq[37]}]
set_property PACKAGE_PIN AK26 [get_ports {ddr_dq[38]}]
set_property PACKAGE_PIN AK27 [get_ports {ddr_dq[39]}]

set_property PACKAGE_PIN AP20 [get_ports {ddr_dqs_t[3]}]
set_property PACKAGE_PIN AP21 [get_ports {ddr_dqs_c[3]}]
set_property PACKAGE_PIN AM21 [get_ports {ddr_dm_n[3]}]
set_property PACKAGE_PIN AM22 [get_ports {ddr_dq[24]}]
set_property PACKAGE_PIN AP24 [get_ports {ddr_dq[25]}]
set_property PACKAGE_PIN AN22 [get_ports {ddr_dq[26]}]
set_property PACKAGE_PIN AN24 [get_ports {ddr_dq[27]}]
set_property PACKAGE_PIN AN23 [get_ports {ddr_dq[28]}]
set_property PACKAGE_PIN AP25 [get_ports {ddr_dq[29]}]
set_property PACKAGE_PIN AP23 [get_ports {ddr_dq[30]}]
set_property PACKAGE_PIN AM24 [get_ports {ddr_dq[31]}]

set_property PACKAGE_PIN AJ20 [get_ports {ddr_dqs_t[2]}]
set_property PACKAGE_PIN AK20 [get_ports {ddr_dqs_c[2]}]
set_property PACKAGE_PIN AJ21 [get_ports {ddr_dm_n[2]}]
set_property PACKAGE_PIN AK22 [get_ports {ddr_dq[16]}]
set_property PACKAGE_PIN AL22 [get_ports {ddr_dq[17]}]
set_property PACKAGE_PIN AM20 [get_ports {ddr_dq[18]}]
set_property PACKAGE_PIN AL23 [get_ports {ddr_dq[19]}]
set_property PACKAGE_PIN AK23 [get_ports {ddr_dq[20]}]
set_property PACKAGE_PIN AL25 [get_ports {ddr_dq[21]}]
set_property PACKAGE_PIN AL20 [get_ports {ddr_dq[22]}]
set_property PACKAGE_PIN AL24 [get_ports {ddr_dq[23]}]

set_property PACKAGE_PIN AH24 [get_ports {ddr_dqs_t[1]}]
set_property PACKAGE_PIN AJ25 [get_ports {ddr_dqs_c[1]}]
set_property PACKAGE_PIN AE25 [get_ports {ddr_dm_n[1]}]
set_property PACKAGE_PIN AF24 [get_ports {ddr_dq[8]}]
set_property PACKAGE_PIN AJ23 [get_ports {ddr_dq[9]}]
set_property PACKAGE_PIN AF23 [get_ports {ddr_dq[10]}]
set_property PACKAGE_PIN AH23 [get_ports {ddr_dq[11]}]
set_property PACKAGE_PIN AG25 [get_ports {ddr_dq[12]}]
set_property PACKAGE_PIN AJ24 [get_ports {ddr_dq[13]}]
set_property PACKAGE_PIN AG24 [get_ports {ddr_dq[14]}]
set_property PACKAGE_PIN AH22 [get_ports {ddr_dq[15]}]

set_property PACKAGE_PIN AG21 [get_ports {ddr_dqs_t[0]}]
set_property PACKAGE_PIN AH21 [get_ports {ddr_dqs_c[0]}]
set_property PACKAGE_PIN AD21 [get_ports {ddr_dm_n[0]}]
set_property PACKAGE_PIN AE20 [get_ports {ddr_dq[0]}]
set_property PACKAGE_PIN AG20 [get_ports {ddr_dq[1]}]
set_property PACKAGE_PIN AF20 [get_ports {ddr_dq[2]}]
set_property PACKAGE_PIN AE22 [get_ports {ddr_dq[3]}]
set_property PACKAGE_PIN AD20 [get_ports {ddr_dq[4]}]
set_property PACKAGE_PIN AG22 [get_ports {ddr_dq[5]}]
set_property PACKAGE_PIN AF22 [get_ports {ddr_dq[6]}]
set_property PACKAGE_PIN AE23 [get_ports {ddr_dq[7]}]



