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            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
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            "DIN": [ { "physical_name": "dina" } ],
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            "WE": [ { "physical_name": "wea" } ]
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        "BRAM_PORTB": {
          "vlnv": "xilinx.com:interface:bram:1.0",
          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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          },
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            "DIN": [ { "physical_name": "dinb" } ],
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            "EN": [ { "physical_name": "enb" } ],
            "WE": [ { "physical_name": "web" } ]
          }
        }
      },
      "memory_maps": {
        "S_1": {
          "address_blocks": {
            "Mem0": {
              "base_address": "0",
              "range": "4096",
              "usage": "memory",
              "access": "read-write",
              "parameters": {
                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
              }
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          }
        }
      }
    }
  }
}