
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2022.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2025 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT 

* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xspi.h"

/*
* The configuration table for devices
*/

XSpi_Config XSpi_ConfigTable[] =
{
	{
		XPAR_SPI_0_DEVICE_ID,
		XPAR_SPI_0_BASEADDR,
		XPAR_SPI_0_FIFO_EXIST,
		XPAR_SPI_0_SPI_SLAVE_ONLY,
		XPAR_SPI_0_NUM_SS_BITS,
		XPAR_SPI_0_NUM_TRANSFER_BITS,
		XPAR_SPI_0_SPI_MODE,
		XPAR_SPI_0_TYPE_OF_AXI4_INTERFACE,
		XPAR_SPI_0_AXI4_BASEADDR,
		XPAR_SPI_0_XIP_MODE,
		XPAR_SPI_0_USE_STARTUP,
		XPAR_SPI_0_FIFO_DEPTH
	},
	{
		XPAR_SPI_1_DEVICE_ID,
		XPAR_SPI_1_BASEADDR,
		XPAR_SPI_1_FIFO_EXIST,
		XPAR_SPI_1_SPI_SLAVE_ONLY,
		XPAR_SPI_1_NUM_SS_BITS,
		XPAR_SPI_1_NUM_TRANSFER_BITS,
		XPAR_SPI_1_SPI_MODE,
		XPAR_SPI_1_TYPE_OF_AXI4_INTERFACE,
		XPAR_SPI_1_AXI4_BASEADDR,
		XPAR_SPI_1_XIP_MODE,
		XPAR_SPI_1_USE_STARTUP,
		XPAR_SPI_1_FIFO_DEPTH
	},
	{
		XPAR_SPI_2_DEVICE_ID,
		XPAR_SPI_2_BASEADDR,
		XPAR_SPI_2_FIFO_EXIST,
		XPAR_SPI_2_SPI_SLAVE_ONLY,
		XPAR_SPI_2_NUM_SS_BITS,
		XPAR_SPI_2_NUM_TRANSFER_BITS,
		XPAR_SPI_2_SPI_MODE,
		XPAR_SPI_2_TYPE_OF_AXI4_INTERFACE,
		XPAR_SPI_2_AXI4_BASEADDR,
		XPAR_SPI_2_XIP_MODE,
		XPAR_SPI_2_USE_STARTUP,
		XPAR_SPI_2_FIFO_DEPTH
	}
};

