/*******************************************************************************
* Copyright (c) 2018 - 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/


#ifndef __XLPD_XIOU_SLCR_H__
#define __XLPD_XIOU_SLCR_H__


#ifdef __cplusplus
extern "C" {
#endif

/**
 *@cond nocomments
 */

/**
 * XlpdXiouSlcr Base Address
 */
#define XLPD_XIOU_SLCR_BASEADDR      0xFF080000UL

/**
 * Register: XlpdXiouSlcrMioPin0
 */
#define XLPD_XIOU_SLCR_MIO_PIN_0    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000000UL )
#define XLPD_XIOU_SLCR_MIO_PIN_0_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin1
 */
#define XLPD_XIOU_SLCR_MIO_PIN_1    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000004UL )
#define XLPD_XIOU_SLCR_MIO_PIN_1_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin2
 */
#define XLPD_XIOU_SLCR_MIO_PIN_2    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000008UL )
#define XLPD_XIOU_SLCR_MIO_PIN_2_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin3
 */
#define XLPD_XIOU_SLCR_MIO_PIN_3    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000000CUL )
#define XLPD_XIOU_SLCR_MIO_PIN_3_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin4
 */
#define XLPD_XIOU_SLCR_MIO_PIN_4    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000010UL )
#define XLPD_XIOU_SLCR_MIO_PIN_4_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin5
 */
#define XLPD_XIOU_SLCR_MIO_PIN_5    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000014UL )
#define XLPD_XIOU_SLCR_MIO_PIN_5_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin6
 */
#define XLPD_XIOU_SLCR_MIO_PIN_6    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000018UL )
#define XLPD_XIOU_SLCR_MIO_PIN_6_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin7
 */
#define XLPD_XIOU_SLCR_MIO_PIN_7    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000001CUL )
#define XLPD_XIOU_SLCR_MIO_PIN_7_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin8
 */
#define XLPD_XIOU_SLCR_MIO_PIN_8    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000020UL )
#define XLPD_XIOU_SLCR_MIO_PIN_8_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin9
 */
#define XLPD_XIOU_SLCR_MIO_PIN_9    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000024UL )
#define XLPD_XIOU_SLCR_MIO_PIN_9_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin10
 */
#define XLPD_XIOU_SLCR_MIO_PIN_10    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000028UL )
#define XLPD_XIOU_SLCR_MIO_PIN_10_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin11
 */
#define XLPD_XIOU_SLCR_MIO_PIN_11    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000002CUL )
#define XLPD_XIOU_SLCR_MIO_PIN_11_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin12
 */
#define XLPD_XIOU_SLCR_MIO_PIN_12    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000030UL )
#define XLPD_XIOU_SLCR_MIO_PIN_12_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin13
 */
#define XLPD_XIOU_SLCR_MIO_PIN_13    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000034UL )
#define XLPD_XIOU_SLCR_MIO_PIN_13_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin14
 */
#define XLPD_XIOU_SLCR_MIO_PIN_14    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000038UL )
#define XLPD_XIOU_SLCR_MIO_PIN_14_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin15
 */
#define XLPD_XIOU_SLCR_MIO_PIN_15    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000003CUL )
#define XLPD_XIOU_SLCR_MIO_PIN_15_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin16
 */
#define XLPD_XIOU_SLCR_MIO_PIN_16    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000040UL )
#define XLPD_XIOU_SLCR_MIO_PIN_16_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin17
 */
#define XLPD_XIOU_SLCR_MIO_PIN_17    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000044UL )
#define XLPD_XIOU_SLCR_MIO_PIN_17_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin18
 */
#define XLPD_XIOU_SLCR_MIO_PIN_18    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000048UL )
#define XLPD_XIOU_SLCR_MIO_PIN_18_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin19
 */
#define XLPD_XIOU_SLCR_MIO_PIN_19    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000004CUL )
#define XLPD_XIOU_SLCR_MIO_PIN_19_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin20
 */
#define XLPD_XIOU_SLCR_MIO_PIN_20    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000050UL )
#define XLPD_XIOU_SLCR_MIO_PIN_20_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin21
 */
#define XLPD_XIOU_SLCR_MIO_PIN_21    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000054UL )
#define XLPD_XIOU_SLCR_MIO_PIN_21_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin22
 */
#define XLPD_XIOU_SLCR_MIO_PIN_22    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000058UL )
#define XLPD_XIOU_SLCR_MIO_PIN_22_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin23
 */
#define XLPD_XIOU_SLCR_MIO_PIN_23    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000005CUL )
#define XLPD_XIOU_SLCR_MIO_PIN_23_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin24
 */
#define XLPD_XIOU_SLCR_MIO_PIN_24    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000060UL )
#define XLPD_XIOU_SLCR_MIO_PIN_24_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioPin25
 */
#define XLPD_XIOU_SLCR_MIO_PIN_25    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000064UL )
#define XLPD_XIOU_SLCR_MIO_PIN_25_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK    0x00000380UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK    0x00000060UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK    0x00000018UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK    0x00000006UL
#define XLPD_XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2EnRx
 */
#define XLPD_XIOU_SLCR_BNK2_EN_RX    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000100UL )
#define XLPD_XIOU_SLCR_BNK2_EN_RX_RSTVAL   0x03ffffffUL

#define XLPD_XIOU_SLCR_BNK2_EN_RX_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_RX_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_EN_RX_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_EN_RX_DEFVAL  0x3ffffffUL

/**
 * Register: XlpdXiouSlcrBnk2SelRx0
 */
#define XLPD_XIOU_SLCR_BNK2_SEL_RX0    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000104UL )
#define XLPD_XIOU_SLCR_BNK2_SEL_RX0_RSTVAL   0xffffffffUL

#define XLPD_XIOU_SLCR_BNK2_SEL_RX0_RX_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SEL_RX0_RX_WIDTH   32UL
#define XLPD_XIOU_SLCR_BNK2_SEL_RX0_RX_MASK    0xffffffffUL
#define XLPD_XIOU_SLCR_BNK2_SEL_RX0_RX_DEFVAL  0xffffffffUL

/**
 * Register: XlpdXiouSlcrBnk2SelRx1
 */
#define XLPD_XIOU_SLCR_BNK2_SEL_RX1    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000108UL )
#define XLPD_XIOU_SLCR_BNK2_SEL_RX1_RSTVAL   0x000fffffUL

#define XLPD_XIOU_SLCR_BNK2_SEL_RX1_RX_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SEL_RX1_RX_WIDTH   20UL
#define XLPD_XIOU_SLCR_BNK2_SEL_RX1_RX_MASK    0x000fffffUL
#define XLPD_XIOU_SLCR_BNK2_SEL_RX1_RX_DEFVAL  0xfffffUL

/**
 * Register: XlpdXiouSlcrBnk2EnRxSchmittHyst
 */
#define XLPD_XIOU_SLCR_BNK2_EN_RX_SCHMITT_HYST    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000010CUL )
#define XLPD_XIOU_SLCR_BNK2_EN_RX_SCHMITT_HYST_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_RX_SCHMITT_HYST_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_RX_SCHMITT_HYST_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_EN_RX_SCHMITT_HYST_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_EN_RX_SCHMITT_HYST_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2EnWkPd
 */
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PD    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000110UL )
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PD_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_WK_PD_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PD_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PD_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PD_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2EnWkPu
 */
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PU    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000114UL )
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PU_RSTVAL   0x03ffffffUL

#define XLPD_XIOU_SLCR_BNK2_EN_WK_PU_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PU_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PU_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_EN_WK_PU_DEFVAL  0x3ffffffUL

/**
 * Register: XlpdXiouSlcrBnk2SelDrv0
 */
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV0    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000118UL )
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV0_RSTVAL   0xaaaaaaaaUL

#define XLPD_XIOU_SLCR_BNK2_SEL_DRV0_DRV_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV0_DRV_WIDTH   32UL
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV0_DRV_MASK    0xffffffffUL
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV0_DRV_DEFVAL  0xaaaaaaaaUL

/**
 * Register: XlpdXiouSlcrBnk2SelDrv1
 */
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV1    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000011CUL )
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV1_RSTVAL   0x000aaaaaUL

#define XLPD_XIOU_SLCR_BNK2_SEL_DRV1_DRV_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV1_DRV_WIDTH   20UL
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV1_DRV_MASK    0x000fffffUL
#define XLPD_XIOU_SLCR_BNK2_SEL_DRV1_DRV_DEFVAL  0xaaaaaUL

/**
 * Register: XlpdXiouSlcrBnk2SelSlew
 */
#define XLPD_XIOU_SLCR_BNK2_SEL_SLEW    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000120UL )
#define XLPD_XIOU_SLCR_BNK2_SEL_SLEW_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_SEL_SLEW_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SEL_SLEW_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_SEL_SLEW_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_SEL_SLEW_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2EnDftOptInv
 */
#define XLPD_XIOU_SLCR_BNK2_EN_DFT_OPT_INV    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000124UL )
#define XLPD_XIOU_SLCR_BNK2_EN_DFT_OPT_INV_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_DFT_OPT_INV_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_DFT_OPT_INV_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_EN_DFT_OPT_INV_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_EN_DFT_OPT_INV_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2EnPad2padLpbck
 */
#define XLPD_XIOU_SLCR_BNK2_EN_PAD2PAD_LPBCK    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000128UL )
#define XLPD_XIOU_SLCR_BNK2_EN_PAD2PAD_LPBCK_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_PAD2PAD_LPBCK_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_PAD2PAD_LPBCK_WIDTH   13UL
#define XLPD_XIOU_SLCR_BNK2_EN_PAD2PAD_LPBCK_MASK    0x00001fffUL
#define XLPD_XIOU_SLCR_BNK2_EN_PAD2PAD_LPBCK_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2RxSpr0
 */
#define XLPD_XIOU_SLCR_BNK2_RX_SPR0    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000012CUL )
#define XLPD_XIOU_SLCR_BNK2_RX_SPR0_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_RX_SPR0_SPR_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_RX_SPR0_SPR_WIDTH   32UL
#define XLPD_XIOU_SLCR_BNK2_RX_SPR0_SPR_MASK    0xffffffffUL
#define XLPD_XIOU_SLCR_BNK2_RX_SPR0_SPR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2RxSpr1
 */
#define XLPD_XIOU_SLCR_BNK2_RX_SPR1    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000130UL )
#define XLPD_XIOU_SLCR_BNK2_RX_SPR1_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_RX_SPR1_SPR_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_RX_SPR1_SPR_WIDTH   20UL
#define XLPD_XIOU_SLCR_BNK2_RX_SPR1_SPR_MASK    0x000fffffUL
#define XLPD_XIOU_SLCR_BNK2_RX_SPR1_SPR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2TxSpr0
 */
#define XLPD_XIOU_SLCR_BNK2_TX_SPR0    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000134UL )
#define XLPD_XIOU_SLCR_BNK2_TX_SPR0_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_TX_SPR0_SPR_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_TX_SPR0_SPR_WIDTH   32UL
#define XLPD_XIOU_SLCR_BNK2_TX_SPR0_SPR_MASK    0xffffffffUL
#define XLPD_XIOU_SLCR_BNK2_TX_SPR0_SPR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2TxSpr1
 */
#define XLPD_XIOU_SLCR_BNK2_TX_SPR1    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000138UL )
#define XLPD_XIOU_SLCR_BNK2_TX_SPR1_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_TX_SPR1_SPR_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_TX_SPR1_SPR_WIDTH   20UL
#define XLPD_XIOU_SLCR_BNK2_TX_SPR1_SPR_MASK    0x000fffffUL
#define XLPD_XIOU_SLCR_BNK2_TX_SPR1_SPR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2SelEn1p8
 */
#define XLPD_XIOU_SLCR_BNK2_SEL_EN1P8    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000013CUL )
#define XLPD_XIOU_SLCR_BNK2_SEL_EN1P8_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_SEL_EN1P8_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SEL_EN1P8_WIDTH   1UL
#define XLPD_XIOU_SLCR_BNK2_SEL_EN1P8_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_BNK2_SEL_EN1P8_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2EnBPorDetect
 */
#define XLPD_XIOU_SLCR_BNK2_EN_B_POR_DETECT    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000140UL )
#define XLPD_XIOU_SLCR_BNK2_EN_B_POR_DETECT_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_B_POR_DETECT_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_B_POR_DETECT_WIDTH   1UL
#define XLPD_XIOU_SLCR_BNK2_EN_B_POR_DETECT_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_BNK2_EN_B_POR_DETECT_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2LpfBypPorDetect
 */
#define XLPD_XIOU_SLCR_BNK2_LPF_BYP_POR_DETECT    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000144UL )
#define XLPD_XIOU_SLCR_BNK2_LPF_BYP_POR_DETECT_RSTVAL   0x00000001UL

#define XLPD_XIOU_SLCR_BNK2_LPF_BYP_POR_DETECT_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_LPF_BYP_POR_DETECT_WIDTH   1UL
#define XLPD_XIOU_SLCR_BNK2_LPF_BYP_POR_DETECT_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_BNK2_LPF_BYP_POR_DETECT_DEFVAL  0x1UL

/**
 * Register: XlpdXiouSlcrBnk2EnLatch
 */
#define XLPD_XIOU_SLCR_BNK2_EN_LATCH    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000148UL )
#define XLPD_XIOU_SLCR_BNK2_EN_LATCH_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_LATCH_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_LATCH_WIDTH   1UL
#define XLPD_XIOU_SLCR_BNK2_EN_LATCH_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_BNK2_EN_LATCH_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2VbgLpfBypB
 */
#define XLPD_XIOU_SLCR_BNK2_VBG_LPF_BYP_B    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000014CUL )
#define XLPD_XIOU_SLCR_BNK2_VBG_LPF_BYP_B_RSTVAL   0x00000001UL

#define XLPD_XIOU_SLCR_BNK2_VBG_LPF_BYP_B_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_VBG_LPF_BYP_B_WIDTH   1UL
#define XLPD_XIOU_SLCR_BNK2_VBG_LPF_BYP_B_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_BNK2_VBG_LPF_BYP_B_DEFVAL  0x1UL

/**
 * Register: XlpdXiouSlcrBnk2EnAmpB
 */
#define XLPD_XIOU_SLCR_BNK2_EN_AMP_B    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000150UL )
#define XLPD_XIOU_SLCR_BNK2_EN_AMP_B_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_AMP_B_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_AMP_B_WIDTH   2UL
#define XLPD_XIOU_SLCR_BNK2_EN_AMP_B_MASK    0x00000003UL
#define XLPD_XIOU_SLCR_BNK2_EN_AMP_B_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2SprBias
 */
#define XLPD_XIOU_SLCR_BNK2_SPR_BIAS    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000154UL )
#define XLPD_XIOU_SLCR_BNK2_SPR_BIAS_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_SPR_BIAS_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SPR_BIAS_WIDTH   4UL
#define XLPD_XIOU_SLCR_BNK2_SPR_BIAS_MASK    0x0000000fUL
#define XLPD_XIOU_SLCR_BNK2_SPR_BIAS_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2DriverBias
 */
#define XLPD_XIOU_SLCR_BNK2_DRIVER_BIAS    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000158UL )
#define XLPD_XIOU_SLCR_BNK2_DRIVER_BIAS_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_DRIVER_BIAS_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_DRIVER_BIAS_WIDTH   15UL
#define XLPD_XIOU_SLCR_BNK2_DRIVER_BIAS_MASK    0x00007fffUL
#define XLPD_XIOU_SLCR_BNK2_DRIVER_BIAS_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2Vmode
 */
#define XLPD_XIOU_SLCR_BNK2_VMODE    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000015CUL )
#define XLPD_XIOU_SLCR_BNK2_VMODE_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_VMODE_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_VMODE_WIDTH   1UL
#define XLPD_XIOU_SLCR_BNK2_VMODE_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_BNK2_VMODE_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2SelAuxIoRx
 */
#define XLPD_XIOU_SLCR_BNK2_SEL_AUX_IO_RX    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000160UL )
#define XLPD_XIOU_SLCR_BNK2_SEL_AUX_IO_RX_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_SEL_AUX_IO_RX_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_SEL_AUX_IO_RX_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_SEL_AUX_IO_RX_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_SEL_AUX_IO_RX_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrBnk2EnTxHsMode
 */
#define XLPD_XIOU_SLCR_BNK2_EN_TX_HS_MODE    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000164UL )
#define XLPD_XIOU_SLCR_BNK2_EN_TX_HS_MODE_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_BNK2_EN_TX_HS_MODE_SHIFT   0UL
#define XLPD_XIOU_SLCR_BNK2_EN_TX_HS_MODE_WIDTH   26UL
#define XLPD_XIOU_SLCR_BNK2_EN_TX_HS_MODE_MASK    0x03ffffffUL
#define XLPD_XIOU_SLCR_BNK2_EN_TX_HS_MODE_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioLpbck
 */
#define XLPD_XIOU_SLCR_MIO_LPBCK    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000200UL )
#define XLPD_XIOU_SLCR_MIO_LPBCK_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_MIO_LPBCK_I2C0_LOOP_I2C1_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_I2C0_LOOP_I2C1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_I2C0_LOOP_I2C1_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_I2C0_LOOP_I2C1_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT   2UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_MIO_LPBCK_SPI0_LOOP_SPI1_SHIFT   0UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_SPI0_LOOP_SPI1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_SPI0_LOOP_SPI1_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_MIO_LPBCK_SPI0_LOOP_SPI1_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioMstTri0
 */
#define XLPD_XIOU_SLCR_MIO_MST_TRI0    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000204UL )
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_RSTVAL   0x03ffffffUL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT   25UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK    0x02000000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT   24UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK    0x01000000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT   23UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK    0x00800000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT   22UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT   21UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK    0x00200000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT   20UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK    0x00100000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT   19UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK    0x00080000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT   18UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK    0x00040000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT   17UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK    0x00020000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT   16UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK    0x00010000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT   15UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK    0x00008000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT   14UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK    0x00004000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT   13UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK    0x00002000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT   12UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK    0x00001000UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT   11UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK    0x00000800UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT   10UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK    0x00000400UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT   9UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK    0x00000200UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT   8UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT   6UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT   4UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK    0x00000010UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT   2UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT   0UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL  0x1UL

/**
 * Register: XlpdXiouSlcrWdtClkSel
 */
#define XLPD_XIOU_SLCR_WDT_CLK_SEL    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000300UL )
#define XLPD_XIOU_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_WDT_CLK_SEL_SHIFT   0UL
#define XLPD_XIOU_SLCR_WDT_CLK_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrCanMioCtrl
 */
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000310UL )
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT   23UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH   1UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK    0x00800000UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT   22UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT   15UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH   7UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK    0x003f8000UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT   8UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH   1UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT   0UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH   7UL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK    0x0000007fUL
#define XLPD_XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrGemClkCtrl
 */
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000320UL )
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT   22UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT   20UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK    0x00300000UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_FIFO_SEL_SHIFT   7UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_FIFO_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_FIFO_SEL_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_FIFO_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_REF_SRC_SEL_SHIFT   6UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_REF_SRC_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_REF_SRC_SEL_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_REF_SRC_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_RX_SRC_SEL_SHIFT   5UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_RX_SRC_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_RX_SRC_SEL_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM1_RX_SRC_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_FIFO_SEL_SHIFT   2UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_FIFO_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_FIFO_SEL_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_FIFO_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_REF_SRC_SEL_SHIFT   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_REF_SRC_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_REF_SRC_SEL_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_REF_SRC_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_RX_SRC_SEL_SHIFT   0UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_RX_SRC_SEL_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_RX_SRC_SEL_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_GEM_CLK_CTRL_GEM0_RX_SRC_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrGem0CoherentCtrl
 */
#define XLPD_XIOU_SLCR_GEM0_COHERENT_CTRL    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000324UL )
#define XLPD_XIOU_SLCR_GEM0_COHERENT_CTRL_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_GEM0_COHERENT_CTRL_AXI_COH_SHIFT   0UL
#define XLPD_XIOU_SLCR_GEM0_COHERENT_CTRL_AXI_COH_WIDTH   4UL
#define XLPD_XIOU_SLCR_GEM0_COHERENT_CTRL_AXI_COH_MASK    0x0000000fUL
#define XLPD_XIOU_SLCR_GEM0_COHERENT_CTRL_AXI_COH_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrGem0InterconnectRoute
 */
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_ROUTE    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000328UL )
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_ROUTE_SHIFT   0UL
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_ROUTE_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_ROUTE_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_ROUTE_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrGem0InterconnectQos
 */
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_QOS    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_QOS_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_QOS_SHIFT   0UL
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_QOS_WIDTH   4UL
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_QOS_MASK    0x0000000fUL
#define XLPD_XIOU_SLCR_GEM0_INTERCONNECT_QOS_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrGem1CoherentCtrl
 */
#define XLPD_XIOU_SLCR_GEM1_COHERENT_CTRL    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000344UL )
#define XLPD_XIOU_SLCR_GEM1_COHERENT_CTRL_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_GEM1_COHERENT_CTRL_AXI_COH_SHIFT   0UL
#define XLPD_XIOU_SLCR_GEM1_COHERENT_CTRL_AXI_COH_WIDTH   4UL
#define XLPD_XIOU_SLCR_GEM1_COHERENT_CTRL_AXI_COH_MASK    0x0000000fUL
#define XLPD_XIOU_SLCR_GEM1_COHERENT_CTRL_AXI_COH_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrGem1InterconnectRoute
 */
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_ROUTE    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000348UL )
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_ROUTE_SHIFT   0UL
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_ROUTE_WIDTH   1UL
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_ROUTE_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_ROUTE_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrGem1InterconnectQos
 */
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_QOS    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_QOS_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_QOS_SHIFT   0UL
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_QOS_WIDTH   4UL
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_QOS_MASK    0x0000000fUL
#define XLPD_XIOU_SLCR_GEM1_INTERCONNECT_QOS_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrTtcApbClk
 */
#define XLPD_XIOU_SLCR_TTC_APB_CLK    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000360UL )
#define XLPD_XIOU_SLCR_TTC_APB_CLK_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT   6UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK    0x000000c0UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT   4UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK    0x00000030UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT   2UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK    0x0000000cUL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT   0UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH   2UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK    0x00000003UL
#define XLPD_XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrMioSel
 */
#define XLPD_XIOU_SLCR_MIO_SEL    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000410UL )
#define XLPD_XIOU_SLCR_MIO_SEL_RSTVAL   0x0003ffffUL

#define XLPD_XIOU_SLCR_MIO_SEL_WWDT1_SHIFT   17UL
#define XLPD_XIOU_SLCR_MIO_SEL_WWDT1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_WWDT1_MASK    0x00020000UL
#define XLPD_XIOU_SLCR_MIO_SEL_WWDT1_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_WWDT0_SHIFT   16UL
#define XLPD_XIOU_SLCR_MIO_SEL_WWDT0_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_WWDT0_MASK    0x00010000UL
#define XLPD_XIOU_SLCR_MIO_SEL_WWDT0_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_I2C1_SHIFT   15UL
#define XLPD_XIOU_SLCR_MIO_SEL_I2C1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_I2C1_MASK    0x00008000UL
#define XLPD_XIOU_SLCR_MIO_SEL_I2C1_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_I2C0_SHIFT   14UL
#define XLPD_XIOU_SLCR_MIO_SEL_I2C0_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_I2C0_MASK    0x00004000UL
#define XLPD_XIOU_SLCR_MIO_SEL_I2C0_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_CAN1_SHIFT   13UL
#define XLPD_XIOU_SLCR_MIO_SEL_CAN1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_CAN1_MASK    0x00002000UL
#define XLPD_XIOU_SLCR_MIO_SEL_CAN1_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_CAN0_SHIFT   12UL
#define XLPD_XIOU_SLCR_MIO_SEL_CAN0_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_CAN0_MASK    0x00001000UL
#define XLPD_XIOU_SLCR_MIO_SEL_CAN0_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_UART1_SHIFT   11UL
#define XLPD_XIOU_SLCR_MIO_SEL_UART1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_UART1_MASK    0x00000800UL
#define XLPD_XIOU_SLCR_MIO_SEL_UART1_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_UART0_SHIFT   10UL
#define XLPD_XIOU_SLCR_MIO_SEL_UART0_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_UART0_MASK    0x00000400UL
#define XLPD_XIOU_SLCR_MIO_SEL_UART0_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_TTC3_SHIFT   9UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC3_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC3_MASK    0x00000200UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC3_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_TTC2_SHIFT   8UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC2_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC2_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC2_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_TTC1_SHIFT   7UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC1_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC1_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_TTC0_SHIFT   6UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC0_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC0_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_MIO_SEL_TTC0_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_SPI1_SHIFT   5UL
#define XLPD_XIOU_SLCR_MIO_SEL_SPI1_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_SPI1_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_MIO_SEL_SPI1_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_SPI0_SHIFT   4UL
#define XLPD_XIOU_SLCR_MIO_SEL_SPI0_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_SPI0_MASK    0x00000010UL
#define XLPD_XIOU_SLCR_MIO_SEL_SPI0_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_GEM1_MDIO_SHIFT   3UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM1_MDIO_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM1_MDIO_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM1_MDIO_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_GEM1RGMII_SHIFT   2UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM1RGMII_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM1RGMII_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM1RGMII_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_GEM0_MDIO_SHIFT   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM0_MDIO_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM0_MDIO_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM0_MDIO_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_MIO_SEL_GEM0RGMII_SHIFT   0UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM0RGMII_WIDTH   1UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM0RGMII_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_MIO_SEL_GEM0RGMII_DEFVAL  0x1UL

/**
 * Register: XlpdXiouSlcrUsbInterconnectRoute
 */
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_ROUTE    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000428UL )
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_USB_INTERCONNECT_ROUTE_SHIFT   0UL
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_ROUTE_WIDTH   1UL
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_ROUTE_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_ROUTE_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrUsbInterconnectQos
 */
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_QOS    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000042CUL )
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_QOS_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_USB_INTERCONNECT_QOS_SHIFT   0UL
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_QOS_WIDTH   4UL
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_QOS_MASK    0x0000000fUL
#define XLPD_XIOU_SLCR_USB_INTERCONNECT_QOS_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrSmidForUsb
 */
#define XLPD_XIOU_SLCR_SMID_FOR_USB    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000430UL )
#define XLPD_XIOU_SLCR_SMID_FOR_USB_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_SMID_FOR_USB_CFG_SHIFT   0UL
#define XLPD_XIOU_SLCR_SMID_FOR_USB_CFG_WIDTH   1UL
#define XLPD_XIOU_SLCR_SMID_FOR_USB_CFG_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_SMID_FOR_USB_CFG_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrCtrl
 */
#define XLPD_XIOU_SLCR_CTRL    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000600UL )
#define XLPD_XIOU_SLCR_CTRL_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
#define XLPD_XIOU_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
#define XLPD_XIOU_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrIsr
 */
#define XLPD_XIOU_SLCR_ISR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000700UL )
#define XLPD_XIOU_SLCR_ISR_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_ISR_ADDR_DECODE_ERR_SHIFT   0UL
#define XLPD_XIOU_SLCR_ISR_ADDR_DECODE_ERR_WIDTH   1UL
#define XLPD_XIOU_SLCR_ISR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrImr
 */
#define XLPD_XIOU_SLCR_IMR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000704UL )
#define XLPD_XIOU_SLCR_IMR_RSTVAL   0x00000001UL

#define XLPD_XIOU_SLCR_IMR_ADDR_DECODE_ERR_SHIFT   0UL
#define XLPD_XIOU_SLCR_IMR_ADDR_DECODE_ERR_WIDTH   1UL
#define XLPD_XIOU_SLCR_IMR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL  0x1UL

/**
 * Register: XlpdXiouSlcrIer
 */
#define XLPD_XIOU_SLCR_IER    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000708UL )
#define XLPD_XIOU_SLCR_IER_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_IER_ADDR_DECODE_ERR_SHIFT   0UL
#define XLPD_XIOU_SLCR_IER_ADDR_DECODE_ERR_WIDTH   1UL
#define XLPD_XIOU_SLCR_IER_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_IER_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrIdr
 */
#define XLPD_XIOU_SLCR_IDR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000070CUL )
#define XLPD_XIOU_SLCR_IDR_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_IDR_ADDR_DECODE_ERR_SHIFT   0UL
#define XLPD_XIOU_SLCR_IDR_ADDR_DECODE_ERR_WIDTH   1UL
#define XLPD_XIOU_SLCR_IDR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrItr
 */
#define XLPD_XIOU_SLCR_ITR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000710UL )
#define XLPD_XIOU_SLCR_ITR_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_ITR_ADDR_DECODE_ERR_SHIFT   0UL
#define XLPD_XIOU_SLCR_ITR_ADDR_DECODE_ERR_WIDTH   1UL
#define XLPD_XIOU_SLCR_ITR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrParityIsr
 */
#define XLPD_XIOU_SLCR_PARITY_ISR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000714UL )
#define XLPD_XIOU_SLCR_PARITY_ISR_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_WWDT0_APB_SHIFT   24UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_WWDT0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_WWDT0_APB_MASK    0x01000000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_WWDT0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XS_SHIFT   23UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XS_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XS_MASK    0x00800000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XS_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XM_SHIFT   22UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XM_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XM_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_XM_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_APB_SHIFT   21UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_APB_MASK    0x00200000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_USB_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART1_APB_SHIFT   20UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART1_APB_MASK    0x00100000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART0_APB_SHIFT   19UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART0_APB_MASK    0x00080000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_UART0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC3_APB_SHIFT   18UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC3_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC3_APB_MASK    0x00040000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC3_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC2_APB_SHIFT   17UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC2_APB_MASK    0x00020000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC1_APB_SHIFT   16UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC1_APB_MASK    0x00010000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC0_APB_SHIFT   15UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC0_APB_MASK    0x00008000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_TTC0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI1_APB_SHIFT   14UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI1_APB_MASK    0x00004000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI0_APB_SHIFT   13UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI0_APB_MASK    0x00002000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SPI0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR2_APB_SHIFT   12UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR2_APB_MASK    0x00001000UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR1_APB_SHIFT   11UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR1_APB_MASK    0x00000800UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_SCNTR1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_SHIFT   10UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000400UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_SHIFT   9UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_MASK    0x00000200UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_APB_SHIFT   8UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_APB_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_APB_SHIFT   7UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_APB_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C1_APB_SHIFT   6UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C1_APB_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C0_APB_SHIFT   5UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C0_APB_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_I2C0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_SHIFT   4UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_MASK    0x00000010UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_SHIFT   3UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM1_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_SHIFT   2UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_GEM0_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN1_APB_SHIFT   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN1_APB_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN0_APB_SHIFT   0UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN0_APB_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_PARITY_ISR_PERR_CAN0_APB_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrParityImr
 */
#define XLPD_XIOU_SLCR_PARITY_IMR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000718UL )
#define XLPD_XIOU_SLCR_PARITY_IMR_RSTVAL   0x01ffffffUL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_WWDT0_APB_SHIFT   24UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_WWDT0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_WWDT0_APB_MASK    0x01000000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_WWDT0_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XS_SHIFT   23UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XS_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XS_MASK    0x00800000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XS_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XM_SHIFT   22UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XM_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XM_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_XM_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_APB_SHIFT   21UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_APB_MASK    0x00200000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_USB_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART1_APB_SHIFT   20UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART1_APB_MASK    0x00100000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART1_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART0_APB_SHIFT   19UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART0_APB_MASK    0x00080000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_UART0_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC3_APB_SHIFT   18UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC3_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC3_APB_MASK    0x00040000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC3_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC2_APB_SHIFT   17UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC2_APB_MASK    0x00020000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC2_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC1_APB_SHIFT   16UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC1_APB_MASK    0x00010000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC1_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC0_APB_SHIFT   15UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC0_APB_MASK    0x00008000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_TTC0_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI1_APB_SHIFT   14UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI1_APB_MASK    0x00004000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI1_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI0_APB_SHIFT   13UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI0_APB_MASK    0x00002000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SPI0_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR2_APB_SHIFT   12UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR2_APB_MASK    0x00001000UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR2_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR1_APB_SHIFT   11UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR1_APB_MASK    0x00000800UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_SCNTR1_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_SHIFT   10UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000400UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_SHIFT   9UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_MASK    0x00000200UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_APB_SHIFT   8UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_APB_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_APB_SHIFT   7UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_APB_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C1_APB_SHIFT   6UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C1_APB_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C1_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C0_APB_SHIFT   5UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C0_APB_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_I2C0_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_SHIFT   4UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_MASK    0x00000010UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_SHIFT   3UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM1_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_SHIFT   2UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_GEM0_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN1_APB_SHIFT   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN1_APB_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN1_APB_DEFVAL  0x1UL

#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN0_APB_SHIFT   0UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN0_APB_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_PARITY_IMR_PERR_CAN0_APB_DEFVAL  0x1UL

/**
 * Register: XlpdXiouSlcrParityIer
 */
#define XLPD_XIOU_SLCR_PARITY_IER    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x0000071CUL )
#define XLPD_XIOU_SLCR_PARITY_IER_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_WWDT0_APB_SHIFT   24UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_WWDT0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_WWDT0_APB_MASK    0x01000000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_WWDT0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XS_SHIFT   23UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XS_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XS_MASK    0x00800000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XS_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XM_SHIFT   22UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XM_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XM_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_XM_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_APB_SHIFT   21UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_APB_MASK    0x00200000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_USB_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART1_APB_SHIFT   20UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART1_APB_MASK    0x00100000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART0_APB_SHIFT   19UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART0_APB_MASK    0x00080000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_UART0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC3_APB_SHIFT   18UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC3_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC3_APB_MASK    0x00040000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC3_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC2_APB_SHIFT   17UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC2_APB_MASK    0x00020000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC1_APB_SHIFT   16UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC1_APB_MASK    0x00010000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC0_APB_SHIFT   15UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC0_APB_MASK    0x00008000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_TTC0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI1_APB_SHIFT   14UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI1_APB_MASK    0x00004000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI0_APB_SHIFT   13UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI0_APB_MASK    0x00002000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SPI0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR2_APB_SHIFT   12UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR2_APB_MASK    0x00001000UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR1_APB_SHIFT   11UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR1_APB_MASK    0x00000800UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_SCNTR1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_SHIFT   10UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000400UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_SHIFT   9UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_MASK    0x00000200UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_APB_SHIFT   8UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_APB_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_APB_SHIFT   7UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_APB_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C1_APB_SHIFT   6UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C1_APB_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C0_APB_SHIFT   5UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C0_APB_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_I2C0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_SHIFT   4UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_MASK    0x00000010UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_SHIFT   3UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM1_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_SHIFT   2UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_GEM0_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN1_APB_SHIFT   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN1_APB_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN0_APB_SHIFT   0UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN0_APB_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_PARITY_IER_PERR_CAN0_APB_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrParityIdr
 */
#define XLPD_XIOU_SLCR_PARITY_IDR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000720UL )
#define XLPD_XIOU_SLCR_PARITY_IDR_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_WWDT0_APB_SHIFT   24UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_WWDT0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_WWDT0_APB_MASK    0x01000000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_WWDT0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XS_SHIFT   23UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XS_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XS_MASK    0x00800000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XS_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XM_SHIFT   22UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XM_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XM_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_XM_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_APB_SHIFT   21UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_APB_MASK    0x00200000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_USB_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART1_APB_SHIFT   20UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART1_APB_MASK    0x00100000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART0_APB_SHIFT   19UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART0_APB_MASK    0x00080000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_UART0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC3_APB_SHIFT   18UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC3_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC3_APB_MASK    0x00040000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC3_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC2_APB_SHIFT   17UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC2_APB_MASK    0x00020000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC1_APB_SHIFT   16UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC1_APB_MASK    0x00010000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC0_APB_SHIFT   15UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC0_APB_MASK    0x00008000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_TTC0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI1_APB_SHIFT   14UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI1_APB_MASK    0x00004000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI0_APB_SHIFT   13UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI0_APB_MASK    0x00002000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SPI0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR2_APB_SHIFT   12UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR2_APB_MASK    0x00001000UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR1_APB_SHIFT   11UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR1_APB_MASK    0x00000800UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_SCNTR1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_SHIFT   10UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000400UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_SHIFT   9UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_MASK    0x00000200UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_APB_SHIFT   8UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_APB_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_APB_SHIFT   7UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_APB_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C1_APB_SHIFT   6UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C1_APB_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C0_APB_SHIFT   5UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C0_APB_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_I2C0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_SHIFT   4UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_MASK    0x00000010UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_SHIFT   3UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM1_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_SHIFT   2UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_GEM0_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN1_APB_SHIFT   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN1_APB_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN0_APB_SHIFT   0UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN0_APB_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_PARITY_IDR_PERR_CAN0_APB_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrParityItr
 */
#define XLPD_XIOU_SLCR_PARITY_ITR    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000724UL )
#define XLPD_XIOU_SLCR_PARITY_ITR_RSTVAL   0x00000000UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_WWDT0_APB_SHIFT   24UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_WWDT0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_WWDT0_APB_MASK    0x01000000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_WWDT0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XS_SHIFT   23UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XS_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XS_MASK    0x00800000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XS_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XM_SHIFT   22UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XM_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XM_MASK    0x00400000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_XM_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_APB_SHIFT   21UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_APB_MASK    0x00200000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_USB_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART1_APB_SHIFT   20UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART1_APB_MASK    0x00100000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART0_APB_SHIFT   19UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART0_APB_MASK    0x00080000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_UART0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC3_APB_SHIFT   18UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC3_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC3_APB_MASK    0x00040000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC3_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC2_APB_SHIFT   17UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC2_APB_MASK    0x00020000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC1_APB_SHIFT   16UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC1_APB_MASK    0x00010000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC0_APB_SHIFT   15UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC0_APB_MASK    0x00008000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_TTC0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI1_APB_SHIFT   14UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI1_APB_MASK    0x00004000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI0_APB_SHIFT   13UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI0_APB_MASK    0x00002000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SPI0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR2_APB_SHIFT   12UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR2_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR2_APB_MASK    0x00001000UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR2_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR1_APB_SHIFT   11UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR1_APB_MASK    0x00000800UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_SCNTR1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_SHIFT   10UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000400UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_SHIFT   9UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_MASK    0x00000200UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_APB_SHIFT   8UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_APB_MASK    0x00000100UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_APB_SHIFT   7UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_APB_MASK    0x00000080UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C1_APB_SHIFT   6UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C1_APB_MASK    0x00000040UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C0_APB_SHIFT   5UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C0_APB_MASK    0x00000020UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_I2C0_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_SHIFT   4UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_MASK    0x00000010UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_SHIFT   3UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_MASK    0x00000008UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM1_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_SHIFT   2UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_MASK    0x00000004UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_GEM0_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN1_APB_SHIFT   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN1_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN1_APB_MASK    0x00000002UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN1_APB_DEFVAL  0x0UL

#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN0_APB_SHIFT   0UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN0_APB_WIDTH   1UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN0_APB_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_PARITY_ITR_PERR_CAN0_APB_DEFVAL  0x0UL

/**
 * Register: XlpdXiouSlcrWprot0
 */
#define XLPD_XIOU_SLCR_WPROT0    ( ( XLPD_XIOU_SLCR_BASEADDR ) + 0x00000728UL )
#define XLPD_XIOU_SLCR_WPROT0_RSTVAL   0x00000001UL

#define XLPD_XIOU_SLCR_WPROT0_ACT_SHIFT   0UL
#define XLPD_XIOU_SLCR_WPROT0_ACT_WIDTH   1UL
#define XLPD_XIOU_SLCR_WPROT0_ACT_MASK    0x00000001UL
#define XLPD_XIOU_SLCR_WPROT0_ACT_DEFVAL  0x1UL

/**
 *@endcond
 */

#ifdef __cplusplus
}
#endif

#endif /* __XLPD_XIOU_SLCR_H__ */
