
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2022.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2025 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT 

* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xaxidma.h"

/*
* The configuration table for devices
*/

XAxiDma_Config XAxiDma_ConfigTable[XPAR_XAXIDMA_NUM_INSTANCES] =
{
	{
		XPAR_AXI_ETHERNET_0_DMA_DEVICE_ID,
		XPAR_AXI_ETHERNET_0_DMA_BASEADDR,
		XPAR_AXI_ETHERNET_0_DMA_SG_INCLUDE_STSCNTRL_STRM,
		XPAR_AXI_ETHERNET_0_DMA_INCLUDE_MM2S,
		XPAR_AXI_ETHERNET_0_DMA_INCLUDE_MM2S_DRE,
		XPAR_AXI_ETHERNET_0_DMA_M_AXI_MM2S_DATA_WIDTH,
		XPAR_AXI_ETHERNET_0_DMA_INCLUDE_S2MM,
		XPAR_AXI_ETHERNET_0_DMA_INCLUDE_S2MM_DRE,
		XPAR_AXI_ETHERNET_0_DMA_M_AXI_S2MM_DATA_WIDTH,
		XPAR_AXI_ETHERNET_0_DMA_INCLUDE_SG,
		XPAR_AXI_ETHERNET_0_DMA_NUM_MM2S_CHANNELS,
		XPAR_AXI_ETHERNET_0_DMA_NUM_S2MM_CHANNELS,
		XPAR_AXI_ETHERNET_0_DMA_MM2S_BURST_SIZE,
		XPAR_AXI_ETHERNET_0_DMA_S2MM_BURST_SIZE,
		XPAR_AXI_ETHERNET_0_DMA_MICRO_DMA,
		XPAR_AXI_ETHERNET_0_DMA_ADDR_WIDTH,
		XPAR_AXI_ETHERNET_0_DMA_SG_LENGTH_WIDTH
	}
};


