#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

/* Definitions for bus frequencies */
#define XPAR_CPU_M_AXI_DP_FREQ_HZ 125000000
/******************************************************************/

/* Canonical definitions for bus frequencies */
/******************************************************************/

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 125000000
#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 125000000

/******************************************************************/


/* Definitions for peripheral MICROBLAZE_0 */
#define XPAR_MICROBLAZE_0_ADDR_SIZE 32
#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 16
#define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_0_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_0_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_0_DADDR_SIZE 32
#define XPAR_MICROBLAZE_0_DATA_SIZE 32
#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 16
#define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 1
#define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 16
#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 8
#define XPAR_MICROBLAZE_0_DC_AXI_MON 0
#define XPAR_MICROBLAZE_0_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_0_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_0_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_0_DEBUG_INTERFACE 0
#define XPAR_MICROBLAZE_0_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_0_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_0_DEBUG_TRACE_ASYNC_RESET 0
#define XPAR_MICROBLAZE_0_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_0_DP_AXI_MON 0
#define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_0_D_AXI 1
#define XPAR_MICROBLAZE_0_D_LMB 1
#define XPAR_MICROBLAZE_0_D_LMB_MON 0
#define XPAR_MICROBLAZE_0_D_LMB_PROTOCOL 0
#define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_0_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_0_ENDIANNESS 1
#define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 1
#define XPAR_MICROBLAZE_0_FREQ 125000000
#define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_0_FSL_LINKS 0
#define XPAR_MICROBLAZE_0_IADDR_SIZE 32
#define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 1
#define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 16
#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 1
#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 8
#define XPAR_MICROBLAZE_0_IC_AXI_MON 0
#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_0_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_0_INSTR_SIZE 32
#define XPAR_MICROBLAZE_0_INTERCONNECT 2
#define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_0_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_0_IP_AXI_MON 0
#define XPAR_MICROBLAZE_0_I_AXI 0
#define XPAR_MICROBLAZE_0_I_LMB 1
#define XPAR_MICROBLAZE_0_I_LMB_MON 0
#define XPAR_MICROBLAZE_0_I_LMB_PROTOCOL 0
#define XPAR_MICROBLAZE_0_LMB_DATA_SIZE 32
#define XPAR_MICROBLAZE_0_LOCKSTEP_MASTER 0
#define XPAR_MICROBLAZE_0_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_MMU_DTLB_SIZE 2
#define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 1
#define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_0_MMU_ZONES 2
#define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_DATA_WIDTH 512
#define XPAR_MICROBLAZE_0_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_0_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_DATA_WIDTH 512
#define XPAR_MICROBLAZE_0_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_0_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_0_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 2
#define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_TRACE_CLK 2
#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_0_OPTIMIZATION 0
#define XPAR_MICROBLAZE_0_PC_WIDTH 32
#define XPAR_MICROBLAZE_0_PIADDR_SIZE 32
#define XPAR_MICROBLAZE_0_PVR 0
#define XPAR_MICROBLAZE_0_PVR_USER1 0x00
#define XPAR_MICROBLAZE_0_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_0_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_0_RESET_MSR_BIP 0
#define XPAR_MICROBLAZE_0_RESET_MSR_DCE 0
#define XPAR_MICROBLAZE_0_RESET_MSR_EE 0
#define XPAR_MICROBLAZE_0_RESET_MSR_EIP 0
#define XPAR_MICROBLAZE_0_RESET_MSR_ICE 0
#define XPAR_MICROBLAZE_0_RESET_MSR_IE 0
#define XPAR_MICROBLAZE_0_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_SCO 0
#define XPAR_MICROBLAZE_0_TEMPORAL_DEPTH 0
#define XPAR_MICROBLAZE_0_TRACE 0
#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_0_USE_BARREL 1
#define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_0_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_0_USE_DCACHE 1
#define XPAR_MICROBLAZE_0_USE_DIV 1
#define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_0_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_0_USE_FPU 1
#define XPAR_MICROBLAZE_0_USE_HW_MUL 1
#define XPAR_MICROBLAZE_0_USE_ICACHE 1
#define XPAR_MICROBLAZE_0_USE_INTERRUPT 2
#define XPAR_MICROBLAZE_0_USE_MMU 0
#define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_0_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 1
#define XPAR_MICROBLAZE_0_COMPONENT_NAME microblaze_bd_microblaze_0_0
#define XPAR_MICROBLAZE_0_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_0_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 9
#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 1

/******************************************************************/

#define XPAR_CPU_ID 0
#define XPAR_MICROBLAZE_ID 0
#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 16
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_DADDR_SIZE 32
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 16
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 32768
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 1
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 16
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 8
#define XPAR_MICROBLAZE_DC_AXI_MON 0
#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_DEBUG_INTERFACE 0
#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_ASYNC_RESET 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_DP_AXI_MON 0
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_D_AXI 1
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_D_LMB_MON 0
#define XPAR_MICROBLAZE_D_LMB_PROTOCOL 0
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 1
#define XPAR_MICROBLAZE_FREQ 125000000
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_IADDR_SIZE 32
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 1
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xFFFFFFFF
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 16
#define XPAR_MICROBLAZE_ICACHE_STREAMS 1
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 8
#define XPAR_MICROBLAZE_IC_AXI_MON 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_INSTR_SIZE 32
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_IP_AXI_MON 0
#define XPAR_MICROBLAZE_I_AXI 0
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_I_LMB_MON 0
#define XPAR_MICROBLAZE_I_LMB_PROTOCOL 0
#define XPAR_MICROBLAZE_LMB_DATA_SIZE 32
#define XPAR_MICROBLAZE_LOCKSTEP_MASTER 0
#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 1
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 2
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 512
#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 512
#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 2
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_TRACE_CLK 2
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_PIADDR_SIZE 32
#define XPAR_MICROBLAZE_PVR 0
#define XPAR_MICROBLAZE_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR_BIP 0
#define XPAR_MICROBLAZE_RESET_MSR_DCE 0
#define XPAR_MICROBLAZE_RESET_MSR_EE 0
#define XPAR_MICROBLAZE_RESET_MSR_EIP 0
#define XPAR_MICROBLAZE_RESET_MSR_ICE 0
#define XPAR_MICROBLAZE_RESET_MSR_IE 0
#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_TEMPORAL_DEPTH 0
#define XPAR_MICROBLAZE_TRACE 0
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_USE_DCACHE 1
#define XPAR_MICROBLAZE_USE_DIV 1
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_FPU 1
#define XPAR_MICROBLAZE_USE_HW_MUL 1
#define XPAR_MICROBLAZE_USE_ICACHE 1
#define XPAR_MICROBLAZE_USE_INTERRUPT 2
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1
#define XPAR_MICROBLAZE_COMPONENT_NAME microblaze_bd_microblaze_0_0
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 9
#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1

/******************************************************************/


/* Definitions for interface DIG_RX0_AXIL */
#define XPAR_DIG_RX0_AXIL_BASEADDR 0x20000000
#define XPAR_DIG_RX0_AXIL_HIGHADDR 0x20000FFF


/* Definitions for interface DIG_RX1_AXIL */
#define XPAR_DIG_RX1_AXIL_BASEADDR 0x20010000
#define XPAR_DIG_RX1_AXIL_HIGHADDR 0x20010FFF


/* Definitions for interface UTIL_REG_AXIL */
#define XPAR_UTIL_REG_AXIL_BASEADDR 0x40050000
#define XPAR_UTIL_REG_AXIL_HIGHADDR 0x40050FFF


/* Definitions for interface TIMING_ENGINE_AXIL */
#define XPAR_TIMING_ENGINE_AXIL_BASEADDR 0x40051000
#define XPAR_TIMING_ENGINE_AXIL_HIGHADDR 0x40051FFF


/* Definitions for interface WF_GEN_AXIL */
#define XPAR_WF_GEN_AXIL_BASEADDR 0x40053000
#define XPAR_WF_GEN_AXIL_HIGHADDR 0x40053FFF

/* Platform specific definitions */
#define PLATFORM_MB
 
/******************************************************************/
#define STDIN_BASEADDRESS 0x41400000
#define STDOUT_BASEADDRESS 0x41400000

/******************************************************************/

/* Definitions for driver AXIDMA */
#define XPAR_XAXIDMA_NUM_INSTANCES 1

/* Definitions for peripheral AXI_ETHERNET_0_DMA */
#define XPAR_AXI_ETHERNET_0_DMA_DEVICE_ID 0
#define XPAR_AXI_ETHERNET_0_DMA_BASEADDR 0x40040000
#define XPAR_AXI_ETHERNET_0_DMA_HIGHADDR 0x4004FFFF
#define XPAR_AXI_ETHERNET_0_DMA_SG_INCLUDE_STSCNTRL_STRM 1
#define XPAR_AXI_ETHERNET_0_DMA_INCLUDE_MM2S_DRE 1
#define XPAR_AXI_ETHERNET_0_DMA_INCLUDE_S2MM_DRE 1
#define XPAR_AXI_ETHERNET_0_DMA_INCLUDE_MM2S 1
#define XPAR_AXI_ETHERNET_0_DMA_INCLUDE_S2MM 1
#define XPAR_AXI_ETHERNET_0_DMA_M_AXI_MM2S_DATA_WIDTH 32
#define XPAR_AXI_ETHERNET_0_DMA_M_AXI_S2MM_DATA_WIDTH 32
#define XPAR_AXI_ETHERNET_0_DMA_INCLUDE_SG 1
#define XPAR_AXI_ETHERNET_0_DMA_ENABLE_MULTI_CHANNEL 0
#define XPAR_AXI_ETHERNET_0_DMA_NUM_MM2S_CHANNELS 1
#define XPAR_AXI_ETHERNET_0_DMA_NUM_S2MM_CHANNELS 1
#define XPAR_AXI_ETHERNET_0_DMA_MM2S_BURST_SIZE 256
#define XPAR_AXI_ETHERNET_0_DMA_S2MM_BURST_SIZE 256
#define XPAR_AXI_ETHERNET_0_DMA_MICRO_DMA 0
#define XPAR_AXI_ETHERNET_0_DMA_ADDR_WIDTH 32
#define XPAR_AXI_ETHERNET_0_DMA_SG_LENGTH_WIDTH 16


/******************************************************************/

/* Canonical definitions for peripheral AXI_ETHERNET_0_DMA */
#define XPAR_AXIDMA_0_DEVICE_ID XPAR_AXI_ETHERNET_0_DMA_DEVICE_ID
#define XPAR_AXIDMA_0_BASEADDR 0x40040000
#define XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM 1
#define XPAR_AXIDMA_0_INCLUDE_MM2S 1
#define XPAR_AXIDMA_0_INCLUDE_MM2S_DRE 1
#define XPAR_AXIDMA_0_M_AXI_MM2S_DATA_WIDTH 32
#define XPAR_AXIDMA_0_INCLUDE_S2MM 1
#define XPAR_AXIDMA_0_INCLUDE_S2MM_DRE 1
#define XPAR_AXIDMA_0_M_AXI_S2MM_DATA_WIDTH 32
#define XPAR_AXIDMA_0_INCLUDE_SG 1
#define XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL 0
#define XPAR_AXIDMA_0_NUM_MM2S_CHANNELS 1
#define XPAR_AXIDMA_0_NUM_S2MM_CHANNELS 1
#define XPAR_AXIDMA_0_MM2S_BURST_SIZE 256
#define XPAR_AXIDMA_0_S2MM_BURST_SIZE 256
#define XPAR_AXIDMA_0_MICRO_DMA 0
#define XPAR_AXIDMA_0_c_addr_width 32
#define XPAR_AXIDMA_0_c_sg_length_width 16


/******************************************************************/

/* Definitions for driver AXIETHERNET */
#define XPAR_XAXIETHERNET_NUM_INSTANCES 1U
/* Definitions for peripheral AXI_ETHERNET_0 */
#define XPAR_AXI_ETHERNET_0_DEVICE_ID 0U
#define XPAR_AXI_ETHERNET_0_BASEADDR 0x40080000U
#define XPAR_AXI_ETHERNET_0_HIGHADDR 0x400BFFFFU
#define XPAR_AXI_ETHERNET_0_TYPE 1U
#define XPAR_AXI_ETHERNET_0_TXCSUM 2U
#define XPAR_AXI_ETHERNET_0_RXCSUM 2U
#define XPAR_AXI_ETHERNET_0_PHY_TYPE 3U
#define XPAR_AXI_ETHERNET_0_TXVLAN_TRAN 0U
#define XPAR_AXI_ETHERNET_0_RXVLAN_TRAN 0U
#define XPAR_AXI_ETHERNET_0_TXVLAN_TAG 0U
#define XPAR_AXI_ETHERNET_0_RXVLAN_TAG 0U
#define XPAR_AXI_ETHERNET_0_TXVLAN_STRP 0U
#define XPAR_AXI_ETHERNET_0_RXVLAN_STRP 0U
#define XPAR_AXI_ETHERNET_0_MCAST_EXTEND 0U
#define XPAR_AXI_ETHERNET_0_STATS 0U
#define XPAR_AXI_ETHERNET_0_AVB 0U
#define XPAR_AXI_ETHERNET_0_Enable_1588 0U
#define XPAR_AXI_ETHERNET_0_SPEED 1000U
#define XPAR_AXI_ETHERNET_0_PHYADDR 1U

/* Canonical definitions for peripheral AXI_ETHERNET_0 */
#define XPAR_AXIETHERNET_0_DEVICE_ID 0U
#define XPAR_AXIETHERNET_0_BASEADDR 0x40080000U
#define XPAR_AXIETHERNET_0_HIGHADDR 0x400BFFFFU
#define XPAR_AXIETHERNET_0_TEMAC_TYPE 1U
#define XPAR_AXIETHERNET_0_TXCSUM 2U
#define XPAR_AXIETHERNET_0_RXCSUM 2U
#define XPAR_AXIETHERNET_0_PHY_TYPE 3U
#define XPAR_AXIETHERNET_0_TXVLAN_TRAN 0U
#define XPAR_AXIETHERNET_0_RXVLAN_TRAN 0U
#define XPAR_AXIETHERNET_0_TXVLAN_TAG 0U
#define XPAR_AXIETHERNET_0_RXVLAN_TAG 0U
#define XPAR_AXIETHERNET_0_TXVLAN_STRP 0U
#define XPAR_AXIETHERNET_0_RXVLAN_STRP 0U
#define XPAR_AXIETHERNET_0_MCAST_EXTEND 0U
#define XPAR_AXIETHERNET_0_STATS 0U
#define XPAR_AXIETHERNET_0_AVB 0U
#define XPAR_AXIETHERNET_0_ENABLE_SGMII_OVER_LVDS 0U
#define XPAR_AXIETHERNET_0_ENABLE_1588 0U
#define XPAR_AXIETHERNET_0_SPEED 1000U
#define XPAR_AXIETHERNET_0_NUM_TABLE_ENTRIES 4U
#define XPAR_AXIETHERNET_0_PHYADDR 1U
#define XPAR_AXIETHERNET_0_INTR 1U


/* AxiEthernet TYPE Enumerations */
#define XPAR_AXI_FIFO    1U
#define XPAR_AXI_DMA     2U
#define XPAR_AXI_MCDMA   3U


/* Canonical Axi parameters for AXI_ETHERNET_0 */
#define XPAR_AXIETHERNET_0_CONNECTED_TYPE XPAR_AXI_DMA
#define XPAR_AXIETHERNET_0_CONNECTED_BASEADDR 0x40040000U
#define XPAR_AXIETHERNET_0_CONNECTED_FIFO_INTR 0xFFU
#define XPAR_AXIETHERNET_0_CONNECTED_DMARX_INTR 5U
#define XPAR_AXIETHERNET_0_CONNECTED_DMATX_INTR 4U
#define XPAR_AXIETHERNET_0_MCDMA_CHAN_CNT 0
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX1_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX2_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX3_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX4_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX5_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX6_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX7_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX8_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX9_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX10_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX11_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX12_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX13_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX14_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX15_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMARX16_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX1_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX2_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX3_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX4_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX5_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX6_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX7_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX8_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX9_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX10_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX11_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX12_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX13_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX14_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX15_INTR 0xFF
#define XPAR_AXIETHERNET_0_CONNECTED_MCDMATX16_INTR 0xFF

/******************************************************************/

/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 6U

/* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x00007FFFU
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  


/* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID 1U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x00007FFFU
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  


/* Definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 2U
#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32U
#define XPAR_AXI_BRAM_CTRL_0_ECC 0U
#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0U
#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0U
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0U
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0U
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x00010000U
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x00017FFFU
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  


/* Definitions for peripheral AXI_BRAM_CTRL_1 */
#define XPAR_AXI_BRAM_CTRL_1_DEVICE_ID 3U
#define XPAR_AXI_BRAM_CTRL_1_DATA_WIDTH 32U
#define XPAR_AXI_BRAM_CTRL_1_ECC 0U
#define XPAR_AXI_BRAM_CTRL_1_FAULT_INJECT 0U
#define XPAR_AXI_BRAM_CTRL_1_CE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_1_UE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_1_ECC_STATUS_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_1_CE_COUNTER_WIDTH 0U
#define XPAR_AXI_BRAM_CTRL_1_ECC_ONOFF_REGISTER 0U
#define XPAR_AXI_BRAM_CTRL_1_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_AXI_BRAM_CTRL_1_WRITE_ACCESS 0U
#define XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR 0x00020000U
#define XPAR_AXI_BRAM_CTRL_1_S_AXI_HIGHADDR 0x00027FFFU
#define XPAR_AXI_BRAM_CTRL_1_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_AXI_BRAM_CTRL_1_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  


/* Definitions for peripheral AXI_BRAM_CTRL_2 */
#define XPAR_AXI_BRAM_CTRL_2_DEVICE_ID 4U
#define XPAR_AXI_BRAM_CTRL_2_DATA_WIDTH 32U
#define XPAR_AXI_BRAM_CTRL_2_ECC 0U
#define XPAR_AXI_BRAM_CTRL_2_FAULT_INJECT 0U
#define XPAR_AXI_BRAM_CTRL_2_CE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_2_UE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_2_ECC_STATUS_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_2_CE_COUNTER_WIDTH 0U
#define XPAR_AXI_BRAM_CTRL_2_ECC_ONOFF_REGISTER 0U
#define XPAR_AXI_BRAM_CTRL_2_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_AXI_BRAM_CTRL_2_WRITE_ACCESS 0U
#define XPAR_AXI_BRAM_CTRL_2_S_AXI_BASEADDR 0x00030000U
#define XPAR_AXI_BRAM_CTRL_2_S_AXI_HIGHADDR 0x00037FFFU
#define XPAR_AXI_BRAM_CTRL_2_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_AXI_BRAM_CTRL_2_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  


/* Definitions for peripheral AXI_BRAM_CTRL_3 */
#define XPAR_AXI_BRAM_CTRL_3_DEVICE_ID 5U
#define XPAR_AXI_BRAM_CTRL_3_DATA_WIDTH 32U
#define XPAR_AXI_BRAM_CTRL_3_ECC 0U
#define XPAR_AXI_BRAM_CTRL_3_FAULT_INJECT 0U
#define XPAR_AXI_BRAM_CTRL_3_CE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_3_UE_FAILING_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_3_ECC_STATUS_REGISTERS 0U
#define XPAR_AXI_BRAM_CTRL_3_CE_COUNTER_WIDTH 0U
#define XPAR_AXI_BRAM_CTRL_3_ECC_ONOFF_REGISTER 0U
#define XPAR_AXI_BRAM_CTRL_3_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_AXI_BRAM_CTRL_3_WRITE_ACCESS 0U
#define XPAR_AXI_BRAM_CTRL_3_S_AXI_BASEADDR 0x00040000U
#define XPAR_AXI_BRAM_CTRL_3_S_AXI_HIGHADDR 0x00047FFFU
#define XPAR_AXI_BRAM_CTRL_3_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_AXI_BRAM_CTRL_3_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  


/******************************************************************/

/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_0_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32U
#define XPAR_BRAM_0_ECC 0U
#define XPAR_BRAM_0_FAULT_INJECT 0U
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_BRAM_0_WRITE_ACCESS 2U
#define XPAR_BRAM_0_BASEADDR 0x00000000U
#define XPAR_BRAM_0_HIGHADDR 0x00007FFFU
#define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU  
#define XPAR_DLMB_0_CNTLR_BASEADDR 0x00000000
#define XPAR_DLMB_0_CNTLR_HIGHADDR 0x00007FFF
#define XPAR_DLMB_CNTLR_BASEADDR XPAR_DLMB_0_CNTLR_BASEADDR
#define XPAR_DLMB_CNTLR_HIGHADDR XPAR_DLMB_0_CNTLR_HIGHADDR

/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32U
#define XPAR_BRAM_1_ECC 0U
#define XPAR_BRAM_1_FAULT_INJECT 0U
#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_BRAM_1_WRITE_ACCESS 2U
#define XPAR_BRAM_1_BASEADDR 0x00000000U
#define XPAR_BRAM_1_HIGHADDR 0x00007FFFU
#define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU  
#define XPAR_ILMB_0_CNTLR_BASEADDR 0x00000000
#define XPAR_ILMB_0_CNTLR_HIGHADDR 0x00007FFF
#define XPAR_ILMB_CNTLR_BASEADDR XPAR_ILMB_0_CNTLR_BASEADDR
#define XPAR_ILMB_CNTLR_HIGHADDR XPAR_ILMB_0_CNTLR_HIGHADDR

/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_BRAM_2_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
#define XPAR_BRAM_2_DATA_WIDTH 32U
#define XPAR_BRAM_2_ECC 0U
#define XPAR_BRAM_2_FAULT_INJECT 0U
#define XPAR_BRAM_2_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_2_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_2_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_2_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_2_WRITE_ACCESS 0U
#define XPAR_BRAM_2_BASEADDR 0x00010000U
#define XPAR_BRAM_2_HIGHADDR 0x00017FFFU
#define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU  

/* Canonical definitions for peripheral AXI_BRAM_CTRL_1 */
#define XPAR_BRAM_3_DEVICE_ID XPAR_AXI_BRAM_CTRL_1_DEVICE_ID
#define XPAR_BRAM_3_DATA_WIDTH 32U
#define XPAR_BRAM_3_ECC 0U
#define XPAR_BRAM_3_FAULT_INJECT 0U
#define XPAR_BRAM_3_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_3_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_3_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_3_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_3_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_3_WRITE_ACCESS 0U
#define XPAR_BRAM_3_BASEADDR 0x00020000U
#define XPAR_BRAM_3_HIGHADDR 0x00027FFFU
#define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU  

/* Canonical definitions for peripheral AXI_BRAM_CTRL_2 */
#define XPAR_BRAM_4_DEVICE_ID XPAR_AXI_BRAM_CTRL_2_DEVICE_ID
#define XPAR_BRAM_4_DATA_WIDTH 32U
#define XPAR_BRAM_4_ECC 0U
#define XPAR_BRAM_4_FAULT_INJECT 0U
#define XPAR_BRAM_4_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_4_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_4_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_4_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_4_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_4_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_4_WRITE_ACCESS 0U
#define XPAR_BRAM_4_BASEADDR 0x00030000U
#define XPAR_BRAM_4_HIGHADDR 0x00037FFFU
#define XPAR_BRAM_4_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_BRAM_4_CTRL_HIGHADDR 0xFFFFFFFEU  

/* Canonical definitions for peripheral AXI_BRAM_CTRL_3 */
#define XPAR_BRAM_5_DEVICE_ID XPAR_AXI_BRAM_CTRL_3_DEVICE_ID
#define XPAR_BRAM_5_DATA_WIDTH 32U
#define XPAR_BRAM_5_ECC 0U
#define XPAR_BRAM_5_FAULT_INJECT 0U
#define XPAR_BRAM_5_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_5_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_5_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_5_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_5_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_5_ECC_ONOFF_RESET_VALUE 0U
#define XPAR_BRAM_5_WRITE_ACCESS 0U
#define XPAR_BRAM_5_BASEADDR 0x00040000U
#define XPAR_BRAM_5_HIGHADDR 0x00047FFFU
#define XPAR_BRAM_5_CTRL_BASEADDR 0xFFFFFFFFU  
#define XPAR_BRAM_5_CTRL_HIGHADDR 0xFFFFFFFEU  


/******************************************************************/


/* Peripheral Definitions for peripheral JESD_JESD204C_0 */
#define XPAR_JESD_JESD204C_0_BASEADDR 0x40060000
#define XPAR_JESD_JESD204C_0_HIGHADDR 0x4006FFFF


/* Peripheral Definitions for peripheral JESD_JESD204C_1 */
#define XPAR_JESD_JESD204C_1_BASEADDR 0x40070000
#define XPAR_JESD_JESD204C_1_HIGHADDR 0x4007FFFF


/* Peripheral Definitions for peripheral JESD_JESD204_PHY_0 */
#define XPAR_JESD_JESD204_PHY_0_BASEADDR 0x400E0000
#define XPAR_JESD_JESD204_PHY_0_HIGHADDR 0x400EFFFF


/******************************************************************/


/* Canonical Definitions for peripheral JESD_JESD204C_0 */
#define XPAR_JESD204C_0_BASEADDR 0x40060000
#define XPAR_JESD204C_0_HIGHADDR 0x4006FFFF


/* Canonical Definitions for peripheral JESD_JESD204C_1 */
#define XPAR_JESD204C_1_BASEADDR 0x40070000
#define XPAR_JESD204C_1_HIGHADDR 0x4007FFFF


/* Canonical Definitions for peripheral JESD_JESD204_PHY_0 */
#define XPAR_JESD204_PHY_0_BASEADDR 0x400E0000
#define XPAR_JESD204_PHY_0_HIGHADDR 0x400EFFFF


/******************************************************************/

/* Definitions for driver IIC */
#define XPAR_XIIC_NUM_INSTANCES 1

/* Definitions for peripheral AXI_IIC_0 */
#define XPAR_AXI_IIC_0_DEVICE_ID 0
#define XPAR_AXI_IIC_0_BASEADDR 0x40110000
#define XPAR_AXI_IIC_0_HIGHADDR 0x4011FFFF
#define XPAR_AXI_IIC_0_TEN_BIT_ADR 0
#define XPAR_AXI_IIC_0_GPO_WIDTH 1


/******************************************************************/

/* Canonical definitions for peripheral AXI_IIC_0 */
#define XPAR_IIC_0_DEVICE_ID XPAR_AXI_IIC_0_DEVICE_ID
#define XPAR_IIC_0_BASEADDR 0x40110000
#define XPAR_IIC_0_HIGHADDR 0x4011FFFF
#define XPAR_IIC_0_TEN_BIT_ADR 0
#define XPAR_IIC_0_GPO_WIDTH 1


/******************************************************************/

#define XPAR_INTC_MAX_NUM_INTR_INPUTS 14
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_HAS_SIE 1
#define XPAR_XINTC_HAS_CIE 1
#define XPAR_XINTC_HAS_IVR 1
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1

/* Definitions for peripheral MICROBLAZE_0_AXI_INTC */
#define XPAR_MICROBLAZE_0_AXI_INTC_DEVICE_ID 0
#define XPAR_MICROBLAZE_0_AXI_INTC_BASEADDR 0x40010000
#define XPAR_MICROBLAZE_0_AXI_INTC_HIGHADDR 0x4001FFFF
#define XPAR_MICROBLAZE_0_AXI_INTC_KIND_OF_INTR 0xFFFFDBC9
#define XPAR_MICROBLAZE_0_AXI_INTC_HAS_FAST 1
#define XPAR_MICROBLAZE_0_AXI_INTC_IVAR_RESET_VALUE 0x0000000000000010
#define XPAR_MICROBLAZE_0_AXI_INTC_NUM_INTR_INPUTS 14
#define XPAR_MICROBLAZE_0_AXI_INTC_NUM_SW_INTR 0
#define XPAR_MICROBLAZE_0_AXI_INTC_ADDR_WIDTH 32


/******************************************************************/

#define XPAR_INTC_SINGLE_BASEADDR 0x40010000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4001FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_MICROBLAZE_0_AXI_INTC_DEVICE_ID
#define XPAR_MICROBLAZE_0_AXI_INTC_TYPE 0U
#define XPAR_AXI_UARTLITE_0_INTERRUPT_MASK 0X000001U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_UARTLITE_0_INTERRUPT_INTR 0U
#define XPAR_AXI_ETHERNET_0_INTERRUPT_MASK 0X000002U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_INTERRUPT_INTR 1U
#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000004U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR 2U
#define XPAR_AXI_ETHERNET_0_MAC_IRQ_MASK 0X000008U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_MAC_IRQ_INTR 3U
#define XPAR_AXI_ETHERNET_0_DMA_MM2S_INTROUT_MASK 0X000010U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_DMA_MM2S_INTROUT_INTR 4U
#define XPAR_AXI_ETHERNET_0_DMA_S2MM_INTROUT_MASK 0X000020U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_DMA_S2MM_INTROUT_INTR 5U
#define XPAR_JESD_JESD204C_0_IRQ_MASK 0X000040U
#define XPAR_MICROBLAZE_0_AXI_INTC_JESD_JESD204C_0_IRQ_INTR 6U
#define XPAR_JESD_JESD204C_1_IRQ_MASK 0X000080U
#define XPAR_MICROBLAZE_0_AXI_INTC_JESD_JESD204C_1_IRQ_INTR 7U
#define XPAR_AXI_QUAD_SPI_0_IP2INTC_IRPT_MASK 0X000100U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_QUAD_SPI_0_IP2INTC_IRPT_INTR 8U
#define XPAR_AXI_QUAD_SPI_1_IP2INTC_IRPT_MASK 0X000200U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_QUAD_SPI_1_IP2INTC_IRPT_INTR 9U
#define XPAR_AXI_FIFO_MM_S_0_INTERRUPT_MASK 0X000400U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_FIFO_MM_S_0_INTERRUPT_INTR 10U
#define XPAR_QSPI_FLASH_IP2INTC_IRPT_MASK 0X000800U
#define XPAR_MICROBLAZE_0_AXI_INTC_QSPI_FLASH_IP2INTC_IRPT_INTR 11U
#define XPAR_SYSTEM_PPS_MASK 0X001000U
#define XPAR_MICROBLAZE_0_AXI_INTC_SYSTEM_PPS_INTR 12U
#define XPAR_AXI_IIC_0_IIC2INTC_IRPT_MASK 0X002000U
#define XPAR_MICROBLAZE_0_AXI_INTC_AXI_IIC_0_IIC2INTC_IRPT_INTR 13U

/******************************************************************/

/* Canonical definitions for peripheral MICROBLAZE_0_AXI_INTC */
#define XPAR_INTC_0_DEVICE_ID XPAR_MICROBLAZE_0_AXI_INTC_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x40010000U
#define XPAR_INTC_0_HIGHADDR 0x4001FFFFU
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFDBC9U
#define XPAR_INTC_0_HAS_FAST 1U
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x0000000000000010U
#define XPAR_INTC_0_NUM_INTR_INPUTS 14U
#define XPAR_INTC_0_NUM_SW_INTR 0U
#define XPAR_INTC_0_ADDR_WIDTH 32U
#define XPAR_INTC_0_INTC_TYPE 0U

#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_UARTLITE_0_INTERRUPT_INTR
#define XPAR_INTC_0_AXIETHERNET_0_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_INTERRUPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR
#define XPAR_INTC_0_AXIETHERNET_0_MAC_IRQ_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_MAC_IRQ_INTR
#define XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_DMA_MM2S_INTROUT_INTR
#define XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_DMA_S2MM_INTROUT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_QUAD_SPI_0_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_SPI_1_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_QUAD_SPI_1_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_FIFO_MM_S_0_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_2_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_QSPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_MICROBLAZE_0_AXI_INTC_AXI_IIC_0_IIC2INTC_IRPT_INTR

/******************************************************************/

/* Definitions for driver LLFIFO */
#define XPAR_XLLFIFO_NUM_INSTANCES 1U

/* Definitions for peripheral AXI_FIFO_MM_S_0 */
#define XPAR_AXI_FIFO_MM_S_0_DEVICE_ID 0U
#define XPAR_AXI_FIFO_MM_S_0_BASEADDR 0x400F0000U
#define XPAR_AXI_FIFO_MM_S_0_HIGHADDR 0x400FFFFFU
#define XPAR_AXI_FIFO_MM_S_0_AXI4_BASEADDR 0U
#define XPAR_AXI_FIFO_MM_S_0_AXI4_HIGHADDR 0U
#define XPAR_AXI_FIFO_MM_S_0_DATA_INTERFACE_TYPE 0U

/* Canonical definitions for peripheral AXI_FIFO_MM_S_0 */
#define XPAR_AXI_FIFO_0_DEVICE_ID 0U
#define XPAR_AXI_FIFO_0_BASEADDR 0x400F0000U
#define XPAR_AXI_FIFO_0_HIGHADDR 0x400FFFFFU
#define XPAR_AXI_FIFO_0_AXI4_BASEADDR 0U
#define XPAR_AXI_FIFO_0_AXI4_HIGHADDR 0U
#define XPAR_AXI_FIFO_0_DATA_INTERFACE_TYPE 0U



/******************************************************************/


/* Definitions for peripheral DDR4_0 */
#define XPAR_DDR4_0_C0_DDR4_MEMORY_MAP_BASEADDR 0x80000000
#define XPAR_DDR4_0_C0_DDR4_MEMORY_MAP_HIGHADDR 0xFFFFFFFF


/******************************************************************/

/* Canonical definitions for peripheral DDR4_0 */
#define XPAR_MIG_0_C0_DDR4_MEMORY_MAP_BASEADDR 0x80000000
#define XPAR_MIG_0_C0_DDR4_MEMORY_MAP_HIGHADDR 0xFFFFFFFF


/******************************************************************/

/* Definitions for driver SPI */
#define XPAR_XSPI_NUM_INSTANCES 3U

/* Definitions for peripheral AXI_QUAD_SPI_0 */
#define XPAR_AXI_QUAD_SPI_0_DEVICE_ID 0U
#define XPAR_AXI_QUAD_SPI_0_BASEADDR 0x400C0000U
#define XPAR_AXI_QUAD_SPI_0_HIGHADDR 0x400CFFFFU
#define XPAR_AXI_QUAD_SPI_0_FIFO_EXIST 1U
#define XPAR_AXI_QUAD_SPI_0_FIFO_DEPTH 16U
#define XPAR_AXI_QUAD_SPI_0_SPI_SLAVE_ONLY 0U
#define XPAR_AXI_QUAD_SPI_0_NUM_SS_BITS 1U
#define XPAR_AXI_QUAD_SPI_0_NUM_TRANSFER_BITS 8U
#define XPAR_AXI_QUAD_SPI_0_SPI_MODE 0U
#define XPAR_AXI_QUAD_SPI_0_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_AXI_QUAD_SPI_0_AXI4_BASEADDR 0U
#define XPAR_AXI_QUAD_SPI_0_AXI4_HIGHADDR 0U
#define XPAR_AXI_QUAD_SPI_0_XIP_MODE 0U

/* Canonical definitions for peripheral AXI_QUAD_SPI_0 */
#define XPAR_SPI_0_DEVICE_ID 0U
#define XPAR_SPI_0_BASEADDR 0x400C0000U
#define XPAR_SPI_0_HIGHADDR 0x400CFFFFU
#define XPAR_SPI_0_FIFO_EXIST 1U
#define XPAR_SPI_0_FIFO_DEPTH 16U
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0U
#define XPAR_SPI_0_NUM_SS_BITS 1U
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8U
#define XPAR_SPI_0_SPI_MODE 0U
#define XPAR_SPI_0_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_SPI_0_AXI4_BASEADDR 0U
#define XPAR_SPI_0_AXI4_HIGHADDR 0U
#define XPAR_SPI_0_XIP_MODE 0U
#define XPAR_SPI_0_USE_STARTUP 0U



/* Definitions for peripheral AXI_QUAD_SPI_1 */
#define XPAR_AXI_QUAD_SPI_1_DEVICE_ID 1U
#define XPAR_AXI_QUAD_SPI_1_BASEADDR 0x400D0000U
#define XPAR_AXI_QUAD_SPI_1_HIGHADDR 0x400DFFFFU
#define XPAR_AXI_QUAD_SPI_1_FIFO_EXIST 1U
#define XPAR_AXI_QUAD_SPI_1_FIFO_DEPTH 16U
#define XPAR_AXI_QUAD_SPI_1_SPI_SLAVE_ONLY 0U
#define XPAR_AXI_QUAD_SPI_1_NUM_SS_BITS 2U
#define XPAR_AXI_QUAD_SPI_1_NUM_TRANSFER_BITS 8U
#define XPAR_AXI_QUAD_SPI_1_SPI_MODE 0U
#define XPAR_AXI_QUAD_SPI_1_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_AXI_QUAD_SPI_1_AXI4_BASEADDR 0U
#define XPAR_AXI_QUAD_SPI_1_AXI4_HIGHADDR 0U
#define XPAR_AXI_QUAD_SPI_1_XIP_MODE 0U

/* Canonical definitions for peripheral AXI_QUAD_SPI_1 */
#define XPAR_SPI_1_DEVICE_ID 1U
#define XPAR_SPI_1_BASEADDR 0x400D0000U
#define XPAR_SPI_1_HIGHADDR 0x400DFFFFU
#define XPAR_SPI_1_FIFO_EXIST 1U
#define XPAR_SPI_1_FIFO_DEPTH 16U
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0U
#define XPAR_SPI_1_NUM_SS_BITS 2U
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8U
#define XPAR_SPI_1_SPI_MODE 0U
#define XPAR_SPI_1_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_SPI_1_AXI4_BASEADDR 0U
#define XPAR_SPI_1_AXI4_HIGHADDR 0U
#define XPAR_SPI_1_XIP_MODE 0U
#define XPAR_SPI_1_USE_STARTUP 0U



/* Definitions for peripheral QSPI_FLASH */
#define XPAR_QSPI_FLASH_DEVICE_ID 2U
#define XPAR_QSPI_FLASH_BASEADDR 0x40100000U
#define XPAR_QSPI_FLASH_HIGHADDR 0x4010FFFFU
#define XPAR_QSPI_FLASH_FIFO_EXIST 1U
#define XPAR_QSPI_FLASH_FIFO_DEPTH 16U
#define XPAR_QSPI_FLASH_SPI_SLAVE_ONLY 0U
#define XPAR_QSPI_FLASH_NUM_SS_BITS 1U
#define XPAR_QSPI_FLASH_NUM_TRANSFER_BITS 8U
#define XPAR_QSPI_FLASH_SPI_MODE 2U
#define XPAR_QSPI_FLASH_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_QSPI_FLASH_AXI4_BASEADDR 0U
#define XPAR_QSPI_FLASH_AXI4_HIGHADDR 0U
#define XPAR_QSPI_FLASH_XIP_MODE 0U

/* Canonical definitions for peripheral QSPI_FLASH */
#define XPAR_SPI_2_DEVICE_ID 2U
#define XPAR_SPI_2_BASEADDR 0x40100000U
#define XPAR_SPI_2_HIGHADDR 0x4010FFFFU
#define XPAR_SPI_2_FIFO_EXIST 1U
#define XPAR_SPI_2_FIFO_DEPTH 16U
#define XPAR_SPI_2_SPI_SLAVE_ONLY 0U
#define XPAR_SPI_2_NUM_SS_BITS 1U
#define XPAR_SPI_2_NUM_TRANSFER_BITS 8U
#define XPAR_SPI_2_SPI_MODE 2U
#define XPAR_SPI_2_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_SPI_2_AXI4_BASEADDR 0U
#define XPAR_SPI_2_AXI4_HIGHADDR 0U
#define XPAR_SPI_2_XIP_MODE 0U
#define XPAR_SPI_2_USE_STARTUP 1U



/******************************************************************/

/* Definitions for driver SYSMON */
#define XPAR_XSYSMON_NUM_INSTANCES 1U

/* Definitions for peripheral SYSTEM_MANAGEMENT_WIZ_0 */
#define XPAR_SYSTEM_MANAGEMENT_WIZ_0_IP_TYPE 1U
#define XPAR_SYSTEM_MANAGEMENT_WIZ_0_DEVICE_ID 0U
#define XPAR_SYSTEM_MANAGEMENT_WIZ_0_BASEADDR 0x40020000U
#define XPAR_SYSTEM_MANAGEMENT_WIZ_0_HIGHADDR 0x4002FFFFU
#define XPAR_SYSTEM_MANAGEMENT_WIZ_0_INCLUDE_INTR 1U


/******************************************************************/

/* Canonical definitions for peripheral SYSTEM_MANAGEMENT_WIZ_0 */
#define XPAR_SYSMON_0_IP_TYPE 1U
#define XPAR_SYSMON_0_DEVICE_ID XPAR_SYSTEM_MANAGEMENT_WIZ_0_DEVICE_ID
#define XPAR_SYSMON_0_BASEADDR 0x40020000U
#define XPAR_SYSMON_0_HIGHADDR 0x4002FFFFU
#define XPAR_SYSMON_0_INCLUDE_INTR 1U


/******************************************************************/

/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1U

/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_DEVICE_ID 0U
#define XPAR_AXI_TIMER_0_BASEADDR 0x40030000U
#define XPAR_AXI_TIMER_0_HIGHADDR 0x4003FFFFU
#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 125000000U


/******************************************************************/

/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID 0U
#define XPAR_TMRCTR_0_BASEADDR 0x40030000U
#define XPAR_TMRCTR_0_HIGHADDR 0x4003FFFFU
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ

/******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 2U

/* Definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_AXI_UARTLITE_0_DEVICE_ID 0U
#define XPAR_AXI_UARTLITE_0_BASEADDR 0x40000000U
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4000FFFFU
#define XPAR_AXI_UARTLITE_0_BAUDRATE 115200U
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0U
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0U
#define XPAR_AXI_UARTLITE_0_DATA_BITS 8U

/* Canonical definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_UARTLITE_0_DEVICE_ID 0U
#define XPAR_UARTLITE_0_BASEADDR 0x40000000U
#define XPAR_UARTLITE_0_HIGHADDR 0x4000FFFFU
#define XPAR_UARTLITE_0_BAUDRATE 115200U
#define XPAR_UARTLITE_0_USE_PARITY 0U
#define XPAR_UARTLITE_0_ODD_PARITY 0U
#define XPAR_UARTLITE_0_DATA_BITS 8U



/* Definitions for peripheral MDM_1 */
#define XPAR_MDM_1_DEVICE_ID 1U
#define XPAR_MDM_1_BASEADDR 0x41400000U
#define XPAR_MDM_1_HIGHADDR 0x41400FFFU
#define XPAR_MDM_1_BAUDRATE 0U
#define XPAR_MDM_1_USE_PARITY 0U
#define XPAR_MDM_1_ODD_PARITY 0U
#define XPAR_MDM_1_DATA_BITS 0U

/* Canonical definitions for peripheral MDM_1 */
#define XPAR_UARTLITE_1_DEVICE_ID 1U
#define XPAR_UARTLITE_1_BASEADDR 0x41400000U
#define XPAR_UARTLITE_1_HIGHADDR 0x41400FFFU
#define XPAR_UARTLITE_1_BAUDRATE 0U
#define XPAR_UARTLITE_1_USE_PARITY 0U
#define XPAR_UARTLITE_1_ODD_PARITY 0U
#define XPAR_UARTLITE_1_DATA_BITS 0U


/******************************************************************/
#endif  /* end of protection macro */
