
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2022.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2025 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT 

* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xbram.h"

/*
* The configuration table for devices
*/

XBram_Config XBram_ConfigTable[] =
{
	{
		XPAR_AXI_BRAM_CTRL_0_DEVICE_ID,
		XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH,
		XPAR_AXI_BRAM_CTRL_0_ECC,
		XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT,
		XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS,
		XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH,
		XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER,
		XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE,
		XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS,
		XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR,
		XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR,
		XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR,
		XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR
	},
	{
		XPAR_AXI_BRAM_CTRL_1_DEVICE_ID,
		XPAR_AXI_BRAM_CTRL_1_DATA_WIDTH,
		XPAR_AXI_BRAM_CTRL_1_ECC,
		XPAR_AXI_BRAM_CTRL_1_FAULT_INJECT,
		XPAR_AXI_BRAM_CTRL_1_CE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_1_UE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_1_ECC_STATUS_REGISTERS,
		XPAR_AXI_BRAM_CTRL_1_CE_COUNTER_WIDTH,
		XPAR_AXI_BRAM_CTRL_1_ECC_ONOFF_REGISTER,
		XPAR_AXI_BRAM_CTRL_1_ECC_ONOFF_RESET_VALUE,
		XPAR_AXI_BRAM_CTRL_1_WRITE_ACCESS,
		XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR,
		XPAR_AXI_BRAM_CTRL_1_S_AXI_HIGHADDR,
		XPAR_AXI_BRAM_CTRL_1_S_AXI_CTRL_BASEADDR,
		XPAR_AXI_BRAM_CTRL_1_S_AXI_CTRL_HIGHADDR
	},
	{
		XPAR_AXI_BRAM_CTRL_2_DEVICE_ID,
		XPAR_AXI_BRAM_CTRL_2_DATA_WIDTH,
		XPAR_AXI_BRAM_CTRL_2_ECC,
		XPAR_AXI_BRAM_CTRL_2_FAULT_INJECT,
		XPAR_AXI_BRAM_CTRL_2_CE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_2_UE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_2_ECC_STATUS_REGISTERS,
		XPAR_AXI_BRAM_CTRL_2_CE_COUNTER_WIDTH,
		XPAR_AXI_BRAM_CTRL_2_ECC_ONOFF_REGISTER,
		XPAR_AXI_BRAM_CTRL_2_ECC_ONOFF_RESET_VALUE,
		XPAR_AXI_BRAM_CTRL_2_WRITE_ACCESS,
		XPAR_AXI_BRAM_CTRL_2_S_AXI_BASEADDR,
		XPAR_AXI_BRAM_CTRL_2_S_AXI_HIGHADDR,
		XPAR_AXI_BRAM_CTRL_2_S_AXI_CTRL_BASEADDR,
		XPAR_AXI_BRAM_CTRL_2_S_AXI_CTRL_HIGHADDR
	},
	{
		XPAR_AXI_BRAM_CTRL_3_DEVICE_ID,
		XPAR_AXI_BRAM_CTRL_3_DATA_WIDTH,
		XPAR_AXI_BRAM_CTRL_3_ECC,
		XPAR_AXI_BRAM_CTRL_3_FAULT_INJECT,
		XPAR_AXI_BRAM_CTRL_3_CE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_3_UE_FAILING_REGISTERS,
		0,
		XPAR_AXI_BRAM_CTRL_3_ECC_STATUS_REGISTERS,
		XPAR_AXI_BRAM_CTRL_3_CE_COUNTER_WIDTH,
		XPAR_AXI_BRAM_CTRL_3_ECC_ONOFF_REGISTER,
		XPAR_AXI_BRAM_CTRL_3_ECC_ONOFF_RESET_VALUE,
		XPAR_AXI_BRAM_CTRL_3_WRITE_ACCESS,
		XPAR_AXI_BRAM_CTRL_3_S_AXI_BASEADDR,
		XPAR_AXI_BRAM_CTRL_3_S_AXI_HIGHADDR,
		XPAR_AXI_BRAM_CTRL_3_S_AXI_CTRL_BASEADDR,
		XPAR_AXI_BRAM_CTRL_3_S_AXI_CTRL_HIGHADDR
	},
	{
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR
	},
	{
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,
		XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR
	}
};


