diff --git a/python/waveform_generator/hdl_sim_check_results.py b/python/waveform_generator/hdl_sim_check_results.py new file mode 100644 index 0000000..88824dd --- /dev/null +++ b/python/waveform_generator/hdl_sim_check_results.py @@ -0,0 +1,36 @@ +from matplotlib import pyplot as plt +from ctypes import * +import numpy as np + + +def read_sim_output(filename, is_float=False): + fid = open(filename, "r") + lines = fid.readlines() + fid.close() + + data = [int(line) for line in lines] + data = np.array(data) + + if is_float: + as_floats = c_float * data.size + data = as_floats.from_buffer(data.astype(np.int32)) + data = np.array(data) + + return data + + +def main(): + data = read_sim_output("sim_out.bin") + data[data >= 2**15] -= 2**16 + data = data[0::2] + 1j * data[1::2] + + plt.figure() + plt.plot(data.real) + plt.plot(data.imag) + plt.title('Sim Output') + plt.grid() + + plt.show() + +if __name__ == '__main__': + main() \ No newline at end of file diff --git a/python/waveform_generator/hdl_sim_config.py b/python/waveform_generator/hdl_sim_config.py new file mode 100644 index 0000000..54d03c6 --- /dev/null +++ b/python/waveform_generator/hdl_sim_config.py @@ -0,0 +1,14 @@ + + +def main(): + fs = 750e6 + f = 10e6 + n = 4096 + + + freq = f/fs * 2**31 + + print(freq) + +if __name__ == '__main__': + main() \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv new file mode 100644 index 0000000..3e4c13b --- /dev/null +++ b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv @@ -0,0 +1,159 @@ +`resetall +`timescale 1ns / 1ps +`default_nettype none + +module gen_ofdm # ( + parameter integer AXI_ADDR_WIDTH = 32, + parameter integer AXI_DATA_WIDTH = 32 +) +( + input wire clk, + input wire reset, + axi4l_intf.slave ctrl_if, + + input wire start_pulse, + + output wire [127:0] iq_out, + output wire iq_out_valid +); + +// ------------------------------ +// AXIL Decode +// ------------------------------ +wire [AXI_ADDR_WIDTH-1 : 0] raddr; +wire [AXI_ADDR_WIDTH-1 : 0] waddr; +wire rden; +wire wren; +wire [AXI_DATA_WIDTH-1 : 0] wdata; +reg [AXI_DATA_WIDTH-1 : 0] rdata; + + +axil_slave +# ( + .DATA_WIDTH(AXI_DATA_WIDTH), + .ADDR_WIDTH(AXI_ADDR_WIDTH) +) axil_slave_i +( + // AXIL Slave + .S_AXI_ACLK(ctrl_if.clk), + .S_AXI_ARESETN(ctrl_if.resetn), + .S_AXI_AWADDR(ctrl_if.awaddr), + .S_AXI_AWPROT(ctrl_if.awprot), + .S_AXI_AWVALID(ctrl_if.awvalid), + .S_AXI_AWREADY(ctrl_if.awready), + .S_AXI_WDATA(ctrl_if.wdata), + .S_AXI_WSTRB(ctrl_if.wstrb), + .S_AXI_WVALID(ctrl_if.wvalid), + .S_AXI_WREADY(ctrl_if.wready), + .S_AXI_BRESP(ctrl_if.bresp), + .S_AXI_BVALID(ctrl_if.bvalid), + .S_AXI_BREADY(ctrl_if.bready), + .S_AXI_ARADDR(ctrl_if.araddr), + .S_AXI_ARPROT(ctrl_if.arprot), + .S_AXI_ARVALID(ctrl_if.arvalid), + .S_AXI_ARREADY(ctrl_if.arready), + .S_AXI_RDATA(ctrl_if.rdata), + .S_AXI_RRESP(ctrl_if.rresp), + .S_AXI_RVALID(ctrl_if.rvalid), + .S_AXI_RREADY(ctrl_if.rready), + + .raddr(raddr), + .waddr(waddr), + .wren(wren), + .rden(rden), + .wdata(wdata), + .rdata(rdata) +); + +// ------------------------------ +// Config Registers +// ------------------------------ +reg [31:0] reg_ctrl; +reg [31:0] reg_freq; +reg [31:0] reg_phase; +reg [31:0] reg_chips; + +always @ (posedge ctrl_if.clk) begin + if (~ctrl_if.resetn) begin + reg_ctrl <= 0; + reg_freq <= 0; + reg_phase <= 0; + end else begin + if (wren) begin + if (waddr[11:0] == 'h000) begin + reg_ctrl <= wdata; + end + if (waddr[11:0] == 'h004) begin + reg_freq <= wdata; + end + if (waddr[11:0] == 'h008) begin + reg_phase <= wdata; + end + if (waddr[11:0] == 'h00C) begin + reg_chips <= wdata; + end + // if (waddr[11:0] == 'h010) begin + // reg_phase <= wdata; + // end + end + end +end + +wire [15:0] n_samp_chip = reg_chips[15:0]; +wire [15:0] n_chip = reg_chips[31:16]; + + +// ------------------------------ +// Bla +// ------------------------------ +reg [24:0] pulse_cnt; +reg [15:0] chip_cnt; +reg [15:0] chip_ind; +reg pulse_active; +reg start_of_pulse; + +always @ (posedge clk) begin + if (reset) begin + chip_cnt <= 0; + chip_ind <= 0; + pulse_active <= 1'b0; + start_of_pulse <= 1'b0; + end else begin + start_of_pulse <= 1'b0; + if (start_pulse) begin + chip_cnt <= 0; + chip_ind <= 0; + pulse_active <= 1'b1; + start_of_pulse <= 1'b1; + end + + if (pulse_active) begin + chip_cnt <= chip_cnt + 1; + if (chip_cnt == n_samp_chip - 1) begin + chip_cnt <= 0; + chip_ind <= chip_ind + 1; + if (chip_ind == n_chip - 1) begin + chip_ind <= 0; + pulse_active = 1'b0; + end + end + end + end +end + + + +gen_sine gen_sine_i ( + .clk(clk), + .reset(reset), + .set_phase(start_of_pulse), + .valid(pulse_active), + .phase(reg_phase), + .frequency(reg_freq), + .iq_out(iq_out), + .iq_out_valid(iq_out_valid) +); + +endmodule +`resetall + diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv new file mode 100644 index 0000000..4d8e3aa --- /dev/null +++ b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv @@ -0,0 +1,72 @@ +`resetall +`timescale 1ns / 1ps +`default_nettype none + +// Generates 4 output samples in parallel +// Samples are 16 bit I and 16 bit Q, 32 bits per sample + +module gen_sine +( + input wire clk, + input wire reset, + input wire set_phase, + input wire valid, + input wire [31:0] phase, + input wire [31:0] frequency, + + output wire [127:0] iq_out, + output wire iq_out_valid +); + +reg set_phase_q; +reg valid_q; +reg valid_q2; +reg [31:0] phase_q; +reg [31:0] frequency_q; +reg [127:0] iq_out_i; + +always @ (posedge clk) begin + set_phase_q <= set_phase; + phase_q <= phase; + frequency_q <= frequency; + valid_q <= valid; + valid_q2 <= valid_q; +end + +genvar i; +generate + for (i = 0; i < 4; i = i + 1) begin + + reg [31:0] phase_accum; + + always @ (posedge clk) begin + if (reset) begin + phase_accum <= 0; + end else if (valid_q) begin + if (set_phase_q) begin + phase_accum <= phase_q + i*frequency_q; + end else begin + phase_accum <= phase_accum + 4*frequency_q; + end + end + end + + + wire [39:0] cordic_phase_in = {{8{phase_accum[31]}}, phase_accum}; + + wfg_cordic wfg_cordic_i ( + .aclk(clk), + .s_axis_phase_tvalid(valid_q2), + .s_axis_phase_tdata(cordic_phase_in), + .m_axis_dout_tvalid(iq_out_valid), + .m_axis_dout_tdata(iq_out_i[i*32+31:i*32]) + ); + + end +endgenerate + +assign iq_out = iq_out_i; + +endmodule +`resetall + \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/sources_1/ip/axi_vip_0/axi_vip_0.xci b/radar_alinx_kintex.srcs/sources_1/ip/axi_vip_0/axi_vip_0.xci new file mode 100644 index 0000000..c786d1b --- /dev/null +++ b/radar_alinx_kintex.srcs/sources_1/ip/axi_vip_0/axi_vip_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_vip_0", + "component_reference": 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"is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv b/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv new file mode 100644 index 0000000..0fb6177 --- /dev/null +++ b/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv @@ -0,0 +1,119 @@ +`timescale 1ns / 1ps + +import axi_vip_pkg::*; +import axi_vip_0_pkg::*; + +module testbench(); + + +reg clk; +reg reset; +reg resetn; + +assign resetn = ~reset; + +localparam T = 4; +always #(T/2) clk=~clk; + +axi4l_intf # ( + .AXI_ADDR_WIDTH(32), + .AXI_DATA_WIDTH(32) +) +ctrl_if ( + .clk(clk), + .resetn(resetn) +); + +axi_vip_0_mst_t vip_mst; +xil_axi_resp_t resp; + +axi_vip_0 axi_vip_inst ( + .aclk(clk), + .aresetn(resetn), + .m_axi_awaddr( ctrl_if.awaddr ), + .m_axi_awprot( ctrl_if.awprot ), + .m_axi_awvalid( ctrl_if.awvalid ), + .m_axi_awready( ctrl_if.awready ), + .m_axi_wdata( ctrl_if.wdata ), + .m_axi_wstrb( ctrl_if.wstrb ), + .m_axi_wvalid( ctrl_if.wvalid ), + .m_axi_wready( ctrl_if.wready ), + .m_axi_bresp( ctrl_if.bresp ), + .m_axi_bvalid( ctrl_if.bvalid ), + .m_axi_bready( ctrl_if.bready ), + .m_axi_araddr( ctrl_if.araddr ), + .m_axi_arprot( ctrl_if.arprot ), + .m_axi_arvalid( ctrl_if.arvalid ), + .m_axi_arready( ctrl_if.arready ), + .m_axi_rdata( ctrl_if.rdata ), + .m_axi_rresp( ctrl_if.rresp ), + .m_axi_rvalid( ctrl_if.rvalid ), + .m_axi_rready( ctrl_if.rready ) + +); + +initial begin + vip_mst = new("vip_mst", axi_vip_inst.inst.IF); + vip_mst.start_master(); +end + +wire [127:0] iq_out; +wire iq_out_valid; +reg start_pulse; + +gen_ofdm dut ( + .clk(clk), + .reset(reset), + + .ctrl_if(ctrl_if), + .start_pulse(start_pulse), + .iq_out(iq_out), + .iq_out_valid(iq_out_valid) +); + +int fid_out; + +initial begin + reset = 1'b1; + clk = 1'b0; + start_pulse = 1'b0; + $display($time, " << Starting the Simulation >>"); + + // Open Output File + fid_out = $fopen("/home/bkiedinger/projects/castelion/radar_alinx_kintex/python/waveform_generator/sim_out.bin", "wb"); + + // Release Reset + repeat(25) @(posedge clk); + reset = 1'b0; + repeat(25) @(posedge clk); + + // Set Control Regs + vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp); + vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 28633115, resp); + vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 0, resp); + vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, ('h00010400), resp); + + + repeat(25) @(posedge clk); + start_pulse = 1'b1; + @(posedge clk); + start_pulse = 1'b0; + + +end + +always @ (posedge clk) begin + if ( iq_out_valid == 1'b1 ) begin + $fwrite(fid_out, "%d\n", iq_out[15:0] ); + $fwrite(fid_out, "%d\n", iq_out[31:16]); + $fwrite(fid_out, "%d\n", iq_out[47:32]); + $fwrite(fid_out, "%d\n", iq_out[63:48]); + $fwrite(fid_out, "%d\n", iq_out[79:64]); + $fwrite(fid_out, "%d\n", iq_out[95:80]); + $fwrite(fid_out, "%d\n", iq_out[111:96]); + $fwrite(fid_out, "%d\n", iq_out[127:112]); + end +end + +endmodule +`resetall diff --git a/radar_alinx_kintex.xpr b/radar_alinx_kintex.xpr index 52f46cd..f888ad8 100755 --- a/radar_alinx_kintex.xpr +++ b/radar_alinx_kintex.xpr @@ -56,20 +56,20 @@