diff --git a/python/radar_manager.py b/python/radar_manager.py index ba4c20d..abffeda 100755 --- a/python/radar_manager.py +++ b/python/radar_manager.py @@ -72,8 +72,8 @@ class RadarManager: # Update UDP packet size # self.packet_size = 4096 - self.packet_size = 16 - self.axi_write_register(0x4005001C, self.packet_size) + # self.packet_size = 16 + # self.axi_write_register(0x4005001C, self.packet_size) self.reset_10g_udp() @@ -403,6 +403,9 @@ class RadarManager: self.load_waveform(0, 1, 0.05, tx_num_samples, num_wf) self.load_waveform(1, 1, 0.05, tx_num_samples, num_wf) + total_bytes_cpi = num_pulses * num_samples * 4 + self.axi_write_register(0x4005001C, total_bytes_cpi) + num_samples_quant = int(self.packet_size / 4) if num_samples % num_samples_quant > 0: print('Packet Size Invalid') diff --git a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc index fa286dd..2cb112e 100755 --- a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc +++ b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc @@ -283,11 +283,11 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p #set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p] # Works with the board at my house -#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] -#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] +set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] +set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] # Works with the board Chris has (broken USB UART) -set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] -set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] +#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] +#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p] set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p] diff --git a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp index 1182220..47756ff 100755 Binary files a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp and b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp differ diff --git a/vitis/bootloader/_ide/bitstream/top.mmi b/vitis/bootloader/_ide/bitstream/top.mmi index 61f4942..8092ce5 100644 --- a/vitis/bootloader/_ide/bitstream/top.mmi +++ b/vitis/bootloader/_ide/bitstream/top.mmi @@ -13,49 +13,49 @@ - + - + - + - + - + - + - + - + @@ -69,97 +69,97 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/vitis/bootloader/_ide/hwspec.checksum b/vitis/bootloader/_ide/hwspec.checksum index d1b9974..7dd77d9 100644 --- a/vitis/bootloader/_ide/hwspec.checksum +++ b/vitis/bootloader/_ide/hwspec.checksum @@ -1 +1 @@ -308456516 \ No newline at end of file +2843589716 \ No newline at end of file diff --git a/vitis/bootloader/bootloader.prj b/vitis/bootloader/bootloader.prj index ecb97b1..e3e22e8 100644 --- a/vitis/bootloader/bootloader.prj +++ b/vitis/bootloader/bootloader.prj @@ -1,5 +1,5 @@ - + diff --git a/vitis/radar/radar.prj b/vitis/radar/radar.prj index fe1b1a7..06d9c01 100755 --- a/vitis/radar/radar.prj +++ b/vitis/radar/radar.prj @@ -1,5 +1,5 @@ - + diff --git a/vitis/radar/src/data_converter_setup.c b/vitis/radar/src/data_converter_setup.c index 7d57c32..e49e389 100755 --- a/vitis/radar/src/data_converter_setup.c +++ b/vitis/radar/src/data_converter_setup.c @@ -525,23 +525,23 @@ void setup_data_converter() { #ifndef IBERT_TESTING // Update FPGA TX Transceiver settings - set_lane_cal(0, 0, 0, 11); - set_lane_cal(1, 10, 5, 11); - set_lane_cal(2, 5, 0, 11); - set_lane_cal(3, 0, 0, 11); - set_lane_cal(4, 0, 0, 11); - set_lane_cal(5, 0, 0, 11); - set_lane_cal(6, 12, 0, 11); - set_lane_cal(7, 0, 0, 11); +// set_lane_cal(0, 0, 0, 11); +// set_lane_cal(1, 10, 5, 11); +// set_lane_cal(2, 5, 0, 11); +// set_lane_cal(3, 0, 0, 11); +// set_lane_cal(4, 0, 0, 11); +// set_lane_cal(5, 0, 0, 11); +// set_lane_cal(6, 12, 0, 11); +// set_lane_cal(7, 0, 0, 11); -// set_lane_cal(0, 9, 0, 7); -// set_lane_cal(1, 9, 0, 7); -// set_lane_cal(2, 9, 0, 7); -// set_lane_cal(3, 9, 0, 7); -// set_lane_cal(4, 9, 0, 7); -// set_lane_cal(5, 9, 0, 7); -// set_lane_cal(6, 9, 0, 7); -// set_lane_cal(7, 9, 0, 7); + set_lane_cal(0, 9, 0, 7); + set_lane_cal(1, 9, 0, 7); + set_lane_cal(2, 9, 0, 7); + set_lane_cal(3, 9, 0, 7); + set_lane_cal(4, 9, 0, 7); + set_lane_cal(5, 9, 0, 7); + set_lane_cal(6, 9, 0, 7); + set_lane_cal(7, 9, 0, 7); vTaskDelay(100); int subclass = jtx_param[uc][0].jesd_subclass; diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h index 864f4b5..6415623 100644 --- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h +++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h @@ -496,8 +496,8 @@ #define PLATFORM_MB /******************************************************************/ -#define STDIN_BASEADDRESS 0x41400000 -#define STDOUT_BASEADDRESS 0x41400000 +#define STDIN_BASEADDRESS 0x40000000 +#define STDOUT_BASEADDRESS 0x40000000 /******************************************************************/ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a index 478417c..8b470ba 100644 Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a differ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a index 29ba479..3510983 100644 Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a differ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss index 14165d1..55fe265 100644 --- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss +++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss @@ -6,8 +6,8 @@ BEGIN OS PARAMETER OS_NAME = freertos10_xilinx PARAMETER OS_VER = 1.12 PARAMETER PROC_INSTANCE = microblaze_0 - PARAMETER stdin = mdm_1 - PARAMETER stdout = mdm_1 + PARAMETER stdin = axi_uartlite_0 + PARAMETER stdout = axi_uartlite_0 PARAMETER total_heap_size = 2097152 END diff --git a/vitis/top/platform.spr b/vitis/top/platform.spr index c14efcb..5f3a325 100755 --- a/vitis/top/platform.spr +++ b/vitis/top/platform.spr @@ -1 +1 @@ -{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} +{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} diff --git a/vitis/top/platform.tcl b/vitis/top/platform.tcl index 8125365..e9d4c1b 100755 --- a/vitis/top/platform.tcl +++ b/vitis/top/platform.tcl @@ -186,3 +186,27 @@ bsp write bsp reload catch {bsp regenerate} platform generate +bsp config stdin "axi_uartlite_0" +bsp config stdout "axi_uartlite_0" +bsp write +bsp reload +catch {bsp regenerate} +platform generate -domains freertos10_xilinx_microblaze_0 +bsp write +bsp reload +platform active {top} +bsp reload +bsp reload +platform generate -domains +bsp config lwip_tcp_keepalive "false" +bsp config stdin "mdm_1" +bsp write +bsp reload +catch {bsp regenerate} +platform generate -domains freertos10_xilinx_microblaze_0 +bsp config stdin "axi_uartlite_0" +bsp write +bsp reload +catch {bsp regenerate} +platform generate -domains freertos10_xilinx_microblaze_0 +platform active {top}