diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v b/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.sv
similarity index 100%
rename from radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v
rename to radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.sv
diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.v b/radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.sv
similarity index 100%
rename from radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.v
rename to radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.sv
diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v b/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv
similarity index 100%
rename from radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v
rename to radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.sv
diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/top.v b/radar_alinx_kintex.srcs/sources_1/hdl/top.sv
similarity index 99%
rename from radar_alinx_kintex.srcs/sources_1/hdl/top.v
rename to radar_alinx_kintex.srcs/sources_1/hdl/top.sv
index f1f36a5..b0cd3f2 100755
--- a/radar_alinx_kintex.srcs/sources_1/hdl/top.v
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/top.sv
@@ -948,7 +948,7 @@ module top #
     wire [127:0] iq_out;
     wire iq_out_valid;
 
-    gen_ofdm dut (
+    gen_ofdm waveform_gen_i (
         .clk(jesd_core_clk),    
         .reset(1'b0),
 
diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/util_reg.v b/radar_alinx_kintex.srcs/sources_1/hdl/util_reg.sv
similarity index 100%
rename from radar_alinx_kintex.srcs/sources_1/hdl/util_reg.v
rename to radar_alinx_kintex.srcs/sources_1/hdl/util_reg.sv
diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v b/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.sv
similarity index 100%
rename from radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v
rename to radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.sv
diff --git a/radar_alinx_kintex.xpr b/radar_alinx_kintex.xpr
index 102c8f6..e8bc643 100755
--- a/radar_alinx_kintex.xpr
+++ b/radar_alinx_kintex.xpr
@@ -458,15 +458,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/hdl/digital_rx_chain.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/digital_rx_chain.sv">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/hdl/ethernet_top.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/ethernet_top.sv">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -486,36 +486,28 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/hdl/timing_engine.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/timing_engine.sv">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/hdl/util_reg.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/util_reg.sv">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/hdl/top.v">
-        <FileInfo SFType="SVerilog">
+      <File Path="$PSRCDIR/sources_1/hdl/top.sv">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/hdl/waveform_gen.v">
-        <FileInfo SFType="SVerilog">
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
+      <File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -531,7 +523,15 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/ip/width_converter/width_converter.xci">
+      <File Path="$PSRCDIR/sources_1/ip/clock_converter/clock_converter.xci">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/hdl/waveform_gen.sv">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>