diff --git a/python/waveform_generator/hdl_sim_check_results.py b/python/waveform_generator/hdl_sim_check_results.py index 88824dd..8a85bc9 100644 --- a/python/waveform_generator/hdl_sim_check_results.py +++ b/python/waveform_generator/hdl_sim_check_results.py @@ -2,6 +2,8 @@ from matplotlib import pyplot as plt from ctypes import * import numpy as np +from read_data_file import db20n + def read_sim_output(filename, is_float=False): fid = open(filename, "r") @@ -24,10 +26,27 @@ def main(): data[data >= 2**15] -= 2**16 data = data[0::2] + 1j * data[1::2] + + x = np.fft.fft(data) + f_axis = np.fft.fftfreq(x.size, d=1/750) + + x = np.fft.fftshift(x) + f_axis = np.fft.fftshift(f_axis) + + + plt.figure() + plt.plot(f_axis, db20n(x)) + + plt.figure() plt.plot(data.real) plt.plot(data.imag) - plt.title('Sim Output') + plt.title('HDL Sim Output - IQ') + plt.grid() + + plt.figure() + plt.plot(np.unwrap(np.angle(data))) + plt.title('HDL Sim Output - Phase') plt.grid() plt.show() diff --git a/python/waveform_generator/hdl_sim_config.py b/python/waveform_generator/hdl_sim_config.py index 54d03c6..909dc86 100644 --- a/python/waveform_generator/hdl_sim_config.py +++ b/python/waveform_generator/hdl_sim_config.py @@ -5,10 +5,16 @@ def main(): f = 10e6 n = 4096 + start_freq = -20507812.5 + start_freq = start_freq/fs * 2**32 + if (start_freq < 0): + start_freq += 2**32 + print(start_freq) - freq = f/fs * 2**31 + delta_freq = 5859375 + delta_freq = delta_freq/fs * 2**32 + print(delta_freq) - print(freq) if __name__ == '__main__': main() \ No newline at end of file diff --git a/python/waveform_generator/wf_ofdm.py b/python/waveform_generator/wf_ofdm.py index 0fdf533..e6110e4 100644 --- a/python/waveform_generator/wf_ofdm.py +++ b/python/waveform_generator/wf_ofdm.py @@ -118,8 +118,8 @@ def wg_ofdm(): do_agile = False n_sub_cpi = 1 n_tx = 1 - n_rx = 2 - n_pol = 2 + n_rx = 1 + n_pol = 1 n_samp = 64 n_samp_chip = 8 @@ -237,6 +237,7 @@ def wg_ofdm(): get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, p)) print(baseband/1e6) + print(start_phase) pulse, _phase = get_waveform(baseband, start_phase, @@ -247,15 +248,27 @@ def wg_ofdm(): n_samp * tx_sample_rate_multiplier, f_samp * tx_sample_rate_multiplier) + print('Num Chips', baseband.size) + print('Start Freq', baseband[0]) + print('Delta Freq', np.unique(np.diff(baseband))) + pulse = np.squeeze(pulse) plt.figure() - plt.plot(pulse[0, :].real) - plt.plot(pulse[0, :].imag) + plt.plot(pulse.real) + plt.plot(pulse.imag) + plt.title('Python Output - IQ') + plt.grid() plt.figure() - plt.plot(pulse[1, :].real) - plt.plot(pulse[1, :].imag) + plt.plot(np.unwrap(np.angle(pulse))) + # plt.plot(np.angle(pulse), '.-') + plt.title('Python Output - Phase') + plt.grid() + + # plt.figure() + # plt.plot(pulse[1, :].real) + # plt.plot(pulse[1, :].imag) plt.show() diff --git a/python/waveform_generator/wf_ofdm_simple.py b/python/waveform_generator/wf_ofdm_simple.py new file mode 100644 index 0000000..4c1156a --- /dev/null +++ b/python/waveform_generator/wf_ofdm_simple.py @@ -0,0 +1,47 @@ +import numpy as np +from matplotlib import pyplot as plt + + +def wg_ofdm(): + + tx_sample_rate = 750e6 + rx_decimation = 16 + rx_sample_rate = tx_sample_rate / rx_decimation + n_rx_samp_per_chip = 16 # Keep at >= x2 of num_chips and start phase will always be 0, if num chips is power of 2? + num_chips = 8 + n_tx_samp_per_chip = n_rx_samp_per_chip * rx_decimation + n_tx_samp_per_pulse = n_tx_samp_per_chip * num_chips + + print(n_tx_samp_per_chip / 4) + + chip_freq = (np.arange(num_chips) - num_chips//2 + 0.5)/num_chips * rx_sample_rate + + # First, generate simple in order waveform + freq = np.repeat(chip_freq, n_tx_samp_per_chip) + + phase = freq / tx_sample_rate + phase = np.cumsum(np.concatenate([[0], phase])) + phase = phase[0:-1] + + # Extract the start phases of each chip, ideally these are always 0 + chip_start_phase = phase[0::n_tx_samp_per_chip] % 1 + print(chip_start_phase) + print(chip_start_phase * 2**16) + print(chip_freq) + + x = np.exp(1j * 2 * np.pi * phase) + + plt.figure() + plt.plot(x.real) + plt.plot(x.imag) + + plt.figure() + plt.plot(np.unwrap(np.angle(x))) + + plt.show() + + + return + +if __name__ == '__main__': + wg_ofdm() \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv b/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv new file mode 100644 index 0000000..1ac93ad --- /dev/null +++ b/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv @@ -0,0 +1,28 @@ +`resetall +`timescale 1ns / 1ps +`default_nettype none + +module delay_shift_register #( + parameter DELAY_CYCLES = 4 +) ( + input wire clk, + input wire reset, + input wire data_in, + output wire data_out +); + + // Declare a register to hold the shifted data + reg [DELAY_CYCLES-1:0] shift_reg; + + always @ (posedge clk) begin + if (reset) begin + shift_reg <= '0; + end else begin + shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in}; + end + end + + assign data_out = shift_reg[DELAY_CYCLES-1]; + +endmodule +`resetall \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv index 3e4c13b..2973495 100644 --- a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv +++ b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv @@ -2,6 +2,75 @@ `timescale 1ns / 1ps `default_nettype none +// Outputs 4 IQ samples in parallel for connection to DAC interface + +// start_pulse - Kicks off output for a single pulse, expected to be a single clock wide +// start_table_irq - This is used to indicate to software that playback from the top of the sequence table has begin +// half_table_irq - This is used to indicate to software that playback from the mid point of the sequence table has begin +// The mid point is defined as (n_total_chips >> 1) +// These interrupts are used in combination to enable software to continually update the sequence table in a ping pong +// fashion while the system is operating + +/* +* ADDR=0x0000 Control Register (reg_ctrl) +* Currently unused +*/ + +/* +* ADDR=0x0004 Start Frequency Register (reg_start_freq) +* Sets the value of the lowest frequency chip, final chip frequincies are calculated using this value, +* the delta frequency, and the sequence number from the ram +* Bit 31:0: Frequency +*/ + +/* +* ADDR=0x0008 Chip Description 0 (reg_chips_0) +* Bit 15:0: Number of total chips in the sequence table +*/ + +/* +* ADDR=0x000C Chip Description 1 (reg_chips_1) +* Bit 15:0: Number of DAC samples per chip divided by 4 (due to parallel output of 4 samples) +* Bit 31:16: Number of Chips per Pulse +*/ + +/* +* ADDR=0x0010 Delta Frequency Register (reg_start_freq) +* Sets the delta frequency value between chips, final chip frequincies are calculated using this value, +* the delta frequency, and the sequence number from the ram +* Bit 31:0: Delta Frequency +*/ + +/* +* ADDR=0x0014 Currently Unused +*/ + +/* +* ADDR=0x0018 Sequence Memory Write Address +* Sets the write address of the sequence memory +* Bit 15:0: BRAM Write Address +*/ + +/* +* ADDR=0x001C Sequence Memory Write Data +* Write a value into the sequence BRAM, and automatically increments the address. +* Repeated writes to this registers store values in sequential address in the BRAM +* Bit 15:0: BRAM Write Data +*/ + +/* +* ADDR=0x0020 Start Phase Memory Write Address +* Sets the write address of the sequence memory +* Bit 15:0: BRAM Write Address +*/ + +/* +* ADDR=0x0024 Start Phase Memory Write Data +* Write a value into the sequence BRAM, and automatically increments the address. +* Repeated writes to this registers store values in sequential address in the BRAM +* Bit 15:0: BRAM Write Data +*/ + module gen_ofdm # ( parameter integer AXI_ADDR_WIDTH = 32, parameter integer AXI_DATA_WIDTH = 32 @@ -13,10 +82,50 @@ module gen_ofdm # ( input wire start_pulse, + output wire start_table_irq, + output wire half_table_irq, output wire [127:0] iq_out, output wire iq_out_valid ); +// ------------------------------ +// BRAM for holding sequence +// ------------------------------ +wire [15:0] read_addr; +wire [15:0] read_sequence; +reg bram_we; +reg [15:0] bram_waddr; +reg [15:0] bram_wdata; + +ofdm_sequence_ram sequence_ram ( + .clka(ctrl_if.clk), + .ena(1'b1), + .wea(bram_we), + .addra(bram_waddr), + .dina(bram_wdata), + .clkb(clk), + .enb(1'b1), + .addrb(read_addr), + .doutb(read_sequence) +); + +wire [15:0] read_phase; +reg phase_bram_we; +reg [15:0] phase_bram_waddr; +reg [15:0] phase_bram_wdata; + +ofdm_sequence_ram phase_ram ( + .clka(ctrl_if.clk), + .ena(1'b1), + .wea(phase_bram_we), + .addra(phase_bram_waddr), + .dina(phase_bram_wdata), + .clkb(clk), + .enb(1'b1), + .addrb(read_addr), + .doutb(read_phase) +); + // ------------------------------ // AXIL Decode // ------------------------------ @@ -69,39 +178,79 @@ axil_slave // Config Registers // ------------------------------ reg [31:0] reg_ctrl; -reg [31:0] reg_freq; -reg [31:0] reg_phase; -reg [31:0] reg_chips; +reg [31:0] reg_start_freq; +reg [31:0] reg_delta_freq; +reg [31:0] reg_delta_phase; +reg [31:0] reg_chips_0; +reg [31:0] reg_chips_1; always @ (posedge ctrl_if.clk) begin if (~ctrl_if.resetn) begin reg_ctrl <= 0; - reg_freq <= 0; - reg_phase <= 0; + reg_start_freq <= 0; + reg_delta_freq <= 0; + reg_chips_0 <= 0; + reg_chips_1 <= 0; + reg_delta_phase <= 0; + bram_we <= 1'b0; + bram_waddr <= 0; + bram_wdata <= 0; + phase_bram_we <= 1'b0; + phase_bram_waddr <= 0; + phase_bram_wdata <= 0; end else begin + + bram_we <= 1'b0; + if (bram_we) begin + bram_waddr <= bram_waddr + 1; + end + + phase_bram_we <= 1'b0; + if (phase_bram_we) begin + phase_bram_waddr <= phase_bram_waddr + 1; + end + if (wren) begin if (waddr[11:0] == 'h000) begin reg_ctrl <= wdata; end if (waddr[11:0] == 'h004) begin - reg_freq <= wdata; + reg_start_freq <= wdata; end if (waddr[11:0] == 'h008) begin - reg_phase <= wdata; + reg_chips_0 <= wdata; end if (waddr[11:0] == 'h00C) begin - reg_chips <= wdata; + reg_chips_1 <= wdata; end - // if (waddr[11:0] == 'h010) begin - // reg_phase <= wdata; - // end + if (waddr[11:0] == 'h010) begin + reg_delta_freq <= wdata; + end + if (waddr[11:0] == 'h014) begin + reg_delta_phase <= wdata; + end + if (waddr[11:0] == 'h018) begin + bram_waddr <= wdata; + end + if (waddr[11:0] == 'h01C) begin + bram_we <= 1'b1; + bram_wdata <= wdata; + end + if (waddr[11:0] == 'h020) begin + phase_bram_waddr <= wdata; + end + if (waddr[11:0] == 'h024) begin + phase_bram_we <= 1'b1; + phase_bram_wdata <= wdata; + end end end end -wire [15:0] n_samp_chip = reg_chips[15:0]; -wire [15:0] n_chip = reg_chips[31:16]; +wire [15:0] n_total_chips = reg_chips_0[15:0]; +wire [15:0] n_samp_per_chip = reg_chips_1[15:0]; +wire [15:0] n_chip_per_pulse = reg_chips_1[31:16]; // ------------------------------ // Bla @@ -109,47 +258,116 @@ wire [15:0] n_chip = reg_chips[31:16]; reg [24:0] pulse_cnt; reg [15:0] chip_cnt; reg [15:0] chip_ind; +reg [15:0] chip_per_pulse_cnt; reg pulse_active; -reg start_of_pulse; +wire set_phase; +reg start_irq; +reg half_irq; + +assign read_addr = chip_ind; +assign start_table_irq = start_irq; +assign half_table_irq = half_irq; always @ (posedge clk) begin if (reset) begin chip_cnt <= 0; chip_ind <= 0; + chip_per_pulse_cnt <= 0; pulse_active <= 1'b0; - start_of_pulse <= 1'b0; end else begin - start_of_pulse <= 1'b0; if (start_pulse) begin chip_cnt <= 0; - chip_ind <= 0; + chip_per_pulse_cnt <= 0; pulse_active <= 1'b1; - start_of_pulse <= 1'b1; end if (pulse_active) begin chip_cnt <= chip_cnt + 1; - if (chip_cnt == n_samp_chip - 1) begin + if (chip_cnt == n_samp_per_chip - 1) begin chip_cnt <= 0; chip_ind <= chip_ind + 1; - if (chip_ind == n_chip - 1) begin - chip_ind <= 0; - pulse_active = 1'b0; + chip_per_pulse_cnt <= chip_per_pulse_cnt + 1; + if (chip_per_pulse_cnt == n_chip_per_pulse - 1) begin + chip_per_pulse_cnt <= 0; + pulse_active <= 1'b0; + if (chip_ind == n_total_chips-1) begin + chip_ind <= 0; + end end end end + + start_irq <= 1'b0; + if (pulse_active) begin + if (chip_cnt == 0) begin + if (chip_ind == 0) begin + start_irq <= 1'b1; + end + end + end + + half_irq <= 1'b0; + if (pulse_active) begin + if (chip_cnt == 0) begin + if (chip_ind == (n_total_chips >> 1)) begin + half_irq <= 1'b1; + end + end + end + + end end +wire [47:0] mult_out; +wire [31:0] chip_delta_freq; +ofdm_freq_mult freq_mult ( + .CLK(clk), + .A(reg_delta_freq), + .B(read_sequence), + .P(mult_out) +); +assign chip_delta_freq = mult_out[31:0]; + +reg [31:0] chip_freq; +reg [15:0] read_phase_q; +reg [15:0] read_phase_q2; +always @ (posedge clk) begin + chip_freq <= chip_delta_freq + reg_start_freq; + read_phase_q <= read_phase; + read_phase_q2 <= read_phase_q; +end + +assign set_phase = (chip_cnt == 0) ? pulse_active : 1'b0; + +wire pulse_active_delayed; +delay_shift_register # ( + .DELAY_CYCLES(4) +) delay_valid ( + .clk(clk), + .reset(reset), + .data_in(pulse_active), + .data_out(pulse_active_delayed) +); + +wire set_phase_delayed; +delay_shift_register # ( + .DELAY_CYCLES(4) +) delay_set_phase ( + .clk(clk), + .reset(reset), + .data_in(set_phase), + .data_out(set_phase_delayed) +); gen_sine gen_sine_i ( .clk(clk), .reset(reset), - .set_phase(start_of_pulse), - .valid(pulse_active), - .phase(reg_phase), - .frequency(reg_freq), + .set_phase(set_phase_delayed), + .valid(pulse_active_delayed), + .phase({read_phase_q2, 16'h0000}), + .frequency(chip_freq), .iq_out(iq_out), .iq_out_valid(iq_out_valid) ); diff --git a/radar_alinx_kintex.srcs/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci b/radar_alinx_kintex.srcs/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci new file mode 100644 index 0000000..825027b --- /dev/null +++ b/radar_alinx_kintex.srcs/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci @@ -0,0 +1,160 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ofdm_freq_mult", + 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"mode": "slave", + "parameters": { + "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ADDR": [ { "physical_name": "addrb" } ], + "CLK": [ { "physical_name": "clkb" } ], + "DOUT": [ { "physical_name": "doutb" } ], + "EN": [ { "physical_name": "enb" } ] + } + } + }, + "memory_maps": { + "S_1": { + "address_blocks": { + "Mem0": { + "base_address": "0", + "range": "4096", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv b/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv index 0fb6177..4b309f6 100644 --- a/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv +++ b/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv @@ -73,6 +73,11 @@ gen_ofdm dut ( int fid_out; +reg [15:0] n_samp_per_chip; +reg [15:0] n_chip_per_pulse; +reg [15:0] n_total_chips; +reg [15:0] n_pulses; + initial begin reset = 1'b1; clk = 1'b0; @@ -87,21 +92,52 @@ initial begin reset = 1'b0; repeat(25) @(posedge clk); + n_samp_per_chip = 64; + n_chip_per_pulse = 8; + n_total_chips = 16; + n_pulses = 4; + + // Set Control Regs - vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp); - vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 28633115, resp); - vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 0, resp); - vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, ('h00010400), resp); + vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 4177526784, resp); // Start Freq + vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, n_total_chips, resp); + vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, (n_chip_per_pulse << 16) | n_samp_per_chip, resp); + vip_mst.AXI4LITE_WRITE_BURST(16'h0010, 0, 33554432, resp); // Delta Freq + + // Load Sequence + vip_mst.AXI4LITE_WRITE_BURST(16'h0018, 0, 0, resp); // Set Start Address + for (int i = 0; i < 8; i = i + 1) begin + vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp); // Load Chirp Sequence + end + for (int i = 0; i < 8; i = i + 1) begin + vip_mst.AXI4LITE_WRITE_BURST(16'h001C, 0, i, resp); // Load Chirp Sequence + end + + // Load Start Phases + // vip_mst.AXI4LITE_WRITE_BURST(16'h0020, 0, 0, resp); // Set Start Address + // for (int i = 0; i < 8; i = i + 1) begin + // vip_mst.AXI4LITE_WRITE_BURST(16'h0024, 0, i, resp); // Load Chirp Sequence + // end + + for (int i = 0; i < n_pulses; i = i + 1) begin + + repeat(1000) @(posedge clk); + start_pulse = 1'b1; + @(posedge clk); + start_pulse = 1'b0; + + repeat(n_samp_per_chip * n_chip_per_pulse) @(posedge clk); + end - repeat(25) @(posedge clk); - start_pulse = 1'b1; - @(posedge clk); - start_pulse = 1'b0; - + repeat(10000) @(posedge clk); + $fclose(fid_out); + $display($time, " << Ending the Simulation >>"); + $stop; end +// Write output data to file always @ (posedge clk) begin if ( iq_out_valid == 1'b1 ) begin $fwrite(fid_out, "%d\n", iq_out[15:0] ); diff --git a/radar_alinx_kintex.xpr b/radar_alinx_kintex.xpr index f888ad8..86dcaff 100755 --- a/radar_alinx_kintex.xpr +++ b/radar_alinx_kintex.xpr @@ -56,20 +56,20 @@