diff --git a/python/data_structures.py b/python/data_structures.py index c12c299..fd00e35 100755 --- a/python/data_structures.py +++ b/python/data_structures.py @@ -8,6 +8,7 @@ ACK_MSG = 4 NACK_MSG = 5 AXI_WRITE_REG_BURST = 6 RF_SPI_WRITE = 7 +CONFIG_FLASH_WRITE = 8 SET_AD9081_DAC_NCO = 128 SET_AD9081_ADC_NCO = 129 SET_LANE_MAP = 130 @@ -92,8 +93,22 @@ class WriteRegBurstType(Structure): ("data", c_uint32 * MAX_BURST_LENGTH) ] - def __init__(self): - init_header(self, AXI_WRITE_REG_BURST) + def __init__(self, msg_id=AXI_WRITE_REG_BURST): + init_header(self, msg_id) + self.address = 0 + self.length = 0 + +class ConfigFlashWriteType(Structure): + _pack_ = 1 + _fields_ = [ + ("header", Header), + ("address", c_uint32), + ("length", c_uint32), + ("data", c_uint8 * MAX_BURST_LENGTH) + ] + + def __init__(self, msg_id=CONFIG_FLASH_WRITE): + init_header(self, msg_id) self.address = 0 self.length = 0 diff --git a/python/radar_manager.py b/python/radar_manager.py index 755b2eb..6eaacd2 100755 --- a/python/radar_manager.py +++ b/python/radar_manager.py @@ -244,6 +244,21 @@ class RadarManager: return + def config_flash_write(self, address, data): + # Make sure address is word aligned + address -= (address % 4) + + # Form message + msg = msg_types.ConfigFlashWriteType(msg_id=msg_types.CONFIG_FLASH_WRITE) + msg.address = address + msg.length = len(data) + for i in range(len(data)): + msg.data[i] = data[i] + + self.send_message(msg) + + return + def load_waveform(self, ch, amp, bw, pw): # addr = 0x0010000 + 0x0010000 * ch diff --git a/python/test_cpi.py b/python/test_cpi.py index 3c11c61..8f23e9e 100755 --- a/python/test_cpi.py +++ b/python/test_cpi.py @@ -2,6 +2,7 @@ import ctypes import time import numpy as np from matplotlib import pyplot as plt +import ipaddress import data_structures import radar_manager @@ -28,7 +29,7 @@ def db20n(x): def main(): print('Hello') - radar = radar_manager.RadarManager() + radar = radar_manager.RadarManager(host='192.168.1.201', port=5002) clk = radar_manager.TIMING_ENGINE_FREQ @@ -41,6 +42,14 @@ def main(): radar.ad9081_write_reg(0x0A0A, 0x60) print(hex(radar.ad9081_read_reg(0x0A0A))) + # Program Config Flash IP Address + ip = ipaddress.IPv4Address('192.168.1.201') + mask = ipaddress.IPv4Address('255.255.255.0') + gw = ipaddress.IPv4Address('192.168.1.1') + port = 5002 + data = bytes(np.array([ip, mask, gw, port], dtype=np.uint32)) + radar.config_flash_write(0xf00000, data) + # CPI Parameters (timing values are in clk ticks) num_pulses = 128 diff --git a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc index 17d6f2f..b15ad0e 100755 --- a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc +++ b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc @@ -283,21 +283,17 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p #set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p] # Works with the board at my house -set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] -set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] +#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] +#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] +# Works with the board Chris has (broken USB UART) +set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] +set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] + set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p] set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p] set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n] create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p] - -# Works with the board Chris has -#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] -#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] -#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p] -#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p] -#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n] -#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p] -##create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p] +#create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p] #set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}] #set_property PACKAGE_PIN H2 [get_ports {jesd_rxp_in[1]}] diff --git a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp index 730fc81..ab3fe7a 100755 Binary files a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp and b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp differ diff --git a/vitis/radar/radar.prj b/vitis/radar/radar.prj index 06d9c01..fe1b1a7 100755 --- a/vitis/radar/radar.prj +++ b/vitis/radar/radar.prj @@ -1,5 +1,5 @@ - + diff --git a/vitis/radar/src/config_flash.c b/vitis/radar/src/config_flash.c new file mode 100755 index 0000000..20671dc --- /dev/null +++ b/vitis/radar/src/config_flash.c @@ -0,0 +1,490 @@ +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "xspi.h" + +#include "project.h" +#include "config_flash.h" + +static XSpi Spi; + +#define SPI_SELECT 0x01 + +/* + * Definitions of the commands shown in this example. + */ +#define COMMAND_PAGE_PROGRAM 0x02 /* Page Program command */ +#define COMMAND_QUAD_WRITE 0x32 /* Quad Input Fast Program */ +#define COMMAND_RANDOM_READ 0x03 /* Random read command */ +#define COMMAND_DUAL_READ 0x3B /* Dual Output Fast Read */ +#define COMMAND_DUAL_IO_READ 0xBB /* Dual IO Fast Read */ +#define COMMAND_QUAD_READ 0x6B /* Quad Output Fast Read */ +#define COMMAND_QUAD_IO_READ 0xEB /* Quad IO Fast Read */ +#define COMMAND_WRITE_ENABLE 0x06 /* Write Enable command */ +#define COMMAND_SECTOR_ERASE 0xD8 /* Sector Erase command */ +#define COMMAND_BULK_ERASE 0xC7 /* Bulk Erase command */ +#define COMMAND_STATUSREG_READ 0x05 /* Status read command */ + +/** + * This definitions specify the EXTRA bytes in each of the command + * transactions. This count includes Command byte, address bytes and any + * don't care bytes needed. + */ +#define READ_WRITE_EXTRA_BYTES 4 /* Read/Write extra bytes */ +#define WRITE_ENABLE_BYTES 1 /* Write Enable bytes */ +#define SECTOR_ERASE_BYTES 4 /* Sector erase extra bytes */ +#define BULK_ERASE_BYTES 1 /* Bulk erase extra bytes */ +#define STATUS_READ_BYTES 2 /* Status read bytes count */ +#define STATUS_WRITE_BYTES 2 /* Status write bytes count */ + +/* + * Flash not busy mask in the status register of the flash device. + */ +#define FLASH_SR_IS_READY_MASK 0x01 /* Ready mask */ + +/* + * Number of bytes per page in the flash device. + */ +#define PAGE_SIZE 256 + +/* + * Byte Positions. + */ +#define BYTE1 0 /* Byte 1 position */ +#define BYTE2 1 /* Byte 2 position */ +#define BYTE3 2 /* Byte 3 position */ +#define BYTE4 3 /* Byte 4 position */ +#define BYTE5 4 /* Byte 5 position */ +#define BYTE6 5 /* Byte 6 position */ +#define BYTE7 6 /* Byte 7 position */ +#define BYTE8 7 /* Byte 8 position */ + +#define DUAL_READ_DUMMY_BYTES 2 +#define QUAD_READ_DUMMY_BYTES 4 + +#define DUAL_IO_READ_DUMMY_BYTES 2 +#define QUAD_IO_READ_DUMMY_BYTES 5 + +void config_flash_spi_handler(void *CallBackRef, u32 StatusEvent, unsigned int ByteCount); + +volatile static int TransferInProgress; +static int ErrorCount; + +static u8 ReadBuffer[PAGE_SIZE + READ_WRITE_EXTRA_BYTES + 4]; +static u8 WriteBuffer[PAGE_SIZE + READ_WRITE_EXTRA_BYTES]; + +int config_flash_get_status(XSpi *SpiPtr) +{ + int Status; + + /* + * Prepare the Write Buffer. + */ + WriteBuffer[BYTE1] = COMMAND_STATUSREG_READ; + + /* + * Initiate the Transfer. + */ + TransferInProgress = TRUE; + Status = XSpi_Transfer(SpiPtr, WriteBuffer, ReadBuffer, + STATUS_READ_BYTES); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Wait till the Transfer is complete and check if there are any errors + * in the transaction.. + */ + while(TransferInProgress); + if(ErrorCount != 0) { + ErrorCount = 0; + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int config_flash_wait_for_ready(void) +{ + int Status; + u8 StatusReg; + + while(1) { + + /* + * Get the Status Register. The status register content is + * stored at the second byte pointed by the ReadBuffer. + */ + Status = config_flash_get_status(&Spi); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Check if the flash is ready to accept the next command. + * If so break. + */ + StatusReg = ReadBuffer[1]; + if((StatusReg & FLASH_SR_IS_READY_MASK) == 0) { + break; + } + } + +// xil_printf("Flash Ready\r\n"); + + return XST_SUCCESS; +} + +int config_flash_write_enable(XSpi *SpiPtr) +{ + int Status; + + /* + * Wait while the Flash is busy. + */ + Status = config_flash_wait_for_ready(); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Prepare the WriteBuffer. + */ + WriteBuffer[BYTE1] = COMMAND_WRITE_ENABLE; + + /* + * Initiate the Transfer. + */ + TransferInProgress = TRUE; + Status = XSpi_Transfer(SpiPtr, WriteBuffer, NULL, + WRITE_ENABLE_BYTES); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Wait till the Transfer is complete and check if there are any errors + * in the transaction.. + */ + while(TransferInProgress); + if(ErrorCount != 0) { + ErrorCount = 0; + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int config_flash_sector_erase(u32 Addr) +{ + int Status; + + /* + * Perform the Write Enable operation. + */ + Status = config_flash_write_enable(&Spi); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Wait while the Flash is busy. + */ + Status = config_flash_wait_for_ready(); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Prepare the WriteBuffer. + */ + WriteBuffer[BYTE1] = COMMAND_SECTOR_ERASE; + WriteBuffer[BYTE2] = (u8) (Addr >> 16); + WriteBuffer[BYTE3] = (u8) (Addr >> 8); + WriteBuffer[BYTE4] = (u8) (Addr); + + /* + * Initiate the Transfer. + */ + TransferInProgress = TRUE; + Status = XSpi_Transfer(&Spi, WriteBuffer, NULL, + SECTOR_ERASE_BYTES); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Wait till the Transfer is complete and check if there are any errors + * in the transaction.. + */ + while(TransferInProgress); + if(ErrorCount != 0) { + ErrorCount = 0; + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int config_flash_write(u32 Addr, u8 * data, u32 ByteCount) +{ + u32 Index; + int Status; + + /* + * Perform the Write Enable operation. + */ + Status = config_flash_write_enable(&Spi); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + + /* + * Wait while the Flash is busy. + */ + Status = config_flash_wait_for_ready(); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Prepare the WriteBuffer. + */ + WriteBuffer[BYTE1] = COMMAND_PAGE_PROGRAM; + WriteBuffer[BYTE2] = (u8) (Addr >> 16); + WriteBuffer[BYTE3] = (u8) (Addr >> 8); + WriteBuffer[BYTE4] = (u8) Addr; + + + /* + * Fill in the TEST data that is to be written into the Numonyx Serial + * Flash device. + */ + for(Index = 4; Index < ByteCount + READ_WRITE_EXTRA_BYTES; Index++) { +// WriteBuffer[Index] = (u8)((Index - 4) + TestByte); + WriteBuffer[Index] = data[Index - 4]; + } + + /* + * Initiate the Transfer. + */ + TransferInProgress = TRUE; + Status = XSpi_Transfer(&Spi, WriteBuffer, NULL, + (ByteCount + READ_WRITE_EXTRA_BYTES)); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Wait till the Transfer is complete and check if there are any errors + * in the transaction. + */ + while(TransferInProgress); + if(ErrorCount != 0) { + ErrorCount = 0; + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int config_flash_read(u32 Addr, u8 * data, u32 ByteCount) +{ + int Status; + + /* + * Wait while the Flash is busy. + */ + Status = config_flash_wait_for_ready(); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Prepare the WriteBuffer. + */ + u8 ReadCmd = COMMAND_RANDOM_READ; + WriteBuffer[BYTE1] = ReadCmd; + WriteBuffer[BYTE2] = (u8) (Addr >> 16); + WriteBuffer[BYTE3] = (u8) (Addr >> 8); + WriteBuffer[BYTE4] = (u8) Addr; + + if (ReadCmd == COMMAND_DUAL_READ) { + ByteCount += DUAL_READ_DUMMY_BYTES; + } else if (ReadCmd == COMMAND_DUAL_IO_READ) { + ByteCount += DUAL_READ_DUMMY_BYTES; + } else if (ReadCmd == COMMAND_QUAD_IO_READ) { + ByteCount += QUAD_IO_READ_DUMMY_BYTES; + } else if (ReadCmd==COMMAND_QUAD_READ) { + ByteCount += QUAD_READ_DUMMY_BYTES; + } + + /* + * Initiate the Transfer. + */ + TransferInProgress = TRUE; + Status = XSpi_Transfer( &Spi, WriteBuffer, ReadBuffer, + (ByteCount + READ_WRITE_EXTRA_BYTES)); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Wait till the Transfer is complete and check if there are any errors + * in the transaction. + */ + while(TransferInProgress); + if(ErrorCount != 0) { + ErrorCount = 0; + return XST_FAILURE; + } + + for(int i = 0; i < ByteCount; i++) { + data[i] = ReadBuffer[i + READ_WRITE_EXTRA_BYTES]; + } + + return XST_SUCCESS; +} + + +int config_flash_read_config(void) { + + int Status; + + u8 offset = 0x40; + + config_flash_sector_erase(CONFIG_BASE_ADDRESS); +// +// /* +// * Write the data to the Page using Page Program command. +// */ +// xil_printf("Flash Write\r\n"); +// u8 data[PAGE_SIZE]; +// for(int i = 0; i < PAGE_SIZE; i++) { +// data[i] = i + offset; +// } +// +// Status = config_flash_write(CONFIG_BASE_ADDRESS, data, PAGE_SIZE); +// if(Status != XST_SUCCESS) { +// return XST_FAILURE; +// } +// +// /* +// * Clear the read Buffer. +// */ +// for(int Index = 0; Index < PAGE_SIZE + READ_WRITE_EXTRA_BYTES; Index++) { +// ReadBuffer[Index] = 0x0; +// } +// +// /* +// * Read the data from the Page using Random Read command. +// */ +// xil_printf("Flash Read\r\n"); +// Status = config_flash_read(CONFIG_BASE_ADDRESS, data, PAGE_SIZE); +// if(Status != XST_SUCCESS) { +// return XST_FAILURE; +// } +// +// /* +// * Compare the data read against the data written. +// */ +// for(int Index = 0; Index < PAGE_SIZE; Index++) { +// if(data[Index ] != (u8)(Index + offset)) { +// return XST_FAILURE; +// } +// } +// +// xil_printf("Data Matches\r\n"); + + return XST_SUCCESS; + +} + +int config_flash_init(void) { + int Status; + XSpi_Config *ConfigPtr; /* Pointer to Configuration data */ + + /* + * Initialize the SPI driver so that it's ready to use, + * specify the device ID that is generated in xparameters.h. + */ + ConfigPtr = XSpi_LookupConfig(XPAR_QSPI_FLASH_DEVICE_ID); + if (ConfigPtr == NULL) { + return XST_DEVICE_NOT_FOUND; + } + + Status = XSpi_CfgInitialize(&Spi, ConfigPtr, + ConfigPtr->BaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Connect the SPI driver to the interrupt subsystem such that + * interrupts can occur. This function is application specific. + */ + xPortInstallInterruptHandler(XPAR_MICROBLAZE_0_AXI_INTC_QSPI_FLASH_IP2INTC_IRPT_INTR, (XInterruptHandler)XSpi_InterruptHandler, (void *)&Spi); + vPortEnableInterrupt(XPAR_MICROBLAZE_0_AXI_INTC_QSPI_FLASH_IP2INTC_IRPT_INTR); +// Status = SetupInterruptSystem(&Spi); +// if(Status != XST_SUCCESS) { +// return XST_FAILURE; +// } + + /* + * Setup the handler for the SPI that will be called from the interrupt + * context when an SPI status occurs, specify a pointer to the SPI + * driver instance as the callback reference so the handler is able to + * access the instance data. + */ + XSpi_SetStatusHandler(&Spi, &Spi, (XSpi_StatusHandler)config_flash_spi_handler); + + /* + * Set the SPI device as a master and in manual slave select mode such + * that the slave select signal does not toggle for every byte of a + * transfer, this must be done before the slave select is set. + */ + Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | + XSP_MANUAL_SSELECT_OPTION); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Select the quad flash device on the SPI bus, so that it can be + * read and written using the SPI bus. + */ + Status = XSpi_SetSlaveSelect(&Spi, SPI_SELECT); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Start the SPI driver so that interrupts and the device are enabled. + */ + XSpi_Start(&Spi); + +// config_flash_read_config(); + + return XST_SUCCESS; + +} + +void config_flash_spi_handler(void *CallBackRef, u32 StatusEvent, unsigned int ByteCount) +{ + /* + * Indicate the transfer on the SPI bus is no longer in progress + * regardless of the status event. + */ + TransferInProgress = FALSE; + + /* + * If the event was not transfer done, then track it as an error. + */ + if (StatusEvent != XST_SPI_TRANSFER_DONE) { + ErrorCount++; + } +} diff --git a/vitis/radar/src/config_flash.h b/vitis/radar/src/config_flash.h new file mode 100755 index 0000000..996125b --- /dev/null +++ b/vitis/radar/src/config_flash.h @@ -0,0 +1,16 @@ +#ifndef CONFIG_FLASH_H /* prevent circular inclusions */ +#define CONFIG_FLASH_H /* by using protection macros */ + + +#define CONFIG_BASE_ADDRESS 0xf00000 +#define NET_CONFIG_ADDRESS (CONFIG_BASE_ADDRESS + 0) +#define NET_CONFIG_LENGTH 16 + + +int config_flash_init(void); +int config_flash_sector_erase(u32 Addr); +int config_flash_write(u32 Addr, u8 * data, u32 ByteCount); +int config_flash_read(u32 Addr, u8 * data, u32 ByteCount); + + +#endif /* end of protection macro */ diff --git a/vitis/radar/src/ethernet.c b/vitis/radar/src/ethernet.c index b08b27b..75c26ef 100755 --- a/vitis/radar/src/ethernet.c +++ b/vitis/radar/src/ethernet.c @@ -10,6 +10,7 @@ #include "project.h" #include "radar_manager_icd.h" #include "novatel.h" +#include "config_flash.h" #define DEFAULT_IP_ADDRESS "192.168.1.200" #define DEFAULT_GW_ADDRESS "192.168.1.1" @@ -26,24 +27,46 @@ static unsigned char msgBuffer[MAX_MSG_LENGTH]; unsigned char recv_buf[RECV_BUF_SIZE+2]; -void print_ip(char *msg, ip_addr_t *ip) -{ +void print_ip(char *msg, ip_addr_t *ip) { DEBUG_PRINT(msg); DEBUG_PRINT("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip), ip4_addr3(ip), ip4_addr4(ip)); } -void print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw, u16 port) -{ - +void print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw, u16 port) { print_ip("Board IP: ", ip); print_ip("Netmask : ", mask); print_ip("Gateway : ", gw); DEBUG_PRINT("Port : %d\n\r", htons(port)); } -static void assign_default_ip(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw) -{ +static int get_ip_from_config_flash(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw, u16 *port) { + + u8 net_config_data[NET_CONFIG_LENGTH]; + ip_addr_t * net_configs = (ip_addr_t *)net_config_data; + + int ret = config_flash_read(NET_CONFIG_ADDRESS, net_config_data, NET_CONFIG_LENGTH); + + ip->addr = htonl(net_configs[0].addr); + mask->addr = htonl(net_configs[1].addr); + gw->addr = htonl(net_configs[2].addr); + *port = htons((u16)(net_configs[3].addr)); + + printf("Net Config From Flash\r\n"); + print_ip_settings(ip, mask, gw, *port); + + if (ip->addr == 0) { + ret = XST_FAILURE; + } + + if (ip->addr == 0xFFFFFFFF) { + ret = XST_FAILURE; + } + + return ret; +} + +static void assign_default_ip(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw, u16 *port) { int err; DEBUG_PRINT("Configuring default IP %s \r\n", DEFAULT_IP_ADDRESS); @@ -59,6 +82,8 @@ static void assign_default_ip(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw) err = inet_aton(DEFAULT_GW_ADDRESS, gw); if(!err) DEBUG_PRINT("Invalid default gateway address: %d\r\n", err); + + *port = htons(TCP_CONN_PORT); } void eth_sendMessage(u8 * data, int num_bytes) @@ -162,7 +187,7 @@ void tcp_server_task() lwip_init(); /* the mac address of the board. this should be unique per board */ - u16 ip_port = htons(TCP_CONN_PORT); +// u16 ip_port = htons(TCP_CONN_PORT); u8_t mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 }; DEBUG_PRINT("\n\r\n\r"); @@ -192,7 +217,12 @@ void tcp_server_task() (void(*)(void*))xemacif_input_thread, &server_netif, 1024, DEFAULT_THREAD_PRIO); - assign_default_ip(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw)); + u16 ip_port; + int ret = get_ip_from_config_flash(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw), &ip_port); + if (ret != XST_SUCCESS) { + assign_default_ip(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw), &ip_port); + } + printf("Assigned Net Config\r\n"); print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw), ip_port); diff --git a/vitis/radar/src/main.c b/vitis/radar/src/main.c index f0d22c4..3fdc516 100755 --- a/vitis/radar/src/main.c +++ b/vitis/radar/src/main.c @@ -15,6 +15,7 @@ #include "adi_ad9081.h" #include "adi_hmc7044.h" #include "novatel.h" +#include "config_flash.h" XSysMon SysMonInst; //extern XScuGic xInterruptController; @@ -111,7 +112,9 @@ void main_task( void *pvParameters ) { xPortInstallInterruptHandler(XPAR_MICROBLAZE_0_AXI_INTC_SYSTEM_PPS_INTR, (XInterruptHandler) pps_irq_handler, (void *)0); vPortEnableInterrupt(XPAR_MICROBLAZE_0_AXI_INTC_SYSTEM_PPS_INTR); - setup_data_converter(); +// setup_data_converter(); + +// config_flash_sector_erase(CONFIG_BASE_ADDRESS); while (1) { toggleBit(GPO_REG, 0); // Toggle LED @@ -124,6 +127,7 @@ int main(void) { xil_printf("\n\r\n\r================= Start ====================\n\r\n\r"); Xil_Out32(GPO_REG, 0x11); + config_flash_init(); xTaskCreate( status_task, ( const char * ) "status", diff --git a/vitis/radar/src/radar_manager_icd.c b/vitis/radar/src/radar_manager_icd.c index 725e75c..9faa300 100755 --- a/vitis/radar/src/radar_manager_icd.c +++ b/vitis/radar/src/radar_manager_icd.c @@ -7,6 +7,7 @@ #include "project.h" #include "radar_manager_icd.h" #include "ethernet.h" +#include "config_flash.h" void radar_manager_get_message( unsigned char * recv_buf, int n, unsigned char * msg, int * msg_ind, int * header_found) { @@ -178,6 +179,14 @@ void radar_manager_parse_message(u8 * msgBuffer) } break; + case CONFIG_FLASH_WRITE: + { + configFlashWriteType *msg = (configFlashWriteType *)msgBuffer; + config_flash_sector_erase(msg->addr); + config_flash_write(msg->addr, msg->data, msg->length); + } + break; + default: DEBUG_PRINT("Unknown Type 0x%04X!\r\n", header->type); break; diff --git a/vitis/radar/src/radar_manager_icd.h b/vitis/radar/src/radar_manager_icd.h index 9dc3083..556fe5d 100755 --- a/vitis/radar/src/radar_manager_icd.h +++ b/vitis/radar/src/radar_manager_icd.h @@ -16,6 +16,7 @@ void radar_manager_parse_message(u8 * msgBuffer); #define NACK_MSG 5 #define AXI_WRITE_REG_BURST 6 #define RF_SPI_WRITE 7 +#define CONFIG_FLASH_WRITE 8 #define SET_AD9081_DAC_NCO 128 #define SET_AD9081_ADC_NCO 129 #define SET_LANE_MAPPING 130 @@ -53,6 +54,13 @@ typedef struct { unsigned int data[512]; } writeRegBurstType; +typedef struct { + headerType header; + unsigned int addr; + unsigned int length; + uint8_t data[512]; +} configFlashWriteType; + typedef struct { headerType header; unsigned int addr; diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h index 6415623..864f4b5 100644 --- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h +++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h @@ -496,8 +496,8 @@ #define PLATFORM_MB /******************************************************************/ -#define STDIN_BASEADDRESS 0x40000000 -#define STDOUT_BASEADDRESS 0x40000000 +#define STDIN_BASEADDRESS 0x41400000 +#define STDOUT_BASEADDRESS 0x41400000 /******************************************************************/ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a index 8b470ba..478417c 100644 Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a differ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a index 3510983..29ba479 100644 Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a differ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss index 55fe265..14165d1 100644 --- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss +++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss @@ -6,8 +6,8 @@ BEGIN OS PARAMETER OS_NAME = freertos10_xilinx PARAMETER OS_VER = 1.12 PARAMETER PROC_INSTANCE = microblaze_0 - PARAMETER stdin = axi_uartlite_0 - PARAMETER stdout = axi_uartlite_0 + PARAMETER stdin = mdm_1 + PARAMETER stdout = mdm_1 PARAMETER total_heap_size = 2097152 END diff --git a/vitis/top/platform.spr b/vitis/top/platform.spr index 5f3a325..c14efcb 100755 --- a/vitis/top/platform.spr +++ b/vitis/top/platform.spr @@ -1 +1 @@ -{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} +{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} diff --git a/vitis/top/platform.tcl b/vitis/top/platform.tcl index 6dd4e11..5e08fe3 100755 --- a/vitis/top/platform.tcl +++ b/vitis/top/platform.tcl @@ -98,3 +98,12 @@ bsp write bsp reload catch {bsp regenerate} platform generate +platform active {top} +bsp reload +bsp config stdin "mdm_1" +bsp config stdout "mdm_1" +bsp write +bsp reload +catch {bsp regenerate} +platform generate -domains freertos10_xilinx_microblaze_0 +bsp reload