diff --git a/python/data_recorder.py b/python/data_recorder.py index 012f725..586017b 100755 --- a/python/data_recorder.py +++ b/python/data_recorder.py @@ -122,6 +122,9 @@ class DataRecorder: self.write_queue.put(n) offset += n + if offset >= len(self.buffer): + if self.port == 1234: + print('hmmm', n, offset, len(self.buffer)) offset = offset % len(self.buffer) # print(offset) diff --git a/python/radar_manager.py b/python/radar_manager.py index 9ef1310..7c11a6f 100755 --- a/python/radar_manager.py +++ b/python/radar_manager.py @@ -253,16 +253,20 @@ class RadarManager: self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x8, start_sample >> 2) # Setup RX Strobe - self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample) - self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples) + # self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample >> 2) + # self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples >> 2) + # Just force the enable high all the time before we start running + self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, 0x1FFFFFFF) def setup_tx(self, num_samples, start_sample): self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 2) self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 2) # Setup TX Strobe - self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample) - self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples) + # self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample >> 2) + # self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples >> 2) + # Just force the enable high all the time before we start running + self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, 0x1FFFFFFF) def start_running(self): for i in range(NUM_RX): @@ -274,7 +278,9 @@ class RadarManager: self.axi_write_register(TIMING_ENGINE_ADDR + 0x0, 1) # Timing Engine Reset for i in range(NUM_RX): self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x0, 1) # RX Reset + self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, 0x0FFFFFF) # Clear RX Enable self.axi_write_register(WAVEFORM_GEN_ADDR + 0x0, 1) # TX Reset + self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, 0x0FFFFFF) # Clear TX Enable def setup_rf_attenuators(self, rf_atten): self.rf_spi_write((1 << 0), 6, rf_atten[0]) # TX0 RF (ADRF5730) diff --git a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc index 3c54f12..f5de7aa 100755 --- a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc +++ b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc @@ -11,6 +11,7 @@ set_property CFGBVS VCCO [current_design] #------------------------------------------- set_false_path -from [get_cells util_reg_i/reg_*] set_false_path -from [get_cells timing_engine_i/reg_*] +set_false_path -from [get_cells timing_engine_i/genblk1*reg_*] set_false_path -from [get_cells timing_engine_i/system_time_start_of_cpi*] set_false_path -from [get_cells *digital_rx_chain_i/reg_*] set_false_path -from [get_cells waveform_gen_i/reg_*] @@ -32,32 +33,67 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_n] # set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_p] # set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_n] +#------------------------------------------- +# I2C +#------------------------------------------- +set_property PACKAGE_PIN P24 [get_ports i2c_scl] +set_property PACKAGE_PIN P25 [get_ports i2c_sda] + +set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl] +set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda] + #------------------------------------------- # RF Attenautors #------------------------------------------- -set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin] -set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk] -set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le] -set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin] -set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk] -set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le] -set_property PACKAGE_PIN K25 [get_ports txlo_drv_en] +# FMC2 +#set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin] +#set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk] +#set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le] +#set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin] +#set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk] +#set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le] +#set_property PACKAGE_PIN K25 [get_ports txlo_drv_en] -set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin] -set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk] -set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le] -set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin] -set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk] -set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le] -set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en] +#set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin] +#set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk] +#set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le] +#set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin] +#set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk] +#set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le] +#set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en] -set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin] -set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk] -set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le] -set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin] -set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk] -set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le] -set_property PACKAGE_PIN K27 [get_ports rx1_lna_en] +#set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin] +#set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk] +#set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le] +#set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin] +#set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk] +#set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le] +#set_property PACKAGE_PIN K27 [get_ports rx1_lna_en] + +# FMC1 +set_property PACKAGE_PIN AE28 [get_ports tx0_rf_attn_sin] +set_property PACKAGE_PIN AB34 [get_ports tx0_rf_attn_clk] +set_property PACKAGE_PIN AA34 [get_ports tx0_rf_attn_le] +set_property PACKAGE_PIN AC34 [get_ports tx1_rf_attn_sin] +set_property PACKAGE_PIN AF34 [get_ports tx1_rf_attn_clk] +set_property PACKAGE_PIN AE33 [get_ports tx1_rf_attn_le] +set_property PACKAGE_PIN AD34 [get_ports txlo_drv_en] + +set_property PACKAGE_PIN AF33 [get_ports rx0_rf_attn_sin] +set_property PACKAGE_PIN AG30 [get_ports rx0_rf_attn_clk] +set_property PACKAGE_PIN AF30 [get_ports rx0_rf_attn_le] +set_property PACKAGE_PIN U21 [get_ports rx0_if_attn_sin] +set_property PACKAGE_PIN AB20 [get_ports rx0_if_attn_clk] +set_property PACKAGE_PIN AA20 [get_ports rx0_if_attn_le] +set_property PACKAGE_PIN U22 [get_ports rx0_lna_en] + +set_property PACKAGE_PIN AC28 [get_ports rx1_rf_attn_sin] +set_property PACKAGE_PIN AE30 [get_ports rx1_rf_attn_clk] +set_property PACKAGE_PIN AD29 [get_ports rx1_rf_attn_le] +set_property PACKAGE_PIN AC33 [get_ports rx1_if_attn_sin] +set_property PACKAGE_PIN AF32 [get_ports rx1_if_attn_clk] +set_property PACKAGE_PIN AE32 [get_ports rx1_if_attn_le] +set_property PACKAGE_PIN AD33 [get_ports rx1_lna_en] set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_sin] set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_clk] @@ -214,6 +250,8 @@ set_property PACKAGE_PIN D25 [get_ports jesd_sysref_n] set_property IOSTANDARD LVDS [get_ports jesd_sysref_p] set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sysref_p] +set_property DQS_BIAS TRUE [get_ports jesd_sysref_p] +set_property DQS_BIAS TRUE [get_ports jesd_sysref_n] set_property PACKAGE_PIN K5 [get_ports jesd_qpll0_refclk_n] set_property PACKAGE_PIN K6 [get_ports jesd_qpll0_refclk_p] @@ -222,13 +260,15 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p #set_property PACKAGE_PIN P5 [get_ports jesd_qpll0_refclk_n] #set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p] -#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] -#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] +set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] +set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] -set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] -set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] +#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] +#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p] +set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p] +set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n] create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_n] #set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}] @@ -396,108 +436,21 @@ connect_debug_port u_ila_0/probe5 [get_nets [list util_reg_i/spi_shift_data]] connect_debug_port u_ila_0/probe10 [get_nets [list util_reg_i/le_active]] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list microblaze_bd_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]] +connect_debug_port u_ila_0/clk [get_nets [list jesd_core_clk]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 8 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {util_reg_i/spi_bit_cnt_reg[0]} {util_reg_i/spi_bit_cnt_reg[1]} {util_reg_i/spi_bit_cnt_reg[2]} {util_reg_i/spi_bit_cnt_reg[3]} {util_reg_i/spi_bit_cnt_reg[4]} {util_reg_i/spi_bit_cnt_reg[5]} {util_reg_i/spi_bit_cnt_reg[6]} {util_reg_i/spi_bit_cnt_reg[7]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 32 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {util_reg_i/reg_spi_data[0]} {util_reg_i/reg_spi_data[1]} {util_reg_i/reg_spi_data[2]} {util_reg_i/reg_spi_data[3]} {util_reg_i/reg_spi_data[4]} {util_reg_i/reg_spi_data[5]} {util_reg_i/reg_spi_data[6]} {util_reg_i/reg_spi_data[7]} {util_reg_i/reg_spi_data[8]} {util_reg_i/reg_spi_data[9]} {util_reg_i/reg_spi_data[10]} {util_reg_i/reg_spi_data[11]} {util_reg_i/reg_spi_data[12]} {util_reg_i/reg_spi_data[13]} {util_reg_i/reg_spi_data[14]} {util_reg_i/reg_spi_data[15]} {util_reg_i/reg_spi_data[16]} {util_reg_i/reg_spi_data[17]} {util_reg_i/reg_spi_data[18]} {util_reg_i/reg_spi_data[19]} {util_reg_i/reg_spi_data[20]} {util_reg_i/reg_spi_data[21]} {util_reg_i/reg_spi_data[22]} {util_reg_i/reg_spi_data[23]} {util_reg_i/reg_spi_data[24]} {util_reg_i/reg_spi_data[25]} {util_reg_i/reg_spi_data[26]} {util_reg_i/reg_spi_data[27]} {util_reg_i/reg_spi_data[28]} {util_reg_i/reg_spi_data[29]} {util_reg_i/reg_spi_data[30]} {util_reg_i/reg_spi_data[31]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 8 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {util_reg_i/spi_clk_cnt_reg[0]} {util_reg_i/spi_clk_cnt_reg[1]} {util_reg_i/spi_clk_cnt_reg[2]} {util_reg_i/spi_clk_cnt_reg[3]} {util_reg_i/spi_clk_cnt_reg[4]} {util_reg_i/spi_clk_cnt_reg[5]} {util_reg_i/spi_clk_cnt_reg[6]} {util_reg_i/spi_clk_cnt_reg[7]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 5 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {util_reg_i/le_count_reg[0]} {util_reg_i/le_count_reg[1]} {util_reg_i/le_count_reg[2]} {util_reg_i/le_count_reg[3]} {util_reg_i/le_count_reg[4]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 1 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list util_reg_i/start_spi_transaction]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list tx0_rf_attn_clk_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list tx0_rf_attn_le_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list tx0_rf_attn_sin_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list rx0_if_attn_clk_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list rx0_if_attn_le_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -set_property port_width 1 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list rx0_if_attn_sin_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -set_property port_width 1 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list rx0_rf_attn_clk_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] -set_property port_width 1 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list rx0_rf_attn_le_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] -set_property port_width 1 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list rx0_rf_attn_sin_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -set_property port_width 1 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list rx1_if_attn_clk_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -set_property port_width 1 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list rx1_if_attn_le_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -set_property port_width 1 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list rx1_if_attn_sin_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -set_property port_width 1 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list rx1_rf_attn_clk_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] -set_property port_width 1 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list rx1_rf_attn_le_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] -set_property port_width 1 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list rx1_rf_attn_sin_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -set_property port_width 1 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list tx1_rf_attn_clk_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] -set_property port_width 1 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list tx1_rf_attn_le_OBUF]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -set_property port_width 1 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list tx1_rf_attn_sin_OBUF]] +set_property port_width 1 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list microblaze_bd_i/jesd/util_ds_buf_1_IBUF_OUT]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd b/radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd index 44c373d..94131f1 100755 --- a/radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd +++ b/radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd @@ -1,8 +1,8 @@ { "design": { "design_info": { - "boundary_crc": "0x1F2328300D1AB620", - "device": "xcku040-ffva1156-2-i", + "boundary_crc": "0xF42ED0D8FE15BA23", + "device": "xcku040-ffva1156-1-c", "gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/bd/microblaze_bd", "name": "microblaze_bd", "rev_ctrl_bd_flag": "RevCtrlBdOff", @@ -11,39 +11,28 @@ "validated": "true" }, "design_tree": { - "microblaze_0": "", "microblaze_0_local_memory": { - "dlmb_v10": "", - "ilmb_v10": "", "dlmb_bram_if_cntlr": "", + "dlmb_v10": "", "ilmb_bram_if_cntlr": "", + "ilmb_v10": "", "lmb_bram": "" }, - "microblaze_0_axi_periph": { - "xbar": "", - "s00_couplers": {}, - "m00_couplers": {}, - "m01_couplers": {}, - "m02_couplers": {}, - "m03_couplers": {}, - "m04_couplers": {}, - "m05_couplers": {}, - "m06_couplers": {}, - "m07_couplers": { - "auto_cc": "" - }, - "m08_couplers": {}, - "m09_couplers": {}, - "m10_couplers": {} + "jesd": { + "jesd204_phy_0": "", + "jesd204c_0": "", + "jesd204c_1": "", + "util_ds_buf_0": "", + "util_ds_buf_1": "" }, - "microblaze_0_axi_intc": "", - "microblaze_0_xlconcat": "", - "mdm_1": "", - "rst_150": "", - "axi_uartlite_0": "", - "axi_timer_0": "", + "axi_bram_ctrl_0": "", + "axi_bram_ctrl_1": "", + "axi_bram_ctrl_2": "", + "axi_bram_ctrl_3": "", "axi_ethernet_0": "", - "ddr4_0": "", + "axi_ethernet_0_dma": "", + "axi_fifo_mm_s_0": "", + "axi_iic_0": "", "axi_interconnect_0": { "xbar": "", "s00_couplers": { @@ -70,23 +59,6 @@ "m00_data_fifo": "" } }, - "rst_ddr": "", - "axi_ethernet_0_dma": "", - "clk_wiz_0": "", - "system_management_wiz_0": "", - "axi_quad_spi_0": "", - "axi_quad_spi_1": "", - "jesd": { - "jesd204_phy_0": "", - "jesd204c_1": "", - "jesd204c_0": "", - "util_ds_buf_1": "", - "util_ds_buf_0": "" - }, - "axi_bram_ctrl_0": "", - "axi_bram_ctrl_2": "", - "axi_bram_ctrl_3": "", - "axi_bram_ctrl_1": "", "axi_interconnect_1": { "xbar": "", "s00_couplers": {}, @@ -101,12 +73,42 @@ "m08_couplers": {}, "m09_couplers": {}, "m10_couplers": {}, - "m11_couplers": {} + "m11_couplers": {}, + "m12_couplers": {} }, - "axi_fifo_mm_s_0": "", + "axi_quad_spi_0": "", + "axi_quad_spi_1": "", + "qspi_flash": "", + "axi_timer_0": "", + "axi_uartlite_0": "", "axis_dwidth_converter_0": "", "axis_dwidth_converter_1": "", - "qspi_flash": "" + "clk_wiz_0": "", + "ddr4_0": "", + "mdm_1": "", + "microblaze_0": "", + "microblaze_0_axi_intc": "", + "microblaze_0_axi_periph": { + "xbar": "", + "s00_couplers": {}, + "m00_couplers": {}, + "m01_couplers": {}, + "m02_couplers": {}, + "m03_couplers": {}, + "m04_couplers": {}, + "m05_couplers": {}, + "m06_couplers": {}, + "m07_couplers": { + "auto_cc": "" + }, + "m08_couplers": {}, + "m09_couplers": {}, + "m10_couplers": {} + }, + "microblaze_0_xlconcat": "", + "rst_ddr": "", + "rst_150": "", + "system_management_wiz_0": "" }, "interface_ports": { "clk_200_in": { @@ -230,11 +232,11 @@ "value_src": "default" }, "CAS_LATENCY": { - "value": "17", + "value": "15", "value_src": "user_prop" }, "CAS_WRITE_LATENCY": { - "value": "12", + "value": "11", "value_src": "user_prop" }, "CS_ENABLED": { @@ -270,7 +272,7 @@ "value_src": "user_prop" }, "TIMEPERIOD_PS": { - "value": "833", + "value": "1000", "value_src": "user_prop" } }, @@ -385,7 +387,7 @@ "value": "32" }, "FREQ_HZ": { - "value": "150000000", + "value": "125000000", "value_src": "user_prop" }, "HAS_BRESP": { @@ -432,16 +434,16 @@ "value_src": "ip_prop" }, "NUM_READ_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_READ_THREADS": { "value": "1", "value_src": "default" }, "NUM_WRITE_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_WRITE_THREADS": { "value": "1", @@ -1344,7 +1346,7 @@ "value": "32" }, "FREQ_HZ": { - "value": "150000000", + "value": "125000000", "value_src": "user_prop" }, "HAS_BRESP": { @@ -1391,16 +1393,16 @@ "value_src": "ip_prop" }, "NUM_READ_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_READ_THREADS": { "value": "1", "value_src": "default" }, "NUM_WRITE_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_WRITE_THREADS": { "value": "1", @@ -1736,7 +1738,7 @@ "value": "32" }, "FREQ_HZ": { - "value": "150000000", + "value": "125000000", "value_src": "user_prop" }, "HAS_BRESP": { @@ -1783,16 +1785,16 @@ "value_src": "ip_prop" }, "NUM_READ_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_READ_THREADS": { "value": "1", "value_src": "default" }, "NUM_WRITE_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_WRITE_THREADS": { "value": "1", @@ -1976,7 +1978,7 @@ "value": "32" }, "FREQ_HZ": { - "value": "150000000", + "value": "125000000", "value_src": "user_prop" }, "HAS_BRESP": { @@ -2023,16 +2025,16 @@ "value_src": "ip_prop" }, "NUM_READ_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_READ_THREADS": { "value": "1", "value_src": "default" }, "NUM_WRITE_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_WRITE_THREADS": { "value": "1", @@ -2215,7 +2217,7 @@ "value": "32" }, "FREQ_HZ": { - "value": "150000000", + "value": "125000000", "value_src": "user_prop" }, "HAS_BRESP": { @@ -2262,16 +2264,16 @@ "value_src": "ip_prop" }, "NUM_READ_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_READ_THREADS": { "value": "1", "value_src": "default" }, "NUM_WRITE_OUTSTANDING": { - "value": "1", - "value_src": "default" + "value": "2", + "value_src": "default_prop" }, "NUM_WRITE_THREADS": { "value": "1", @@ -2472,6 +2474,37 @@ "direction": "I" } } + }, + "i2c": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:iic:1.0", + "vlnv": "xilinx.com:interface:iic_rtl:1.0", + "port_maps": { + "SCL_I": { + "physical_name": "i2c_scl_i", + "direction": "I" + }, + "SCL_O": { + "physical_name": "i2c_scl_o", + "direction": "O" + }, + "SCL_T": { + "physical_name": "i2c_scl_t", + "direction": "O" + }, + "SDA_I": { + "physical_name": "i2c_sda_i", + "direction": "I" + }, + "SDA_O": { + "physical_name": "i2c_sda_o", + "direction": "O" + }, + "SDA_T": { + "physical_name": "i2c_sda_t", + "direction": "O" + } + } } }, "ports": { @@ -2522,7 +2555,7 @@ "value_src": "user_prop" }, "FREQ_HZ": { - "value": "150000000", + "value": "125000000", "value_src": "user_prop" }, "FREQ_TOLERANCE_HZ": { @@ -2715,154 +2748,6 @@ } }, "components": { - "microblaze_0": { - "vlnv": "xilinx.com:ip:microblaze:11.0", - "xci_name": "microblaze_bd_microblaze_0_0", - "xci_path": "ip/microblaze_bd_microblaze_0_0/microblaze_bd_microblaze_0_0.xci", - "inst_hier_path": "microblaze_0", - "parameters": { - "C_BRANCH_TARGET_CACHE_SIZE": { - "value": "0" - }, - "C_CACHE_BYTE_SIZE": { - "value": "32768" - }, - "C_DCACHE_BYTE_SIZE": { - "value": "32768" - }, - "C_DCACHE_DATA_WIDTH": { - "value": "1" - }, - "C_DCACHE_LINE_LEN": { - "value": "16" - }, - "C_DCACHE_VICTIMS": { - "value": "8" - }, - "C_DEBUG_ENABLED": { - "value": "1" - }, - "C_DIV_ZERO_EXCEPTION": { - "value": "1" - }, - "C_D_AXI": { - "value": "1" - }, - "C_D_LMB": { - "value": "1" - }, - "C_FPU_EXCEPTION": { - "value": "1" - }, - "C_ICACHE_DATA_WIDTH": { - "value": "1" - }, - "C_ICACHE_LINE_LEN": { - "value": "16" - }, - "C_ICACHE_STREAMS": { - "value": "1" - }, - "C_ICACHE_VICTIMS": { - "value": "8" - }, - "C_I_LMB": { - "value": "1" - }, - "C_M_AXI_D_BUS_EXCEPTION": { - "value": "1" - }, - "C_USE_BRANCH_TARGET_CACHE": { - "value": "0" - }, - "C_USE_DCACHE": { - "value": "1" - }, - "C_USE_FPU": { - "value": "1" - }, - "C_USE_ICACHE": { - "value": "1" - }, - "G_TEMPLATE_LIST": { - "value": "9" - } - }, - "interface_ports": { - "DLMB": { - "vlnv": "xilinx.com:interface:lmb_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - }, - "ILMB": { - "vlnv": "xilinx.com:interface:lmb_rtl:1.0", - "mode": "Master", - "address_space_ref": "Instruction", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - }, - "M_AXI_DP": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - }, - "M_AXI_DC": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - }, - "M_AXI_IC": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Instruction", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - } - }, - "addressing": { - "address_spaces": { - "Data": { - "range": "4G", - "width": "32" - }, - "Instruction": { - "range": "4G", - "width": "32" - } - } - }, - "hdl_attributes": { - "BMM_INFO_PROCESSOR": { - "value": "microblaze-le > microblaze_bd microblaze_0_local_memory/dlmb_bram_if_cntlr", - "value_src": "default" - }, - "KEEP_HIERARCHY": { - "value": "yes", - "value_src": "default" - } - } - }, "microblaze_0_local_memory": { "interface_ports": { "DLMB": { @@ -2887,36 +2772,6 @@ } }, "components": { - "dlmb_v10": { - "vlnv": "xilinx.com:ip:lmb_v10:3.0", - "xci_name": "microblaze_bd_dlmb_v10_0", - "xci_path": "ip/microblaze_bd_dlmb_v10_0/microblaze_bd_dlmb_v10_0.xci", - "inst_hier_path": "microblaze_0_local_memory/dlmb_v10", - "interface_ports": { - "LMB_M": { - "vlnv": "xilinx.com:interface:lmb_rtl:1.0", - "mode": "MirroredMaster", - "bridges": [ - "LMB_Sl_0" - ] - } - } - }, - "ilmb_v10": { - "vlnv": "xilinx.com:ip:lmb_v10:3.0", - "xci_name": "microblaze_bd_ilmb_v10_0", - "xci_path": "ip/microblaze_bd_ilmb_v10_0/microblaze_bd_ilmb_v10_0.xci", - "inst_hier_path": "microblaze_0_local_memory/ilmb_v10", - "interface_ports": { - "LMB_M": { - "vlnv": "xilinx.com:interface:lmb_rtl:1.0", - "mode": "MirroredMaster", - "bridges": [ - "LMB_Sl_0" - ] - } - } - }, "dlmb_bram_if_cntlr": { "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", "xci_name": "microblaze_bd_dlmb_bram_if_cntlr_0", @@ -2938,6 +2793,21 @@ } } }, + "dlmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "microblaze_bd_dlmb_v10_0", + "xci_path": "ip/microblaze_bd_dlmb_v10_0/microblaze_bd_dlmb_v10_0.xci", + "inst_hier_path": "microblaze_0_local_memory/dlmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, "ilmb_bram_if_cntlr": { "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", "xci_name": "microblaze_bd_ilmb_bram_if_cntlr_0", @@ -2949,15 +2819,45 @@ } } }, + "ilmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "microblaze_bd_ilmb_v10_0", + "xci_path": "ip/microblaze_bd_ilmb_v10_0/microblaze_bd_ilmb_v10_0.xci", + "inst_hier_path": "microblaze_0_local_memory/ilmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, "lmb_bram": { "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", "xci_name": "microblaze_bd_lmb_bram_0", "xci_path": "ip/microblaze_bd_lmb_bram_0/microblaze_bd_lmb_bram_0.xci", "inst_hier_path": "microblaze_0_local_memory/lmb_bram", "parameters": { + "Enable_B": { + "value": "Use_ENB_Pin" + }, "Memory_Type": { "value": "True_Dual_Port_RAM" }, + "Port_B_Clock": { + "value": "100" + }, + "Port_B_Enable_Rate": { + "value": "100" + }, + "Port_B_Write_Rate": { + "value": "50" + }, + "Use_RSTB_Pin": { + "value": "true" + }, "use_bram_block": { "value": "BRAM_Controller" } @@ -3006,1473 +2906,696 @@ "SYS_Rst_1": { "ports": [ "SYS_Rst", - "dlmb_v10/SYS_Rst", "dlmb_bram_if_cntlr/LMB_Rst", - "ilmb_v10/SYS_Rst", - "ilmb_bram_if_cntlr/LMB_Rst" + "dlmb_v10/SYS_Rst", + "ilmb_bram_if_cntlr/LMB_Rst", + "ilmb_v10/SYS_Rst" ] }, "microblaze_0_Clk": { "ports": [ "LMB_Clk", - "dlmb_v10/LMB_Clk", "dlmb_bram_if_cntlr/LMB_Clk", - "ilmb_v10/LMB_Clk", - "ilmb_bram_if_cntlr/LMB_Clk" + "dlmb_v10/LMB_Clk", + "ilmb_bram_if_cntlr/LMB_Clk", + "ilmb_v10/LMB_Clk" ] } } }, - "microblaze_0_axi_periph": { - "vlnv": "xilinx.com:ip:axi_interconnect:2.1", - "xci_path": "ip/microblaze_bd_microblaze_0_axi_periph_0/microblaze_bd_microblaze_0_axi_periph_0.xci", - "inst_hier_path": "microblaze_0_axi_periph", - "xci_name": "microblaze_bd_microblaze_0_axi_periph_0", - "parameters": { - "NUM_MI": { - "value": "11" - }, - "NUM_SI": { - "value": "1" - } - }, + "jesd": { "interface_ports": { - "S00_AXI": { + "s_axi_tx": { "mode": "Slave", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, - "M00_AXI": { - "mode": "Master", + "jesd_axis_tx": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + }, + "jesd_axis_tx_cmd": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + }, + "s_axi_rx": { + "mode": "Slave", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, - "M01_AXI": { + "jesd_axis_rx": { "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + }, + "jesd_axis_rx_cmd": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + }, + "jesd_sysref": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0", + "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0" + }, + "jesd_qpll0_refclk": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0", + "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0" + }, + "s_axi_phy": { + "mode": "Slave", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M02_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M03_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M04_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M05_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "CLK_DOMAIN": { - "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", - "value_src": "undefined" - } - } - }, - "M06_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "CLK_DOMAIN": { - "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", - "value_src": "undefined" - } - } - }, - "M07_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "M08_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "CLK_DOMAIN": { - "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", - "value_src": "undefined" - } - } - }, - "M09_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "CLK_DOMAIN": { - "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", - "value_src": "undefined" - } - } - }, - "M10_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "CLK_DOMAIN": { - "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", - "value_src": "undefined" - } - } } }, "ports": { - "ACLK": { + "mb_axi_clk": { "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_RESET": { - "value": "ARESETN" - } - } + "direction": "I" }, - "ARESETN": { + "jesd_txp_out": { + "direction": "O", + "left": "7", + "right": "0" + }, + "jesd_txn_out": { + "direction": "O", + "left": "7", + "right": "0" + }, + "jesd_rxp_in": { + "direction": "I", + "left": "7", + "right": "0" + }, + "jesd_rxn_in": { + "direction": "I", + "left": "7", + "right": "0" + }, + "mb_axi_aresetn": { "type": "rst", "direction": "I" }, - "S00_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S00_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S00_ARESETN" - } - } - }, - "S00_ARESETN": { - "type": "rst", + "jesd_tx_core_reset": { "direction": "I" }, - "M00_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M00_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M00_ARESETN" - } - } + "irq": { + "direction": "O" }, - "M00_ARESETN": { + "jesd_axis_tx_aresetn": { "type": "rst", + "direction": "O" + }, + "jesd_rx_core_reset": { "direction": "I" }, - "M01_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M01_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M01_ARESETN" - } - } + "irq1": { + "direction": "O" }, - "M01_ARESETN": { + "jesd_axis_rx_aresetn": { "type": "rst", + "direction": "O" + }, + "common0_qpll1_lock_out": { + "direction": "O" + }, + "common1_qpll1_lock_out": { + "direction": "O" + }, + "jesd_core_clk": { "direction": "I" }, - "M02_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M02_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M02_ARESETN" - } - } - }, - "M02_ARESETN": { - "type": "rst", + "jesd_tx_sys_reset": { "direction": "I" }, - "M03_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M03_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M03_ARESETN" - } - } - }, - "M03_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M04_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M04_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M04_ARESETN" - } - } - }, - "M04_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M05_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M05_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M05_ARESETN" - } - } - }, - "M05_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M06_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M06_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M06_ARESETN" - } - } - }, - "M06_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M07_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M07_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M07_ARESETN" - } - } - }, - "M07_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M08_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M08_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M08_ARESETN" - } - } - }, - "M08_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M09_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M09_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M09_ARESETN" - } - } - }, - "M09_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M10_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M10_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M10_ARESETN" - } - } - }, - "M10_ARESETN": { - "type": "rst", + "jesd_rx_sys_reset": { "direction": "I" } }, "components": { - "xbar": { - "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "microblaze_bd_xbar_0", - "xci_path": "ip/microblaze_bd_xbar_0/microblaze_bd_xbar_0.xci", - "inst_hier_path": "microblaze_0_axi_periph/xbar", + "jesd204_phy_0": { + "vlnv": "xilinx.com:ip:jesd204_phy:4.0", + "xci_name": "microblaze_bd_jesd204_phy_0_0", + "xci_path": "ip/microblaze_bd_jesd204_phy_0_0/microblaze_bd_jesd204_phy_0_0.xci", + "inst_hier_path": "jesd/jesd204_phy_0", "parameters": { - "NUM_MI": { - "value": "11" + "Axi_Lite": { + "value": "true" }, - "NUM_SI": { + "C_LANES": { + "value": "8" + }, + "C_PLL_SELECTION": { "value": "1" }, - "STRATEGY": { - "value": "0" + "DRPCLK_FREQ": { + "value": "125.0" + }, + "Equalization_Mode": { + "value": "High_Loss" + }, + "GT_Line_Rate": { + "value": "12.375" + }, + "GT_Location": { + "value": "X0Y12" + }, + "GT_REFCLK_FREQ": { + "value": "187.5" + }, + "Ins_Loss": { + "value": "30" + }, + "RX_GT_Line_Rate": { + "value": "12.375" + }, + "RX_GT_REFCLK_FREQ": { + "value": "187.5" + }, + "RX_PLL_SELECTION": { + "value": "1" + }, + "Rx_JesdVersion": { + "value": "1" + }, + "Rx_use_64b": { + "value": "1" + }, + "TransceiverControl": { + "value": "false" + }, + "Tx_JesdVersion": { + "value": "1" + }, + "Tx_use_64b": { + "value": "1" } }, "interface_ports": { - "S00_AXI": { + "s_axi": { "vlnv": "xilinx.com:interface:aximm_rtl:1.0", "mode": "Slave", - "bridges": [ - "M00_AXI", - "M01_AXI", - "M02_AXI", - "M03_AXI", - "M04_AXI", - "M05_AXI", - "M06_AXI", - "M07_AXI", - "M08_AXI", - "M09_AXI", - "M10_AXI" - ] + "memory_map_ref": "s_axi" + } + }, + "addressing": { + "memory_maps": { + "s_axi": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "4K", + "width": "12", + "usage": "register" + } + } + } } } }, - "s00_couplers": { + "jesd204c_0": { + "vlnv": "xilinx.com:ip:jesd204c:4.2", + "xci_name": "microblaze_bd_jesd204c_0_0", + "xci_path": "ip/microblaze_bd_jesd204c_0_0/microblaze_bd_jesd204c_0_0.xci", + "inst_hier_path": "jesd/jesd204c_0", + "parameters": { + "AXICLK_FREQ": { + "value": "150.0" + }, + "C_LANES": { + "value": "8" + }, + "C_NODE_IS_TRANSMIT": { + "value": "0" + }, + "C_PLL_SELECTION": { + "value": "1" + }, + "DRPCLK_FREQ": { + "value": "187.5" + }, + "GT_Line_Rate": { + "value": "12.375" + }, + "GT_REFCLK_FREQ": { + "value": "187.5" + } + }, "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { + "s_axi": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + "memory_map_ref": "s_axi" } }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" + "addressing": { + "memory_maps": { + "s_axi": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "4K", + "width": "12", + "usage": "register" + } } } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "s00_couplers_to_s00_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] } } }, - "m00_couplers": { + "jesd204c_1": { + "vlnv": "xilinx.com:ip:jesd204c:4.2", + "xci_name": "microblaze_bd_jesd204c_1_0", + "xci_path": "ip/microblaze_bd_jesd204c_1_0/microblaze_bd_jesd204c_1_0.xci", + "inst_hier_path": "jesd/jesd204c_1", + "parameters": { + "AXICLK_FREQ": { + "value": "150" + }, + "C_LANES": { + "value": "8" + }, + "C_PLL_SELECTION": { + "value": "1" + }, + "DRPCLK_FREQ": { + "value": "187.5" + }, + "GT_Line_Rate": { + "value": "12.375" + }, + "GT_REFCLK_FREQ": { + "value": "187.5" + } + }, "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { + "s_axi": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + "memory_map_ref": "s_axi" } }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" + "addressing": { + "memory_maps": { + "s_axi": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "4K", + "width": "12", + "usage": "register" + } } } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m00_couplers_to_m00_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] } } }, - "m01_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m01_couplers_to_m01_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] + "util_ds_buf_0": { + "vlnv": "xilinx.com:ip:util_ds_buf:2.2", + "xci_name": "microblaze_bd_util_ds_buf_0_0", + "xci_path": "ip/microblaze_bd_util_ds_buf_0_0/microblaze_bd_util_ds_buf_0_0.xci", + "inst_hier_path": "jesd/util_ds_buf_0", + "parameters": { + "C_BUF_TYPE": { + "value": "IBUFDSGTE" } } }, - "m02_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m02_couplers_to_m02_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m03_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m03_couplers_to_m03_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m04_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m04_couplers_to_m04_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m05_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m05_couplers_to_m05_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m06_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m06_couplers_to_m06_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m07_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "components": { - "auto_cc": { - "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", - "xci_name": "microblaze_bd_auto_cc_0", - "xci_path": "ip/microblaze_bd_auto_cc_0/microblaze_bd_auto_cc_0.xci", - "inst_hier_path": "microblaze_0_axi_periph/m07_couplers/auto_cc", - "interface_ports": { - "S_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M_AXI" - ] - } - } - } - }, - "interface_nets": { - "auto_cc_to_m07_couplers": { - "interface_ports": [ - "M_AXI", - "auto_cc/M_AXI" - ] - }, - "m07_couplers_to_auto_cc": { - "interface_ports": [ - "S_AXI", - "auto_cc/S_AXI" - ] - } - }, - "nets": { - "M_ACLK_1": { - "ports": [ - "M_ACLK", - "auto_cc/m_axi_aclk" - ] - }, - "M_ARESETN_1": { - "ports": [ - "M_ARESETN", - "auto_cc/m_axi_aresetn" - ] - }, - "S_ACLK_1": { - "ports": [ - "S_ACLK", - "auto_cc/s_axi_aclk" - ] - }, - "S_ARESETN_1": { - "ports": [ - "S_ARESETN", - "auto_cc/s_axi_aresetn" - ] - } - } - }, - "m08_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m08_couplers_to_m08_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m09_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m09_couplers_to_m09_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - }, - "m10_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m10_couplers_to_m10_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] + "util_ds_buf_1": { + "vlnv": "xilinx.com:ip:util_ds_buf:2.2", + "xci_name": "microblaze_bd_util_ds_buf_1_0", + "xci_path": "ip/microblaze_bd_util_ds_buf_1_0/microblaze_bd_util_ds_buf_1_0.xci", + "inst_hier_path": "jesd/util_ds_buf_1", + "parameters": { + "C_BUF_TYPE": { + "value": "IBUFDS" } } } }, "interface_nets": { - "m00_couplers_to_microblaze_0_axi_periph": { + "Conn1": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "jesd_sysref", + "util_ds_buf_1/CLK_IN_D" ] }, - "m01_couplers_to_microblaze_0_axi_periph": { + "Conn2": { "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" + "jesd_qpll0_refclk", + "util_ds_buf_0/CLK_IN_D" ] }, - "m02_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt0_rx": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "jesd204_phy_0/gt0_rx", + "jesd204c_0/gt0_rx" ] }, - "m03_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt1_rx": { "interface_ports": [ - "M03_AXI", - "m03_couplers/M_AXI" + "jesd204_phy_0/gt1_rx", + "jesd204c_0/gt1_rx" ] }, - "m04_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt2_rx": { "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" + "jesd204_phy_0/gt2_rx", + "jesd204c_0/gt2_rx" ] }, - "m05_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt3_rx": { "interface_ports": [ - "M05_AXI", - "m05_couplers/M_AXI" + "jesd204_phy_0/gt3_rx", + "jesd204c_0/gt3_rx" ] }, - "m06_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt4_rx": { "interface_ports": [ - "M06_AXI", - "m06_couplers/M_AXI" + "jesd204_phy_0/gt4_rx", + "jesd204c_0/gt4_rx" ] }, - "m07_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt5_rx": { "interface_ports": [ - "M07_AXI", - "m07_couplers/M_AXI" + "jesd204_phy_0/gt5_rx", + "jesd204c_0/gt5_rx" ] }, - "m08_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt6_rx": { "interface_ports": [ - "M08_AXI", - "m08_couplers/M_AXI" + "jesd204_phy_0/gt6_rx", + "jesd204c_0/gt6_rx" ] }, - "m09_couplers_to_microblaze_0_axi_periph": { + "jesd204_phy_0_gt7_rx": { "interface_ports": [ - "M09_AXI", - "m09_couplers/M_AXI" + "jesd204_phy_0/gt7_rx", + "jesd204c_0/gt7_rx" ] }, - "m10_couplers_to_microblaze_0_axi_periph": { + "jesd204c_0_m_axis_rx": { "interface_ports": [ - "M10_AXI", - "m10_couplers/M_AXI" + "jesd_axis_rx", + "jesd204c_0/m_axis_rx" ] }, - "microblaze_0_axi_periph_to_s00_couplers": { + "jesd204c_0_m_axis_rx_cmd": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "jesd_axis_rx_cmd", + "jesd204c_0/m_axis_rx_cmd" ] }, - "s00_couplers_to_xbar": { + "jesd204c_1_gt0_tx": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "jesd204c_1/gt0_tx", + "jesd204_phy_0/gt0_tx" ] }, - "xbar_to_m00_couplers": { + "jesd204c_1_gt1_tx": { "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" + "jesd204c_1/gt1_tx", + "jesd204_phy_0/gt1_tx" ] }, - "xbar_to_m01_couplers": { + "jesd204c_1_gt2_tx": { "interface_ports": [ - "xbar/M01_AXI", - "m01_couplers/S_AXI" + "jesd204c_1/gt2_tx", + "jesd204_phy_0/gt2_tx" ] }, - "xbar_to_m02_couplers": { + "jesd204c_1_gt3_tx": { "interface_ports": [ - "xbar/M02_AXI", - "m02_couplers/S_AXI" + "jesd204c_1/gt3_tx", + "jesd204_phy_0/gt3_tx" ] }, - "xbar_to_m03_couplers": { + "jesd204c_1_gt4_tx": { "interface_ports": [ - "xbar/M03_AXI", - "m03_couplers/S_AXI" + "jesd204c_1/gt4_tx", + "jesd204_phy_0/gt4_tx" ] }, - "xbar_to_m04_couplers": { + "jesd204c_1_gt5_tx": { "interface_ports": [ - "xbar/M04_AXI", - "m04_couplers/S_AXI" + "jesd204c_1/gt5_tx", + "jesd204_phy_0/gt5_tx" ] }, - "xbar_to_m05_couplers": { + "jesd204c_1_gt6_tx": { "interface_ports": [ - "xbar/M05_AXI", - "m05_couplers/S_AXI" + "jesd204c_1/gt6_tx", + "jesd204_phy_0/gt6_tx" ] }, - "xbar_to_m06_couplers": { + "jesd204c_1_gt7_tx": { "interface_ports": [ - "xbar/M06_AXI", - "m06_couplers/S_AXI" + "jesd204c_1/gt7_tx", + "jesd204_phy_0/gt7_tx" ] }, - "xbar_to_m07_couplers": { + "microblaze_0_axi_periph_M07_AXI": { "interface_ports": [ - "xbar/M07_AXI", - "m07_couplers/S_AXI" + "s_axi_rx", + "jesd204c_0/s_axi" ] }, - "xbar_to_m08_couplers": { + "microblaze_0_axi_periph_M08_AXI": { "interface_ports": [ - "xbar/M08_AXI", - "m08_couplers/S_AXI" + "s_axi_tx", + "jesd204c_1/s_axi" ] }, - "xbar_to_m09_couplers": { + "s_axi_phy_1": { "interface_ports": [ - "xbar/M09_AXI", - "m09_couplers/S_AXI" + "s_axi_phy", + "jesd204_phy_0/s_axi" ] }, - "xbar_to_m10_couplers": { + "s_axis_tx_0_1": { "interface_ports": [ - "xbar/M10_AXI", - "m10_couplers/S_AXI" + "jesd_axis_tx", + "jesd204c_1/s_axis_tx" + ] + }, + "s_axis_tx_cmd_0_1": { + "interface_ports": [ + "jesd_axis_tx_cmd", + "jesd204c_1/s_axis_tx_cmd" ] } }, "nets": { - "M00_ACLK_1": { + "jesd204_phy_0_common0_qpll0_lock_out": { "ports": [ - "M00_ACLK", - "m00_couplers/M_ACLK" + "jesd204_phy_0/common0_qpll0_lock_out", + "common0_qpll1_lock_out" ] }, - "M00_ARESETN_1": { + "jesd204_phy_0_common1_qpll0_lock_out": { "ports": [ - "M00_ARESETN", - "m00_couplers/M_ARESETN" + "jesd204_phy_0/common1_qpll0_lock_out", + "common1_qpll1_lock_out" ] }, - "M01_ACLK_1": { + "jesd204_phy_0_rx_reset_done": { "ports": [ - "M01_ACLK", - "m01_couplers/M_ACLK" + "jesd204_phy_0/rx_reset_done", + "jesd204c_0/rx_reset_done" ] }, - "M01_ARESETN_1": { + "jesd204_phy_0_tx_reset_done": { "ports": [ - "M01_ARESETN", - "m01_couplers/M_ARESETN" + "jesd204_phy_0/tx_reset_done", + "jesd204c_1/tx_reset_done" ] }, - "M02_ACLK_1": { + "jesd204_phy_0_txn_out": { "ports": [ - "M02_ACLK", - "m02_couplers/M_ACLK" + "jesd204_phy_0/txn_out", + "jesd_txn_out" ] }, - "M02_ARESETN_1": { + "jesd204_phy_0_txoutclk": { "ports": [ - "M02_ARESETN", - "m02_couplers/M_ARESETN" + "jesd_core_clk", + "jesd204_phy_0/tx_core_clk", + "jesd204_phy_0/rx_core_clk", + "jesd204c_0/rx_core_clk", + "jesd204c_1/tx_core_clk" ] }, - "M03_ACLK_1": { + "jesd204_phy_0_txp_out": { "ports": [ - "M03_ACLK", - "m03_couplers/M_ACLK" + "jesd204_phy_0/txp_out", + "jesd_txp_out" ] }, - "M03_ARESETN_1": { + "jesd204c_0_irq": { "ports": [ - "M03_ARESETN", - "m03_couplers/M_ARESETN" + "jesd204c_0/irq", + "irq1" ] }, - "M04_ACLK_1": { + "jesd204c_0_rx_aresetn": { "ports": [ - "M04_ACLK", - "m04_couplers/M_ACLK" + "jesd204c_0/rx_aresetn", + "jesd_axis_rx_aresetn" ] }, - "M04_ARESETN_1": { + "jesd204c_0_rx_reset_gt": { "ports": [ - "M04_ARESETN", - "m04_couplers/M_ARESETN" + "jesd204c_0/rx_reset_gt", + "jesd204_phy_0/rx_reset_gt" ] }, - "M05_ACLK_1": { + "jesd204c_1_irq": { "ports": [ - "M05_ACLK", - "m05_couplers/M_ACLK" + "jesd204c_1/irq", + "irq" ] }, - "M05_ARESETN_1": { + "jesd204c_1_tx_aresetn": { "ports": [ - "M05_ARESETN", - "m05_couplers/M_ARESETN" + "jesd204c_1/tx_aresetn", + "jesd_axis_tx_aresetn" ] }, - "M06_ACLK_1": { + "jesd204c_1_tx_reset_gt": { "ports": [ - "M06_ACLK", - "m06_couplers/M_ACLK" + "jesd204c_1/tx_reset_gt", + "jesd204_phy_0/tx_reset_gt" ] }, - "M06_ARESETN_1": { + "microblaze_0_Clk": { "ports": [ - "M06_ARESETN", - "m06_couplers/M_ARESETN" + "mb_axi_clk", + "jesd204_phy_0/drpclk", + "jesd204_phy_0/s_axi_aclk", + "jesd204c_0/s_axi_aclk", + "jesd204c_1/s_axi_aclk" ] }, - "M07_ACLK_1": { + "rst_clk_wiz_1_100M_peripheral_aresetn": { "ports": [ - "M07_ACLK", - "m07_couplers/M_ACLK" + "mb_axi_aresetn", + "jesd204_phy_0/s_axi_aresetn", + "jesd204c_0/s_axi_aresetn", + "jesd204c_1/s_axi_aresetn" ] }, - "M07_ARESETN_1": { + "rx_core_reset_0_1": { "ports": [ - "M07_ARESETN", - "m07_couplers/M_ARESETN" + "jesd_rx_core_reset", + "jesd204c_0/rx_core_reset" ] }, - "M08_ACLK_1": { + "rx_sys_reset_0_1": { "ports": [ - "M08_ACLK", - "m08_couplers/M_ACLK" + "jesd_rx_sys_reset", + "jesd204_phy_0/rx_sys_reset" ] }, - "M08_ARESETN_1": { + "rxn_in_0_1": { "ports": [ - "M08_ARESETN", - "m08_couplers/M_ARESETN" + "jesd_rxn_in", + "jesd204_phy_0/rxn_in" ] }, - "M09_ACLK_1": { + "rxp_in_0_1": { "ports": [ - "M09_ACLK", - "m09_couplers/M_ACLK" + "jesd_rxp_in", + "jesd204_phy_0/rxp_in" ] }, - "M09_ARESETN_1": { + "tx_core_reset_0_1": { "ports": [ - "M09_ARESETN", - "m09_couplers/M_ARESETN" + "jesd_tx_core_reset", + "jesd204c_1/tx_core_reset" ] }, - "M10_ACLK_1": { + "tx_sys_reset_0_1": { "ports": [ - "M10_ACLK", - "m10_couplers/M_ACLK" + "jesd_tx_sys_reset", + "jesd204_phy_0/tx_sys_reset" ] }, - "M10_ARESETN_1": { + "util_ds_buf_0_IBUF_OUT": { "ports": [ - "M10_ARESETN", - "m10_couplers/M_ARESETN" + "util_ds_buf_0/IBUF_OUT", + "jesd204_phy_0/cpll_refclk", + "jesd204_phy_0/qpll0_refclk", + "jesd204_phy_0/qpll1_refclk" ] }, - "S00_ACLK_1": { + "util_ds_buf_1_IBUF_OUT": { "ports": [ - "S00_ACLK", - "s00_couplers/S_ACLK" - ] - }, - "S00_ARESETN_1": { - "ports": [ - "S00_ARESETN", - "s00_couplers/S_ARESETN" - ] - }, - "microblaze_0_axi_periph_ACLK_net": { - "ports": [ - "ACLK", - "xbar/aclk", - "s00_couplers/M_ACLK", - "m00_couplers/S_ACLK", - "m01_couplers/S_ACLK", - "m02_couplers/S_ACLK", - "m03_couplers/S_ACLK", - "m04_couplers/S_ACLK", - "m05_couplers/S_ACLK", - "m06_couplers/S_ACLK", - "m07_couplers/S_ACLK", - "m08_couplers/S_ACLK", - "m09_couplers/S_ACLK", - "m10_couplers/S_ACLK" - ] - }, - "microblaze_0_axi_periph_ARESETN_net": { - "ports": [ - "ARESETN", - "xbar/aresetn", - "s00_couplers/M_ARESETN", - "m00_couplers/S_ARESETN", - "m01_couplers/S_ARESETN", - "m02_couplers/S_ARESETN", - "m03_couplers/S_ARESETN", - "m04_couplers/S_ARESETN", - "m05_couplers/S_ARESETN", - "m06_couplers/S_ARESETN", - "m07_couplers/S_ARESETN", - "m08_couplers/S_ARESETN", - "m09_couplers/S_ARESETN", - "m10_couplers/S_ARESETN" + "util_ds_buf_1/IBUF_OUT", + "jesd204c_0/rx_sysref", + "jesd204c_1/tx_sysref" ] } } }, - "microblaze_0_axi_intc": { - "vlnv": "xilinx.com:ip:axi_intc:4.1", - "xci_name": "microblaze_bd_microblaze_0_axi_intc_0", - "xci_path": "ip/microblaze_bd_microblaze_0_axi_intc_0/microblaze_bd_microblaze_0_axi_intc_0.xci", - "inst_hier_path": "microblaze_0_axi_intc", + "axi_bram_ctrl_0": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "microblaze_bd_axi_bram_ctrl_0_0", + "xci_path": "ip/microblaze_bd_axi_bram_ctrl_0_0/microblaze_bd_axi_bram_ctrl_0_0.xci", + "inst_hier_path": "axi_bram_ctrl_0", "parameters": { - "C_HAS_FAST": { + "PROTOCOL": { + "value": "AXI4LITE" + }, + "SINGLE_PORT_BRAM": { "value": "1" } } }, - "microblaze_0_xlconcat": { - "vlnv": "xilinx.com:ip:xlconcat:2.1", - "xci_name": "microblaze_bd_microblaze_0_xlconcat_0", - "xci_path": "ip/microblaze_bd_microblaze_0_xlconcat_0/microblaze_bd_microblaze_0_xlconcat_0.xci", - "inst_hier_path": "microblaze_0_xlconcat", + "axi_bram_ctrl_1": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "microblaze_bd_axi_bram_ctrl_0_1", + "xci_path": "ip/microblaze_bd_axi_bram_ctrl_0_1/microblaze_bd_axi_bram_ctrl_0_1.xci", + "inst_hier_path": "axi_bram_ctrl_1", "parameters": { - "NUM_PORTS": { - "value": "13" + "PROTOCOL": { + "value": "AXI4LITE" + }, + "SINGLE_PORT_BRAM": { + "value": "1" } } }, - "mdm_1": { - "vlnv": "xilinx.com:ip:mdm:3.2", - "xci_name": "microblaze_bd_mdm_1_0", - "xci_path": "ip/microblaze_bd_mdm_1_0/microblaze_bd_mdm_1_0.xci", - "inst_hier_path": "mdm_1" - }, - "rst_150": { - "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", - "xci_name": "microblaze_bd_rst_clk_wiz_1_100M_0", - "xci_path": "ip/microblaze_bd_rst_clk_wiz_1_100M_0/microblaze_bd_rst_clk_wiz_1_100M_0.xci", - "inst_hier_path": "rst_150" - }, - "axi_uartlite_0": { - "vlnv": "xilinx.com:ip:axi_uartlite:2.0", - "xci_name": "microblaze_bd_axi_uartlite_0_0", - "xci_path": "ip/microblaze_bd_axi_uartlite_0_0/microblaze_bd_axi_uartlite_0_0.xci", - "inst_hier_path": "axi_uartlite_0", + "axi_bram_ctrl_2": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "microblaze_bd_axi_bram_ctrl_1_1", + "xci_path": "ip/microblaze_bd_axi_bram_ctrl_1_1/microblaze_bd_axi_bram_ctrl_1_1.xci", + "inst_hier_path": "axi_bram_ctrl_2", "parameters": { - "C_BAUDRATE": { - "value": "115200" + "PROTOCOL": { + "value": "AXI4LITE" + }, + "SINGLE_PORT_BRAM": { + "value": "1" } } }, - "axi_timer_0": { - "vlnv": "xilinx.com:ip:axi_timer:2.0", - "xci_name": "microblaze_bd_axi_timer_0_0", - "xci_path": "ip/microblaze_bd_axi_timer_0_0/microblaze_bd_axi_timer_0_0.xci", - "inst_hier_path": "axi_timer_0" + "axi_bram_ctrl_3": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "microblaze_bd_axi_bram_ctrl_1_2", + "xci_path": "ip/microblaze_bd_axi_bram_ctrl_1_2/microblaze_bd_axi_bram_ctrl_1_2.xci", + "inst_hier_path": "axi_bram_ctrl_3", + "parameters": { + "PROTOCOL": { + "value": "AXI4LITE" + }, + "SINGLE_PORT_BRAM": { + "value": "1" + } + } }, "axi_ethernet_0": { "vlnv": "xilinx.com:ip:axi_ethernet:7.2", @@ -4577,52 +3700,114 @@ } } }, - "ddr4_0": { - "vlnv": "xilinx.com:ip:ddr4:2.2", - "xci_name": "microblaze_bd_ddr4_0_0", - "xci_path": "ip/microblaze_bd_ddr4_0_0/microblaze_bd_ddr4_0_0.xci", - "inst_hier_path": "ddr4_0", + "axi_ethernet_0_dma": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "xci_name": "microblaze_bd_axi_ethernet_0_dma_1", + "xci_path": "ip/microblaze_bd_axi_ethernet_0_dma_1/microblaze_bd_axi_ethernet_0_dma_1.xci", + "inst_hier_path": "axi_ethernet_0_dma", "parameters": { - "ADDN_UI_CLKOUT1_FREQ_HZ": { - "value": "150" + "c_include_mm2s_dre": { + "value": "1" }, - "ADDN_UI_CLKOUT2_FREQ_HZ": { - "value": "300" + "c_include_s2mm_dre": { + "value": "1" }, - "C0.DDR4_DataWidth": { - "value": "64" + "c_mm2s_burst_size": { + "value": "256" }, - "C0.DDR4_InputClockPeriod": { - "value": "4998" + "c_s2mm_burst_size": { + "value": "256" }, - "C0.DDR4_MemoryPart": { - "value": "MT40A512M16LY-075" + "c_sg_length_width": { + "value": "16" + }, + "c_sg_use_stsapp_length": { + "value": "1" } }, "interface_ports": { - "C0_DDR4_S_AXI": { + "M_AXI_SG": { "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "memory_map_ref": "C0_DDR4_MEMORY_MAP" + "mode": "Master", + "address_space_ref": "Data_SG", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_MM2S": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data_MM2S", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_S2MM": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data_S2MM", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } } }, "addressing": { - "memory_maps": { - "C0_DDR4_MEMORY_MAP": { - "address_blocks": { - "C0_DDR4_ADDRESS_BLOCK": { - "base_address": "0", - "range": "4G", - "width": "32", - "usage": "memory", - "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", - "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" - } - } + "address_spaces": { + "Data_SG": { + "range": "4G", + "width": "32" + }, + "Data_MM2S": { + "range": "4G", + "width": "32" + }, + "Data_S2MM": { + "range": "4G", + "width": "32" } } } }, + "axi_fifo_mm_s_0": { + "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2", + "xci_name": "microblaze_bd_axi_fifo_mm_s_0_0", + "xci_path": "ip/microblaze_bd_axi_fifo_mm_s_0_0/microblaze_bd_axi_fifo_mm_s_0_0.xci", + "inst_hier_path": "axi_fifo_mm_s_0", + "parameters": { + "C_AXIS_TUSER_WIDTH": { + "value": "4" + }, + "C_DATA_INTERFACE_TYPE": { + "value": "0" + }, + "C_S_AXI4_DATA_WIDTH": { + "value": "32" + }, + "C_USE_TX_CTRL": { + "value": "0" + }, + "C_USE_TX_DATA": { + "value": "1" + } + } + }, + "axi_iic_0": { + "vlnv": "xilinx.com:ip:axi_iic:2.1", + "xci_name": "microblaze_bd_axi_iic_0_0", + "xci_path": "ip/microblaze_bd_axi_iic_0_0/microblaze_bd_axi_iic_0_0.xci", + "inst_hier_path": "axi_iic_0", + "parameters": { + "IIC_FREQ_KHZ": { + "value": "50" + } + } + }, "axi_interconnect_0": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", "xci_path": "ip/microblaze_bd_axi_interconnect_0_0/microblaze_bd_axi_interconnect_0_0.xci", @@ -4660,11 +3845,6 @@ "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, - "M00_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, "S01_AXI": { "mode": "Slave", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", @@ -4684,6 +3864,11 @@ "mode": "Slave", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { @@ -4716,22 +3901,6 @@ "type": "rst", "direction": "I" }, - "M00_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M00_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M00_ARESETN" - } - } - }, - "M00_ARESETN": { - "type": "rst", - "direction": "I" - }, "S01_ACLK": { "type": "clk", "direction": "I", @@ -4795,13 +3964,29 @@ "S04_ARESETN": { "type": "rst", "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" } }, "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "microblaze_bd_xbar_1", - "xci_path": "ip/microblaze_bd_xbar_1/microblaze_bd_xbar_1.xci", + "xci_name": "microblaze_bd_xbar_3", + "xci_path": "ip/microblaze_bd_xbar_3/microblaze_bd_xbar_3.xci", "inst_hier_path": "axi_interconnect_0/xbar", "parameters": { "NUM_MI": { @@ -5319,8 +4504,8 @@ }, "auto_cc": { "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", - "xci_name": "microblaze_bd_auto_cc_1", - "xci_path": "ip/microblaze_bd_auto_cc_1/microblaze_bd_auto_cc_1.xci", + "xci_name": "microblaze_bd_auto_cc_0", + "xci_path": "ip/microblaze_bd_auto_cc_0/microblaze_bd_auto_cc_0.xci", "inst_hier_path": "axi_interconnect_0/s03_couplers/auto_cc", "interface_ports": { "S_AXI": { @@ -5447,8 +4632,8 @@ }, "auto_cc": { "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", - "xci_name": "microblaze_bd_auto_cc_2", - "xci_path": "ip/microblaze_bd_auto_cc_2/microblaze_bd_auto_cc_2.xci", + "xci_name": "microblaze_bd_auto_cc_1", + "xci_path": "ip/microblaze_bd_auto_cc_1/microblaze_bd_auto_cc_1.xci", "inst_hier_path": "axi_interconnect_0/s04_couplers/auto_cc", "interface_ports": { "S_AXI": { @@ -5777,879 +4962,6 @@ } } }, - "rst_ddr": { - "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", - "xci_name": "microblaze_bd_proc_sys_reset_0_0", - "xci_path": "ip/microblaze_bd_proc_sys_reset_0_0/microblaze_bd_proc_sys_reset_0_0.xci", - "inst_hier_path": "rst_ddr" - }, - "axi_ethernet_0_dma": { - "vlnv": "xilinx.com:ip:axi_dma:7.1", - "xci_name": "microblaze_bd_axi_ethernet_0_dma_1", - "xci_path": "ip/microblaze_bd_axi_ethernet_0_dma_1/microblaze_bd_axi_ethernet_0_dma_1.xci", - "inst_hier_path": "axi_ethernet_0_dma", - "parameters": { - "c_include_mm2s_dre": { - "value": "1" - }, - "c_include_s2mm_dre": { - "value": "1" - }, - "c_mm2s_burst_size": { - "value": "256" - }, - "c_s2mm_burst_size": { - "value": "256" - }, - "c_sg_length_width": { - "value": "16" - }, - "c_sg_use_stsapp_length": { - "value": "1" - } - }, - "interface_ports": { - "M_AXI_SG": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data_SG", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - }, - "M_AXI_MM2S": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data_MM2S", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - }, - "M_AXI_S2MM": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data_S2MM", - "base_address": { - "minimum": "0x00000000", - "maximum": "0xFFFFFFFF", - "width": "32" - } - } - }, - "addressing": { - "address_spaces": { - "Data_SG": { - "range": "4G", - "width": "32" - }, - "Data_MM2S": { - "range": "4G", - "width": "32" - }, - "Data_S2MM": { - "range": "4G", - "width": "32" - } - } - } - }, - "clk_wiz_0": { - "vlnv": "xilinx.com:ip:clk_wiz:6.0", - "xci_name": "microblaze_bd_clk_wiz_0_1", - "xci_path": "ip/microblaze_bd_clk_wiz_0_1/microblaze_bd_clk_wiz_0_1.xci", - "inst_hier_path": "clk_wiz_0", - "parameters": { - "CLKOUT1_JITTER": { - "value": "150.364" - }, - "CLKOUT1_REQUESTED_OUT_FREQ": { - "value": "125" - }, - "CLKOUT2_JITTER": { - "value": "126.608" - }, - "CLKOUT2_PHASE_ERROR": { - "value": "164.985" - }, - "CLKOUT2_REQUESTED_OUT_FREQ": { - "value": "333.33333" - }, - "CLKOUT2_USED": { - "value": "true" - }, - "CLKOUT3_JITTER": { - "value": "211.559" - }, - "CLKOUT3_PHASE_ERROR": { - "value": "164.985" - }, - "CLKOUT3_REQUESTED_OUT_FREQ": { - "value": "25" - }, - "CLKOUT3_USED": { - "value": "true" - }, - "MMCM_CLKOUT0_DIVIDE_F": { - "value": "8.000" - }, - "MMCM_CLKOUT1_DIVIDE": { - "value": "3" - }, - "MMCM_CLKOUT2_DIVIDE": { - "value": "40" - }, - "NUM_OUT_CLKS": { - "value": "3" - }, - "PRIM_SOURCE": { - "value": "Global_buffer" - }, - "USE_LOCKED": { - "value": "false" - }, - "USE_RESET": { - "value": "false" - } - } - }, - "system_management_wiz_0": { - "vlnv": "xilinx.com:ip:system_management_wiz:1.3", - "xci_name": "microblaze_bd_system_management_wiz_0_0", - "xci_path": "ip/microblaze_bd_system_management_wiz_0_0/microblaze_bd_system_management_wiz_0_0.xci", - "inst_hier_path": "system_management_wiz_0", - "parameters": { - "CHANNEL_ENABLE_VBRAM": { - "value": "false" - }, - "CHANNEL_ENABLE_VCCAUX": { - "value": "false" - }, - "CHANNEL_ENABLE_VCCINT": { - "value": "false" - }, - "CHANNEL_ENABLE_VP_VN": { - "value": "false" - }, - "ENABLE_TEMP_BUS": { - "value": "false" - }, - "OT_ALARM": { - "value": "false" - }, - "USER_TEMP_ALARM": { - "value": "false" - }, - "VCCAUX_ALARM": { - "value": "false" - }, - "VCCINT_ALARM": { - "value": "false" - } - } - }, - "axi_quad_spi_0": { - "vlnv": "xilinx.com:ip:axi_quad_spi:3.2", - "xci_name": "microblaze_bd_axi_quad_spi_0_0", - "xci_path": "ip/microblaze_bd_axi_quad_spi_0_0/microblaze_bd_axi_quad_spi_0_0.xci", - "inst_hier_path": "axi_quad_spi_0", - "parameters": { - "C_NUM_SS_BITS": { - "value": "1" - }, - "Multiples16": { - "value": "2" - } - } - }, - "axi_quad_spi_1": { - "vlnv": "xilinx.com:ip:axi_quad_spi:3.2", - "xci_name": "microblaze_bd_axi_quad_spi_1_0", - "xci_path": "ip/microblaze_bd_axi_quad_spi_1_0/microblaze_bd_axi_quad_spi_1_0.xci", - "inst_hier_path": "axi_quad_spi_1", - "parameters": { - "C_NUM_SS_BITS": { - "value": "2" - }, - "Multiples16": { - "value": "2" - } - } - }, - "jesd": { - "interface_ports": { - "s_axi_tx": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "jesd_axis_tx": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0" - }, - "jesd_axis_tx_cmd": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0" - }, - "s_axi_rx": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "jesd_axis_rx": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0" - }, - "jesd_axis_rx_cmd": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", - "vlnv": "xilinx.com:interface:axis_rtl:1.0" - }, - "jesd_sysref": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0", - "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0" - }, - "jesd_qpll0_refclk": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0", - "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0" - }, - "s_axi_phy": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "mb_axi_clk": { - "type": "clk", - "direction": "I" - }, - "jesd_txp_out": { - "direction": "O", - "left": "7", - "right": "0" - }, - "jesd_txn_out": { - "direction": "O", - "left": "7", - "right": "0" - }, - "jesd_rxp_in": { - "direction": "I", - "left": "7", - "right": "0" - }, - "jesd_rxn_in": { - "direction": "I", - "left": "7", - "right": "0" - }, - "mb_axi_aresetn": { - "type": "rst", - "direction": "I" - }, - "jesd_tx_core_reset": { - "direction": "I" - }, - "irq": { - "direction": "O" - }, - "jesd_axis_tx_aresetn": { - "type": "rst", - "direction": "O" - }, - "jesd_rx_core_reset": { - "direction": "I" - }, - "irq1": { - "direction": "O" - }, - "jesd_axis_rx_aresetn": { - "type": "rst", - "direction": "O" - }, - "common0_qpll1_lock_out": { - "direction": "O" - }, - "common1_qpll1_lock_out": { - "direction": "O" - }, - "jesd_core_clk": { - "direction": "I" - }, - "jesd_tx_sys_reset": { - "direction": "I" - }, - "jesd_rx_sys_reset": { - "direction": "I" - } - }, - "components": { - "jesd204_phy_0": { - "vlnv": "xilinx.com:ip:jesd204_phy:4.0", - "xci_name": "microblaze_bd_jesd204_phy_0_0", - "xci_path": "ip/microblaze_bd_jesd204_phy_0_0/microblaze_bd_jesd204_phy_0_0.xci", - "inst_hier_path": "jesd/jesd204_phy_0", - "parameters": { - "Axi_Lite": { - "value": "true" - }, - "C_LANES": { - "value": "8" - }, - "C_PLL_SELECTION": { - "value": "1" - }, - "DRPCLK_FREQ": { - "value": "125.0" - }, - "Equalization_Mode": { - "value": "High_Loss" - }, - "GT_Line_Rate": { - "value": "12.375" - }, - "GT_Location": { - "value": "X0Y12" - }, - "GT_REFCLK_FREQ": { - "value": "187.5" - }, - "RX_GT_Line_Rate": { - "value": "12.375" - }, - "RX_GT_REFCLK_FREQ": { - "value": "187.5" - }, - "RX_PLL_SELECTION": { - "value": "1" - }, - "Rx_JesdVersion": { - "value": "1" - }, - "Rx_use_64b": { - "value": "1" - }, - "TransceiverControl": { - "value": "false" - }, - "Tx_JesdVersion": { - "value": "1" - }, - "Tx_use_64b": { - "value": "1" - } - }, - "interface_ports": { - "s_axi": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "memory_map_ref": "s_axi" - } - }, - "addressing": { - "memory_maps": { - "s_axi": { - "address_blocks": { - "Reg": { - "base_address": "0", - "range": "4K", - "width": "12", - "usage": "register" - } - } - } - } - } - }, - "jesd204c_1": { - "vlnv": "xilinx.com:ip:jesd204c:4.2", - "xci_name": "microblaze_bd_jesd204c_1_0", - "xci_path": "ip/microblaze_bd_jesd204c_1_0/microblaze_bd_jesd204c_1_0.xci", - "inst_hier_path": "jesd/jesd204c_1", - "parameters": { - "AXICLK_FREQ": { - "value": "150" - }, - "C_LANES": { - "value": "8" - }, - "C_PLL_SELECTION": { - "value": "1" - }, - "DRPCLK_FREQ": { - "value": "187.5" - }, - "GT_Line_Rate": { - "value": "12.375" - }, - "GT_REFCLK_FREQ": { - "value": "187.5" - } - }, - "interface_ports": { - "s_axi": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "memory_map_ref": "s_axi" - } - }, - "addressing": { - "memory_maps": { - "s_axi": { - "address_blocks": { - "Reg": { - "base_address": "0", - "range": "4K", - "width": "12", - "usage": "register" - } - } - } - } - } - }, - "jesd204c_0": { - "vlnv": "xilinx.com:ip:jesd204c:4.2", - "xci_name": "microblaze_bd_jesd204c_0_0", - "xci_path": "ip/microblaze_bd_jesd204c_0_0/microblaze_bd_jesd204c_0_0.xci", - "inst_hier_path": "jesd/jesd204c_0", - "parameters": { - "AXICLK_FREQ": { - "value": "150.0" - }, - "C_LANES": { - "value": "8" - }, - "C_NODE_IS_TRANSMIT": { - "value": "0" - }, - "C_PLL_SELECTION": { - "value": "1" - }, - "DRPCLK_FREQ": { - "value": "187.5" - }, - "GT_Line_Rate": { - "value": "12.375" - }, - "GT_REFCLK_FREQ": { - "value": "187.5" - } - }, - "interface_ports": { - "s_axi": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "memory_map_ref": "s_axi" - } - }, - "addressing": { - "memory_maps": { - "s_axi": { - "address_blocks": { - "Reg": { - "base_address": "0", - "range": "4K", - "width": "12", - "usage": "register" - } - } - } - } - } - }, - "util_ds_buf_1": { - "vlnv": "xilinx.com:ip:util_ds_buf:2.2", - "xci_name": "microblaze_bd_util_ds_buf_1_0", - "xci_path": "ip/microblaze_bd_util_ds_buf_1_0/microblaze_bd_util_ds_buf_1_0.xci", - "inst_hier_path": "jesd/util_ds_buf_1", - "parameters": { - "C_BUF_TYPE": { - "value": "IBUFDS" - } - } - }, - "util_ds_buf_0": { - "vlnv": "xilinx.com:ip:util_ds_buf:2.2", - "xci_name": "microblaze_bd_util_ds_buf_0_0", - "xci_path": "ip/microblaze_bd_util_ds_buf_0_0/microblaze_bd_util_ds_buf_0_0.xci", - "inst_hier_path": "jesd/util_ds_buf_0", - "parameters": { - "C_BUF_TYPE": { - "value": "IBUFDSGTE" - } - } - } - }, - "interface_nets": { - "Conn1": { - "interface_ports": [ - "jesd_sysref", - "util_ds_buf_1/CLK_IN_D" - ] - }, - "Conn2": { - "interface_ports": [ - "jesd_qpll0_refclk", - "util_ds_buf_0/CLK_IN_D" - ] - }, - "jesd204_phy_0_gt0_rx": { - "interface_ports": [ - "jesd204_phy_0/gt0_rx", - "jesd204c_0/gt0_rx" - ] - }, - "jesd204_phy_0_gt1_rx": { - "interface_ports": [ - "jesd204_phy_0/gt1_rx", - "jesd204c_0/gt1_rx" - ] - }, - "jesd204_phy_0_gt2_rx": { - "interface_ports": [ - "jesd204_phy_0/gt2_rx", - "jesd204c_0/gt2_rx" - ] - }, - "jesd204_phy_0_gt3_rx": { - "interface_ports": [ - "jesd204_phy_0/gt3_rx", - "jesd204c_0/gt3_rx" - ] - }, - "jesd204_phy_0_gt4_rx": { - "interface_ports": [ - "jesd204_phy_0/gt4_rx", - "jesd204c_0/gt4_rx" - ] - }, - "jesd204_phy_0_gt5_rx": { - "interface_ports": [ - "jesd204_phy_0/gt5_rx", - "jesd204c_0/gt5_rx" - ] - }, - "jesd204_phy_0_gt6_rx": { - "interface_ports": [ - "jesd204_phy_0/gt6_rx", - "jesd204c_0/gt6_rx" - ] - }, - "jesd204_phy_0_gt7_rx": { - "interface_ports": [ - "jesd204_phy_0/gt7_rx", - "jesd204c_0/gt7_rx" - ] - }, - "jesd204c_0_m_axis_rx": { - "interface_ports": [ - "jesd_axis_rx", - "jesd204c_0/m_axis_rx" - ] - }, - "jesd204c_0_m_axis_rx_cmd": { - "interface_ports": [ - "jesd_axis_rx_cmd", - "jesd204c_0/m_axis_rx_cmd" - ] - }, - "jesd204c_1_gt0_tx": { - "interface_ports": [ - "jesd204c_1/gt0_tx", - "jesd204_phy_0/gt0_tx" - ] - }, - "jesd204c_1_gt1_tx": { - "interface_ports": [ - "jesd204c_1/gt1_tx", - "jesd204_phy_0/gt1_tx" - ] - }, - "jesd204c_1_gt2_tx": { - "interface_ports": [ - "jesd204c_1/gt2_tx", - "jesd204_phy_0/gt2_tx" - ] - }, - "jesd204c_1_gt3_tx": { - "interface_ports": [ - "jesd204c_1/gt3_tx", - "jesd204_phy_0/gt3_tx" - ] - }, - "jesd204c_1_gt4_tx": { - "interface_ports": [ - "jesd204c_1/gt4_tx", - "jesd204_phy_0/gt4_tx" - ] - }, - "jesd204c_1_gt5_tx": { - "interface_ports": [ - "jesd204c_1/gt5_tx", - "jesd204_phy_0/gt5_tx" - ] - }, - "jesd204c_1_gt6_tx": { - "interface_ports": [ - "jesd204c_1/gt6_tx", - "jesd204_phy_0/gt6_tx" - ] - }, - "jesd204c_1_gt7_tx": { - "interface_ports": [ - "jesd204c_1/gt7_tx", - "jesd204_phy_0/gt7_tx" - ] - }, - "microblaze_0_axi_periph_M07_AXI": { - "interface_ports": [ - "s_axi_rx", - "jesd204c_0/s_axi" - ] - }, - "microblaze_0_axi_periph_M08_AXI": { - "interface_ports": [ - "s_axi_tx", - "jesd204c_1/s_axi" - ] - }, - "s_axi_phy_1": { - "interface_ports": [ - "s_axi_phy", - "jesd204_phy_0/s_axi" - ] - }, - "s_axis_tx_0_1": { - "interface_ports": [ - "jesd_axis_tx", - "jesd204c_1/s_axis_tx" - ] - }, - "s_axis_tx_cmd_0_1": { - "interface_ports": [ - "jesd_axis_tx_cmd", - "jesd204c_1/s_axis_tx_cmd" - ] - } - }, - "nets": { - "jesd204_phy_0_common0_qpll0_lock_out": { - "ports": [ - "jesd204_phy_0/common0_qpll0_lock_out", - "common0_qpll1_lock_out" - ] - }, - "jesd204_phy_0_common1_qpll0_lock_out": { - "ports": [ - "jesd204_phy_0/common1_qpll0_lock_out", - "common1_qpll1_lock_out" - ] - }, - "jesd204_phy_0_rx_reset_done": { - "ports": [ - "jesd204_phy_0/rx_reset_done", - "jesd204c_0/rx_reset_done" - ] - }, - "jesd204_phy_0_tx_reset_done": { - "ports": [ - "jesd204_phy_0/tx_reset_done", - "jesd204c_1/tx_reset_done" - ] - }, - "jesd204_phy_0_txn_out": { - "ports": [ - "jesd204_phy_0/txn_out", - "jesd_txn_out" - ] - }, - "jesd204_phy_0_txoutclk": { - "ports": [ - "jesd_core_clk", - "jesd204c_1/tx_core_clk", - "jesd204_phy_0/tx_core_clk", - "jesd204c_0/rx_core_clk", - "jesd204_phy_0/rx_core_clk" - ] - }, - "jesd204_phy_0_txp_out": { - "ports": [ - "jesd204_phy_0/txp_out", - "jesd_txp_out" - ] - }, - "jesd204c_0_irq": { - "ports": [ - "jesd204c_0/irq", - "irq1" - ] - }, - "jesd204c_0_rx_aresetn": { - "ports": [ - "jesd204c_0/rx_aresetn", - "jesd_axis_rx_aresetn" - ] - }, - "jesd204c_0_rx_reset_gt": { - "ports": [ - "jesd204c_0/rx_reset_gt", - "jesd204_phy_0/rx_reset_gt" - ] - }, - "jesd204c_1_irq": { - "ports": [ - "jesd204c_1/irq", - "irq" - ] - }, - "jesd204c_1_tx_aresetn": { - "ports": [ - "jesd204c_1/tx_aresetn", - "jesd_axis_tx_aresetn" - ] - }, - "jesd204c_1_tx_reset_gt": { - "ports": [ - "jesd204c_1/tx_reset_gt", - "jesd204_phy_0/tx_reset_gt" - ] - }, - "microblaze_0_Clk": { - "ports": [ - "mb_axi_clk", - "jesd204c_0/s_axi_aclk", - "jesd204c_1/s_axi_aclk", - "jesd204_phy_0/drpclk", - "jesd204_phy_0/s_axi_aclk" - ] - }, - "rst_clk_wiz_1_100M_peripheral_aresetn": { - "ports": [ - "mb_axi_aresetn", - "jesd204c_0/s_axi_aresetn", - "jesd204c_1/s_axi_aresetn", - "jesd204_phy_0/s_axi_aresetn" - ] - }, - "rx_core_reset_0_1": { - "ports": [ - "jesd_rx_core_reset", - "jesd204c_0/rx_core_reset" - ] - }, - "rx_sys_reset_0_1": { - "ports": [ - "jesd_rx_sys_reset", - "jesd204_phy_0/rx_sys_reset" - ] - }, - "rxn_in_0_1": { - "ports": [ - "jesd_rxn_in", - "jesd204_phy_0/rxn_in" - ] - }, - "rxp_in_0_1": { - "ports": [ - "jesd_rxp_in", - "jesd204_phy_0/rxp_in" - ] - }, - "tx_core_reset_0_1": { - "ports": [ - "jesd_tx_core_reset", - "jesd204c_1/tx_core_reset" - ] - }, - "tx_sys_reset_0_1": { - "ports": [ - "jesd_tx_sys_reset", - "jesd204_phy_0/tx_sys_reset" - ] - }, - "util_ds_buf_0_IBUF_OUT": { - "ports": [ - "util_ds_buf_0/IBUF_OUT", - "jesd204_phy_0/cpll_refclk", - "jesd204_phy_0/qpll0_refclk", - "jesd204_phy_0/qpll1_refclk" - ] - }, - "util_ds_buf_1_IBUF_OUT": { - "ports": [ - "util_ds_buf_1/IBUF_OUT", - "jesd204c_0/rx_sysref", - "jesd204c_1/tx_sysref" - ] - } - } - }, - "axi_bram_ctrl_0": { - "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", - "xci_name": "microblaze_bd_axi_bram_ctrl_0_0", - "xci_path": "ip/microblaze_bd_axi_bram_ctrl_0_0/microblaze_bd_axi_bram_ctrl_0_0.xci", - "inst_hier_path": "axi_bram_ctrl_0", - "parameters": { - "PROTOCOL": { - "value": "AXI4LITE" - }, - "SINGLE_PORT_BRAM": { - "value": "1" - } - } - }, - "axi_bram_ctrl_2": { - "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", - "xci_name": "microblaze_bd_axi_bram_ctrl_1_1", - "xci_path": "ip/microblaze_bd_axi_bram_ctrl_1_1/microblaze_bd_axi_bram_ctrl_1_1.xci", - "inst_hier_path": "axi_bram_ctrl_2", - "parameters": { - "PROTOCOL": { - "value": "AXI4LITE" - }, - "SINGLE_PORT_BRAM": { - "value": "1" - } - } - }, - "axi_bram_ctrl_3": { - "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", - "xci_name": "microblaze_bd_axi_bram_ctrl_1_2", - "xci_path": "ip/microblaze_bd_axi_bram_ctrl_1_2/microblaze_bd_axi_bram_ctrl_1_2.xci", - "inst_hier_path": "axi_bram_ctrl_3", - "parameters": { - "PROTOCOL": { - "value": "AXI4LITE" - }, - "SINGLE_PORT_BRAM": { - "value": "1" - } - } - }, - "axi_bram_ctrl_1": { - "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", - "xci_name": "microblaze_bd_axi_bram_ctrl_0_1", - "xci_path": "ip/microblaze_bd_axi_bram_ctrl_0_1/microblaze_bd_axi_bram_ctrl_0_1.xci", - "inst_hier_path": "axi_bram_ctrl_1", - "parameters": { - "PROTOCOL": { - "value": "AXI4LITE" - }, - "SINGLE_PORT_BRAM": { - "value": "1" - } - } - }, "axi_interconnect_1": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", "xci_path": "ip/microblaze_bd_axi_interconnect_1_0/microblaze_bd_axi_interconnect_1_0.xci", @@ -6657,7 +4969,7 @@ "xci_name": "microblaze_bd_axi_interconnect_1_0", "parameters": { "NUM_MI": { - "value": "12" + "value": "13" } }, "interface_ports": { @@ -6725,6 +5037,11 @@ "mode": "Master", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M12_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { @@ -6948,17 +5265,33 @@ "M11_ARESETN": { "type": "rst", "direction": "I" + }, + "M12_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M12_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M12_ARESETN" + } + } + }, + "M12_ARESETN": { + "type": "rst", + "direction": "I" } }, "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "microblaze_bd_xbar_2", - "xci_path": "ip/microblaze_bd_xbar_2/microblaze_bd_xbar_2.xci", + "xci_name": "microblaze_bd_xbar_4", + "xci_path": "ip/microblaze_bd_xbar_4/microblaze_bd_xbar_4.xci", "inst_hier_path": "axi_interconnect_1/xbar", "parameters": { "NUM_MI": { - "value": "12" + "value": "13" }, "NUM_SI": { "value": "1" @@ -6983,7 +5316,8 @@ "M08_AXI", "M09_AXI", "M10_AXI", - "M11_AXI" + "M11_AXI", + "M12_AXI" ] } } @@ -7715,6 +6049,62 @@ ] } } + }, + "m12_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m12_couplers_to_m12_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } } }, "interface_nets": { @@ -7796,6 +6186,12 @@ "m11_couplers/M_AXI" ] }, + "m12_couplers_to_axi_interconnect_1": { + "interface_ports": [ + "M12_AXI", + "m12_couplers/M_AXI" + ] + }, "s00_couplers_to_xbar": { "interface_ports": [ "s00_couplers/M_AXI", @@ -7873,6 +6269,12 @@ "xbar/M11_AXI", "m11_couplers/S_AXI" ] + }, + "xbar_to_m12_couplers": { + "interface_ports": [ + "xbar/M12_AXI", + "m12_couplers/S_AXI" + ] } }, "nets": { @@ -7894,6 +6296,7 @@ "m09_couplers/M_ACLK", "m10_couplers/M_ACLK", "m11_couplers/M_ACLK", + "m12_couplers/M_ACLK", "m00_couplers/S_ACLK", "m01_couplers/S_ACLK", "m02_couplers/S_ACLK", @@ -7905,7 +6308,8 @@ "m08_couplers/S_ACLK", "m09_couplers/S_ACLK", "m10_couplers/S_ACLK", - "m11_couplers/S_ACLK" + "m11_couplers/S_ACLK", + "m12_couplers/S_ACLK" ] }, "axi_interconnect_1_ARESETN_net": { @@ -7926,6 +6330,7 @@ "m09_couplers/M_ARESETN", "m10_couplers/M_ARESETN", "m11_couplers/M_ARESETN", + "m12_couplers/M_ARESETN", "m00_couplers/S_ARESETN", "m01_couplers/S_ARESETN", "m02_couplers/S_ARESETN", @@ -7937,53 +6342,37 @@ "m08_couplers/S_ARESETN", "m09_couplers/S_ARESETN", "m10_couplers/S_ARESETN", - "m11_couplers/S_ARESETN" + "m11_couplers/S_ARESETN", + "m12_couplers/S_ARESETN" ] } } }, - "axi_fifo_mm_s_0": { - "vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2", - "xci_name": "microblaze_bd_axi_fifo_mm_s_0_0", - "xci_path": "ip/microblaze_bd_axi_fifo_mm_s_0_0/microblaze_bd_axi_fifo_mm_s_0_0.xci", - "inst_hier_path": "axi_fifo_mm_s_0", + "axi_quad_spi_0": { + "vlnv": "xilinx.com:ip:axi_quad_spi:3.2", + "xci_name": "microblaze_bd_axi_quad_spi_0_0", + "xci_path": "ip/microblaze_bd_axi_quad_spi_0_0/microblaze_bd_axi_quad_spi_0_0.xci", + "inst_hier_path": "axi_quad_spi_0", "parameters": { - "C_AXIS_TUSER_WIDTH": { - "value": "4" - }, - "C_DATA_INTERFACE_TYPE": { - "value": "0" - }, - "C_S_AXI4_DATA_WIDTH": { - "value": "32" - }, - "C_USE_TX_CTRL": { - "value": "0" - }, - "C_USE_TX_DATA": { + "C_NUM_SS_BITS": { "value": "1" + }, + "Multiples16": { + "value": "2" } } }, - "axis_dwidth_converter_0": { - "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1", - "xci_name": "microblaze_bd_axis_dwidth_converter_0_0", - "xci_path": "ip/microblaze_bd_axis_dwidth_converter_0_0/microblaze_bd_axis_dwidth_converter_0_0.xci", - "inst_hier_path": "axis_dwidth_converter_0", + "axi_quad_spi_1": { + "vlnv": "xilinx.com:ip:axi_quad_spi:3.2", + "xci_name": "microblaze_bd_axi_quad_spi_1_0", + "xci_path": "ip/microblaze_bd_axi_quad_spi_1_0/microblaze_bd_axi_quad_spi_1_0.xci", + "inst_hier_path": "axi_quad_spi_1", "parameters": { - "M_TDATA_NUM_BYTES": { - "value": "4" - } - } - }, - "axis_dwidth_converter_1": { - "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1", - "xci_name": "microblaze_bd_axis_dwidth_converter_1_0", - "xci_path": "ip/microblaze_bd_axis_dwidth_converter_1_0/microblaze_bd_axis_dwidth_converter_1_0.xci", - "inst_hier_path": "axis_dwidth_converter_1", - "parameters": { - "M_TDATA_NUM_BYTES": { - "value": "8" + "C_NUM_SS_BITS": { + "value": "2" + }, + "Multiples16": { + "value": "2" } } }, @@ -8006,6 +6395,1863 @@ "value": "1" } } + }, + "axi_timer_0": { + "vlnv": "xilinx.com:ip:axi_timer:2.0", + "xci_name": "microblaze_bd_axi_timer_0_0", + "xci_path": "ip/microblaze_bd_axi_timer_0_0/microblaze_bd_axi_timer_0_0.xci", + "inst_hier_path": "axi_timer_0" + }, + "axi_uartlite_0": { + "vlnv": "xilinx.com:ip:axi_uartlite:2.0", + "xci_name": "microblaze_bd_axi_uartlite_0_0", + "xci_path": "ip/microblaze_bd_axi_uartlite_0_0/microblaze_bd_axi_uartlite_0_0.xci", + "inst_hier_path": "axi_uartlite_0", + "parameters": { + "C_BAUDRATE": { + "value": "115200" + }, + "C_S_AXI_ACLK_FREQ_HZ": { + "value": "125000000" + } + } + }, + "axis_dwidth_converter_0": { + "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1", + "xci_name": "microblaze_bd_axis_dwidth_converter_0_0", + "xci_path": "ip/microblaze_bd_axis_dwidth_converter_0_0/microblaze_bd_axis_dwidth_converter_0_0.xci", + "inst_hier_path": "axis_dwidth_converter_0", + "parameters": { + "M_TDATA_NUM_BYTES": { + "value": "4" + } + } + }, + "axis_dwidth_converter_1": { + "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1", + "xci_name": "microblaze_bd_axis_dwidth_converter_1_0", + "xci_path": "ip/microblaze_bd_axis_dwidth_converter_1_0/microblaze_bd_axis_dwidth_converter_1_0.xci", + "inst_hier_path": "axis_dwidth_converter_1", + "parameters": { + "HAS_MI_TKEEP": { + "value": "1" + }, + "M_TDATA_NUM_BYTES": { + "value": "8" + } + } + }, + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "microblaze_bd_clk_wiz_0_1", + "xci_path": "ip/microblaze_bd_clk_wiz_0_1/microblaze_bd_clk_wiz_0_1.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLKIN1_JITTER_PS": { + "value": "80.0" + }, + "CLKOUT1_JITTER": { + "value": "119.348" + }, + "CLKOUT1_PHASE_ERROR": { + "value": "96.948" + }, + "CLKOUT1_REQUESTED_OUT_FREQ": { + "value": "125" + }, + "CLKOUT2_JITTER": { + "value": "99.263" + }, + "CLKOUT2_PHASE_ERROR": { + "value": "96.948" + }, + "CLKOUT2_REQUESTED_OUT_FREQ": { + "value": "333.33333" + }, + "CLKOUT2_USED": { + "value": "true" + }, + "CLKOUT3_JITTER": { + "value": "165.419" + }, + "CLKOUT3_PHASE_ERROR": { + "value": "96.948" + }, + "CLKOUT3_REQUESTED_OUT_FREQ": { + "value": "25" + }, + "CLKOUT3_USED": { + "value": "true" + }, + "MMCM_CLKFBOUT_MULT_F": { + "value": "8.000" + }, + "MMCM_CLKIN1_PERIOD": { + "value": "8.000" + }, + "MMCM_CLKOUT0_DIVIDE_F": { + "value": "8.000" + }, + "MMCM_CLKOUT1_DIVIDE": { + "value": "3" + }, + "MMCM_CLKOUT2_DIVIDE": { + "value": "40" + }, + "MMCM_DIVCLK_DIVIDE": { + "value": "1" + }, + "NUM_OUT_CLKS": { + "value": "3" + }, + "PRIM_SOURCE": { + "value": "Global_buffer" + }, + "USE_LOCKED": { + "value": "false" + }, + "USE_RESET": { + "value": "false" + } + } + }, + "ddr4_0": { + "vlnv": "xilinx.com:ip:ddr4:2.2", + "xci_name": "microblaze_bd_ddr4_0_0", + "xci_path": "ip/microblaze_bd_ddr4_0_0/microblaze_bd_ddr4_0_0.xci", + "inst_hier_path": "ddr4_0", + "parameters": { + "ADDN_UI_CLKOUT1_FREQ_HZ": { + "value": "125" + }, + "ADDN_UI_CLKOUT2_FREQ_HZ": { + "value": "None" + }, + "C0.BANK_GROUP_WIDTH": { + "value": "1" + }, + "C0.DDR4_AxiAddressWidth": { + "value": "32" + }, + "C0.DDR4_AxiDataWidth": { + "value": "512" + }, + "C0.DDR4_CasLatency": { + "value": "15" + }, + "C0.DDR4_CasWriteLatency": { + "value": "11" + }, + "C0.DDR4_DataWidth": { + "value": "64" + }, + "C0.DDR4_InputClockPeriod": { + "value": "5000" + }, + "C0.DDR4_MemoryPart": { + "value": "MT40A512M16LY-075" + }, + "C0.DDR4_TimePeriod": { + "value": "1000" + } + }, + "interface_ports": { + "C0_DDR4_S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "C0_DDR4_MEMORY_MAP" + } + }, + "addressing": { + "memory_maps": { + "C0_DDR4_MEMORY_MAP": { + "address_blocks": { + "C0_DDR4_ADDRESS_BLOCK": { + "base_address": "0", + "range": "4G", + "width": "32", + "usage": "memory", + "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", + "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" + } + } + } + } + } + }, + "mdm_1": { + "vlnv": "xilinx.com:ip:mdm:3.2", + "xci_name": "microblaze_bd_mdm_1_0", + "xci_path": "ip/microblaze_bd_mdm_1_0/microblaze_bd_mdm_1_0.xci", + "inst_hier_path": "mdm_1" + }, + "microblaze_0": { + "vlnv": "xilinx.com:ip:microblaze:11.0", + "xci_name": "microblaze_bd_microblaze_0_0", + "xci_path": "ip/microblaze_bd_microblaze_0_0/microblaze_bd_microblaze_0_0.xci", + "inst_hier_path": "microblaze_0", + "parameters": { + "C_ADDR_TAG_BITS": { + "value": "16" + }, + "C_BRANCH_TARGET_CACHE_SIZE": { + "value": "0" + }, + "C_CACHE_BYTE_SIZE": { + "value": "32768" + }, + "C_DCACHE_ADDR_TAG": { + "value": "16" + }, + "C_DCACHE_BYTE_SIZE": { + "value": "32768" + }, + "C_DCACHE_DATA_WIDTH": { + "value": "1" + }, + "C_DCACHE_LINE_LEN": { + "value": "16" + }, + "C_DCACHE_USE_WRITEBACK": { + "value": "1" + }, + "C_DCACHE_VICTIMS": { + "value": "8" + }, + "C_DEBUG_ENABLED": { + "value": "1" + }, + "C_DIV_ZERO_EXCEPTION": { + "value": "1" + }, + "C_D_AXI": { + "value": "1" + }, + "C_D_LMB": { + "value": "1" + }, + "C_FPU_EXCEPTION": { + "value": "1" + }, + "C_ICACHE_DATA_WIDTH": { + "value": "1" + }, + "C_ICACHE_LINE_LEN": { + "value": "16" + }, + "C_ICACHE_STREAMS": { + "value": "1" + }, + "C_ICACHE_VICTIMS": { + "value": "8" + }, + "C_ILL_OPCODE_EXCEPTION": { + "value": "1" + }, + "C_I_LMB": { + "value": "1" + }, + "C_M_AXI_D_BUS_EXCEPTION": { + "value": "1" + }, + "C_M_AXI_I_BUS_EXCEPTION": { + "value": "1" + }, + "C_NUMBER_OF_PC_BRK": { + "value": "2" + }, + "C_OPCODE_0x0_ILLEGAL": { + "value": "1" + }, + "C_UNALIGNED_EXCEPTIONS": { + "value": "1" + }, + "C_USE_BARREL": { + "value": "1" + }, + "C_USE_BRANCH_TARGET_CACHE": { + "value": "0" + }, + "C_USE_DCACHE": { + "value": "1" + }, + "C_USE_DIV": { + "value": "1" + }, + "C_USE_FPU": { + "value": "1" + }, + "C_USE_HW_MUL": { + "value": "1" + }, + "C_USE_ICACHE": { + "value": "1" + }, + "C_USE_MSR_INSTR": { + "value": "1" + }, + "C_USE_PCMP_INSTR": { + "value": "1" + }, + "C_USE_STACK_PROTECTION": { + "value": "1" + }, + "G_TEMPLATE_LIST": { + "value": "9" + }, + "G_USE_EXCEPTIONS": { + "value": "1" + } + }, + "interface_ports": { + "DLMB": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "ILMB": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "Master", + "address_space_ref": "Instruction", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_DP": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_DC": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_IC": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Instruction", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32" + }, + "Instruction": { + "range": "4G", + "width": "32" + } + } + }, + "hdl_attributes": { + "BMM_INFO_PROCESSOR": { + "value": "microblaze-le > microblaze_bd microblaze_0_local_memory/dlmb_bram_if_cntlr", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "microblaze_0_axi_intc": { + "vlnv": "xilinx.com:ip:axi_intc:4.1", + "xci_name": "microblaze_bd_microblaze_0_axi_intc_0", + "xci_path": "ip/microblaze_bd_microblaze_0_axi_intc_0/microblaze_bd_microblaze_0_axi_intc_0.xci", + "inst_hier_path": "microblaze_0_axi_intc", + "parameters": { + "C_HAS_FAST": { + "value": "1" + } + } + }, + "microblaze_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/microblaze_bd_microblaze_0_axi_periph_0/microblaze_bd_microblaze_0_axi_periph_0.xci", + "inst_hier_path": "microblaze_0_axi_periph", + "xci_name": "microblaze_bd_microblaze_0_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "11" + }, + "NUM_SI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M03_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M04_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M05_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", + "value_src": "undefined" + } + } + }, + "M06_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", + "value_src": "undefined" + } + } + }, + "M07_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M08_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", + "value_src": "undefined" + } + } + }, + "M09_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", + "value_src": "undefined" + } + } + }, + "M10_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "microblaze_bd_ddr4_0_0_c0_ddr4_ui_clk", + "value_src": "undefined" + } + } + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M02_ARESETN" + } + } + }, + "M02_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M03_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M03_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M03_ARESETN" + } + } + }, + "M03_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M04_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M04_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M04_ARESETN" + } + } + }, + "M04_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M05_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M05_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M05_ARESETN" + } + } + }, + "M05_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M06_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M06_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M06_ARESETN" + } + } + }, + "M06_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M07_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M07_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M07_ARESETN" + } + } + }, + "M07_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M08_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M08_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M08_ARESETN" + } + } + }, + "M08_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M09_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M09_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M09_ARESETN" + } + } + }, + "M09_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M10_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M10_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M10_ARESETN" + } + } + }, + "M10_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "microblaze_bd_xbar_5", + "xci_path": "ip/microblaze_bd_xbar_5/microblaze_bd_xbar_5.xci", + "inst_hier_path": "microblaze_0_axi_periph/xbar", + "parameters": { + "NUM_MI": { + "value": "11" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI", + "M03_AXI", + "M04_AXI", + "M05_AXI", + "M06_AXI", + "M07_AXI", + "M08_AXI", + "M09_AXI", + "M10_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m02_couplers_to_m02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m03_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m03_couplers_to_m03_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m04_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m04_couplers_to_m04_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m05_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m05_couplers_to_m05_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m06_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m06_couplers_to_m06_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m07_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_cc": { + "vlnv": "xilinx.com:ip:axi_clock_converter:2.1", + "xci_name": "microblaze_bd_auto_cc_2", + "xci_path": "ip/microblaze_bd_auto_cc_2/microblaze_bd_auto_cc_2.xci", + "inst_hier_path": "microblaze_0_axi_periph/m07_couplers/auto_cc", + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_cc_to_m07_couplers": { + "interface_ports": [ + "M_AXI", + "auto_cc/M_AXI" + ] + }, + "m07_couplers_to_auto_cc": { + "interface_ports": [ + "S_AXI", + "auto_cc/S_AXI" + ] + } + }, + "nets": { + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "auto_cc/m_axi_aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "auto_cc/m_axi_aresetn" + ] + }, + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_cc/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_cc/s_axi_aresetn" + ] + } + } + }, + "m08_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m08_couplers_to_m08_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m09_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m09_couplers_to_m09_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m10_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m10_couplers_to_m10_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "m01_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M01_AXI", + "m01_couplers/M_AXI" + ] + }, + "m02_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M02_AXI", + "m02_couplers/M_AXI" + ] + }, + "m03_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M03_AXI", + "m03_couplers/M_AXI" + ] + }, + "m04_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M04_AXI", + "m04_couplers/M_AXI" + ] + }, + "m05_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M05_AXI", + "m05_couplers/M_AXI" + ] + }, + "m06_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M06_AXI", + "m06_couplers/M_AXI" + ] + }, + "m07_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M07_AXI", + "m07_couplers/M_AXI" + ] + }, + "m08_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M08_AXI", + "m08_couplers/M_AXI" + ] + }, + "m09_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M09_AXI", + "m09_couplers/M_AXI" + ] + }, + "m10_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M10_AXI", + "m10_couplers/M_AXI" + ] + }, + "microblaze_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "xbar_to_m02_couplers": { + "interface_ports": [ + "xbar/M02_AXI", + "m02_couplers/S_AXI" + ] + }, + "xbar_to_m03_couplers": { + "interface_ports": [ + "xbar/M03_AXI", + "m03_couplers/S_AXI" + ] + }, + "xbar_to_m04_couplers": { + "interface_ports": [ + "xbar/M04_AXI", + "m04_couplers/S_AXI" + ] + }, + "xbar_to_m05_couplers": { + "interface_ports": [ + "xbar/M05_AXI", + "m05_couplers/S_AXI" + ] + }, + "xbar_to_m06_couplers": { + "interface_ports": [ + "xbar/M06_AXI", + "m06_couplers/S_AXI" + ] + }, + "xbar_to_m07_couplers": { + "interface_ports": [ + "xbar/M07_AXI", + "m07_couplers/S_AXI" + ] + }, + "xbar_to_m08_couplers": { + "interface_ports": [ + "xbar/M08_AXI", + "m08_couplers/S_AXI" + ] + }, + "xbar_to_m09_couplers": { + "interface_ports": [ + "xbar/M09_AXI", + "m09_couplers/S_AXI" + ] + }, + "xbar_to_m10_couplers": { + "interface_ports": [ + "xbar/M10_AXI", + "m10_couplers/S_AXI" + ] + } + }, + "nets": { + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] + }, + "M01_ACLK_1": { + "ports": [ + "M01_ACLK", + "m01_couplers/M_ACLK" + ] + }, + "M01_ARESETN_1": { + "ports": [ + "M01_ARESETN", + "m01_couplers/M_ARESETN" + ] + }, + "M02_ACLK_1": { + "ports": [ + "M02_ACLK", + "m02_couplers/M_ACLK" + ] + }, + "M02_ARESETN_1": { + "ports": [ + "M02_ARESETN", + "m02_couplers/M_ARESETN" + ] + }, + "M03_ACLK_1": { + "ports": [ + "M03_ACLK", + "m03_couplers/M_ACLK" + ] + }, + "M03_ARESETN_1": { + "ports": [ + "M03_ARESETN", + "m03_couplers/M_ARESETN" + ] + }, + "M04_ACLK_1": { + "ports": [ + "M04_ACLK", + "m04_couplers/M_ACLK" + ] + }, + "M04_ARESETN_1": { + "ports": [ + "M04_ARESETN", + "m04_couplers/M_ARESETN" + ] + }, + "M05_ACLK_1": { + "ports": [ + "M05_ACLK", + "m05_couplers/M_ACLK" + ] + }, + "M05_ARESETN_1": { + "ports": [ + "M05_ARESETN", + "m05_couplers/M_ARESETN" + ] + }, + "M06_ACLK_1": { + "ports": [ + "M06_ACLK", + "m06_couplers/M_ACLK" + ] + }, + "M06_ARESETN_1": { + "ports": [ + "M06_ARESETN", + "m06_couplers/M_ARESETN" + ] + }, + "M07_ACLK_1": { + "ports": [ + "M07_ACLK", + "m07_couplers/M_ACLK" + ] + }, + "M07_ARESETN_1": { + "ports": [ + "M07_ARESETN", + "m07_couplers/M_ARESETN" + ] + }, + "M08_ACLK_1": { + "ports": [ + "M08_ACLK", + "m08_couplers/M_ACLK" + ] + }, + "M08_ARESETN_1": { + "ports": [ + "M08_ARESETN", + "m08_couplers/M_ARESETN" + ] + }, + "M09_ACLK_1": { + "ports": [ + "M09_ACLK", + "m09_couplers/M_ACLK" + ] + }, + "M09_ARESETN_1": { + "ports": [ + "M09_ARESETN", + "m09_couplers/M_ARESETN" + ] + }, + "M10_ACLK_1": { + "ports": [ + "M10_ACLK", + "m10_couplers/M_ACLK" + ] + }, + "M10_ARESETN_1": { + "ports": [ + "M10_ARESETN", + "m10_couplers/M_ARESETN" + ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "microblaze_0_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK", + "m02_couplers/S_ACLK", + "m03_couplers/S_ACLK", + "m04_couplers/S_ACLK", + "m05_couplers/S_ACLK", + "m06_couplers/S_ACLK", + "m07_couplers/S_ACLK", + "m08_couplers/S_ACLK", + "m09_couplers/S_ACLK", + "m10_couplers/S_ACLK" + ] + }, + "microblaze_0_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN", + "m02_couplers/S_ARESETN", + "m03_couplers/S_ARESETN", + "m04_couplers/S_ARESETN", + "m05_couplers/S_ARESETN", + "m06_couplers/S_ARESETN", + "m07_couplers/S_ARESETN", + "m08_couplers/S_ARESETN", + "m09_couplers/S_ARESETN", + "m10_couplers/S_ARESETN" + ] + } + } + }, + "microblaze_0_xlconcat": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "microblaze_bd_microblaze_0_xlconcat_0", + "xci_path": "ip/microblaze_bd_microblaze_0_xlconcat_0/microblaze_bd_microblaze_0_xlconcat_0.xci", + "inst_hier_path": "microblaze_0_xlconcat", + "parameters": { + "NUM_PORTS": { + "value": "14" + }, + "dout_width": { + "value": "14" + } + } + }, + "rst_ddr": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "microblaze_bd_proc_sys_reset_0_0", + "xci_path": "ip/microblaze_bd_proc_sys_reset_0_0/microblaze_bd_proc_sys_reset_0_0.xci", + "inst_hier_path": "rst_ddr" + }, + "rst_150": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "microblaze_bd_rst_clk_wiz_1_100M_0", + "xci_path": "ip/microblaze_bd_rst_clk_wiz_1_100M_0/microblaze_bd_rst_clk_wiz_1_100M_0.xci", + "inst_hier_path": "rst_150" + }, + "system_management_wiz_0": { + "vlnv": "xilinx.com:ip:system_management_wiz:1.3", + "xci_name": "microblaze_bd_system_management_wiz_0_0", + "xci_path": "ip/microblaze_bd_system_management_wiz_0_0/microblaze_bd_system_management_wiz_0_0.xci", + "inst_hier_path": "system_management_wiz_0", + "parameters": { + "CHANNEL_ENABLE_VBRAM": { + "value": "false" + }, + "CHANNEL_ENABLE_VCCAUX": { + "value": "false" + }, + "CHANNEL_ENABLE_VCCINT": { + "value": "false" + }, + "CHANNEL_ENABLE_VP_VN": { + "value": "false" + }, + "ENABLE_TEMP_BUS": { + "value": "false" + }, + "INTERFACE_SELECTION": { + "value": "Enable_AXI" + }, + "OT_ALARM": { + "value": "false" + }, + "USER_TEMP_ALARM": { + "value": "false" + }, + "VCCAUX_ALARM": { + "value": "false" + }, + "VCCINT_ALARM": { + "value": "false" + } + } } }, "interface_nets": { @@ -8105,6 +8351,12 @@ "axi_fifo_mm_s_0/AXI_STR_TXD" ] }, + "axi_iic_0_IIC": { + "interface_ports": [ + "i2c", + "axi_iic_0/IIC" + ] + }, "axi_interconnect_0_M00_AXI": { "interface_ports": [ "axi_interconnect_0/M00_AXI", @@ -8171,6 +8423,12 @@ "qspi_flash/AXI_LITE" ] }, + "axi_interconnect_1_M12_AXI": { + "interface_ports": [ + "axi_interconnect_1/M12_AXI", + "axi_iic_0/S_AXI" + ] + }, "axi_quad_spi_0_SPI_0": { "interface_ports": [ "fmc_spi0", @@ -8437,6 +8695,12 @@ "microblaze_0_xlconcat/In10" ] }, + "axi_iic_0_iic2intc_irpt": { + "ports": [ + "axi_iic_0/iic2intc_irpt", + "microblaze_0_xlconcat/In13" + ] + }, "axi_quad_spi_0_ip2intc_irpt": { "ports": [ "axi_quad_spi_0/ip2intc_irpt", @@ -8488,16 +8752,16 @@ "ddr4_0_c0_ddr4_ui_clk": { "ports": [ "ddr4_0/c0_ddr4_ui_clk", - "rst_ddr/slowest_sync_clk", + "axi_ethernet_0/axis_clk", + "axi_ethernet_0_dma/m_axi_sg_aclk", + "axi_ethernet_0_dma/m_axi_mm2s_aclk", + "axi_ethernet_0_dma/m_axi_s2mm_aclk", "axi_interconnect_0/ACLK", "axi_interconnect_0/S00_ACLK", "axi_interconnect_0/M00_ACLK", "axi_interconnect_0/S01_ACLK", "axi_interconnect_0/S02_ACLK", - "axi_ethernet_0_dma/m_axi_sg_aclk", - "axi_ethernet_0_dma/m_axi_mm2s_aclk", - "axi_ethernet_0_dma/m_axi_s2mm_aclk", - "axi_ethernet_0/axis_clk" + "rst_ddr/slowest_sync_clk" ] }, "ddr4_0_c0_init_calib_complete": { @@ -8509,8 +8773,8 @@ "ext_reset_in_0_1": { "ports": [ "ext_reset_in_200", - "rst_150/ext_reset_in", - "rst_ddr/ext_reset_in" + "rst_ddr/ext_reset_in", + "rst_150/ext_reset_in" ] }, "jesd204_phy_0_txn_out": { @@ -8570,38 +8834,18 @@ "microblaze_0_Clk": { "ports": [ "ddr4_0/addn_ui_clkout1", - "microblaze_0/Clk", - "microblaze_0_axi_periph/ACLK", - "microblaze_0_axi_periph/S00_ACLK", - "microblaze_0_axi_periph/M00_ACLK", - "microblaze_0_axi_intc/s_axi_aclk", - "microblaze_0_axi_intc/processor_clk", "microblaze_0_local_memory/LMB_Clk", - "rst_150/slowest_sync_clk", - "axi_uartlite_0/s_axi_aclk", - "microblaze_0_axi_periph/M01_ACLK", - "axi_timer_0/s_axi_aclk", - "microblaze_0_axi_periph/M02_ACLK", - "microblaze_0_axi_periph/M03_ACLK", - "microblaze_0_axi_periph/M04_ACLK", - "axi_ethernet_0/s_axi_lite_clk", - "axi_ethernet_0_dma/s_axi_lite_aclk", - "axi_interconnect_0/S03_ACLK", - "axi_interconnect_0/S04_ACLK", - "clk_wiz_0/clk_in1", - "system_management_wiz_0/s_axi_aclk", - "microblaze_0_axi_periph/M05_ACLK", - "microblaze_0_axi_periph/M06_ACLK", "mb_axi_clk", - "axi_quad_spi_0/ext_spi_clk", - "axi_quad_spi_0/s_axi_aclk", - "axi_quad_spi_1/ext_spi_clk", - "axi_quad_spi_1/s_axi_aclk", "jesd/mb_axi_clk", "axi_bram_ctrl_0/s_axi_aclk", - "axi_bram_ctrl_3/s_axi_aclk", - "axi_bram_ctrl_2/s_axi_aclk", "axi_bram_ctrl_1/s_axi_aclk", + "axi_bram_ctrl_2/s_axi_aclk", + "axi_bram_ctrl_3/s_axi_aclk", + "axi_ethernet_0/s_axi_lite_clk", + "axi_ethernet_0_dma/s_axi_lite_aclk", + "axi_iic_0/s_axi_aclk", + "axi_interconnect_0/S03_ACLK", + "axi_interconnect_0/S04_ACLK", "axi_interconnect_1/ACLK", "axi_interconnect_1/S00_ACLK", "axi_interconnect_1/M00_ACLK", @@ -8615,11 +8859,33 @@ "axi_interconnect_1/M08_ACLK", "axi_interconnect_1/M09_ACLK", "axi_interconnect_1/M10_ACLK", + "axi_interconnect_1/M11_ACLK", + "axi_interconnect_1/M12_ACLK", + "axi_quad_spi_0/ext_spi_clk", + "axi_quad_spi_0/s_axi_aclk", + "axi_quad_spi_1/ext_spi_clk", + "axi_quad_spi_1/s_axi_aclk", + "qspi_flash/s_axi_aclk", + "axi_timer_0/s_axi_aclk", + "axi_uartlite_0/s_axi_aclk", + "clk_wiz_0/clk_in1", + "microblaze_0/Clk", + "microblaze_0_axi_intc/s_axi_aclk", + "microblaze_0_axi_intc/processor_clk", + "microblaze_0_axi_periph/ACLK", + "microblaze_0_axi_periph/S00_ACLK", + "microblaze_0_axi_periph/M00_ACLK", + "microblaze_0_axi_periph/M01_ACLK", + "microblaze_0_axi_periph/M02_ACLK", + "microblaze_0_axi_periph/M03_ACLK", + "microblaze_0_axi_periph/M04_ACLK", + "microblaze_0_axi_periph/M05_ACLK", + "microblaze_0_axi_periph/M06_ACLK", "microblaze_0_axi_periph/M08_ACLK", "microblaze_0_axi_periph/M09_ACLK", "microblaze_0_axi_periph/M10_ACLK", - "axi_interconnect_1/M11_ACLK", - "qspi_flash/s_axi_aclk" + "rst_150/slowest_sync_clk", + "system_management_wiz_0/s_axi_aclk" ] }, "microblaze_0_intr": { @@ -8650,31 +8916,17 @@ "rst_clk_wiz_1_100M_peripheral_aresetn": { "ports": [ "rst_150/peripheral_aresetn", - "microblaze_0_axi_periph/ARESETN", - "microblaze_0_axi_periph/S00_ARESETN", - "microblaze_0_axi_periph/M00_ARESETN", - "microblaze_0_axi_intc/s_axi_aresetn", - "microblaze_0_axi_periph/M01_ARESETN", - "axi_uartlite_0/s_axi_aresetn", - "axi_timer_0/s_axi_aresetn", - "microblaze_0_axi_periph/M02_ARESETN", - "microblaze_0_axi_periph/M03_ARESETN", - "microblaze_0_axi_periph/M04_ARESETN", - "axi_ethernet_0/s_axi_lite_resetn", - "axi_ethernet_0_dma/axi_resetn", - "axi_interconnect_0/S03_ARESETN", - "axi_interconnect_0/S04_ARESETN", - "system_management_wiz_0/s_axi_aresetn", - "microblaze_0_axi_periph/M05_ARESETN", - "microblaze_0_axi_periph/M06_ARESETN", "mb_axi_aresetn", - "axi_quad_spi_0/s_axi_aresetn", - "axi_quad_spi_1/s_axi_aresetn", "jesd/mb_axi_aresetn", "axi_bram_ctrl_0/s_axi_aresetn", - "axi_bram_ctrl_3/s_axi_aresetn", - "axi_bram_ctrl_2/s_axi_aresetn", "axi_bram_ctrl_1/s_axi_aresetn", + "axi_bram_ctrl_2/s_axi_aresetn", + "axi_bram_ctrl_3/s_axi_aresetn", + "axi_ethernet_0/s_axi_lite_resetn", + "axi_ethernet_0_dma/axi_resetn", + "axi_iic_0/s_axi_aresetn", + "axi_interconnect_0/S03_ARESETN", + "axi_interconnect_0/S04_ARESETN", "axi_interconnect_1/ARESETN", "axi_interconnect_1/S00_ARESETN", "axi_interconnect_1/M00_ARESETN", @@ -8688,10 +8940,26 @@ "axi_interconnect_1/M08_ARESETN", "axi_interconnect_1/M09_ARESETN", "axi_interconnect_1/M10_ARESETN", + "axi_interconnect_1/M11_ARESETN", + "axi_interconnect_1/M12_ARESETN", + "axi_quad_spi_0/s_axi_aresetn", + "axi_quad_spi_1/s_axi_aresetn", + "axi_timer_0/s_axi_aresetn", + "axi_uartlite_0/s_axi_aresetn", + "microblaze_0_axi_intc/s_axi_aresetn", + "microblaze_0_axi_periph/ARESETN", + "microblaze_0_axi_periph/S00_ARESETN", + "microblaze_0_axi_periph/M00_ARESETN", + "microblaze_0_axi_periph/M01_ARESETN", + "microblaze_0_axi_periph/M02_ARESETN", + "microblaze_0_axi_periph/M03_ARESETN", + "microblaze_0_axi_periph/M04_ARESETN", + "microblaze_0_axi_periph/M05_ARESETN", + "microblaze_0_axi_periph/M06_ARESETN", "microblaze_0_axi_periph/M08_ARESETN", "microblaze_0_axi_periph/M09_ARESETN", "microblaze_0_axi_periph/M10_ARESETN", - "axi_interconnect_1/M11_ARESETN" + "system_management_wiz_0/s_axi_aresetn" ] }, "rst_ddr_mb_reset": { @@ -8703,12 +8971,12 @@ "rst_ddr_peripheral_aresetn": { "ports": [ "rst_ddr/peripheral_aresetn", - "ddr4_0/c0_ddr4_aresetn", "axi_interconnect_0/ARESETN", "axi_interconnect_0/S00_ARESETN", "axi_interconnect_0/M00_ARESETN", "axi_interconnect_0/S01_ARESETN", - "axi_interconnect_0/S02_ARESETN" + "axi_interconnect_0/S02_ARESETN", + "ddr4_0/c0_ddr4_aresetn" ] }, "rx_core_reset_0_1": { @@ -8739,18 +9007,18 @@ "ports": [ "eth_clk", "axi_fifo_mm_s_0/s_axi_aclk", - "microblaze_0_axi_periph/M07_ACLK", "axis_dwidth_converter_0/aclk", - "axis_dwidth_converter_1/aclk" + "axis_dwidth_converter_1/aclk", + "microblaze_0_axi_periph/M07_ACLK" ] }, "s_axi_aresetn_0_1": { "ports": [ "eth_resetn", "axi_fifo_mm_s_0/s_axi_aresetn", - "microblaze_0_axi_periph/M07_ARESETN", "axis_dwidth_converter_0/aresetn", - "axis_dwidth_converter_1/aresetn" + "axis_dwidth_converter_1/aresetn", + "microblaze_0_axi_periph/M07_ARESETN" ] }, "s_axi_aresetn_0_2": { @@ -8827,6 +9095,43 @@ } } }, + "/axi_ethernet_0_dma": { + "address_spaces": { + "Data_SG": { + "segments": { + "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": { + "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK", + "offset": "0x80000000", + "range": "2G", + "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", + "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" + } + } + }, + "Data_MM2S": { + "segments": { + "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": { + "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK", + "offset": "0x80000000", + "range": "2G", + "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", + "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" + } + } + }, + "Data_S2MM": { + "segments": { + "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": { + "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK", + "offset": "0x80000000", + "range": "2G", + "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", + "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" + } + } + } + } + }, "/microblaze_0": { "address_spaces": { "Data": { @@ -8867,6 +9172,11 @@ "range": "64K", "offset_high_param": "C_HIGHADDR" }, + "SEG_axi_iic_0_Reg": { + "address_block": "/axi_iic_0/S_AXI/Reg", + "offset": "0x40110000", + "range": "64K" + }, "SEG_axi_quad_spi_0_Reg": { "address_block": "/axi_quad_spi_0/AXI_LITE/Reg", "offset": "0x400C0000", @@ -8978,43 +9288,6 @@ } } } - }, - "/axi_ethernet_0_dma": { - "address_spaces": { - "Data_SG": { - "segments": { - "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": { - "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK", - "offset": "0x80000000", - "range": "2G", - "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", - "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" - } - } - }, - "Data_MM2S": { - "segments": { - "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": { - "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK", - "offset": "0x80000000", - "range": "2G", - "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", - "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" - } - } - }, - "Data_S2MM": { - "segments": { - "SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK": { - "address_block": "/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK", - "offset": "0x80000000", - "range": "2G", - "offset_base_param": "C0_DDR4_MEMORY_MAP_BASEADDR", - "offset_high_param": "C0_DDR4_MEMORY_MAP_HIGHADDR" - } - } - } - } } } } diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v b/radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v new file mode 100755 index 0000000..d69782b --- /dev/null +++ b/radar_alinx_kintex.srcs/sources_1/hdl/pulse_generator.v @@ -0,0 +1,45 @@ +`resetall +`timescale 1ns / 1ps +`default_nettype none + +module pulse_generator # +( + parameter integer COUNTER_BITS = 28 +) +( + input wire clk, + input wire rst, + input wire [COUNTER_BITS-1:0] pulse_length, + output wire start_of_pulse, + output wire pulse_out +); + +reg [COUNTER_BITS-1:0] pulse_cnt; +reg pulse_active; + +assign pulse_out = pulse_active; + +always @ (posedge clk) begin + if (rst == 1'b1) begin + pulse_cnt <= 0; + end else begin + if (start_of_pulse) begin + pulse_active <= 1; + end + + if (pulse_active) begin + pulse_cnt <= pulse_cnt - 1; + if (pulse_cnt == 0) begin + pulse_active <= 0; + end + end + + end +end + + + +endmodule + + +`resetall \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v b/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v index 261c5cd..757124b 100755 --- a/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v +++ b/radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v @@ -83,8 +83,8 @@ reg [27:0] reg_pri; reg [27:0] reg_num_pulses; reg [27:0] reg_inter_cpi; reg [31:0] reg_pps_sec_set; -reg [31:0] reg_pulse_width [NUM_TIMING_PULSES-1:0]; -reg [31:0] reg_pulse_start [NUM_TIMING_PULSES-1:0]; +reg [27:0] reg_pulse_width [NUM_TIMING_PULSES-1:0]; +reg [28:0] reg_pulse_start [NUM_TIMING_PULSES-1:0]; reg [63:0] system_time; reg [63:0] pps_frac_sec; @@ -141,7 +141,7 @@ generate for (gen_reg = 0; gen_reg < NUM_TIMING_PULSES; gen_reg = gen_reg + 1) begin always @ (posedge ctrl_if.clk) begin if (reset) begin - reg_pulse_start[gen_reg] <= 0; + reg_pulse_start[gen_reg] <= 28'hFFFFFF; end else if (wren && waddr[11:0] == ('h080 + gen_reg*8)) begin reg_pulse_start[gen_reg] <= wdata; end @@ -396,14 +396,17 @@ end // ------------------------------ // Pulse Generators // ------------------------------ -reg [NUM_TIMING_PULSES-1:0] pulse_start; +reg [NUM_TIMING_PULSES-1:0] pulse_start; +reg [NUM_TIMING_PULSES-1:0] timing_pulses_i; genvar j; generate for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin + assign timing_pulses[j] = timing_pulses_i | reg_pulse_start[j][28]; + always @ (posedge clk) begin - if (pri_cnt == reg_pulse_start[j]) begin + if (pri_cnt == reg_pulse_start[j][27:0]) begin pulse_start[j] <= 1; end else begin pulse_start[j] <= 0; @@ -415,7 +418,7 @@ generate .rst(rst), .pulse_length(reg_pulse_width[j]), .start_of_pulse(pulse_start[j]), - .pulse_out(timing_pulses[j]) + .pulse_out(timing_pulses_i[j]) ); end diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/top.v b/radar_alinx_kintex.srcs/sources_1/hdl/top.v index 3990eb9..46bbddc 100755 --- a/radar_alinx_kintex.srcs/sources_1/hdl/top.v +++ b/radar_alinx_kintex.srcs/sources_1/hdl/top.v @@ -42,6 +42,10 @@ module top # output wire fmc_power_en, input wire pps, + // I2C + inout wire i2c_scl, + inout wire i2c_sda, + // RF Control output wire tx0_rf_attn_sin, //ADRF5730 output wire tx0_rf_attn_clk, //ADRF5730 @@ -286,6 +290,26 @@ module top # .T(fmc_spi1_ss_t)); + // I2C For changing regulator voltage + wire i2c_scl_i; + wire i2c_scl_o; + wire i2c_scl_t; + wire i2c_sda_i; + wire i2c_sda_o; + wire i2c_sda_t; + + IOBUF i2c_scl_iobuf + (.I(i2c_scl_o), + .IO(i2c_scl), + .O(i2c_scl_i), + .T(i2c_scl_t)); + IOBUF i2c_sda_iobuf + (.I(i2c_sda_o), + .IO(i2c_sda), + .O(i2c_sda_i), + .T(i2c_sda_t)); + + // ------------------------------ // BD // ------------------------------ @@ -370,6 +394,13 @@ module top # microblaze_bd microblaze_bd_i ( + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_scl_t(i2c_scl_t), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + .i2c_sda_t(i2c_sda_t), + .STARTUP_IO_cfgclk(), .STARTUP_IO_cfgmclk(), .STARTUP_IO_eos(), diff --git a/radar_alinx_kintex.srcs/sources_1/ip/axis_switch_0/axis_switch_0.xci b/radar_alinx_kintex.srcs/sources_1/ip/axis_switch_0/axis_switch_0.xci index 34c7ca9..5619694 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/axis_switch_0/axis_switch_0.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/axis_switch_0/axis_switch_0.xci @@ -350,9 +350,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/clock_converter/clock_converter.xci b/radar_alinx_kintex.srcs/sources_1/ip/clock_converter/clock_converter.xci index 490783c..1adeb42 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/clock_converter/clock_converter.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/clock_converter/clock_converter.xci @@ -42,9 +42,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/data_fifo/data_fifo.xci b/radar_alinx_kintex.srcs/sources_1/ip/data_fifo/data_fifo.xci index a0b8b40..036ad3c 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/data_fifo/data_fifo.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/data_fifo/data_fifo.xci @@ -60,9 +60,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci b/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci index 71c0f23..cd9a9fe 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci @@ -42,9 +42,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci b/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci index 75fdc88..206ab91 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci @@ -39,9 +39,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci b/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci index 82984e1..b81cdd6 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci @@ -23,7 +23,7 @@ "INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], "INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], - "RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -31,18 +31,18 @@ "PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], "TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ], "TX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ], - "TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ], - "TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ], + "TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], - "TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ], + "TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ], "RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ], "RX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ], - "RX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ], - "RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ], + "RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], @@ -50,7 +50,7 @@ "RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], "RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ], "RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ], - "RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ], + "RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ], @@ -168,7 +168,7 @@ "LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ], "ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ], + "INTERNAL_PRESET": [ { "value": "10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], @@ -181,9 +181,9 @@ "SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -830,9 +830,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -874,10 +874,10 @@ "gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ], "gthrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gthrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxgearboxslip_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txheader_in": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ], "txsequence_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ], diff --git a/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci b/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci index 6535396..cde3119 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci @@ -23,7 +23,7 @@ "INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], "INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], - "RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -32,17 +32,17 @@ "TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ], "TX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ], + "TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], - "TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ], + "TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ], "RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ], "RX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ], + "RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], @@ -50,7 +50,7 @@ "RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], "RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ], "RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ], - "RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ], + "RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ], @@ -168,7 +168,7 @@ "LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ], "ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ], + "INTERNAL_PRESET": [ { "value": "10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "14", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], @@ -181,9 +181,9 @@ "SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -830,9 +830,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/hdr_fifo/hdr_fifo.xci b/radar_alinx_kintex.srcs/sources_1/ip/hdr_fifo/hdr_fifo.xci index 1c10a21..65f2e24 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/hdr_fifo/hdr_fifo.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/hdr_fifo/hdr_fifo.xci @@ -60,9 +60,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/hdr_mem/hdr_mem.xci b/radar_alinx_kintex.srcs/sources_1/ip/hdr_mem/hdr_mem.xci index ac08347..9b27eb4 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/hdr_mem/hdr_mem.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/hdr_mem/hdr_mem.xci @@ -34,17 +34,17 @@ "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Read_Width_A": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Operating_Mode_A": [ { "value": "NO_CHANGE", "resolve_type": "user", "usage": "all" } ], + "Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Operating_Mode_A": [ { "value": "NO_CHANGE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ], "Write_Width_B": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "Read_Width_B": [ { "value": "64", "resolve_type": "user", "usage": "all" } ], + "Read_Width_B": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ], - "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], @@ -66,10 +66,10 @@ "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ], "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -166,9 +166,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci b/radar_alinx_kintex.srcs/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci index 41ddf56..426f6cd 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci @@ -60,9 +60,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci b/radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci index 2367e7a..a11ce98 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci @@ -14,7 +14,7 @@ "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ], "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ], "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], @@ -34,17 +34,17 @@ "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Write_Depth_A": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Read_Width_A": [ { "value": "32", "resolve_type": "user", "usage": "all" } ], + "Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ], "Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ], "Write_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Read_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ], - "Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ], + "Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], @@ -66,10 +66,10 @@ "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Port_B_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Write_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ], "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -166,9 +166,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/sources_1/ip/width_converter/width_converter.xci b/radar_alinx_kintex.srcs/sources_1/ip/width_converter/width_converter.xci index d223237..a30f2c3 100755 --- a/radar_alinx_kintex.srcs/sources_1/ip/width_converter/width_converter.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/width_converter/width_converter.xci @@ -39,9 +39,9 @@ "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], + "SPEEDGRADE": [ { "value": "-1" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "C" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp index 1a7253a..a23d964 100755 Binary files a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp and b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp differ diff --git a/radar_alinx_kintex.xpr b/radar_alinx_kintex.xpr index 18164ad..ac4c3ec 100755 --- a/radar_alinx_kintex.xpr +++ b/radar_alinx_kintex.xpr @@ -7,7 +7,7 @@