diff --git a/python/waveform_generator/wf_ofdm.py b/python/waveform_generator/wf_ofdm.py new file mode 100644 index 0000000..d19760b --- /dev/null +++ b/python/waveform_generator/wf_ofdm.py @@ -0,0 +1,234 @@ +import numpy as np + + +# get one chip of a multi-chip OFDM waveform +def get_chip( + baseband, + start_phase, + f_samp, + N_samp_chip, + N_pulse, + n_tx, + n_pulse, + n_sub_cpi, +): + # pylint: disable-msg=too-many-arguments + # TODO: @Charlie, remove disable and fix + # unused args + + s_p = np.sum( + [ + start_phase[n_tx, n_sub_cpi, nn % N_pulse] + for nn in range(N_pulse * n_sub_cpi + n_pulse) + ] + ) + + phase = ( + s_p + baseband[n_tx, n_sub_cpi, n_pulse] * np.arange(N_samp_chip) / f_samp + ) + x = np.exp(2 * np.pi * 1j * phase) + return x, phase + +# synthesize the transmit waveform in intermediate frequency sample space +def get_waveform(baseband, start_phase, N_tx, N_sub_cpi, N_f_pulse, N_samp_chip, N_samp, f_samp): + pulse = np.zeros((N_tx, N_sub_cpi, N_samp), dtype=complex) + phase = np.zeros((N_tx, N_sub_cpi, N_samp)) + + for n_tx in range(N_tx): + for n_sub_cpi in range(N_sub_cpi): + for n_f_pulse in range(N_f_pulse): + ( + pulse[ + n_tx, + n_sub_cpi, + n_f_pulse * N_samp_chip: ( + N_samp_chip + n_f_pulse * N_samp_chip + ), + ], + phase[ + n_tx, + n_sub_cpi, + n_f_pulse * N_samp_chip: ( + N_samp_chip + n_f_pulse * N_samp_chip + ), + ], + ) = get_chip(baseband, start_phase, f_samp, N_samp_chip, N_f_pulse, n_tx, n_f_pulse, n_sub_cpi) + + return pulse, phase + + +def get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, perm): + f_chip = 5859375.0 + f_c = 16300000255.999992 + k_rgft = 256 + b = 23437500.0 + + + t_chip = 1 / f_chip + n_tx_n_pol = n_tx * n_pol + + # frequencies with respect to baseband + baseband = f_chip * (perm - (n_f - 1) / 2) + start_phase = baseband * t_chip + + f_sa = f_c + baseband + chip_samples = int(np.ceil(k_rgft * f_chip / f_samp)) + + chip_center_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse), dtype=int) + chip_lower_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse), dtype=int) + chip_upper_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse), dtype=int) + time_shift_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse)) + f_sa_dmux = np.zeros((n_sub_cpi, n_rx, n_tx_n_pol, n_f_pulse)) + for n_sub_cpi_ind in range(n_sub_cpi): + for n_rx_ind in range(n_rx): + for n_tx_ind in range(n_tx_n_pol): + for n_f_pulse_ind in range(n_f_pulse): + time_shift_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = ( + n_f_pulse_ind * n_samp_chip + n_samp_chip / 2 + ) + chip_center_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = int( + np.round( + k_rgft + * (baseband[n_tx_ind, n_sub_cpi_ind, n_f_pulse_ind] + b / 2) + / f_samp + ) + ) + chip_lower_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = int( + np.round( + chip_center_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] + - chip_samples / 2 + ) + ) + chip_upper_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = ( + chip_lower_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] + chip_samples + ) + f_sa_dmux[n_sub_cpi_ind, n_rx_ind, n_tx_ind, n_f_pulse_ind] = f_sa[ + n_tx_ind, n_sub_cpi_ind, n_f_pulse_ind + ] + return + +def wg_ofdm(): + # wp = inputs.wp.proto # just to make code easier to read + n_f = 4 + n_f_pulse = 4 + do_random = False + do_agile = False + n_sub_cpi = 1 + n_tx = 1 + n_rx = 2 + n_pol = 2 + n_samp = 32 + n_samp_chip = 8 + f_samp = 46875000.0 + tx_sample_rate_multiplier = 16 + n_gen_pulses = 1 + rng = np.random.default_rng(seed=42) + perm_list = [] + sequence = np.arange(n_f) + unique_sub_cpi = n_gen_pulses // n_sub_cpi + for n_p in range(unique_sub_cpi): + if do_random and (do_agile or n_p == 0): + # if we are here, we are doing random pulses and + # 1. it is pulse zero so we set the permutation for all of + # the pulses + # or + # 2. we are agile and we set a new permutation for every pulse + sequence = rng.permutation(n_f) + elif n_p == 0: + # if we are here, we are not random, so set the sequence equal + # to a range, which will give an LFM waveform + sequence = np.arange(n_f) + if n_pol == 1: + perm = np.reshape( + sequence, + (n_tx, n_sub_cpi, n_f_pulse), + ) + elif n_pol == 2: + perm = np.zeros( + ( + n_pol * n_tx, + n_sub_cpi, + n_f_pulse, + ), + dtype=int, + ) + for n_tx_ind in range(n_tx): + perm[n_tx_ind, :, :] = np.reshape( + sequence[n_f * n_tx_ind: n_f * (n_tx_ind + 1)], + (n_sub_cpi, n_f_pulse), + ) + if n_tx_ind == 0: + perm[n_tx + n_tx_ind, :, :] = np.reshape( + sequence[n_f * (n_tx_ind + 1) - 1:: -1], + (n_sub_cpi, n_f_pulse), + ) + else: + perm[n_tx + n_tx_ind, :, :] = np.reshape( + sequence[n_f * (n_tx_ind + 1) - 1: n_f * n_tx_ind - 1: -1], + (n_sub_cpi, n_f_pulse), + ) + # fill the permutation we just generated in to a list + perm_list.append(perm) + + # generate a set of pulse parameters for every element of our list + perm_list_full = [] + # at this point, we need to create pulse parameters for the full number of + # pulses in the CPI, even though the waveform generator will only generate + # a subset of those. + # so N_pulses defined above is the number of pulses to generate + # wp.N_pulses is the total number of pulses in a CPI. + # note that here, N_pulses = wp.N_gen_pulses is the number of pulses + # we use to size the output buffer. + # Additional note, in the tactical system, wp.N_gen_pulses must always + # be equal to wp.N_pulses, these two only differ in testing. + for n_p in range(unique_sub_cpi): + perm_list_full.append(perm_list[n_p % unique_sub_cpi]) + + # pp_list = PulseParamsList( + # pulse_params=[get_pulse_params(wp=wp, perm=p) for p in perm_list_full] + # ) + + [get_pulse_params(n_tx, n_rx, f_samp, n_samp_chip, n_f, n_f_pulse, n_sub_cpi, n_pol, p) for p in perm_list_full] + + subpulses = np.ndarray( + shape=( + unique_sub_cpi, + n_tx * n_pol, + n_sub_cpi, + n_samp * tx_sample_rate_multiplier, + 2, # I/Q + ), + dtype=np.uint16, + ) + + amplitude_quant = 2 ** (16 - 1) - 1 + zero_quant = 0 + + # This generates transmit waveforms for the whole CPI + for n_cpi in range(unique_sub_cpi): + pulse, _phase = get_waveform( + np.array( + pp_list.pulse_params[n_cpi].baseband.elements, dtype=np.double + ).reshape(tuple(pp_list.pulse_params[n_cpi].baseband.dimensions)), + np.array( + pp_list.pulse_params[n_cpi].start_phase.elements, dtype=np.double + ).reshape(tuple(pp_list.pulse_params[n_cpi].start_phase.dimensions)), + n_tx * n_pol, + n_sub_cpi, + n_f_pulse, + n_samp_chip * tx_sample_rate_multiplier, + n_samp * tx_sample_rate_multiplier, + f_samp * tx_sample_rate_multiplier, + ) + + subpulses[n_cpi, ..., 0] = np.round( + (amplitude_quant * np.real(pulse) + zero_quant).astype(np.uint16) + ) + subpulses[n_cpi, ..., 1] = np.round( + (amplitude_quant * np.imag(pulse) + zero_quant).astype(np.uint16) + ) + + return + +if __name__ == '__main__': + wg_ofdm() \ No newline at end of file diff --git a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc index 2cb112e..fa286dd 100755 --- a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc +++ b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc @@ -283,11 +283,11 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p #set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p] # Works with the board at my house -set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] -set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] +#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p] +#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n] # Works with the board Chris has (broken USB UART) -#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] -#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] +set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p] +set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n] set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p] set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p] diff --git a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp index 47756ff..80ca93a 100755 Binary files a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp and b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp differ diff --git a/vitis/bootloader/_ide/launch/Debugger_bootloader-Default.launch b/vitis/bootloader/_ide/launch/Debugger_bootloader-Default.launch index 09bc464..20f84d7 100644 --- a/vitis/bootloader/_ide/launch/Debugger_bootloader-Default.launch +++ b/vitis/bootloader/_ide/launch/Debugger_bootloader-Default.launch @@ -13,12 +13,12 @@ - + - + - + @@ -26,7 +26,7 @@ - + diff --git a/vitis/bootloader/src/bootloader.c b/vitis/bootloader/src/bootloader.c index 049281d..65033aa 100644 --- a/vitis/bootloader/src/bootloader.c +++ b/vitis/bootloader/src/bootloader.c @@ -165,7 +165,7 @@ int main() uint8_t ret; #ifdef VERBOSE - print ("\r\nSREC SPI Bootloader\r\n"); + xil_printf ("\r\nSREC SPI Bootloader\r\n"); #endif sleep(3); @@ -183,7 +183,7 @@ int main() */ Status = XSpi_Initialize(&Spi, SPI_DEVICE_ID); if(Status != XST_SUCCESS) { - print("init fail"); + xil_printf("init fail"); return XST_FAILURE; } @@ -195,7 +195,7 @@ int main() Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION); if(Status != XST_SUCCESS) { - print("options fail"); + xil_printf("options fail"); return XST_FAILURE; } @@ -205,7 +205,7 @@ int main() */ Status = XSpi_SetSlaveSelect(&Spi, SPI_SELECT); if(Status != XST_SUCCESS) { - print("slave select fail"); + xil_printf("slave select fail"); return XST_FAILURE; } @@ -219,36 +219,36 @@ int main() init_stdout(); sleep(1); - print ("Read Flash ID"); + xil_printf ("Read Flash ID"); Status = FlashReadID( ); if(Status != XST_SUCCESS) { - print("flash read id fail"); + xil_printf("flash read id fail"); return XST_FAILURE; } - print ("Read Flash ID"); + xil_printf ("Read Flash ID"); Status = FlashReadID( ); if(Status != XST_SUCCESS) { - print("flash read id fail"); + xil_printf("flash read id fail"); return XST_FAILURE; } - print ("Read Flash ID"); + xil_printf ("Read Flash ID"); Status = FlashReadID( ); if(Status != XST_SUCCESS) { - print("flash read id fail"); + xil_printf("flash read id fail"); return XST_FAILURE; } #ifdef VERBOSE - print ("Loading SREC image from flash @ address: "); + xil_printf ("Loading SREC image from flash @ address: "); putnum (FLASH_IMAGE_BASEADDR); - print ("\r\n"); + xil_printf ("\r\n"); #endif sleep(1); - print ("After Sleep"); + xil_printf ("After Sleep"); flbuf = (u32)FLASH_IMAGE_BASEADDR; ret = load_exec (); @@ -257,12 +257,12 @@ int main() #ifdef VERBOSE if (ret > LD_SREC_LINE_ERROR) { - print ("ERROR in SREC line: "); + xil_printf ("ERROR in SREC line: "); putnum (srec_line); - print (errors[ret]); + xil_printf (errors[ret]); } else { - print ("ERROR: "); - print (errors[ret]); + xil_printf ("ERROR: "); + xil_printf (errors[ret]); } #endif @@ -386,9 +386,9 @@ static void display_progress (uint32_t count) { /* Send carriage return */ outbyte (CR); - print ("Bootloader: Processed (0x)"); + xil_printf ("Bootloader: Processed (0x)"); putnum (count); - print (" S-records"); + xil_printf (" S-records"); } #endif @@ -417,7 +417,7 @@ static uint8_t load_exec () #ifdef VERBOSE if (srec_line % 16 == 0) { - // Don't print every line because it takes forever over UART + // Don't xil_printf every line because it takes forever over UART display_progress (srec_line); } #endif @@ -449,9 +449,9 @@ static uint8_t load_exec () mode = READ_WRITE_EXTRA_BYTES; } #ifdef VERBOSE - print ("\r\nExecuting program starting at address: "); + xil_printf ("\r\nExecuting program starting at address: "); putnum ((uint32_t)laddr); - print ("\r\n"); + xil_printf ("\r\n"); #endif (*laddr)(); diff --git a/vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl b/vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl index ecd7401..ecc6510 100644 --- a/vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl +++ b/vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl @@ -10,10 +10,15 @@ # source /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader_system/_ide/scripts/debugger_bootloader-default.tcl # connect -url tcp:127.0.0.1:3121 +targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && level==0 && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-13822093-0"} +fpga -file /home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/download.bit targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" } loadhw -hw /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/hw/top.xsa -regs configparams mdm-detect-bscan-mask 2 targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" } +rst -system +after 3000 +targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" } dow /home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader/Debug/bootloader.elf targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" } con diff --git a/vitis/radar/radar.prj b/vitis/radar/radar.prj index 06d9c01..fe1b1a7 100755 --- a/vitis/radar/radar.prj +++ b/vitis/radar/radar.prj @@ -1,5 +1,5 @@ - + diff --git a/vitis/radar/src/data_converter_setup.c b/vitis/radar/src/data_converter_setup.c index e49e389..7d57c32 100755 --- a/vitis/radar/src/data_converter_setup.c +++ b/vitis/radar/src/data_converter_setup.c @@ -525,23 +525,23 @@ void setup_data_converter() { #ifndef IBERT_TESTING // Update FPGA TX Transceiver settings -// set_lane_cal(0, 0, 0, 11); -// set_lane_cal(1, 10, 5, 11); -// set_lane_cal(2, 5, 0, 11); -// set_lane_cal(3, 0, 0, 11); -// set_lane_cal(4, 0, 0, 11); -// set_lane_cal(5, 0, 0, 11); -// set_lane_cal(6, 12, 0, 11); -// set_lane_cal(7, 0, 0, 11); + set_lane_cal(0, 0, 0, 11); + set_lane_cal(1, 10, 5, 11); + set_lane_cal(2, 5, 0, 11); + set_lane_cal(3, 0, 0, 11); + set_lane_cal(4, 0, 0, 11); + set_lane_cal(5, 0, 0, 11); + set_lane_cal(6, 12, 0, 11); + set_lane_cal(7, 0, 0, 11); - set_lane_cal(0, 9, 0, 7); - set_lane_cal(1, 9, 0, 7); - set_lane_cal(2, 9, 0, 7); - set_lane_cal(3, 9, 0, 7); - set_lane_cal(4, 9, 0, 7); - set_lane_cal(5, 9, 0, 7); - set_lane_cal(6, 9, 0, 7); - set_lane_cal(7, 9, 0, 7); +// set_lane_cal(0, 9, 0, 7); +// set_lane_cal(1, 9, 0, 7); +// set_lane_cal(2, 9, 0, 7); +// set_lane_cal(3, 9, 0, 7); +// set_lane_cal(4, 9, 0, 7); +// set_lane_cal(5, 9, 0, 7); +// set_lane_cal(6, 9, 0, 7); +// set_lane_cal(7, 9, 0, 7); vTaskDelay(100); int subclass = jtx_param[uc][0].jesd_subclass; diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h index 6415623..864f4b5 100644 --- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h +++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h @@ -496,8 +496,8 @@ #define PLATFORM_MB /******************************************************************/ -#define STDIN_BASEADDRESS 0x40000000 -#define STDOUT_BASEADDRESS 0x40000000 +#define STDIN_BASEADDRESS 0x41400000 +#define STDOUT_BASEADDRESS 0x41400000 /******************************************************************/ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a index 8b470ba..478417c 100644 Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a differ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a index 3510983..29ba479 100644 Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a differ diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss index 55fe265..14165d1 100644 --- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss +++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss @@ -6,8 +6,8 @@ BEGIN OS PARAMETER OS_NAME = freertos10_xilinx PARAMETER OS_VER = 1.12 PARAMETER PROC_INSTANCE = microblaze_0 - PARAMETER stdin = axi_uartlite_0 - PARAMETER stdout = axi_uartlite_0 + PARAMETER stdin = mdm_1 + PARAMETER stdout = mdm_1 PARAMETER total_heap_size = 2097152 END diff --git a/vitis/top/platform.spr b/vitis/top/platform.spr index 5f3a325..c14efcb 100755 --- a/vitis/top/platform.spr +++ b/vitis/top/platform.spr @@ -1 +1 @@ -{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} +{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} diff --git a/vitis/top/platform.tcl b/vitis/top/platform.tcl index e9d4c1b..c3bb0fb 100755 --- a/vitis/top/platform.tcl +++ b/vitis/top/platform.tcl @@ -210,3 +210,29 @@ bsp reload catch {bsp regenerate} platform generate -domains freertos10_xilinx_microblaze_0 platform active {top} +platform active {top} +bsp reload +bsp config stdin "mdm_1" +bsp config stdout "mdm_1" +bsp write +bsp reload +catch {bsp regenerate} +bsp write +platform generate +platform active {top} +platform generate -domains +bsp reload +bsp config stdin "axi_uartlite_0" +bsp config stdout "axi_uartlite_0" +bsp write +bsp reload +catch {bsp regenerate} +platform generate -domains freertos10_xilinx_microblaze_0 +platform active {top} +bsp reload +bsp config stdin "mdm_1" +bsp config stdout "mdm_1" +bsp write +bsp reload +catch {bsp regenerate} +platform generate -domains freertos10_xilinx_microblaze_0