diff --git a/python/filter_design.py b/python/filter_design.py
new file mode 100644
index 0000000..6d08c4b
--- /dev/null
+++ b/python/filter_design.py
@@ -0,0 +1,26 @@
+import numpy as np
+import scipy
+from matplotlib import pyplot as plt
+
+def main():
+    # Design some filter coefficients
+    n_taps = 33
+    cutoff = 1 / 2
+    filt_coeffs = scipy.signal.firwin(n_taps, cutoff)
+    nfft = 1024
+    filt_resp = np.fft.fft(filt_coeffs, nfft)
+    filt_resp = np.fft.fftshift(filt_resp)
+
+    freq_axis = (np.arange(nfft) - (nfft/2)) / nfft
+
+    plt.figure()
+    plt.plot(freq_axis, 20*np.log10(np.abs(filt_resp)))
+    plt.ylabel('dB')
+    plt.xlabel('Normalized Frequency')
+    plt.title('Filter Response')
+    plt.grid()
+    plt.show()
+
+if __name__ == '__main__':
+
+    main()
diff --git a/python/radar_manager.py b/python/radar_manager.py
index c3400df..5a5be58 100755
--- a/python/radar_manager.py
+++ b/python/radar_manager.py
@@ -329,7 +329,7 @@ class RadarManager:
         self.axi_write_register(TIMING_ENGINE_ADDR + 0x8, num_pulses)
         self.axi_write_register(TIMING_ENGINE_ADDR + 0x10, inter_cpi - 1)
 
-    def setup_rx(self, num_samples, start_sample):
+    def setup_rx(self, num_samples, start_sample, dec_rate):
         for i in range(NUM_RX):
             if JESD204B:
                 self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x4, num_samples >> 1)
@@ -338,6 +338,10 @@ class RadarManager:
                 self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x4, num_samples >> 2)
                 self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x8, start_sample >> 2)
 
+            # Decimation Selection
+            dec_sel = int(np.log2(dec_rate))
+            self.axi_write_register(DIG_RX_ADDR + i * DIG_RX_STRIDE + 0xC, dec_sel)
+
             # Setup RX Strobe
             # self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample >> 2)
             # self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples >> 2)
@@ -384,9 +388,9 @@ class RadarManager:
 
 
     def configure_cpi(self, pri, inter_cpi, num_pulses, num_samples, start_sample,
-                      tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset):
-        self.load_waveform(0, 1, 0.1, tx_num_samples)
-        self.load_waveform(1, 1, 0.1, tx_num_samples)
+                      tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset, dec_rate):
+        self.load_waveform(0, 1, 0.05, tx_num_samples)
+        self.load_waveform(1, 1, 0.05, tx_num_samples)
 
         num_samples_quant = int(self.packet_size / 4)
         if num_samples % num_samples_quant > 0:
@@ -400,7 +404,7 @@ class RadarManager:
         self.setup_rf_attenuators(rf_atten)
 
         adc_nco = 1e9 % f_adc
-        dac_nco = 1.001e9 % f_dac
+        dac_nco = 1e9 % f_dac
 
         # adc_nco = 2e9
         # adc_nyquist_zone = np.floor(adc_nco / (f_adc / 2))
@@ -416,7 +420,7 @@ class RadarManager:
             self.set_dac_nco(i, dac_nco)
 
         self.setup_timing_engine(pri, num_pulses, inter_cpi)
-        self.setup_rx(num_samples, start_sample)
+        self.setup_rx(num_samples, start_sample, dec_rate)
         self.setup_tx(tx_num_samples, tx_start_sample)
         self.setup_cpi_header(pri, inter_cpi, num_pulses, num_samples, start_sample,
                       tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset)
\ No newline at end of file
diff --git a/python/read_data_file.py b/python/read_data_file.py
index eb4b796..169fe9e 100755
--- a/python/read_data_file.py
+++ b/python/read_data_file.py
@@ -25,7 +25,7 @@ def main():
     headers = []
     offset = 0
 
-    file = 'test1.bin'
+    file = 'test0.bin'
     fid = open(file, 'rb')
 
     # Find header, recording buffer could have wrapped depending on data rate and how long we ran for
@@ -86,21 +86,21 @@ def main():
     vmin = -60
     vmax = 0
 
-    plt.figure()
-    plt.plot(np.diff(cpi_times))
-    plt.plot(np.diff(pps_frac))
-    # plt.ylim([0, .04])
+    # plt.figure()
+    # plt.plot(np.diff(cpi_times))
+    # plt.plot(np.diff(pps_frac))
+    # # plt.ylim([0, .04])
 
-    # plt.figure()
-    # plt.plot(iq.T.real, '.-')
-    # plt.plot(iq.T.imag, '--.')
-    # plt.grid()
-    #
-    # plt.figure()
-    # plt.imshow(db20n(iq), aspect='auto', interpolation='nearest', vmin=vmin, vmax=vmax)
-    # plt.ylabel('Pulse Count')
-    # plt.xlabel('Sample Count')
-    # plt.colorbar()
+    plt.figure()
+    plt.plot(iq.T.real, '.-')
+    plt.plot(iq.T.imag, '--.')
+    plt.grid()
+
+    plt.figure()
+    plt.imshow(db20n(iq), aspect='auto', interpolation='nearest', vmin=vmin, vmax=vmax)
+    plt.ylabel('Pulse Count')
+    plt.xlabel('Sample Count')
+    plt.colorbar()
 
 
     plt.show()
diff --git a/python/test_cpi.py b/python/test_cpi.py
index 875e8d1..cf50400 100755
--- a/python/test_cpi.py
+++ b/python/test_cpi.py
@@ -45,9 +45,9 @@ def main():
     # CPI Parameters (timing values are in clk ticks)
     num_pulses = 128
     # Should be multiple of udp packet size, currently 4096 bytes, or 1024 samples
-    num_samples = 16384
+    num_samples = 4096
     start_sample = 2000
-    tx_num_samples = 1024
+    tx_num_samples = 4096
     tx_start_sample = start_sample
     prf = 8000
     pri = int(1/prf * clk)
@@ -57,11 +57,13 @@ def main():
     inter_cpi = 20000
     tx_lo_offset = 10e6
     rx_lo_offset = 0
-    test_duration = 60
+    dec_rate = 16
+    test_duration = 2
 
     pri_float = pri / clk
 
     print('PRI', pri_float, 'PRF', 1 / pri_float)
+    print('Sampling Duration (usec)', (tx_num_samples / radar_manager.BASEBAND_SAMPLE_RATE * dec_rate)/1e-6)
     print('Expected Data Rate', num_samples * 4 / pri_float / 1e6)
 
 
@@ -72,7 +74,8 @@ def main():
     recorder1.start_recording('test1.bin', True)
 
     radar.configure_cpi(pri, inter_cpi, num_pulses, num_samples, start_sample,
-                        tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset)
+                        tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset,
+                        dec_rate)
 
     print('Start Running')
     radar.start_running()
diff --git a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
index b15ad0e..be89228 100755
--- a/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
+++ b/radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
@@ -283,11 +283,11 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
 #set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
 
 # Works with the board at my house
-#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
-#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
+set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
+set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
 # Works with the board Chris has (broken USB UART)
-set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
-set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
+#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
+#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
 
 set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
 set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
diff --git a/radar_alinx_kintex.srcs/set_build_date.tcl b/radar_alinx_kintex.srcs/set_build_date.tcl
new file mode 100755
index 0000000..a03c44f
--- /dev/null
+++ b/radar_alinx_kintex.srcs/set_build_date.tcl
@@ -0,0 +1,40 @@
+# Current date, time, and seconds since epoch
+# 0 = 4-digit year
+# 1 = 2-digit year
+# 2 = 2-digit month
+# 3 = 2-digit day
+# 4 = 2-digit hour
+# 5 = 2-digit minute
+# 6 = 2-digit second
+# 7 = Epoch (seconds since 1970-01-01_00:00:00)
+# Array index                                   0  1  2  3  4  5  6  7
+set datetime_arr [clock format [clock seconds] -format {%Y %y %m %d %H %M %S 00}]
+# Example :
+# 2020 20 05 27 13 45 45 00
+ 
+# Get the datecode in the yyyy-mm-dd format
+set datecode [lindex $datetime_arr 0][lindex $datetime_arr 2][lindex $datetime_arr 3]
+# Get the timecode in the hh-mm-ss-00 format
+set timecode [lindex $datetime_arr 4][lindex $datetime_arr 5][lindex $datetime_arr 6][lindex $datetime_arr 7]
+# Show this in the log
+puts DATECODE=$datecode
+puts TIMECODE=$timecode
+ 
+# # Get the git hashtag for this project
+# set curr_dir [pwd]
+# set proj_dir [get_property DIRECTORY [current_project]]
+# cd $proj_dir
+# 
+# if { [catch {exec git rev-parse --short=8 HEAD}] } {
+#     puts "No git version control in the $proj_dir directory"
+#     set git_hash 00000000
+# } else {
+#     set git_hash [exec git rev-parse --short=8 HEAD]
+# }
+# # Show this in the log
+# puts HASHCODE=$git_hash
+ 
+# Update the generics
+set initial_generics [get_property generic [current_fileset]]
+#set_property generic "$initial_generics G_DATE_CODE=32'h$datecode G_TIME_CODE=32'h$timecode G_HASH_CODE=32'h$git_hash" [current_fileset]
+set_property generic "$initial_generics DATE_CODE=32'h$datecode TIME_CODE=32'h$timecode" [current_fileset]
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bd b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bd
new file mode 100644
index 0000000..088fd14
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bd
@@ -0,0 +1,951 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0x5199E03713246BDA",
+      "device": "xcku040-ffva1156-2-i",
+      "gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd",
+      "name": "decimation_bd",
+      "rev_ctrl_bd_flag": "RevCtrlBdOff",
+      "synth_flow_mode": "Singular",
+      "tool_version": "2022.2",
+      "validated": "true"
+    },
+    "design_tree": {
+      "axis_broadcaster_0": "",
+      "dec_2_width": "",
+      "dec_2_fir": "",
+      "dec_8_fir": "",
+      "dec_4_fir": "",
+      "dec_16_fir": "",
+      "axis_broadcaster_1": "",
+      "axis_broadcaster_2": "",
+      "dec_4_width": "",
+      "dec_16_width": "",
+      "dec_8_width": ""
+    },
+    "interface_ports": {
+      "dec_by_2": {
+        "mode": "Master",
+        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
+        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+        "parameters": {
+          "CLK_DOMAIN": {
+            "value": "decimation_bd_clk",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "280000000"
+          },
+          "HAS_TKEEP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TLAST": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TREADY": {
+            "value": "1",
+            "value_src": "default"
+          },
+          "HAS_TSTRB": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "LAYERED_METADATA": {
+            "value": "undef",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.0",
+            "value_src": "default"
+          },
+          "TDATA_NUM_BYTES": {
+            "value": "12",
+            "value_src": "default_prop"
+          },
+          "TDEST_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TID_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TUSER_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          }
+        },
+        "port_maps": {
+          "TVALID": {
+            "physical_name": "dec_by_2_tvalid",
+            "direction": "O"
+          },
+          "TREADY": {
+            "physical_name": "dec_by_2_tready",
+            "direction": "I"
+          },
+          "TDATA": {
+            "physical_name": "dec_by_2_tdata",
+            "direction": "O",
+            "left": "95",
+            "right": "0"
+          }
+        }
+      },
+      "dec_by_4": {
+        "mode": "Master",
+        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
+        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+        "parameters": {
+          "CLK_DOMAIN": {
+            "value": "decimation_bd_clk",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "280000000"
+          },
+          "HAS_TKEEP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TLAST": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TREADY": {
+            "value": "1",
+            "value_src": "default"
+          },
+          "HAS_TSTRB": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "LAYERED_METADATA": {
+            "value": "undef",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.0",
+            "value_src": "default"
+          },
+          "TDATA_NUM_BYTES": {
+            "value": "12",
+            "value_src": "default_prop"
+          },
+          "TDEST_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TID_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TUSER_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          }
+        },
+        "port_maps": {
+          "TVALID": {
+            "physical_name": "dec_by_4_tvalid",
+            "direction": "O"
+          },
+          "TREADY": {
+            "physical_name": "dec_by_4_tready",
+            "direction": "I"
+          },
+          "TDATA": {
+            "physical_name": "dec_by_4_tdata",
+            "direction": "O",
+            "left": "95",
+            "right": "0"
+          }
+        }
+      },
+      "in_i": {
+        "mode": "Slave",
+        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
+        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+        "parameters": {
+          "CLK_DOMAIN": {
+            "value": "decimation_bd_clk",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "280000000"
+          },
+          "HAS_TKEEP": {
+            "value": "0"
+          },
+          "HAS_TLAST": {
+            "value": "0"
+          },
+          "HAS_TREADY": {
+            "value": "1"
+          },
+          "HAS_TSTRB": {
+            "value": "0"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "LAYERED_METADATA": {
+            "value": "undef"
+          },
+          "PHASE": {
+            "value": "0.0",
+            "value_src": "default"
+          },
+          "TDATA_NUM_BYTES": {
+            "value": "8"
+          },
+          "TDEST_WIDTH": {
+            "value": "0"
+          },
+          "TID_WIDTH": {
+            "value": "0"
+          },
+          "TUSER_WIDTH": {
+            "value": "0"
+          }
+        },
+        "port_maps": {
+          "TDATA": {
+            "physical_name": "in_i_tdata",
+            "direction": "I",
+            "left": "63",
+            "right": "0"
+          },
+          "TREADY": {
+            "physical_name": "in_i_tready",
+            "direction": "O"
+          },
+          "TVALID": {
+            "physical_name": "in_i_tvalid",
+            "direction": "I"
+          }
+        }
+      },
+      "dec_by_8": {
+        "mode": "Master",
+        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
+        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+        "parameters": {
+          "CLK_DOMAIN": {
+            "value": "decimation_bd_clk",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "280000000"
+          },
+          "HAS_TKEEP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TLAST": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TREADY": {
+            "value": "1",
+            "value_src": "default"
+          },
+          "HAS_TSTRB": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "LAYERED_METADATA": {
+            "value": "undef",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.0",
+            "value_src": "default"
+          },
+          "TDATA_NUM_BYTES": {
+            "value": "12",
+            "value_src": "default_prop"
+          },
+          "TDEST_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TID_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TUSER_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          }
+        },
+        "port_maps": {
+          "TVALID": {
+            "physical_name": "dec_by_8_tvalid",
+            "direction": "O"
+          },
+          "TREADY": {
+            "physical_name": "dec_by_8_tready",
+            "direction": "I"
+          },
+          "TDATA": {
+            "physical_name": "dec_by_8_tdata",
+            "direction": "O",
+            "left": "95",
+            "right": "0"
+          }
+        }
+      },
+      "dec_by_16": {
+        "mode": "Master",
+        "vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
+        "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+        "parameters": {
+          "CLK_DOMAIN": {
+            "value": "decimation_bd_clk",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "280000000"
+          },
+          "HAS_TKEEP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TLAST": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "HAS_TREADY": {
+            "value": "1",
+            "value_src": "default"
+          },
+          "HAS_TSTRB": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "LAYERED_METADATA": {
+            "value": "undef",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.0",
+            "value_src": "default"
+          },
+          "TDATA_NUM_BYTES": {
+            "value": "12",
+            "value_src": "default_prop"
+          },
+          "TDEST_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TID_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "TUSER_WIDTH": {
+            "value": "0",
+            "value_src": "default"
+          }
+        },
+        "port_maps": {
+          "TVALID": {
+            "physical_name": "dec_by_16_tvalid",
+            "direction": "O"
+          },
+          "TREADY": {
+            "physical_name": "dec_by_16_tready",
+            "direction": "I"
+          },
+          "TDATA": {
+            "physical_name": "dec_by_16_tdata",
+            "direction": "O",
+            "left": "95",
+            "right": "0"
+          }
+        }
+      }
+    },
+    "ports": {
+      "clk": {
+        "type": "clk",
+        "direction": "I",
+        "parameters": {
+          "ASSOCIATED_BUSIF": {
+            "value": "dec_by_2:in_i:dec_by_4:dec_by_8:dec_by_16"
+          },
+          "ASSOCIATED_RESET": {
+            "value": "rstn"
+          },
+          "CLK_DOMAIN": {
+            "value": "decimation_bd_clk",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "280000000"
+          },
+          "FREQ_TOLERANCE_HZ": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.0",
+            "value_src": "default"
+          }
+        }
+      },
+      "rstn": {
+        "type": "rst",
+        "direction": "I",
+        "parameters": {
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "POLARITY": {
+            "value": "ACTIVE_LOW",
+            "value_src": "default"
+          }
+        }
+      }
+    },
+    "components": {
+      "axis_broadcaster_0": {
+        "vlnv": "xilinx.com:ip:axis_broadcaster:1.1",
+        "xci_name": "decimation_bd_axis_broadcaster_0_0",
+        "xci_path": "ip/decimation_bd_axis_broadcaster_0_0/decimation_bd_axis_broadcaster_0_0.xci",
+        "inst_hier_path": "axis_broadcaster_0"
+      },
+      "dec_2_width": {
+        "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1",
+        "xci_name": "decimation_bd_axis_dwidth_converter_0_0",
+        "xci_path": "ip/decimation_bd_axis_dwidth_converter_0_0/decimation_bd_axis_dwidth_converter_0_0.xci",
+        "inst_hier_path": "dec_2_width",
+        "parameters": {
+          "M_TDATA_NUM_BYTES": {
+            "value": "12"
+          }
+        }
+      },
+      "dec_2_fir": {
+        "vlnv": "xilinx.com:ip:fir_compiler:7.2",
+        "xci_name": "decimation_bd_fir_compiler_0_0",
+        "xci_path": "ip/decimation_bd_fir_compiler_0_0/decimation_bd_fir_compiler_0_0.xci",
+        "inst_hier_path": "dec_2_fir",
+        "parameters": {
+          "Clock_Frequency": {
+            "value": "300.0"
+          },
+          "CoefficientVector": {
+            "value": [
+              "-1.56146976e-18, -1.88787840e-03,  2.24491365e-18,  3.86247830e-03, -4.19119720e-18, -8.24246660e-03,  7.10401637e-18,  1.59471140e-02, -1.05399209e-17, -2.86765592e-02,  1.39758253e-17, ",
+              "5.07185616e-02, -1.68886445e-17, -9.80159075e-02,  1.88349281e-17,  3.15941764e-01,  5.00705787e-01,  3.15941764e-01,  1.88349281e-17, -9.80159075e-02, -1.68886445e-17,  5.07185616e-02, ",
+              "1.39758253e-17, -2.86765592e-02, -1.05399209e-17,  1.59471140e-02,  7.10401637e-18, -8.24246660e-03, -4.19119720e-18,  3.86247830e-03,  2.24491365e-18, -1.88787840e-03, -1.56146976e-18"
+            ]
+          },
+          "Coefficient_Fractional_Bits": {
+            "value": "15"
+          },
+          "Coefficient_Sets": {
+            "value": "1"
+          },
+          "Coefficient_Sign": {
+            "value": "Signed"
+          },
+          "Coefficient_Structure": {
+            "value": "Symmetric"
+          },
+          "Coefficient_Width": {
+            "value": "16"
+          },
+          "ColumnConfig": {
+            "value": "17"
+          },
+          "Data_Fractional_Bits": {
+            "value": "15"
+          },
+          "Data_Width": {
+            "value": "16"
+          },
+          "Decimation_Rate": {
+            "value": "2"
+          },
+          "Filter_Architecture": {
+            "value": "Systolic_Multiply_Accumulate"
+          },
+          "Filter_Type": {
+            "value": "Decimation"
+          },
+          "Has_ARESETn": {
+            "value": "true"
+          },
+          "Interpolation_Rate": {
+            "value": "1"
+          },
+          "Number_Channels": {
+            "value": "1"
+          },
+          "Output_Rounding_Mode": {
+            "value": "Truncate_LSBs"
+          },
+          "Output_Width": {
+            "value": "17"
+          },
+          "Quantization": {
+            "value": "Quantize_Only"
+          },
+          "RateSpecification": {
+            "value": "Input_Sample_Period"
+          },
+          "SamplePeriod": {
+            "value": "0.25"
+          },
+          "Sample_Frequency": {
+            "value": "0.001"
+          },
+          "Zero_Pack_Factor": {
+            "value": "1"
+          }
+        }
+      },
+      "dec_8_fir": {
+        "vlnv": "xilinx.com:ip:fir_compiler:7.2",
+        "xci_name": "decimation_bd_dec_2_fir_0",
+        "xci_path": "ip/decimation_bd_dec_2_fir_0/decimation_bd_dec_2_fir_0.xci",
+        "inst_hier_path": "dec_8_fir",
+        "parameters": {
+          "Clock_Frequency": {
+            "value": "300.0"
+          },
+          "CoefficientVector": {
+            "value": [
+              "-1.56146976e-18, -1.88787840e-03,  2.24491365e-18,  3.86247830e-03, -4.19119720e-18, -8.24246660e-03,  7.10401637e-18,  1.59471140e-02, -1.05399209e-17, -2.86765592e-02,  1.39758253e-17, ",
+              "5.07185616e-02, -1.68886445e-17, -9.80159075e-02,  1.88349281e-17,  3.15941764e-01,  5.00705787e-01,  3.15941764e-01,  1.88349281e-17, -9.80159075e-02, -1.68886445e-17,  5.07185616e-02, ",
+              "1.39758253e-17, -2.86765592e-02, -1.05399209e-17,  1.59471140e-02,  7.10401637e-18, -8.24246660e-03, -4.19119720e-18,  3.86247830e-03,  2.24491365e-18, -1.88787840e-03, -1.56146976e-18"
+            ]
+          },
+          "Coefficient_Fractional_Bits": {
+            "value": "15"
+          },
+          "Coefficient_Sets": {
+            "value": "1"
+          },
+          "Coefficient_Sign": {
+            "value": "Signed"
+          },
+          "Coefficient_Structure": {
+            "value": "Symmetric"
+          },
+          "Coefficient_Width": {
+            "value": "16"
+          },
+          "ColumnConfig": {
+            "value": "9"
+          },
+          "Data_Fractional_Bits": {
+            "value": "15"
+          },
+          "Data_Width": {
+            "value": "18"
+          },
+          "Decimation_Rate": {
+            "value": "2"
+          },
+          "Filter_Architecture": {
+            "value": "Systolic_Multiply_Accumulate"
+          },
+          "Filter_Type": {
+            "value": "Decimation"
+          },
+          "Has_ARESETn": {
+            "value": "true"
+          },
+          "Interpolation_Rate": {
+            "value": "1"
+          },
+          "Number_Channels": {
+            "value": "1"
+          },
+          "Output_Rounding_Mode": {
+            "value": "Truncate_LSBs"
+          },
+          "Output_Width": {
+            "value": "19"
+          },
+          "Quantization": {
+            "value": "Quantize_Only"
+          },
+          "RateSpecification": {
+            "value": "Input_Sample_Period"
+          },
+          "SamplePeriod": {
+            "value": "1"
+          },
+          "Sample_Frequency": {
+            "value": "0.001"
+          },
+          "Zero_Pack_Factor": {
+            "value": "1"
+          }
+        }
+      },
+      "dec_4_fir": {
+        "vlnv": "xilinx.com:ip:fir_compiler:7.2",
+        "xci_name": "decimation_bd_dec_2_fir_1",
+        "xci_path": "ip/decimation_bd_dec_2_fir_1/decimation_bd_dec_2_fir_1.xci",
+        "inst_hier_path": "dec_4_fir",
+        "parameters": {
+          "Clock_Frequency": {
+            "value": "300.0"
+          },
+          "CoefficientVector": {
+            "value": [
+              "-1.56146976e-18, -1.88787840e-03,  2.24491365e-18,  3.86247830e-03, -4.19119720e-18, -8.24246660e-03,  7.10401637e-18,  1.59471140e-02, -1.05399209e-17, -2.86765592e-02,  1.39758253e-17, ",
+              "5.07185616e-02, -1.68886445e-17, -9.80159075e-02,  1.88349281e-17,  3.15941764e-01,  5.00705787e-01,  3.15941764e-01,  1.88349281e-17, -9.80159075e-02, -1.68886445e-17,  5.07185616e-02, ",
+              "1.39758253e-17, -2.86765592e-02, -1.05399209e-17,  1.59471140e-02,  7.10401637e-18, -8.24246660e-03, -4.19119720e-18,  3.86247830e-03,  2.24491365e-18, -1.88787840e-03, -1.56146976e-18"
+            ]
+          },
+          "Coefficient_Fractional_Bits": {
+            "value": "15"
+          },
+          "Coefficient_Sets": {
+            "value": "1"
+          },
+          "Coefficient_Sign": {
+            "value": "Signed"
+          },
+          "Coefficient_Structure": {
+            "value": "Symmetric"
+          },
+          "Coefficient_Width": {
+            "value": "16"
+          },
+          "ColumnConfig": {
+            "value": "17"
+          },
+          "Data_Fractional_Bits": {
+            "value": "15"
+          },
+          "Data_Width": {
+            "value": "17"
+          },
+          "Decimation_Rate": {
+            "value": "2"
+          },
+          "Filter_Architecture": {
+            "value": "Systolic_Multiply_Accumulate"
+          },
+          "Filter_Type": {
+            "value": "Decimation"
+          },
+          "Has_ARESETn": {
+            "value": "true"
+          },
+          "Interpolation_Rate": {
+            "value": "1"
+          },
+          "Number_Channels": {
+            "value": "1"
+          },
+          "Output_Rounding_Mode": {
+            "value": "Truncate_LSBs"
+          },
+          "Output_Width": {
+            "value": "18"
+          },
+          "Quantization": {
+            "value": "Quantize_Only"
+          },
+          "RateSpecification": {
+            "value": "Input_Sample_Period"
+          },
+          "SamplePeriod": {
+            "value": "0.5"
+          },
+          "Sample_Frequency": {
+            "value": "0.001"
+          },
+          "Zero_Pack_Factor": {
+            "value": "1"
+          }
+        }
+      },
+      "dec_16_fir": {
+        "vlnv": "xilinx.com:ip:fir_compiler:7.2",
+        "xci_name": "decimation_bd_dec_2_fir_2",
+        "xci_path": "ip/decimation_bd_dec_2_fir_2/decimation_bd_dec_2_fir_2.xci",
+        "inst_hier_path": "dec_16_fir",
+        "parameters": {
+          "Clock_Frequency": {
+            "value": "300.0"
+          },
+          "CoefficientVector": {
+            "value": [
+              "-1.56146976e-18, -1.88787840e-03,  2.24491365e-18,  3.86247830e-03, -4.19119720e-18, -8.24246660e-03,  7.10401637e-18,  1.59471140e-02, -1.05399209e-17, -2.86765592e-02,  1.39758253e-17, ",
+              "5.07185616e-02, -1.68886445e-17, -9.80159075e-02,  1.88349281e-17,  3.15941764e-01,  5.00705787e-01,  3.15941764e-01,  1.88349281e-17, -9.80159075e-02, -1.68886445e-17,  5.07185616e-02, ",
+              "1.39758253e-17, -2.86765592e-02, -1.05399209e-17,  1.59471140e-02,  7.10401637e-18, -8.24246660e-03, -4.19119720e-18,  3.86247830e-03,  2.24491365e-18, -1.88787840e-03, -1.56146976e-18"
+            ]
+          },
+          "Coefficient_Fractional_Bits": {
+            "value": "15"
+          },
+          "Coefficient_Sets": {
+            "value": "1"
+          },
+          "Coefficient_Sign": {
+            "value": "Signed"
+          },
+          "Coefficient_Structure": {
+            "value": "Symmetric"
+          },
+          "Coefficient_Width": {
+            "value": "16"
+          },
+          "ColumnConfig": {
+            "value": "5"
+          },
+          "Data_Fractional_Bits": {
+            "value": "15"
+          },
+          "Data_Width": {
+            "value": "19"
+          },
+          "Decimation_Rate": {
+            "value": "2"
+          },
+          "Filter_Architecture": {
+            "value": "Systolic_Multiply_Accumulate"
+          },
+          "Filter_Type": {
+            "value": "Decimation"
+          },
+          "Has_ARESETn": {
+            "value": "true"
+          },
+          "Interpolation_Rate": {
+            "value": "1"
+          },
+          "Number_Channels": {
+            "value": "1"
+          },
+          "Output_Rounding_Mode": {
+            "value": "Truncate_LSBs"
+          },
+          "Output_Width": {
+            "value": "20"
+          },
+          "Quantization": {
+            "value": "Quantize_Only"
+          },
+          "RateSpecification": {
+            "value": "Input_Sample_Period"
+          },
+          "SamplePeriod": {
+            "value": "2"
+          },
+          "Sample_Frequency": {
+            "value": "0.001"
+          },
+          "Zero_Pack_Factor": {
+            "value": "1"
+          }
+        }
+      },
+      "axis_broadcaster_1": {
+        "vlnv": "xilinx.com:ip:axis_broadcaster:1.1",
+        "xci_name": "decimation_bd_axis_broadcaster_0_1",
+        "xci_path": "ip/decimation_bd_axis_broadcaster_0_1/decimation_bd_axis_broadcaster_0_1.xci",
+        "inst_hier_path": "axis_broadcaster_1"
+      },
+      "axis_broadcaster_2": {
+        "vlnv": "xilinx.com:ip:axis_broadcaster:1.1",
+        "xci_name": "decimation_bd_axis_broadcaster_0_2",
+        "xci_path": "ip/decimation_bd_axis_broadcaster_0_2/decimation_bd_axis_broadcaster_0_2.xci",
+        "inst_hier_path": "axis_broadcaster_2"
+      },
+      "dec_4_width": {
+        "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1",
+        "xci_name": "decimation_bd_dec_2_width_0",
+        "xci_path": "ip/decimation_bd_dec_2_width_0/decimation_bd_dec_2_width_0.xci",
+        "inst_hier_path": "dec_4_width",
+        "parameters": {
+          "M_TDATA_NUM_BYTES": {
+            "value": "12"
+          }
+        }
+      },
+      "dec_16_width": {
+        "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1",
+        "xci_name": "decimation_bd_dec_2_width_1",
+        "xci_path": "ip/decimation_bd_dec_2_width_1/decimation_bd_dec_2_width_1.xci",
+        "inst_hier_path": "dec_16_width",
+        "parameters": {
+          "M_TDATA_NUM_BYTES": {
+            "value": "12"
+          }
+        }
+      },
+      "dec_8_width": {
+        "vlnv": "xilinx.com:ip:axis_dwidth_converter:1.1",
+        "xci_name": "decimation_bd_dec_2_width_2",
+        "xci_path": "ip/decimation_bd_dec_2_width_2/decimation_bd_dec_2_width_2.xci",
+        "inst_hier_path": "dec_8_width",
+        "parameters": {
+          "M_TDATA_NUM_BYTES": {
+            "value": "12"
+          }
+        }
+      }
+    },
+    "interface_nets": {
+      "axis_broadcaster_0_M00_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_0/M00_AXIS",
+          "dec_2_width/S_AXIS"
+        ]
+      },
+      "axis_broadcaster_0_M01_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_0/M01_AXIS",
+          "dec_4_fir/S_AXIS_DATA"
+        ]
+      },
+      "axis_broadcaster_1_M00_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_1/M00_AXIS",
+          "dec_4_width/S_AXIS"
+        ]
+      },
+      "axis_broadcaster_1_M01_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_1/M01_AXIS",
+          "dec_8_fir/S_AXIS_DATA"
+        ]
+      },
+      "axis_broadcaster_2_M00_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_2/M00_AXIS",
+          "dec_8_width/S_AXIS"
+        ]
+      },
+      "axis_broadcaster_2_M01_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_2/M01_AXIS",
+          "dec_16_fir/S_AXIS_DATA"
+        ]
+      },
+      "dec_16_fir_M_AXIS_DATA": {
+        "interface_ports": [
+          "dec_16_fir/M_AXIS_DATA",
+          "dec_16_width/S_AXIS"
+        ]
+      },
+      "dec_16_width_M_AXIS": {
+        "interface_ports": [
+          "dec_by_16",
+          "dec_16_width/M_AXIS"
+        ]
+      },
+      "dec_2_fir_M_AXIS_DATA": {
+        "interface_ports": [
+          "dec_2_fir/M_AXIS_DATA",
+          "axis_broadcaster_0/S_AXIS"
+        ]
+      },
+      "dec_2_width_M_AXIS": {
+        "interface_ports": [
+          "dec_by_2",
+          "dec_2_width/M_AXIS"
+        ]
+      },
+      "dec_4_fir_M_AXIS_DATA": {
+        "interface_ports": [
+          "dec_4_fir/M_AXIS_DATA",
+          "axis_broadcaster_1/S_AXIS"
+        ]
+      },
+      "dec_4_width_M_AXIS": {
+        "interface_ports": [
+          "dec_by_4",
+          "dec_4_width/M_AXIS"
+        ]
+      },
+      "dec_8_fir_M_AXIS_DATA": {
+        "interface_ports": [
+          "dec_8_fir/M_AXIS_DATA",
+          "axis_broadcaster_2/S_AXIS"
+        ]
+      },
+      "dec_8_width_M_AXIS": {
+        "interface_ports": [
+          "dec_by_8",
+          "dec_8_width/M_AXIS"
+        ]
+      },
+      "in_i_1": {
+        "interface_ports": [
+          "in_i",
+          "dec_2_fir/S_AXIS_DATA"
+        ]
+      }
+    },
+    "nets": {
+      "Net": {
+        "ports": [
+          "clk",
+          "dec_2_fir/aclk",
+          "axis_broadcaster_0/aclk",
+          "dec_4_fir/aclk",
+          "axis_broadcaster_1/aclk",
+          "dec_8_fir/aclk",
+          "axis_broadcaster_2/aclk",
+          "dec_16_fir/aclk",
+          "dec_2_width/aclk",
+          "dec_4_width/aclk",
+          "dec_16_width/aclk",
+          "dec_8_width/aclk"
+        ]
+      },
+      "Net1": {
+        "ports": [
+          "rstn",
+          "axis_broadcaster_0/aresetn",
+          "dec_2_fir/aresetn",
+          "dec_4_fir/aresetn",
+          "axis_broadcaster_1/aresetn",
+          "dec_8_fir/aresetn",
+          "axis_broadcaster_2/aresetn",
+          "dec_16_fir/aresetn",
+          "dec_4_width/aresetn",
+          "dec_8_width/aresetn",
+          "dec_2_width/aresetn",
+          "dec_16_width/aresetn"
+        ]
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bda b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bda
new file mode 100644
index 0000000..e015e98
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bda
@@ -0,0 +1,42 @@
+<?xml version="1.0" encoding="utf-8"?>
+<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
+  <key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
+  <key id="BP" for="node" attr.name="base_param" attr.type="string"/>
+  <key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
+  <key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
+  <key id="HP" for="node" attr.name="high_param" attr.type="string"/>
+  <key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
+  <key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
+  <key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
+  <key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
+  <key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
+  <key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
+  <key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
+  <key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
+  <key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
+  <key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
+  <key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
+  <key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
+  <key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
+  <key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
+  <key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
+  <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
+  <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
+    <node id="n0">
+      <data key="VH">2</data>
+      <data key="VM">decimation_bd</data>
+      <data key="VT">VR</data>
+    </node>
+    <node id="n1">
+      <data key="TU">active</data>
+      <data key="VH">2</data>
+      <data key="VT">PM</data>
+    </node>
+    <node id="n2">
+      <data key="VM">decimation_bd</data>
+      <data key="VT">BC</data>
+    </node>
+    <edge id="e0" source="n2" target="n0"/>
+    <edge id="e1" source="n0" target="n1"/>
+  </graph>
+</graphml>
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0/decimation_bd_axis_broadcaster_0_0.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0/decimation_bd_axis_broadcaster_0_0.xci
new file mode 100644
index 0000000..7da64ed
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0/decimation_bd_axis_broadcaster_0_0.xci
@@ -0,0 +1,218 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "decimation_bd_axis_broadcaster_0_0",
+    "cell_name": "axis_broadcaster_0",
+    "component_reference": "xilinx.com:ip:axis_broadcaster:1.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0",
+    "parameters": {
+      "component_parameters": {
+        "NUM_MI": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TDATA_NUM_BYTES": [ { "value": "6", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_TDATA_NUM_BYTES": [ { "value": "6", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_SPLITTER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TREADY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_TDATA_REMAP": [ { "value": "tdata[47:0]", "resolve_type": "user", "usage": "all" } ],
+        "M01_TDATA_REMAP": [ { "value": "tdata[47:0]", "resolve_type": "user", "usage": "all" } ],
+        "M02_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
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+        "M04_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M05_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M06_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
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+        "M11_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M12_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M13_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M14_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M15_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M16_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M00_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M01_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M02_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M03_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M04_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M05_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M06_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M07_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M08_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M09_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M10_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M11_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M12_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M13_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M14_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M15_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M16_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "decimation_bd_axis_broadcaster_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
+        "C_NUM_MI_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexu" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku040" } ],
+        "PACKAGE": [ { "value": "ffva1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
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+        "aresetn": [ { "direction": "in" } ],
+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0x000000000000" } ],
+        "m_axis_tvalid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "95", "size_right": "0" } ]
+      },
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
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+            "TUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+ format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency user_bitoffset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ]
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+          },
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+            "TVALID": [ { "physical_name": "m_axis_tvalid", "physical_left": "0", "physical_right": "0" } ]
+          }
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "6", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata", "physical_left": "95", "physical_right": "48" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid", "physical_left": "1", "physical_right": "1" } ]
+          }
+        },
+        "RSTIF": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "CLKIF": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "M00_AXIS:M01_AXIS:M02_AXIS:M03_AXIS:M04_AXIS:M05_AXIS:M06_AXIS:M07_AXIS:M08_AXIS:M09_AXIS:M10_AXIS:M11_AXIS:M12_AXIS:M13_AXIS:M14_AXIS:M15_AXIS:S_AXIS", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_1/decimation_bd_axis_broadcaster_0_1.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_1/decimation_bd_axis_broadcaster_0_1.xci
new file mode 100644
index 0000000..e108925
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_1/decimation_bd_axis_broadcaster_0_1.xci
@@ -0,0 +1,218 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "decimation_bd_axis_broadcaster_0_1",
+    "cell_name": "axis_broadcaster_1",
+    "component_reference": "xilinx.com:ip:axis_broadcaster:1.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_1",
+    "parameters": {
+      "component_parameters": {
+        "NUM_MI": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_SPLITTER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TREADY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TLAST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_TDATA_REMAP": [ { "value": "tdata[23:0]", "resolve_type": "user", "usage": "all" } ],
+        "M01_TDATA_REMAP": [ { "value": "tdata[23:0]", "resolve_type": "user", "usage": "all" } ],
+        "M02_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M03_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M04_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M05_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M06_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M07_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M08_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M09_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M10_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M11_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M12_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M13_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M14_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M15_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M16_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M00_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M01_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M02_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M03_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M04_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M05_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M06_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M07_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M08_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M09_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M10_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M11_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M12_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M13_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M14_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M15_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M16_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "decimation_bd_axis_broadcaster_0_1", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
+        "C_NUM_MI_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexu" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku040" } ],
+        "PACKAGE": [ { "value": "ffva1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_1" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "23", "size_right": "0", "driver_value": "0x000000" } ],
+        "m_axis_tvalid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "47", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 18} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value vect} size {attribs {resolve_type generated dependency vect_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency vect_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 18} bitoffset {attribs {resolve_type immediate dependency {} format l
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+imum {}} value data_valid} enabled {attribs {resolve_type generated dependency data_valid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_valid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated dependency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chanid_bitoffset
+ format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency user_bitoffset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ]
+          }
+        },
+        "M00_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata", "physical_left": "23", "physical_right": "0" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid", "physical_left": "0", "physical_right": "0" } ]
+          }
+        },
+        "M01_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata", "physical_left": "47", "physical_right": "24" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid", "physical_left": "1", "physical_right": "1" } ]
+          }
+        },
+        "RSTIF": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "CLKIF": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "M00_AXIS:M01_AXIS:M02_AXIS:M03_AXIS:M04_AXIS:M05_AXIS:M06_AXIS:M07_AXIS:M08_AXIS:M09_AXIS:M10_AXIS:M11_AXIS:M12_AXIS:M13_AXIS:M14_AXIS:M15_AXIS:S_AXIS", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_2/decimation_bd_axis_broadcaster_0_2.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_2/decimation_bd_axis_broadcaster_0_2.xci
new file mode 100644
index 0000000..2c97b8a
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_2/decimation_bd_axis_broadcaster_0_2.xci
@@ -0,0 +1,218 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "decimation_bd_axis_broadcaster_0_2",
+    "cell_name": "axis_broadcaster_2",
+    "component_reference": "xilinx.com:ip:axis_broadcaster:1.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_2",
+    "parameters": {
+      "component_parameters": {
+        "NUM_MI": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_SPLITTER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S_TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TREADY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TLAST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M00_TDATA_REMAP": [ { "value": "tdata[23:0]", "resolve_type": "user", "usage": "all" } ],
+        "M01_TDATA_REMAP": [ { "value": "tdata[23:0]", "resolve_type": "user", "usage": "all" } ],
+        "M02_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M03_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M04_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M05_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M06_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M07_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M08_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M09_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M10_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M11_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M12_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M13_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M14_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M15_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M16_TDATA_REMAP": [ { "value": "TDATA[7:0]", "resolve_type": "user", "usage": "all" } ],
+        "M00_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M01_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M02_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M03_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M04_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M05_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M06_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M07_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M08_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M09_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M10_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M11_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M12_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M13_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M14_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M15_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "M16_TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "decimation_bd_axis_broadcaster_0_2", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
+        "C_NUM_MI_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexu" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku040" } ],
+        "PACKAGE": [ { "value": "ffva1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_2" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "23", "size_right": "0", "driver_value": "0x000000" } ],
+        "m_axis_tvalid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "47", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 19} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 19} bitoffset {attribs {resolve_type immediate dependency {} format l
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+ency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_data_valid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data_valid} enabled {attribs {resolve_type generated dependency data_valid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_valid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated depe
+ndency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chanid_bitoffset format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type
+ generated dependency user_bitoffset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ]
+          }
+        },
+        "M00_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata", "physical_left": "23", "physical_right": "0" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid", "physical_left": "0", "physical_right": "0" } ]
+          }
+        },
+        "M01_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata", "physical_left": "47", "physical_right": "24" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid", "physical_left": "1", "physical_right": "1" } ]
+          }
+        },
+        "RSTIF": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "CLKIF": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "M00_AXIS:M01_AXIS:M02_AXIS:M03_AXIS:M04_AXIS:M05_AXIS:M06_AXIS:M07_AXIS:M08_AXIS:M09_AXIS:M10_AXIS:M11_AXIS:M12_AXIS:M13_AXIS:M14_AXIS:M15_AXIS:S_AXIS", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_dwidth_converter_0_0/decimation_bd_axis_dwidth_converter_0_0.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_dwidth_converter_0_0/decimation_bd_axis_dwidth_converter_0_0.xci
new file mode 100644
index 0000000..95119c6
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_dwidth_converter_0_0/decimation_bd_axis_dwidth_converter_0_0.xci
@@ -0,0 +1,157 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "decimation_bd_axis_dwidth_converter_0_0",
+    "cell_name": "dec_2_width",
+    "component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_dwidth_converter_0_0",
+    "parameters": {
+      "component_parameters": {
+        "S_TDATA_NUM_BYTES": [ { "value": "6", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TDATA_NUM_BYTES": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TLAST": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "decimation_bd_axis_dwidth_converter_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
+        "C_S_AXIS_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TDATA_WIDTH": [ { "value": "96", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintexu" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xcku040" } ],
+        "PACKAGE": [ { "value": "ffva1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_axis_dwidth_converter_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_tready": [ { "direction": "out" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0x000000000000" } ],
+        "m_axis_tvalid": [ { "direction": "out" } ],
+        "m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "95", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "S_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "6", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "s_axis_tready" } ],
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ]
+          }
+        },
+        "M_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "12", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "m_axis_tready" } ],
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ]
+          }
+        },
+        "RSTIF": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
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\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_0/decimation_bd_dec_2_fir_0.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_0/decimation_bd_dec_2_fir_0.xci
new file mode 100644
index 0000000..32b45e7
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_0/decimation_bd_dec_2_fir_0.xci
@@ -0,0 +1,360 @@
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+          }
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
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+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
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+          }
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+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
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+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
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+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "aclken_intf": {
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+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
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+            "TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
+            "TREADY": [ { "physical_name": "s_axis_data_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
+          }
+        },
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 19} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 19} bitoffset {attribs {resolve_type immediate dependency {} format l
+ong minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value path} size {attribs {resolve_type generated dependency path_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency path_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency out_width format long minimum {} maximum {}} value 19} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency out_fractwidth format long minimum {} maximum {}} value 15} signed {attribs {resolve_type generated dependency out_signed format bool minimum {} maximum {}} value true}}}}}}}}} TDATA_WIDTH 24 TUSER {datatype {name {attribs {resolve_type immediate depend
+ency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_data_valid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data_valid} enabled {attribs {resolve_type generated dependency data_valid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_valid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated depe
+ndency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chanid_bitoffset format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type
+ generated dependency user_bitoffset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_1/decimation_bd_dec_2_fir_1.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_1/decimation_bd_dec_2_fir_1.xci
new file mode 100644
index 0000000..1a72471
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_1/decimation_bd_dec_2_fir_1.xci
@@ -0,0 +1,360 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "decimation_bd_dec_2_fir_1",
+    "cell_name": "dec_4_fir",
+    "component_reference": "xilinx.com:ip:fir_compiler:7.2",
+    "ip_revision": "18",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_1",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "decimation_bd_dec_2_fir_1", "resolve_type": "user", "usage": "all" } ],
+        "GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientSource": [ { "value": "Vector", "resolve_type": "user", "usage": "all" } ],
+        "CoefficientVector": [ { "value": "-1.56146976e-18, -1.88787840e-03,  2.24491365e-18,  3.86247830e-03, -4.19119720e-18, -8.24246660e-03,  7.10401637e-18,  1.59471140e-02, -1.05399209e-17, -2.86765592e-02,  1.39758253e-17,  5.07185616e-02, -1.68886445e-17, -9.80159075e-02,  1.88349281e-17,  3.15941764e-01,  5.00705787e-01,  3.15941764e-01,  1.88349281e-17, -9.80159075e-02, -1.68886445e-17,  5.07185616e-02,  1.39758253e-17, -2.86765592e-02, -1.05399209e-17,  1.59471140e-02,  7.10401637e-18, -8.24246660e-03, -4.19119720e-18,  3.86247830e-03,  2.24491365e-18, -1.88787840e-03, -1.56146976e-18", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Sets": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Coefficient_Reload": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Filter_Type": [ { "value": "Decimation", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Rate_Change_Type": [ { "value": "Integer", "resolve_type": "user", "usage": "all" } ],
+        "Interpolation_Rate": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Decimation_Rate": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Zero_Pack_Factor": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Channel_Sequence": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
+        "Number_Channels": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Select_Pattern": [ { "value": "All", "resolve_type": "user", "usage": "all" } ],
+        "Pattern_List": [ { "value": "P4-0,P4-1,P4-2,P4-3,P4-4", "resolve_type": "user", "usage": "all" } ],
+        "Number_Paths": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RateSpecification": [ { "value": "Input_Sample_Period", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "HardwareOversamplingRate": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SamplePeriod": [ { "value": "0.5", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Sample_Frequency": [ { "value": "0.001", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Clock_Frequency": [ { "value": "300.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "Coefficient_Sign": [ { "value": "Signed", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Quantization": [ { "value": "Quantize_Only", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Coefficient_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BestPrecision": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_2/decimation_bd_dec_2_fir_2.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_2/decimation_bd_dec_2_fir_2.xci
new file mode 100644
index 0000000..ae04796
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_fir_2/decimation_bd_dec_2_fir_2.xci
@@ -0,0 +1,360 @@
+{
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+    "ip_revision": "18",
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+        "Filter_Selection": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
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+ong minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value path} size {attribs {resolve_type generated dependency path_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency path_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency out_width format long minimum {} maximum {}} value 20} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency out_fractwidth format long minimum {} maximum {}} value 15} signed {attribs {resolve_type generated dependency out_signed format bool minimum {} maximum {}} value true}}}}}}}}} TDATA_WIDTH 24 TUSER {datatype {name {attribs {resolve_type immediate depend
+ency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_data_valid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data_valid} enabled {attribs {resolve_type generated dependency data_valid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_valid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated depe
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_0/decimation_bd_dec_2_width_0.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_0/decimation_bd_dec_2_width_0.xci
new file mode 100644
index 0000000..b3f8abe
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_0/decimation_bd_dec_2_width_0.xci
@@ -0,0 +1,157 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "decimation_bd_dec_2_width_0",
+    "cell_name": "dec_4_width",
+    "component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_0",
+    "parameters": {
+      "component_parameters": {
+        "S_TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "HAS_TKEEP": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "decimation_bd_dec_2_width_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
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+        "C_S_AXIS_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
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+        "BASE_BOARD_PART": [ { "value": "" } ],
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+        "STATIC_POWER": [ { "value": "" } ],
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+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
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+      },
+      "runtime_parameters": {
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+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
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+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
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+        "s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_tready": [ { "direction": "out" } ],
+        "s_axis_tdata": [ { "direction": "in", "size_left": "23", "size_right": "0", "driver_value": "0x000000" } ],
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+        "m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "95", "size_right": "0" } ]
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "s_axis_tready" } ],
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ]
+          }
+        },
+        "M_AXIS": {
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "12", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "m_axis_tready" } ],
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ]
+          }
+        },
+        "RSTIF": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "CLKIF": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M_AXIS", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_1/decimation_bd_dec_2_width_1.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_1/decimation_bd_dec_2_width_1.xci
new file mode 100644
index 0000000..0603313
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_1/decimation_bd_dec_2_width_1.xci
@@ -0,0 +1,161 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "decimation_bd_dec_2_width_1",
+    "cell_name": "dec_16_width",
+    "component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_1",
+    "parameters": {
+      "component_parameters": {
+        "S_TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TDATA_NUM_BYTES": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "Component_Name": [ { "value": "decimation_bd_dec_2_width_1", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
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+        "C_S_AXIS_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
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+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
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+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M_AXIS", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_2/decimation_bd_dec_2_width_2.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_2/decimation_bd_dec_2_width_2.xci
new file mode 100644
index 0000000..19dea53
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_2/decimation_bd_dec_2_width_2.xci
@@ -0,0 +1,157 @@
+{
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+  "ip_inst": {
+    "xci_name": "decimation_bd_dec_2_width_2",
+    "cell_name": "dec_8_width",
+    "component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
+    "ip_revision": "26",
+    "gen_directory": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_2",
+    "parameters": {
+      "component_parameters": {
+        "S_TDATA_NUM_BYTES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "M_TDATA_NUM_BYTES": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TLAST": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "decimation_bd_dec_2_width_2", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
+        "C_S_AXIS_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TDATA_WIDTH": [ { "value": "96", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
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+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
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+        "PACKAGE": [ { "value": "ffva1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
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+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
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+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ],
+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "26" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_dec_2_width_2" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2022.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
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+        "m_axis_tvalid": [ { "direction": "out" } ],
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+            "HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TVALID": [ { "physical_name": "s_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "s_axis_tready" } ],
+            "TDATA": [ { "physical_name": "s_axis_tdata" } ]
+          }
+        },
+        "M_AXIS": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "12", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_fir_compiler_0_0/decimation_bd_fir_compiler_0_0.xci b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_fir_compiler_0_0/decimation_bd_fir_compiler_0_0.xci
new file mode 100644
index 0000000..04f5388
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_fir_compiler_0_0/decimation_bd_fir_compiler_0_0.xci
@@ -0,0 +1,360 @@
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+        "C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_PACKET_SIZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
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+        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
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+        "IPREVISION": [ { "value": "18" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../radar_alinx_kintex.gen/sources_1/bd/decimation_bd/ip/decimation_bd_fir_compiler_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
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+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
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+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
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+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
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+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
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+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
+            "TREADY": [ { "physical_name": "s_axis_data_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
+          }
+        },
+        "M_AXIS_DATA": {
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
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+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "280000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "decimation_bd_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 41} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value vect} size {attribs {resolve_type generated dependency vect_size format long minimum {} maximum {}} value 2} stride {attribs {resolve_type generated dependency vect_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 17} bitoffset {attribs {resolve_type immediate dependency {} format l
+ong minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 17} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value path} size {attribs {resolve_type generated dependency path_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency path_stride format long minimum {} maximum {}} value 24} data
+type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency out_width format long minimum {} maximum {}} value 17} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency out_fractwidth format long minimum {} maximum {}} value 15} signed {attribs {resolve_type generated dependency out_signed format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 48 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_data_valid {name {attribs {resolve_type immediate dependency {} format string minimum {} max
+imum {}} value data_valid} enabled {attribs {resolve_type generated dependency data_valid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_valid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated dependency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chanid_bitoffset
+ format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency user_bitoffset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ui/bd_37ca4332.ui b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ui/bd_37ca4332.ui
new file mode 100644
index 0000000..5f3f21e
--- /dev/null
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ui/bd_37ca4332.ui
@@ -0,0 +1,47 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-400,-66",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
+#  -string -flagsOSRD
+preplace port dec_by_2 -pg 1 -lvl 9 -x 2330 -y 220 -defaultsOSRD
+preplace port dec_by_4 -pg 1 -lvl 9 -x 2330 -y 80 -defaultsOSRD
+preplace port in_i -pg 1 -lvl 0 -x -100 -y 170 -defaultsOSRD
+preplace port dec_by_8 -pg 1 -lvl 9 -x 2330 -y 540 -defaultsOSRD
+preplace port dec_by_16 -pg 1 -lvl 9 -x 2330 -y 400 -defaultsOSRD
+preplace port port-id_clk -pg 1 -lvl 0 -x -100 -y 230 -defaultsOSRD
+preplace port port-id_rstn -pg 1 -lvl 0 -x -100 -y 200 -defaultsOSRD
+preplace inst axis_broadcaster_0 -pg 1 -lvl 2 -x 370 -y 210 -defaultsOSRD
+preplace inst dec_2_width -pg 1 -lvl 8 -x 2200 -y 220 -defaultsOSRD
+preplace inst dec_2_fir -pg 1 -lvl 1 -x 70 -y 190 -defaultsOSRD
+preplace inst dec_8_fir -pg 1 -lvl 5 -x 1320 -y 330 -defaultsOSRD
+preplace inst dec_4_fir -pg 1 -lvl 3 -x 690 -y 280 -defaultsOSRD
+preplace inst dec_16_fir -pg 1 -lvl 7 -x 1940 -y 380 -defaultsOSRD
+preplace inst axis_broadcaster_1 -pg 1 -lvl 4 -x 1000 -y 300 -defaultsOSRD
+preplace inst axis_broadcaster_2 -pg 1 -lvl 6 -x 1620 -y 350 -defaultsOSRD
+preplace inst dec_4_width -pg 1 -lvl 8 -x 2200 -y 80 -defaultsOSRD
+preplace inst dec_16_width -pg 1 -lvl 8 -x 2200 -y 400 -defaultsOSRD
+preplace inst dec_8_width -pg 1 -lvl 8 -x 2200 -y 540 -defaultsOSRD
+preplace netloc Net 1 0 8 -70 270 210 300 540 190 830 220 1160 410 1460 430 1790 460 2080
+preplace netloc Net1 1 0 8 -80 280 220 290 520 180 840 380 1170 420 1470 440 1780 470 2090
+preplace netloc dec_2_fir_M_AXIS_DATA 1 1 1 N 190
+preplace netloc axis_broadcaster_0_M01_AXIS 1 2 1 530 220n
+preplace netloc dec_4_fir_M_AXIS_DATA 1 3 1 N 280
+preplace netloc axis_broadcaster_1_M01_AXIS 1 4 1 N 310
+preplace netloc dec_8_fir_M_AXIS_DATA 1 5 1 N 330
+preplace netloc axis_broadcaster_2_M01_AXIS 1 6 1 N 360
+preplace netloc axis_broadcaster_0_M00_AXIS 1 2 6 N 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ
+preplace netloc axis_broadcaster_1_M00_AXIS 1 4 4 1150 60 NJ 60 NJ 60 NJ
+preplace netloc axis_broadcaster_2_M00_AXIS 1 6 2 1770 520 NJ
+preplace netloc dec_16_fir_M_AXIS_DATA 1 7 1 N 380
+preplace netloc dec_2_width_M_AXIS 1 8 1 NJ 220
+preplace netloc dec_4_width_M_AXIS 1 8 1 NJ 80
+preplace netloc dec_8_width_M_AXIS 1 8 1 NJ 540
+preplace netloc dec_16_width_M_AXIS 1 8 1 NJ 400
+preplace netloc in_i_1 1 0 1 NJ 170
+levelinfo -pg 1 -100 70 370 690 1000 1320 1620 1940 2200 2330
+pagesize -pg 1 -db -bbox -sgen -180 0 2450 620
+"
+}
+
diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v b/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v
index 5fef4c9..592f968 100755
--- a/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v
@@ -7,6 +7,7 @@ module digital_rx_chain #
     parameter CTRL_REG_ADDR = 32'h00000000,
     parameter NUM_SAMPLES_REG_ADDR = 32'h00000004,
     parameter START_SAMPLE_REG_ADDR = 32'h00000008,
+    parameter DEC_SELECT_REG_ADDR = 32'h0000000C,
     
     parameter integer AXI_ADDR_WIDTH	= 32,
     parameter integer AXI_DATA_WIDTH	= 32,
@@ -34,6 +35,8 @@ module digital_rx_chain #
 reg        out_tvalid_r;
 wire       out_tlast_r;
 wire       out_tstart_r;
+reg [63:0] out_tdata_i_r;
+reg [63:0] out_tdata_q_r;
 
 // ------------------------------
 // Register Inputs for timing
@@ -45,8 +48,19 @@ reg [JESD_DATA_WIDTH-1:0] in_tdata_q_reg;
 always @ (posedge clk) begin
     in_tstart_reg <= start_of_pulse;
     in_tvalid_reg <= in_tvalid;
-    in_tdata_i_reg <= in_tdata_i;
-    in_tdata_q_reg <= in_tdata_q;
+//    in_tdata_i_reg <= in_tdata_i;
+//    in_tdata_q_reg <= in_tdata_q;
+
+    in_tdata_i_reg[15:0]     = in_tdata_i[63:48];
+    in_tdata_i_reg[31:16]    = in_tdata_i[47:32];
+    in_tdata_i_reg[47:32]    = in_tdata_i[31:16];
+    in_tdata_i_reg[63:48]    = in_tdata_i[15:0];
+    
+    in_tdata_q_reg[15:0]     = in_tdata_q[63:48];
+    in_tdata_q_reg[31:16]    = in_tdata_q[47:32];
+    in_tdata_q_reg[47:32]    = in_tdata_q[31:16];
+    in_tdata_q_reg[63:48]    = in_tdata_q[15:0];   
+    
 end
 
 
@@ -105,6 +119,7 @@ wire reset;
 reg [31:0]  reg_ctrl;
 reg [15:0]  reg_num_samples;
 reg [27:0]  reg_start_sample;
+reg [3:0]   reg_dec_select;
 
 always @ (posedge ctrl_if.clk) begin
     if (~ctrl_if.resetn) begin
@@ -130,6 +145,14 @@ always @ (posedge ctrl_if.clk) begin
     end
 end
 
+always @ (posedge ctrl_if.clk) begin
+    if (~ctrl_if.resetn) begin
+        reg_dec_select <= 0;
+    end else if (wren && waddr[11:0] == DEC_SELECT_REG_ADDR) begin
+        reg_dec_select <= wdata;
+    end
+end
+
 always @ (posedge ctrl_if.clk) begin
     if (rden) begin
         if ( raddr[11:0] == CTRL_REG_ADDR ) 
@@ -138,6 +161,8 @@ always @ (posedge ctrl_if.clk) begin
             rdata <= reg_num_samples;   
         if ( raddr[11:0] == START_SAMPLE_REG_ADDR ) 
             rdata <= reg_start_sample;   
+        if ( raddr[11:0] == DEC_SELECT_REG_ADDR ) 
+            rdata <= reg_dec_select;               
     end      
 end
 
@@ -167,6 +192,7 @@ reg pulse_active;
 reg pulse_active_q;
 reg pulse_active_fed;
 reg pulse_active_fed_q;
+reg pulse_active_fed_stretch;
 
 // Delay event pulse by start sample
 reg [27:0] start_sample_cnt;
@@ -200,6 +226,9 @@ always @ (posedge clk) begin
     end
 end
 
+// Reset for filters after pulse
+assign pulse_active_fed_stretch = pulse_active_fed || pulse_active_fed_q;
+
 always @ (posedge clk) begin
     if (reset == 1'b1) begin
         sample_cnt <= 0;
@@ -231,7 +260,157 @@ end
 
 assign out_tlast_r = ((sample_cnt == reg_num_samples-1) && out_tvalid_r) ? 1'b1 : 1'b0;
 assign out_tstart_r = ((sample_cnt == 0) && out_tvalid_r) ? 1'b1 : 1'b0;
-assign out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
+//assign out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
+
+
+// ------------------------------
+// Decimation
+// ------------------------------
+wire         dec_by_2_tvalid_i;
+wire         dec_by_2_tvalid_q;
+wire  [95:0] dec_by_2_tdata_i;
+wire  [95:0] dec_by_2_tdata_q;
+wire  [63:0] dec_by_2_tdata_i_slice;
+wire  [63:0] dec_by_2_tdata_q_slice;
+
+wire         dec_by_4_tvalid_i;
+wire         dec_by_4_tvalid_q;
+wire  [95:0] dec_by_4_tdata_i;
+wire  [95:0] dec_by_4_tdata_q;
+wire  [63:0] dec_by_4_tdata_i_slice;
+wire  [63:0] dec_by_4_tdata_q_slice;
+
+wire         dec_by_8_tvalid_i;
+wire         dec_by_8_tvalid_q;
+wire  [95:0] dec_by_8_tdata_i;
+wire  [95:0] dec_by_8_tdata_q;
+wire  [63:0] dec_by_8_tdata_i_slice;
+wire  [63:0] dec_by_8_tdata_q_slice;
+
+wire         dec_by_16_tvalid_i;
+wire         dec_by_16_tvalid_q;
+wire  [95:0] dec_by_16_tdata_i;
+wire  [95:0] dec_by_16_tdata_q;
+wire  [63:0] dec_by_16_tdata_i_slice;
+wire  [63:0] dec_by_16_tdata_q_slice;
+
+wire dec_in_valid;
+
+
+assign dec_in_valid = in_tvalid_reg && (pulse_active || delay_active_fed);
+
+
+decimation_bd decimation_bd_i
+   (.rstn(~pulse_active_fed_stretch),
+    .clk(clk),
+    .in_i_tdata(in_tdata_i_reg),
+    .in_i_tready(),
+    .in_i_tvalid(dec_in_valid),
+    .dec_by_2_tdata(dec_by_2_tdata_i),
+    .dec_by_2_tvalid(dec_by_2_tvalid_i),
+    .dec_by_2_tready(1'b1),
+    .dec_by_4_tdata(dec_by_4_tdata_i),
+    .dec_by_4_tvalid(dec_by_4_tvalid_i),
+    .dec_by_4_tready(1'b1),
+    .dec_by_8_tdata(dec_by_8_tdata_i),
+    .dec_by_8_tvalid(dec_by_8_tvalid_i),
+    .dec_by_8_tready(1'b1),
+    .dec_by_16_tdata(dec_by_16_tdata_i),
+    .dec_by_16_tvalid(dec_by_16_tvalid_i),
+    .dec_by_16_tready(1'b1)        
+    );
+
+decimation_bd decimation_bd_q
+   (.rstn(~pulse_active_fed_stretch),
+    .clk(clk),
+    .in_i_tdata(in_tdata_q_reg),
+    .in_i_tready(),
+    .in_i_tvalid(dec_in_valid),
+    .dec_by_2_tdata(dec_by_2_tdata_q),
+    .dec_by_2_tvalid(dec_by_2_tvalid_q),
+    .dec_by_2_tready(1'b1),
+    .dec_by_4_tdata(dec_by_4_tdata_q),
+    .dec_by_4_tvalid(dec_by_4_tvalid_q),
+    .dec_by_4_tready(1'b1),
+    .dec_by_8_tdata(dec_by_8_tdata_q),
+    .dec_by_8_tvalid(dec_by_8_tvalid_q),
+    .dec_by_8_tready(1'b1),
+    .dec_by_16_tdata(dec_by_16_tdata_q),
+    .dec_by_16_tvalid(dec_by_16_tvalid_q),
+    .dec_by_16_tready(1'b1)
+    );    
+
+assign dec_by_2_tdata_i_slice[15:0]  = dec_by_2_tdata_i[15:0];
+assign dec_by_2_tdata_i_slice[31:16] = dec_by_2_tdata_i[39:24];
+assign dec_by_2_tdata_i_slice[47:32] = dec_by_2_tdata_i[63:48];
+assign dec_by_2_tdata_i_slice[63:48] = dec_by_2_tdata_i[87:72];
+assign dec_by_2_tdata_q_slice[15:0]  = dec_by_2_tdata_q[15:0];
+assign dec_by_2_tdata_q_slice[31:16] = dec_by_2_tdata_q[39:24];
+assign dec_by_2_tdata_q_slice[47:32] = dec_by_2_tdata_q[63:48];
+assign dec_by_2_tdata_q_slice[63:48] = dec_by_2_tdata_q[87:72];
+
+assign dec_by_4_tdata_i_slice[15:0]  = dec_by_4_tdata_i[15:0];
+assign dec_by_4_tdata_i_slice[31:16] = dec_by_4_tdata_i[39:24];
+assign dec_by_4_tdata_i_slice[47:32] = dec_by_4_tdata_i[63:48];
+assign dec_by_4_tdata_i_slice[63:48] = dec_by_4_tdata_i[87:72];
+assign dec_by_4_tdata_q_slice[15:0]  = dec_by_4_tdata_q[15:0];
+assign dec_by_4_tdata_q_slice[31:16] = dec_by_4_tdata_q[39:24];
+assign dec_by_4_tdata_q_slice[47:32] = dec_by_4_tdata_q[63:48];
+assign dec_by_4_tdata_q_slice[63:48] = dec_by_4_tdata_q[87:72];
+
+assign dec_by_8_tdata_i_slice[15:0]  = dec_by_8_tdata_i[15:0];
+assign dec_by_8_tdata_i_slice[31:16] = dec_by_8_tdata_i[39:24];
+assign dec_by_8_tdata_i_slice[47:32] = dec_by_8_tdata_i[63:48];
+assign dec_by_8_tdata_i_slice[63:48] = dec_by_8_tdata_i[87:72];
+assign dec_by_8_tdata_q_slice[15:0]  = dec_by_8_tdata_q[15:0];
+assign dec_by_8_tdata_q_slice[31:16] = dec_by_8_tdata_q[39:24];
+assign dec_by_8_tdata_q_slice[47:32] = dec_by_8_tdata_q[63:48];
+assign dec_by_8_tdata_q_slice[63:48] = dec_by_8_tdata_q[87:72];
+
+assign dec_by_16_tdata_i_slice[15:0]  = dec_by_16_tdata_i[15:0];
+assign dec_by_16_tdata_i_slice[31:16] = dec_by_16_tdata_i[39:24];
+assign dec_by_16_tdata_i_slice[47:32] = dec_by_16_tdata_i[63:48];
+assign dec_by_16_tdata_i_slice[63:48] = dec_by_16_tdata_i[87:72];
+assign dec_by_16_tdata_q_slice[15:0]  = dec_by_16_tdata_q[15:0];
+assign dec_by_16_tdata_q_slice[31:16] = dec_by_16_tdata_q[39:24];
+assign dec_by_16_tdata_q_slice[47:32] = dec_by_16_tdata_q[63:48];
+assign dec_by_16_tdata_q_slice[63:48] = dec_by_16_tdata_q[87:72];
+
+// ------------------------------
+// Decimation Selection
+// ------------------------------
+always @ * begin
+    case(reg_dec_select)
+        4'b000  : out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
+        4'b001  : out_tvalid_r = dec_by_2_tvalid_i;
+        4'b010  : out_tvalid_r = dec_by_4_tvalid_i;
+        4'b011  : out_tvalid_r = dec_by_8_tvalid_i;
+        4'b100  : out_tvalid_r = dec_by_16_tvalid_i;
+        default : out_tvalid_r = 1'b0;
+    endcase
+end
+
+always @ * begin
+    case(reg_dec_select)
+        4'b000  : out_tdata_i_r = in_tdata_i_reg;
+        4'b001  : out_tdata_i_r = dec_by_2_tdata_i_slice;
+        4'b010  : out_tdata_i_r = dec_by_4_tdata_i_slice;
+        4'b011  : out_tdata_i_r = dec_by_8_tdata_i_slice;
+        4'b100  : out_tdata_i_r = dec_by_16_tdata_i_slice;
+        default : out_tdata_i_r = 1'b0;
+    endcase
+end
+
+always @ * begin
+    case(reg_dec_select)
+        4'b000  : out_tdata_q_r = in_tdata_q_reg;
+        4'b001  : out_tdata_q_r = dec_by_2_tdata_q_slice;
+        4'b010  : out_tdata_q_r = dec_by_4_tdata_q_slice;
+        4'b011  : out_tdata_q_r = dec_by_8_tdata_q_slice;
+        4'b100  : out_tdata_q_r = dec_by_16_tdata_q_slice;
+        default : out_tdata_q_r = 1'b0;
+    endcase
+end
 
 // ------------------------------
 // Buffer
@@ -267,15 +446,25 @@ assign axis_odec_out.tvalid = out_tvalid_r && (pulse_active || delay_active_fed)
 assign axis_odec_out.tlast = out_tlast_r;
 assign axis_odec_out.tuser = out_tstart_r;
 
+assign axis_odec_out.tdata[15:0]     = out_tdata_i_r[15:0];
+assign axis_odec_out.tdata[31:16]    = out_tdata_q_r[15:0];
+assign axis_odec_out.tdata[47:32]    = out_tdata_i_r[31:16];
+assign axis_odec_out.tdata[63:48]    = out_tdata_q_r[31:16];
+assign axis_odec_out.tdata[79:64]    = out_tdata_i_r[47:32];
+assign axis_odec_out.tdata[95:80]    = out_tdata_q_r[47:32];
+assign axis_odec_out.tdata[111:96]   = out_tdata_i_r[63:48];
+assign axis_odec_out.tdata[127:112]  = out_tdata_q_r[63:48];         
+
+//assign axis_odec_out.tdata[15:0]     = in_tdata_i_reg[63:48];
+//assign axis_odec_out.tdata[31:16]    = in_tdata_q_reg[63:48];
+//assign axis_odec_out.tdata[47:32]    = in_tdata_i_reg[47:32];
+//assign axis_odec_out.tdata[63:48]    = in_tdata_q_reg[47:32];
+//assign axis_odec_out.tdata[79:64]    = in_tdata_i_reg[31:16];
+//assign axis_odec_out.tdata[95:80]    = in_tdata_q_reg[31:16];
+//assign axis_odec_out.tdata[111:96]   = in_tdata_i_reg[15:0];
+//assign axis_odec_out.tdata[127:112]  = in_tdata_q_reg[15:0];     
+
 //204C
-assign axis_odec_out.tdata[15:0]     = in_tdata_i_reg[63:48];
-assign axis_odec_out.tdata[31:16]    = in_tdata_q_reg[63:48];
-assign axis_odec_out.tdata[47:32]    = in_tdata_i_reg[47:32];
-assign axis_odec_out.tdata[63:48]    = in_tdata_q_reg[47:32];
-assign axis_odec_out.tdata[79:64]    = in_tdata_i_reg[31:16];
-assign axis_odec_out.tdata[95:80]    = in_tdata_q_reg[31:16];
-assign axis_odec_out.tdata[111:96]   = in_tdata_i_reg[15:0];
-assign axis_odec_out.tdata[127:112]  = in_tdata_q_reg[15:0];     
 
 pulse_buffer_fifo pulse_buffer_fifo_i (
    .s_axis_aresetn(~reset), 
diff --git a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
index 1e55273..0e7e187 100755
Binary files a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp and b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp differ
diff --git a/radar_alinx_kintex.xpr b/radar_alinx_kintex.xpr
index 4777b4d..cd0e3a1 100755
--- a/radar_alinx_kintex.xpr
+++ b/radar_alinx_kintex.xpr
@@ -63,13 +63,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="48"/>
-    <Option Name="WTModelSimExportSim" Val="48"/>
-    <Option Name="WTQuestaExportSim" Val="48"/>
+    <Option Name="WTXSimExportSim" Val="50"/>
+    <Option Name="WTModelSimExportSim" Val="50"/>
+    <Option Name="WTQuestaExportSim" Val="50"/>
     <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="48"/>
-    <Option Name="WTRivieraExportSim" Val="48"/>
-    <Option Name="WTActivehdlExportSim" Val="48"/>
+    <Option Name="WTVcsExportSim" Val="50"/>
+    <Option Name="WTRivieraExportSim" Val="50"/>
+    <Option Name="WTActivehdlExportSim" Val="50"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -746,6 +746,20 @@
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
+    <FileSet Name="decimation_bd" Type="BlockSrcs" RelSrcDir="$PSRCDIR/decimation_bd" RelGenDir="$PGENDIR/decimation_bd">
+      <File Path="$PSRCDIR/sources_1/bd/decimation_bd/decimation_bd.bd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="decimation_bd"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -901,6 +915,18 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="decimation_bd_synth_1" Type="Ft3:Synth" SrcSet="decimation_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="decimation_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/decimation_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
@@ -1125,6 +1151,25 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="decimation_bd_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="decimation_bd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="decimation_bd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/decimation_bd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/decimation_bd_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
   </Runs>
   <MsgRule>
     <MsgAttr Name="RuleType" Val="0"/>
diff --git a/vitis/radar/radar.prj b/vitis/radar/radar.prj
index fe1b1a7..06d9c01 100755
--- a/vitis/radar/radar.prj
+++ b/vitis/radar/radar.prj
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="ASCII"?>
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diff --git a/vitis/radar_system/_ide/flash/radar.elf.srec b/vitis/radar_system/_ide/flash/radar.elf.srec
index 7bc4840..aa48bef 100755
--- a/vitis/radar_system/_ide/flash/radar.elf.srec
+++ b/vitis/radar_system/_ide/flash/radar.elf.srec
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diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h
index 864f4b5..6415623 100644
--- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h
+++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h
@@ -496,8 +496,8 @@
 #define PLATFORM_MB
  
 /******************************************************************/
-#define STDIN_BASEADDRESS 0x41400000
-#define STDOUT_BASEADDRESS 0x41400000
+#define STDIN_BASEADDRESS 0x40000000
+#define STDOUT_BASEADDRESS 0x40000000
 
 /******************************************************************/
 
diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a
index 478417c..8b470ba 100644
Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a differ
diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a
index 29ba479..3510983 100644
Binary files a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a and b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a differ
diff --git a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss
index 14165d1..55fe265 100644
--- a/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss
+++ b/vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss
@@ -6,8 +6,8 @@ BEGIN OS
  PARAMETER OS_NAME = freertos10_xilinx
  PARAMETER OS_VER = 1.12
  PARAMETER PROC_INSTANCE = microblaze_0
- PARAMETER stdin = mdm_1
- PARAMETER stdout = mdm_1
+ PARAMETER stdin = axi_uartlite_0
+ PARAMETER stdout = axi_uartlite_0
  PARAMETER total_heap_size = 2097152
 END
 
diff --git a/vitis/top/platform.spr b/vitis/top/platform.spr
index c14efcb..5f3a325 100755
--- a/vitis/top/platform.spr
+++ b/vitis/top/platform.spr
@@ -1 +1 @@
-{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
+{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
diff --git a/vitis/top/platform.tcl b/vitis/top/platform.tcl
index 5e08fe3..ec8c4cf 100755
--- a/vitis/top/platform.tcl
+++ b/vitis/top/platform.tcl
@@ -107,3 +107,24 @@ bsp reload
 catch {bsp regenerate}
 platform generate -domains freertos10_xilinx_microblaze_0 
 bsp reload
+bsp reload
+bsp config stdin "axi_uartlite_0"
+bsp config stdout "axi_uartlite_0"
+bsp write
+bsp reload
+catch {bsp regenerate}
+platform generate -domains freertos10_xilinx_microblaze_0 
+platform active {top}
+bsp reload
+bsp config stdin "mdm_1"
+bsp config stdout "mdm_1"
+bsp write
+bsp reload
+catch {bsp regenerate}
+platform generate -domains freertos10_xilinx_microblaze_0 
+bsp config stdin "axi_uartlite_0"
+bsp config stdout "axi_uartlite_0"
+bsp write
+bsp reload
+catch {bsp regenerate}
+platform generate -domains freertos10_xilinx_microblaze_0