diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv b/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv index 1ac93ad..214981d 100644 --- a/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv +++ b/radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv @@ -3,22 +3,41 @@ `default_nettype none module delay_shift_register #( - parameter DELAY_CYCLES = 4 + parameter DELAY_CYCLES = 4 , + parameter DATA_WIDTH = 1 ) ( input wire clk, input wire reset, - input wire data_in, - output wire data_out + input wire [DATA_WIDTH-1:0] data_in, + output wire [DATA_WIDTH-1:0] data_out ); + // // Declare a register to hold the shifted data + // reg [DELAY_CYCLES-1:0] shift_reg; + + // always @ (posedge clk) begin + // if (reset) begin + // shift_reg <= '0; + // end else begin + // shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in}; + // end + // end + + // assign data_out = shift_reg[DELAY_CYCLES-1]; + // Declare a register to hold the shifted data - reg [DELAY_CYCLES-1:0] shift_reg; + reg [DATA_WIDTH-1:0] shift_reg [DELAY_CYCLES]; always @ (posedge clk) begin if (reset) begin - shift_reg <= '0; + for (int i = 0; i < DELAY_CYCLES; i = i + 1) begin + shift_reg[i] <= 0; + end end else begin - shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in}; + for (int i = DELAY_CYCLES-1; i > 0; i = i - 1) begin + shift_reg[i] <= shift_reg[i-1]; // Shift right + end + shift_reg[0] <= data_in; end end diff --git a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv index 2973495..76544b4 100644 --- a/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv +++ b/radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv @@ -321,7 +321,7 @@ end wire [47:0] mult_out; wire [31:0] chip_delta_freq; -ofdm_freq_mult freq_mult ( +freq_mult freq_mult ( .CLK(clk), .A(reg_delta_freq), .B(read_sequence), @@ -340,9 +340,20 @@ end assign set_phase = (chip_cnt == 0) ? pulse_active : 1'b0; +wire [15:0] read_phase_delayed; +delay_shift_register # ( + .DELAY_CYCLES(6), + .DATA_WIDTH(16) +) delay_phase ( + .clk(clk), + .reset(reset), + .data_in(read_phase), + .data_out(read_phase_delayed) +); + wire pulse_active_delayed; delay_shift_register # ( - .DELAY_CYCLES(4) + .DELAY_CYCLES(8) ) delay_valid ( .clk(clk), .reset(reset), @@ -352,7 +363,7 @@ delay_shift_register # ( wire set_phase_delayed; delay_shift_register # ( - .DELAY_CYCLES(4) + .DELAY_CYCLES(8) ) delay_set_phase ( .clk(clk), .reset(reset), @@ -366,7 +377,8 @@ gen_sine gen_sine_i ( .reset(reset), .set_phase(set_phase_delayed), .valid(pulse_active_delayed), - .phase({read_phase_q2, 16'h0000}), + // .phase({read_phase_q2, 16'h0000}), + .phase({read_phase_delayed, 16'h0000}), .frequency(chip_freq), .iq_out(iq_out), .iq_out_valid(iq_out_valid) diff --git a/radar_alinx_kintex.srcs/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci b/radar_alinx_kintex.srcs/sources_1/ip/freq_mult/freq_mult.xci similarity index 94% rename from radar_alinx_kintex.srcs/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci rename to radar_alinx_kintex.srcs/sources_1/ip/freq_mult/freq_mult.xci index 825027b..ae3a800 100644 --- a/radar_alinx_kintex.srcs/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci +++ b/radar_alinx_kintex.srcs/sources_1/ip/freq_mult/freq_mult.xci @@ -1,14 +1,14 @@ { "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { - "xci_name": "ofdm_freq_mult", + "xci_name": "freq_mult", "component_reference": "xilinx.com:ip:mult_gen:12.0", "ip_revision": "18", - "gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/ofdm_freq_mult", + "gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/freq_mult", "parameters": { "component_parameters": { "InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Component_Name": [ { "value": "ofdm_freq_mult", "resolve_type": "user", "usage": "all" } ], + "Component_Name": [ { "value": "freq_mult", "resolve_type": "user", "usage": "all" } ], "MultType": [ { "value": "Parallel_Multiplier", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ], "PortAWidth": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -16,14 +16,14 @@ "PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ], "CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ], - "Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Multiplier_Construction": [ { "value": "Use_LUTs", "resolve_type": "user", "usage": "all" } ], "OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ], "Use_Custom_Output_Width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "OutputWidthHigh": [ { "value": "47", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "OutputWidthLow": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], - "PipeStages": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PipeStages": [ { "value": "5", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "ClockEnable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "SyncClear": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -36,14 +36,14 @@ "C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ], "C_HAS_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_LATENCY": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_A_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_B_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_OUT_HIGH": [ { "value": "47", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_OUT_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ], @@ -70,7 +70,7 @@ "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/ofdm_freq_mult" } ], + "OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/freq_mult" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv b/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv index 4b309f6..6e3b61c 100644 --- a/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv +++ b/radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv @@ -114,10 +114,10 @@ initial begin end // Load Start Phases - // vip_mst.AXI4LITE_WRITE_BURST(16'h0020, 0, 0, resp); // Set Start Address - // for (int i = 0; i < 8; i = i + 1) begin - // vip_mst.AXI4LITE_WRITE_BURST(16'h0024, 0, i, resp); // Load Chirp Sequence - // end + vip_mst.AXI4LITE_WRITE_BURST(16'h0020, 0, 0, resp); // Set Start Address + for (int i = 0; i < 8; i = i + 1) begin + vip_mst.AXI4LITE_WRITE_BURST(16'h0024, 0, i, resp); // Load Chirp Sequence + end for (int i = 0; i < n_pulses; i = i + 1) begin diff --git a/radar_alinx_kintex.xpr b/radar_alinx_kintex.xpr index a678364..102c8f6 100755 --- a/radar_alinx_kintex.xpr +++ b/radar_alinx_kintex.xpr @@ -56,20 +56,20 @@