interface axi4_intf#(
      // Width of S_AXI address araddr 
      parameter integer AXI_ADDR_WIDTH	= 32,
      // Width of S_AXI data bus
      parameter integer AXI_DATA_WIDTH	= 32

	) (
	   input wire clk,
	   input wire resetn
	);
   
   logic [(AXI_ADDR_WIDTH-1):0] araddr;
   logic [ 1:0] arburst;
   logic [ 3:0] arcache;
   logic [ 7:0] arlen;
   logic arlock;
   logic [ 2:0] arprot;
   logic [ 3:0] arqos;
   logic arready;
   logic [ 2:0] arsize;
   logic arvalid;
   
   logic [(AXI_ADDR_WIDTH-1):0] awaddr;
   logic [ 1:0] awburst;
   logic [ 3:0] awcache;
   logic [ 7:0] awlen;
   logic awlock;
   logic [ 2:0] awprot;
   logic [ 3:0] awqos;
   logic awready;
   logic [ 2:0] awsize;
   logic awvalid;
   
   logic bready;
   logic [1:0] bresp;
   logic bvalid;
   
   logic [(AXI_DATA_WIDTH-1):0] rdata;
   logic rlast;
   logic rready;
   logic [1:0] rresp;
   logic  rvalid;
   
   logic [(AXI_DATA_WIDTH-1):0] wdata;
   logic wlast;
   logic wready;
   logic [((AXI_DATA_WIDTH/8)-1):0] wstrb;
   logic wvalid;
 
modport  master (
   input clk,
   input resetn,
  
   output araddr,
   output arburst,
   output arcache,
   output arlen,
   output arlock,
   output arprot,
   output arqos,
   input arready,
   output arsize,
   output arvalid,

   output awaddr,
   output awburst,
   output awcache,
   output awlen,
   output awlock,
   output awprot,
   output awqos,
   input awready,
   output awsize,
   output awvalid,
   
   output bready,
   input bresp,
   input bvalid,
   
   input rdata,
   input rlast,
   output rready,
   input rresp,
   input rvalid,
   
   output wdata,
   output wlast,
   input wready,
   output wstrb,
   output wvalid);     

modport  slave (
   input clk,
   input resetn,
   
   input araddr,
   input arburst,
   input arcache,
   input arlen,
   input arlock,
   input arprot,
   input arqos,
   output arready,
   input arsize,
   input arvalid,

   input awaddr,
   input awburst,
   input awcache,
   input awlen,
   input awlock,
   input awprot,
   input awqos,
   output awready,
   input awsize,
   input awvalid,
   
   input bready,
   output bresp,
   output bvalid,
   
   output rdata,
   output rlast,
   input rready,
   output rresp,
   output rvalid,
   
   input wdata,
   input wlast,
   output wready,
   input wstrb,
   input wvalid);   

endinterface


interface axi4l_intf#(
      // Width of S_AXI address araddr 
      parameter integer AXI_ADDR_WIDTH	= 32,
      // Width of S_AXI data bus
      parameter integer AXI_DATA_WIDTH	= 32

	) (
	   input wire clk,
	   input wire resetn
	);

   logic [(AXI_ADDR_WIDTH-1):0] araddr;
   logic [2:0] arprot;
   logic arready;
   logic arvalid;
   
   logic [(AXI_ADDR_WIDTH-1):0] awaddr;
   logic [2:0] awprot;
   logic awready;
   logic awvalid;
   
   logic bready;
   logic [1:0] bresp;
   logic bvalid;
   
   logic [(AXI_DATA_WIDTH-1):0] rdata;
   logic rready;
   logic [1:0] rresp;
   logic  rvalid;
   
   logic [(AXI_DATA_WIDTH-1):0] wdata;
   logic wready;
   logic [((AXI_DATA_WIDTH/8)-1):0] wstrb;
   logic wvalid;
 
modport  master (
   input clk,
   input resetn,
   
   output araddr,
   output arprot,
   input arready,
   output arvalid,
   
   output awaddr,
   output awprot,
   input awready,
   output awvalid,
   
   output bready,
   input bresp,
   input bvalid,
   
   input rdata,
   output rready,
   input rresp,
   input rvalid,
   
   output wdata,
   input wready,
   output wstrb,
   output wvalid);     

modport  slave (
   input clk,
   input resetn,
   
   input araddr,
   input arprot,
   output arready,
   input arvalid,
   
   input awaddr,
   input awprot,
   output awready,
   input awvalid,
   
   input bready,
   output bresp,
   output bvalid,
   
   output rdata,
   input rready,
   output rresp,
   output rvalid,
   
   input wdata,
   output wready,
   input wstrb,
   input wvalid);   

endinterface

interface axi4s_intf#(
      // Width of S_AXI data bus
      parameter integer AXI_DATA_WIDTH	= 32,
      parameter integer AXI_ID_WIDTH	= 4,
      parameter integer AXI_DEST_WIDTH	= 4,
      parameter integer AXI_USER_WIDTH	= 4

	) (
	   input wire clk,
	   input wire resetn
	);
      
   logic [(AXI_DATA_WIDTH-1):0] tdata;
   logic tready;
   logic [((AXI_DATA_WIDTH/8)-1):0] tstrb;
   logic [((AXI_DATA_WIDTH/8)-1):0] tkeep;
   logic tvalid;
   logic tlast;
   logic [(AXI_ID_WIDTH-1):0] tid;
   logic [(AXI_DEST_WIDTH-1):0] tdest;
   logic [(AXI_USER_WIDTH-1):0] tuser;
 
modport  master (
   input clk,
   input resetn,
   
   output tdata,
   input tready,
   output tstrb,
   output tkeep,
   output tvalid,
   output tlast,
   output tid,
   output tdest,
   output tuser);     

modport  slave (
   input clk,
   input resetn,
   
   input tdata,
   output tready,
   input tstrb,
   input tkeep,
   input tvalid,
   input tlast,
   input tid,
   input tdest,
   input tuser);     


endinterface