`resetall
`timescale 1ns / 1ps
`default_nettype none

module pulse_generator #
(
    parameter integer COUNTER_BITS	= 28
)
(
    input  wire                     clk,
    input  wire                     rst,
    input  wire [COUNTER_BITS-1:0]  pulse_length,
    input  wire                     start_of_pulse,
    output wire                     pulse_out,
    output wire                     pulse_tlast
);

reg [COUNTER_BITS-1:0]  pulse_cnt;
reg pulse_active;

assign pulse_out = pulse_active;

assign pulse_tlast = (pulse_cnt == 0) ? pulse_active : 0;

always @ (posedge clk) begin
    if (rst == 1'b1) begin
        pulse_cnt <= 0;
        pulse_active <= 0;
    end else begin
        if (start_of_pulse) begin
            pulse_active <= 1;
            pulse_cnt <= pulse_length;
        end

        if (pulse_active) begin
            pulse_cnt <= pulse_cnt - 1;
            if (pulse_cnt == 0) begin
                pulse_active <= 0;
            end
        end

    end
end


endmodule


`resetall