{
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    "cell_name": "axi_timer_0",
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    "ip_revision": "29",
    "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_timer_0_0",
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        "TRIG1_ASSERT": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
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        "GEN1_ASSERT": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
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        "C_S_AXI_ADDR_WIDTH": [ { "value": "5", "format": "long", "usage": "all" } ]
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      "project_parameters": {
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        "BASE_BOARD_PART": [ { "value": "" } ],
        "BOARD_CONNECTIONS": [ { "value": "" } ],
        "DEVICE": [ { "value": "xczu7ev" } ],
        "PACKAGE": [ { "value": "ffvc1156" } ],
        "PREFHDL": [ { "value": "VERILOG" } ],
        "SILICON_REVISION": [ { "value": "" } ],
        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
        "SPEEDGRADE": [ { "value": "-2" } ],
        "STATIC_POWER": [ { "value": "" } ],
        "TEMPERATURE_GRADE": [ { "value": "I" } ],
        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
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      "runtime_parameters": {
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        "IPREVISION": [ { "value": "29" } ],
        "MANAGED": [ { "value": "TRUE" } ],
        "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_timer_0_0" } ],
        "SELECTEDSIMMODEL": [ { "value": "" } ],
        "SHAREDDIR": [ { "value": "../../ipshared" } ],
        "SWVERSION": [ { "value": "2022.2" } ],
        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
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    "boundary": {
      "ports": {
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        "capturetrig1": [ { "direction": "in", "driver_value": "0" } ],
        "generateout0": [ { "direction": "out" } ],
        "generateout1": [ { "direction": "out" } ],
        "pwm0": [ { "direction": "out" } ],
        "interrupt": [ { "direction": "out" } ],
        "freeze": [ { "direction": "in", "driver_value": "0" } ],
        "s_axi_aclk": [ { "direction": "in" } ],
        "s_axi_aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
        "s_axi_awaddr": [ { "direction": "in", "size_left": "4", "size_right": "0" } ],
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        "s_axi_awready": [ { "direction": "out" } ],
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        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
        "s_axi_rvalid": [ { "direction": "out" } ],
        "s_axi_rready": [ { "direction": "in" } ]
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      "interfaces": {
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          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
            "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
            "BREADY": [ { "physical_name": "s_axi_bready" } ],
            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
            "RREADY": [ { "physical_name": "s_axi_rready" } ],
            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
            "WREADY": [ { "physical_name": "s_axi_wready" } ],
            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
            "WVALID": [ { "physical_name": "s_axi_wvalid" } ]
          }
        },
        "S_AXI_ACLK": {
          "vlnv": "xilinx.com:signal:clock:1.0",
          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
            "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "CLK": [ { "physical_name": "s_axi_aclk" } ]
          }
        },
        "S_AXI_RST": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "s_axi_aresetn" } ]
          }
        },
        "INTERRUPT": {
          "vlnv": "xilinx.com:signal:interrupt:1.0",
          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
          "mode": "master",
          "parameters": {
            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "INTERRUPT": [ { "physical_name": "interrupt" } ]
          }
        }
      },
      "memory_maps": {
        "S_AXI": {
          "display_name": "S_AXI_MEM",
          "description": "Memory Map for S_AXI",
          "address_blocks": {
            "Reg": {
              "base_address": "0",
              "range": "512",
              "display_name": "Reg",
              "description": "Register Block",
              "usage": "register",
              "access": "read-write",
              "registers": {
                "TCSR0": {
                  "address_offset": "0x0",
                  "size": 32,
                  "display_name": "Timer 0 Control and Status Register",
                  "description": "Timer 0 Control and Status Register",
                  "is_volatile": true,
                  "access": "read-write",
                  "reset_value": "0x0",
                  "fields": {
                    "MDT0": {
                      "bit_offset": 0,
                      "bit_width": 1,
                      "display_name": "Timer 0 Mode",
                      "description": "Timer 0 Mode\n0 - Timer mode is generate\n1 - Timer mode is capture\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "UDT0": {
                      "bit_offset": 1,
                      "bit_width": 1,
                      "display_name": "Timer 0 Up/Down Count",
                      "description": "Up/Down Count Timer 0\n  0 - Timer functions as up counter\n  1 - Timer functions as down counter\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "GENT0": {
                      "bit_offset": 2,
                      "bit_width": 1,
                      "display_name": "Generate Signal Timer 0",
                      "description": "Enable External Generate Signal Timer 0\n  0 - Disables external generate signal\n  1 - Enables external generate signal\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "CAPT0": {
                      "bit_offset": 3,
                      "bit_width": 1,
                      "display_name": "Capture Trigger Timer 0",
                      "description": "Enable External Capture Trigger Timer 0\n  0 - Disables external capture trigger\n  1 - Enables external capture trigger\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ARHT0": {
                      "bit_offset": 4,
                      "bit_width": 1,
                      "display_name": "Auto Reload/Hold Timer 0",
                      "description": "Auto Reload/Hold Timer 0.\nWhen the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. \nIn Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.      0 = Hold counter or capture value. The TLR must be read before providing the external capture.      1 = Reload generate value or overwrite capture value\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "LOAD0": {
                      "bit_offset": 5,
                      "bit_width": 1,
                      "display_name": "Load Timer 0",
                      "description": "Load Timer 0      0 = No load      1 = Loads timer with value in TLR0 Setting this bit loads timer/counter register (TCR0) with a specified value in the timer/counter load register (TLR0).  This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT0) bit in TCSR0.\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ENIT0": {
                      "bit_offset": 6,
                      "bit_width": 1,
                      "display_name": "Enable Interrupt for Timer 0",
                      "description": "Enable Interrupt for Timer 0\nEnables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T0INT) in TCSR0.      0 - Disable interrupt signal   1 - Enable interrupt signal\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ENT0": {
                      "bit_offset": 7,
                      "bit_width": 1,
                      "display_name": "Enable Timer 0",
                      "description": "Enable Timer 0\n  0 - Disable timer (counter halts)\n  1 - Enable timer (counter runs)\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "T0INT": {
                      "bit_offset": 8,
                      "bit_width": 1,
                      "display_name": "Timer 0 Interrupt",
                      "description": "Timer 0 Interrupt\nIndicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.\nRead:      0 - No interrupt has occurred      1 - Interrupt has occurred  Write:      0 - No change in state of T0INT   1 - Clear T0INT (clear to 0)\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "PWMA0": {
                      "bit_offset": 9,
                      "bit_width": 1,
                      "display_name": "Pulse Width Modulation for Timer 0",
                      "description": "Enable Pulse Width Modulation for Timer 0      0 - Disable pulse width modulation      1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair.  Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0 and C_GEN0_ASSERT and C_GEN1_ASSERT must be 1.\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ENALL": {
                      "bit_offset": 10,
                      "bit_width": 1,
                      "display_name": "Enable All Timers",
                      "description": "Enable All Timers      0 - No effect on timers      1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. \nWriting a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. \n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "CASC": {
                      "bit_offset": 11,
                      "bit_width": 1,
                      "display_name": "Cascade Mode of Timers",
                      "description": "Enable cascade mode of timers      0 - Disable cascaded operation      1 - Enable cascaded operation Cascaded operation requires using Timer 0 and Timer 1 together as a pair.  The counting event for the Timer 1 is when the Timer 0 rolls over from all 1s to all 0s or vice-versa when counting down.\nTLR0 and TLR1 are used for lower 32-bit and higher 32-bit respectively. Similarly, TCR0 contains lower 32-bits for the 64-bit counter and TCR1 contains the higher 32-bits.\nOnly TCSR0 is valid for both the timer/counters in this mode.\nThis CASC bit must be set before enabling the timer/counter.\n",
                      "is_volatile": true,
                      "access": "read-write"
                    }
                  }
                },
                "TLR0": {
                  "address_offset": "0x4",
                  "size": 32,
                  "display_name": "Timer 0 Load Register",
                  "description": "Timer 0 Load Register",
                  "is_volatile": true,
                  "access": "read-write",
                  "reset_value": "0x0",
                  "fields": {
                    "TCLR0": {
                      "bit_offset": 0,
                      "bit_width": 32,
                      "display_name": "Timer/Counter Load Register",
                      "description": "Timer/Counter Load Register\n",
                      "is_volatile": true,
                      "access": "read-write"
                    }
                  }
                },
                "TCR0": {
                  "address_offset": "0x8",
                  "size": 32,
                  "display_name": "Timer 0 Counter Register",
                  "description": "Timer 0 Counter Register",
                  "is_volatile": true,
                  "access": "read-only",
                  "reset_value": "0x0",
                  "fields": {
                    "TCR0": {
                      "bit_offset": 0,
                      "bit_width": 32,
                      "display_name": "Timer/Counter Register",
                      "description": "Timer/Counter Register\n",
                      "is_volatile": true,
                      "access": "read-only"
                    }
                  }
                },
                "TCSR1": {
                  "address_offset": "0x10",
                  "size": 32,
                  "display_name": "Timer 1 Control and Status Register",
                  "description": "Timer 1 Control and Status Register",
                  "is_volatile": true,
                  "access": "read-write",
                  "reset_value": "0x0",
                  "fields": {
                    "MDT1": {
                      "bit_offset": 0,
                      "bit_width": 1,
                      "display_name": "Timer 1 Mode",
                      "description": "Timer 1 Mode\n  0 - Timer mode is generate\n  1 - Timer mode is capture\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "UDT1": {
                      "bit_offset": 1,
                      "bit_width": 1,
                      "display_name": "Timer 1 Up/Down Count",
                      "description": "Up/Down Count Timer 1\n  0 - Timer functions as up counter\n  1 - Timer functions as down counter\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "GENT1": {
                      "bit_offset": 2,
                      "bit_width": 1,
                      "display_name": "Generate Signal Timer 1",
                      "description": "Enable External Generate Signal Timer 1\n  0 - Disables external generate signal\n  1 - Enables external generate signal\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "CAPT1": {
                      "bit_offset": 3,
                      "bit_width": 1,
                      "display_name": "Capture Trigger Timer 1",
                      "description": "Enable External Capture Trigger Timer 1\n  0 - Disables external capture trigger\n  1 - Enables external capture trigger\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ARHT1": {
                      "bit_offset": 4,
                      "bit_width": 1,
                      "display_name": "Auto Reload/Hold Timer 1",
                      "description": "Auto Reload/Hold Timer 1.\nWhen the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. \nIn Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.\n0 = Hold counter or capture value. The TLR must be read before providing the external capture.   \n1 = Reload generate value or overwrite capture value\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "LOAD1": {
                      "bit_offset": 5,
                      "bit_width": 1,
                      "display_name": "Load Timer 1",
                      "description": "Load Timer 1      0 = No load      1 = Loads timer with value in TLR1 Setting this bit loads timer/counter register (TCR1) with a specified value in the timer/counter load register (TLR1).  This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT1) bit in TCSR1.\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ENIT1": {
                      "bit_offset": 6,
                      "bit_width": 1,
                      "display_name": "Enable Interrupt for Timer 1",
                      "description": "Enable Interrupt for Timer 1\nEnables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T1INT) in TCSR1.      0 - Disable interrupt signal      1 - Enable interrupt signal\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ENT1": {
                      "bit_offset": 7,
                      "bit_width": 1,
                      "display_name": "Enable Timer 1",
                      "description": "Enable Timer 1\n  0 - Disable timer (counter halts)\n  1 - Enable timer (counter runs)\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "T1INT": {
                      "bit_offset": 8,
                      "bit_width": 1,
                      "display_name": "Timer 1 Interrupt",
                      "description": "Timer 1 Interrupt\nIndicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.\nRead:      0 - No interrupt has occurred      1 - Interrupt has occurred  Write:      0 - No change in state of T0INT      1 - Clear T1INT (clear to 0)\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "PWMA1": {
                      "bit_offset": 9,
                      "bit_width": 1,
                      "display_name": "Pulse Width Modulation for Timer 1",
                      "description": "Enable Pulse Width Modulation for Timer 1      0 - Disable pulse width modulation      1 - Enable pulse width modulation  PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0.\n",
                      "is_volatile": true,
                      "access": "read-write"
                    },
                    "ENALL": {
                      "bit_offset": 10,
                      "bit_width": 1,
                      "display_name": "Enable All Timers",
                      "description": "Enable All Timers      0 - No effect on timers      1 - Enable all timers (counters run)  This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. \n",
                      "is_volatile": true,
                      "access": "read-write"
                    }
                  }
                },
                "TLR1": {
                  "address_offset": "0x14",
                  "size": 32,
                  "display_name": "Timer 1 Load Register",
                  "description": "Timer 1 Load Register",
                  "is_volatile": true,
                  "access": "read-write",
                  "reset_value": "0x0",
                  "fields": {
                    "TCLR1": {
                      "bit_offset": 0,
                      "bit_width": 32,
                      "display_name": "Timer/Counter Load Register",
                      "description": "Timer/Counter Load Register\n",
                      "is_volatile": true,
                      "access": "read-write"
                    }
                  }
                },
                "TCR1": {
                  "address_offset": "0x18",
                  "size": 32,
                  "display_name": "Timer 1 Counter Register",
                  "description": "Timer 1 Counter Register",
                  "is_volatile": true,
                  "access": "read-only",
                  "reset_value": "0x0",
                  "fields": {
                    "TCR1": {
                      "bit_offset": 0,
                      "bit_width": 32,
                      "display_name": "Timer/Counter Register",
                      "description": "Timer/Counter Register\n",
                      "is_volatile": true,
                      "access": "read-only"
                    }
                  }
                }
              }
            }
          }
        }
      }
    }
  }
}