{
  "design": {
    "design_info": {
      "boundary_crc": "0x170138D2157C3",
      "device": "xczu7ev-ffvc1156-2-i",
      "gen_directory": "../../../../project_1.gen/sources_1/bd/design_1",
      "name": "design_1",
      "rev_ctrl_bd_flag": "RevCtrlBdOff",
      "synth_flow_mode": "Singular",
      "tool_version": "2022.2",
      "validated": "true"
    },
    "design_tree": {
      "axi_interconnect_0": {
        "xbar": "",
        "s00_couplers": {},
        "m00_couplers": {},
        "m01_couplers": {},
        "m02_couplers": {},
        "m03_couplers": {},
        "m04_couplers": {}
      },
      "axi_timer_0": "",
      "axi_uartlite_0": "",
      "clk_wiz_1": "",
      "mdm_1": "",
      "microblaze_0": "",
      "microblaze_0_axi_intc": "",
      "microblaze_0_axi_periph": {
        "xbar": "",
        "s00_couplers": {
          "auto_cc": ""
        },
        "s01_couplers": {
          "auto_ds": "",
          "auto_pc": ""
        },
        "m00_couplers": {},
        "m01_couplers": {},
        "m02_couplers": {},
        "m03_couplers": {},
        "m04_couplers": {},
        "m05_couplers": {},
        "m06_couplers": {}
      },
      "microblaze_0_local_memory": {
        "dlmb_bram_if_cntlr": "",
        "dlmb_v10": "",
        "ilmb_bram_if_cntlr": "",
        "ilmb_v10": "",
        "lmb_bram": ""
      },
      "microblaze_0_xlconcat": "",
      "rst_clk_wiz_1_100M": "",
      "system_management_wiz_0": "",
      "util_ds_buf_0": "",
      "xdma_0": "",
      "xlconstant_0": "",
      "zynq_ultra_ps_e_0": "",
      "axi_interconnect_1": {
        "xbar": "",
        "s00_couplers": {
          "s00_data_fifo": ""
        },
        "s01_couplers": {
          "s01_data_fifo": ""
        },
        "m00_couplers": {
          "m00_data_fifo": ""
        }
      }
    },
    "interface_ports": {
      "UART_0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:uart:1.0",
        "vlnv": "xilinx.com:interface:uart_rtl:1.0",
        "port_maps": {
          "RxD": {
            "physical_name": "UART_0_rxd",
            "direction": "I"
          },
          "TxD": {
            "physical_name": "UART_0_txd",
            "direction": "O"
          }
        }
      },
      "axil_descriptors": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_descriptors",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_descriptors_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_descriptors_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_descriptors_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_descriptors_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_descriptors_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_descriptors_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_descriptors_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_descriptors_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_descriptors_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_descriptors_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_descriptors_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_descriptors_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_descriptors_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_descriptors_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_descriptors_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_descriptors_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_descriptors_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_descriptors_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_descriptors_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_dma_ctrl0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_dma_ctrl0",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_dma_ctrl0_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_dma_ctrl0_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_dma_ctrl0_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_dma_ctrl0_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_dma_ctrl0_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_dma_ctrl0_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_dma_ctrl0_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_dma_ctrl0_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_dma_ctrl0_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_dma_ctrl0_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_dma_ctrl0_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_dma_ctrl0_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_dma_ctrl0_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_dma_ctrl0_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_dma_ctrl0_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_dma_ctrl0_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_dma_ctrl0_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_dma_ctrl0_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_dma_ctrl0_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_dma_ctrl1": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_dma_ctrl1",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_dma_ctrl1_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_dma_ctrl1_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_dma_ctrl1_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_dma_ctrl1_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_dma_ctrl1_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_dma_ctrl1_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_dma_ctrl1_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_dma_ctrl1_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_dma_ctrl1_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_dma_ctrl1_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_dma_ctrl1_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_dma_ctrl1_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_dma_ctrl1_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_dma_ctrl1_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_dma_ctrl1_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_dma_ctrl1_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_dma_ctrl1_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_dma_ctrl1_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_dma_ctrl1_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_util": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_util",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_util_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_util_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_util_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_util_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_util_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_util_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_util_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_util_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_util_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_util_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_util_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_util_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_util_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_util_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_util_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_util_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_util_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_util_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_util_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "pcie_mgt_0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:pcie_7x_mgt:1.0",
        "vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0",
        "port_maps": {
          "rxn": {
            "physical_name": "pcie_mgt_0_rxn",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "rxp": {
            "physical_name": "pcie_mgt_0_rxp",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "txn": {
            "physical_name": "pcie_mgt_0_txn",
            "direction": "O",
            "left": "7",
            "right": "0"
          },
          "txp": {
            "physical_name": "pcie_mgt_0_txp",
            "direction": "O",
            "left": "7",
            "right": "0"
          }
        }
      },
      "pcie_refclk": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "default"
          }
        },
        "port_maps": {
          "CLK_P": {
            "physical_name": "pcie_refclk_clk_p",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "CLK_N": {
            "physical_name": "pcie_refclk_clk_n",
            "direction": "I",
            "left": "0",
            "right": "0"
          }
        }
      },
      "sys_clk": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "200000000"
          }
        },
        "port_maps": {
          "CLK_N": {
            "physical_name": "sys_clk_clk_n",
            "direction": "I"
          },
          "CLK_P": {
            "physical_name": "sys_clk_clk_p",
            "direction": "I"
          }
        }
      },
      "axil_timing": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_timing",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_timing_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_timing_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_timing_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_timing_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_timing_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_timing_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_timing_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_timing_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_timing_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_timing_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_timing_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_timing_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_timing_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_timing_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_timing_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_timing_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_timing_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_timing_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_timing_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_data_gen": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_data_gen",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_data_gen_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_data_gen_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_data_gen_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_data_gen_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_data_gen_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_data_gen_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_data_gen_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_data_gen_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_data_gen_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_data_gen_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_data_gen_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_data_gen_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_data_gen_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_data_gen_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_data_gen_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_data_gen_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_data_gen_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_data_gen_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_data_gen_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "pcie_m_axi0": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0"
          },
          "AWUSER_WIDTH": {
            "value": "0"
          },
          "BUSER_WIDTH": {
            "value": "0"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "256"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1"
          },
          "HAS_BURST": {
            "value": "1"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "0"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1"
          },
          "HAS_WSTRB": {
            "value": "1"
          },
          "ID_WIDTH": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "256"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "16"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4"
          },
          "READ_WRITE_MODE": {
            "value": "WRITE_ONLY"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "RUSER_WIDTH": {
            "value": "0"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_WIDTH": {
            "value": "0"
          }
        },
        "address_space_ref": "pcie_m_axi0",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x00FFFFFFFFFF",
          "width": "40"
        },
        "port_maps": {
          "AWADDR": {
            "physical_name": "pcie_m_axi0_awaddr",
            "direction": "I",
            "left": "39",
            "right": "0"
          },
          "AWLEN": {
            "physical_name": "pcie_m_axi0_awlen",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "AWSIZE": {
            "physical_name": "pcie_m_axi0_awsize",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWBURST": {
            "physical_name": "pcie_m_axi0_awburst",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "AWLOCK": {
            "physical_name": "pcie_m_axi0_awlock",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWCACHE": {
            "physical_name": "pcie_m_axi0_awcache",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "pcie_m_axi0_awprot",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWQOS": {
            "physical_name": "pcie_m_axi0_awqos",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "pcie_m_axi0_awvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "pcie_m_axi0_awready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "pcie_m_axi0_wdata",
            "direction": "I",
            "left": "255",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "pcie_m_axi0_wstrb",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "WLAST": {
            "physical_name": "pcie_m_axi0_wlast",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "pcie_m_axi0_wvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "pcie_m_axi0_wready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "pcie_m_axi0_bresp",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "pcie_m_axi0_bvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "pcie_m_axi0_bready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREGION": {
            "physical_name": "pcie_m_axi0_awregion",
            "direction": "I",
            "left": "3",
            "right": "0"
          }
        }
      },
      "pcie_m_axi1": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0"
          },
          "AWUSER_WIDTH": {
            "value": "0"
          },
          "BUSER_WIDTH": {
            "value": "0"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "256"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1"
          },
          "HAS_BURST": {
            "value": "1"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "0"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1"
          },
          "HAS_WSTRB": {
            "value": "1"
          },
          "ID_WIDTH": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "256"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "16"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4"
          },
          "READ_WRITE_MODE": {
            "value": "WRITE_ONLY"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "RUSER_WIDTH": {
            "value": "0"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_WIDTH": {
            "value": "0"
          }
        },
        "address_space_ref": "pcie_m_axi1",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x00FFFFFFFFFF",
          "width": "40"
        },
        "port_maps": {
          "AWADDR": {
            "physical_name": "pcie_m_axi1_awaddr",
            "direction": "I",
            "left": "39",
            "right": "0"
          },
          "AWLEN": {
            "physical_name": "pcie_m_axi1_awlen",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "AWSIZE": {
            "physical_name": "pcie_m_axi1_awsize",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWBURST": {
            "physical_name": "pcie_m_axi1_awburst",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "AWLOCK": {
            "physical_name": "pcie_m_axi1_awlock",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWCACHE": {
            "physical_name": "pcie_m_axi1_awcache",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "pcie_m_axi1_awprot",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWQOS": {
            "physical_name": "pcie_m_axi1_awqos",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "pcie_m_axi1_awvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "pcie_m_axi1_awready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "pcie_m_axi1_wdata",
            "direction": "I",
            "left": "255",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "pcie_m_axi1_wstrb",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "WLAST": {
            "physical_name": "pcie_m_axi1_wlast",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "pcie_m_axi1_wvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "pcie_m_axi1_wready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "pcie_m_axi1_bresp",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "pcie_m_axi1_bvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "pcie_m_axi1_bready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREGION": {
            "physical_name": "pcie_m_axi1_awregion",
            "direction": "I",
            "left": "3",
            "right": "0"
          }
        }
      }
    },
    "ports": {
      "axi_pcie_aresetn": {
        "type": "rst",
        "direction": "O",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "const_prop"
          }
        }
      },
      "axi_pcie_clk": {
        "type": "clk",
        "direction": "O",
        "parameters": {
          "ASSOCIATED_BUSIF": {
            "value": "axil_dma_ctrl1:axil_dma_ctrl0:axil_descriptors:axil_timing:axil_data_gen:axil_util:pcie_m_axi0:pcie_m_axi1"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          }
        }
      },
      "axil_clk": {
        "type": "clk",
        "direction": "O",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "design_1_clk_wiz_1_0_clk_out1",
            "value_src": "default_prop"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "ip_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "ip_prop"
          }
        }
      },
      "axil_resetn": {
        "type": "rst",
        "direction": "O",
        "left": "0",
        "right": "0",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "const_prop"
          }
        }
      },
      "pcie_cfg_ltssm_state": {
        "direction": "O",
        "left": "5",
        "right": "0"
      },
      "pcie_rstn": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW"
          }
        }
      },
      "pcie_user_lnk_up": {
        "direction": "O"
      },
      "usr_irq_req": {
        "direction": "I",
        "left": "0",
        "right": "0"
      }
    },
    "components": {
      "axi_interconnect_0": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci",
        "inst_hier_path": "axi_interconnect_0",
        "xci_name": "design_1_axi_interconnect_0_0",
        "parameters": {
          "NUM_MI": {
            "value": "5"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M02_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M03_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M04_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M01_ARESETN"
              }
            }
          },
          "M01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M02_ARESETN"
              }
            }
          },
          "M02_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M03_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M03_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M03_ARESETN"
              }
            }
          },
          "M03_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M04_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M04_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M04_ARESETN"
              }
            }
          },
          "M04_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "design_1_xbar_0",
            "xci_path": "ip/design_1_xbar_0/design_1_xbar_0.xci",
            "inst_hier_path": "axi_interconnect_0/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "5"
              },
              "NUM_SI": {
                "value": "1"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI",
                  "M01_AXI",
                  "M02_AXI",
                  "M03_AXI",
                  "M04_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "s00_couplers_to_s00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m01_couplers_to_m01_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m02_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m02_couplers_to_m02_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m03_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m03_couplers_to_m03_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m04_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m04_couplers_to_m04_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "axi_interconnect_0_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "m00_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "m01_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M01_AXI",
              "m01_couplers/M_AXI"
            ]
          },
          "m02_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M02_AXI",
              "m02_couplers/M_AXI"
            ]
          },
          "m03_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M03_AXI",
              "m03_couplers/M_AXI"
            ]
          },
          "m04_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M04_AXI",
              "m04_couplers/M_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "xbar_to_m01_couplers": {
            "interface_ports": [
              "xbar/M01_AXI",
              "m01_couplers/S_AXI"
            ]
          },
          "xbar_to_m02_couplers": {
            "interface_ports": [
              "xbar/M02_AXI",
              "m02_couplers/S_AXI"
            ]
          },
          "xbar_to_m03_couplers": {
            "interface_ports": [
              "xbar/M03_AXI",
              "m03_couplers/S_AXI"
            ]
          },
          "xbar_to_m04_couplers": {
            "interface_ports": [
              "xbar/M04_AXI",
              "m04_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "axi_interconnect_0_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/S_ACLK",
              "s00_couplers/M_ACLK",
              "m00_couplers/M_ACLK",
              "m01_couplers/M_ACLK",
              "m02_couplers/M_ACLK",
              "m03_couplers/M_ACLK",
              "m04_couplers/M_ACLK",
              "m00_couplers/S_ACLK",
              "m01_couplers/S_ACLK",
              "m02_couplers/S_ACLK",
              "m03_couplers/S_ACLK",
              "m04_couplers/S_ACLK"
            ]
          },
          "axi_interconnect_0_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/S_ARESETN",
              "s00_couplers/M_ARESETN",
              "m00_couplers/M_ARESETN",
              "m01_couplers/M_ARESETN",
              "m02_couplers/M_ARESETN",
              "m03_couplers/M_ARESETN",
              "m04_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN",
              "m01_couplers/S_ARESETN",
              "m02_couplers/S_ARESETN",
              "m03_couplers/S_ARESETN",
              "m04_couplers/S_ARESETN"
            ]
          }
        }
      },
      "axi_timer_0": {
        "vlnv": "xilinx.com:ip:axi_timer:2.0",
        "xci_name": "design_1_axi_timer_0_0",
        "xci_path": "ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci",
        "inst_hier_path": "axi_timer_0"
      },
      "axi_uartlite_0": {
        "vlnv": "xilinx.com:ip:axi_uartlite:2.0",
        "xci_name": "design_1_axi_uartlite_0_0",
        "xci_path": "ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci",
        "inst_hier_path": "axi_uartlite_0",
        "parameters": {
          "C_BAUDRATE": {
            "value": "115200"
          }
        }
      },
      "clk_wiz_1": {
        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
        "xci_name": "design_1_clk_wiz_1_0",
        "xci_path": "ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xci",
        "inst_hier_path": "clk_wiz_1",
        "parameters": {
          "CLKIN1_JITTER_PS": {
            "value": "50.0"
          },
          "CLKOUT1_JITTER": {
            "value": "106.024"
          },
          "CLKOUT1_PHASE_ERROR": {
            "value": "82.655"
          },
          "MMCM_CLKFBOUT_MULT_F": {
            "value": "6.000"
          },
          "MMCM_CLKIN1_PERIOD": {
            "value": "5.000"
          },
          "MMCM_CLKIN2_PERIOD": {
            "value": "10.0"
          },
          "PRIM_SOURCE": {
            "value": "Differential_clock_capable_pin"
          },
          "USE_LOCKED": {
            "value": "true"
          },
          "USE_RESET": {
            "value": "false"
          }
        }
      },
      "mdm_1": {
        "vlnv": "xilinx.com:ip:mdm:3.2",
        "xci_name": "design_1_mdm_1_0",
        "xci_path": "ip/design_1_mdm_1_0/design_1_mdm_1_0.xci",
        "inst_hier_path": "mdm_1"
      },
      "microblaze_0": {
        "vlnv": "xilinx.com:ip:microblaze:11.0",
        "xci_name": "design_1_microblaze_0_0",
        "xci_path": "ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci",
        "inst_hier_path": "microblaze_0",
        "parameters": {
          "C_ADDR_TAG_BITS": {
            "value": "0"
          },
          "C_DCACHE_ADDR_TAG": {
            "value": "0"
          },
          "C_DEBUG_ENABLED": {
            "value": "1"
          },
          "C_D_AXI": {
            "value": "1"
          },
          "C_D_LMB": {
            "value": "1"
          },
          "C_I_LMB": {
            "value": "1"
          },
          "C_USE_BARREL": {
            "value": "1"
          },
          "C_USE_DIV": {
            "value": "1"
          },
          "C_USE_HW_MUL": {
            "value": "1"
          },
          "C_USE_PCMP_INSTR": {
            "value": "1"
          },
          "C_USE_STACK_PROTECTION": {
            "value": "1"
          },
          "G_TEMPLATE_LIST": {
            "value": "0"
          }
        },
        "interface_ports": {
          "DLMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "ILMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Instruction",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "M_AXI_DP": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          }
        },
        "addressing": {
          "address_spaces": {
            "Data": {
              "range": "4G",
              "width": "32"
            },
            "Instruction": {
              "range": "4G",
              "width": "32"
            }
          }
        },
        "hdl_attributes": {
          "BMM_INFO_PROCESSOR": {
            "value": "microblaze-le > design_1 microblaze_0_local_memory/dlmb_bram_if_cntlr",
            "value_src": "default"
          },
          "KEEP_HIERARCHY": {
            "value": "yes",
            "value_src": "default"
          }
        }
      },
      "microblaze_0_axi_intc": {
        "vlnv": "xilinx.com:ip:axi_intc:4.1",
        "xci_name": "design_1_microblaze_0_axi_intc_0",
        "xci_path": "ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci",
        "inst_hier_path": "microblaze_0_axi_intc",
        "parameters": {
          "C_HAS_FAST": {
            "value": "1"
          }
        }
      },
      "microblaze_0_axi_periph": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci",
        "inst_hier_path": "microblaze_0_axi_periph",
        "xci_name": "design_1_microblaze_0_axi_periph_0",
        "parameters": {
          "NUM_MI": {
            "value": "7"
          },
          "NUM_SI": {
            "value": "2"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "S01_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M02_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "M03_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "M04_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "M05_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "M06_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M01_ARESETN"
              }
            }
          },
          "M01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S01_ARESETN"
              }
            }
          },
          "S01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M02_ARESETN"
              }
            }
          },
          "M02_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M03_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M03_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M03_ARESETN"
              }
            }
          },
          "M03_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M04_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M04_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M04_ARESETN"
              }
            }
          },
          "M04_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M05_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M05_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M05_ARESETN"
              }
            }
          },
          "M05_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M06_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M06_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M06_ARESETN"
              }
            }
          },
          "M06_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "design_1_xbar_1",
            "xci_path": "ip/design_1_xbar_1/design_1_xbar_1.xci",
            "inst_hier_path": "microblaze_0_axi_periph/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "7"
              },
              "NUM_SI": {
                "value": "2"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI",
                  "M01_AXI",
                  "M02_AXI",
                  "M03_AXI",
                  "M04_AXI",
                  "M05_AXI",
                  "M06_AXI"
                ]
              },
              "S01_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI",
                  "M01_AXI",
                  "M02_AXI",
                  "M03_AXI",
                  "M04_AXI",
                  "M05_AXI",
                  "M06_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "auto_cc": {
                "vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
                "xci_name": "design_1_auto_cc_0",
                "xci_path": "ip/design_1_auto_cc_0/design_1_auto_cc_0.xci",
                "inst_hier_path": "microblaze_0_axi_periph/s00_couplers/auto_cc",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_cc_to_s00_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "auto_cc/M_AXI"
                ]
              },
              "s00_couplers_to_auto_cc": {
                "interface_ports": [
                  "S_AXI",
                  "auto_cc/S_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "auto_cc/m_axi_aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "auto_cc/m_axi_aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_cc/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_cc/s_axi_aresetn"
                ]
              }
            }
          },
          "s01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "auto_ds": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "design_1_auto_ds_0",
                "xci_path": "ip/design_1_auto_ds_0/design_1_auto_ds_0.xci",
                "inst_hier_path": "microblaze_0_axi_periph/s01_couplers/auto_ds",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "32"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "256"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_pc": {
                "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
                "xci_name": "design_1_auto_pc_0",
                "xci_path": "ip/design_1_auto_pc_0/design_1_auto_pc_0.xci",
                "inst_hier_path": "microblaze_0_axi_periph/s01_couplers/auto_pc",
                "parameters": {
                  "MI_PROTOCOL": {
                    "value": "AXI4LITE"
                  },
                  "SI_PROTOCOL": {
                    "value": "AXI4"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_ds_to_auto_pc": {
                "interface_ports": [
                  "auto_ds/M_AXI",
                  "auto_pc/S_AXI"
                ]
              },
              "auto_pc_to_s01_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "auto_pc/M_AXI"
                ]
              },
              "s01_couplers_to_auto_ds": {
                "interface_ports": [
                  "S_AXI",
                  "auto_ds/S_AXI"
                ]
              }
            },
            "nets": {
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_ds/s_axi_aclk",
                  "auto_pc/aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_ds/s_axi_aresetn",
                  "auto_pc/aresetn"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m01_couplers_to_m01_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m02_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m02_couplers_to_m02_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m03_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m03_couplers_to_m03_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m04_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m04_couplers_to_m04_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m05_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m05_couplers_to_m05_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m06_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m06_couplers_to_m06_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "m00_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "m01_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M01_AXI",
              "m01_couplers/M_AXI"
            ]
          },
          "m02_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M02_AXI",
              "m02_couplers/M_AXI"
            ]
          },
          "m03_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M03_AXI",
              "m03_couplers/M_AXI"
            ]
          },
          "m04_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M04_AXI",
              "m04_couplers/M_AXI"
            ]
          },
          "m05_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M05_AXI",
              "m05_couplers/M_AXI"
            ]
          },
          "m06_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M06_AXI",
              "m06_couplers/M_AXI"
            ]
          },
          "microblaze_0_axi_periph_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "microblaze_0_axi_periph_to_s01_couplers": {
            "interface_ports": [
              "S01_AXI",
              "s01_couplers/S_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "s01_couplers_to_xbar": {
            "interface_ports": [
              "s01_couplers/M_AXI",
              "xbar/S01_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "xbar_to_m01_couplers": {
            "interface_ports": [
              "xbar/M01_AXI",
              "m01_couplers/S_AXI"
            ]
          },
          "xbar_to_m02_couplers": {
            "interface_ports": [
              "xbar/M02_AXI",
              "m02_couplers/S_AXI"
            ]
          },
          "xbar_to_m03_couplers": {
            "interface_ports": [
              "xbar/M03_AXI",
              "m03_couplers/S_AXI"
            ]
          },
          "xbar_to_m04_couplers": {
            "interface_ports": [
              "xbar/M04_AXI",
              "m04_couplers/S_AXI"
            ]
          },
          "xbar_to_m05_couplers": {
            "interface_ports": [
              "xbar/M05_AXI",
              "m05_couplers/S_AXI"
            ]
          },
          "xbar_to_m06_couplers": {
            "interface_ports": [
              "xbar/M06_AXI",
              "m06_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "M00_ACLK_1": {
            "ports": [
              "M00_ACLK",
              "m00_couplers/M_ACLK"
            ]
          },
          "M00_ARESETN_1": {
            "ports": [
              "M00_ARESETN",
              "m00_couplers/M_ARESETN"
            ]
          },
          "M01_ACLK_1": {
            "ports": [
              "M01_ACLK",
              "m01_couplers/M_ACLK"
            ]
          },
          "M01_ARESETN_1": {
            "ports": [
              "M01_ARESETN",
              "m01_couplers/M_ARESETN"
            ]
          },
          "M02_ACLK_1": {
            "ports": [
              "M02_ACLK",
              "m02_couplers/M_ACLK"
            ]
          },
          "M02_ARESETN_1": {
            "ports": [
              "M02_ARESETN",
              "m02_couplers/M_ARESETN"
            ]
          },
          "M03_ACLK_1": {
            "ports": [
              "M03_ACLK",
              "m03_couplers/M_ACLK"
            ]
          },
          "M03_ARESETN_1": {
            "ports": [
              "M03_ARESETN",
              "m03_couplers/M_ARESETN"
            ]
          },
          "M04_ACLK_1": {
            "ports": [
              "M04_ACLK",
              "m04_couplers/M_ACLK"
            ]
          },
          "M04_ARESETN_1": {
            "ports": [
              "M04_ARESETN",
              "m04_couplers/M_ARESETN"
            ]
          },
          "M05_ACLK_1": {
            "ports": [
              "M05_ACLK",
              "m05_couplers/M_ACLK"
            ]
          },
          "M05_ARESETN_1": {
            "ports": [
              "M05_ARESETN",
              "m05_couplers/M_ARESETN"
            ]
          },
          "M06_ACLK_1": {
            "ports": [
              "M06_ACLK",
              "m06_couplers/M_ACLK"
            ]
          },
          "M06_ARESETN_1": {
            "ports": [
              "M06_ARESETN",
              "m06_couplers/M_ARESETN"
            ]
          },
          "S00_ACLK_1": {
            "ports": [
              "S00_ACLK",
              "s00_couplers/S_ACLK"
            ]
          },
          "S00_ARESETN_1": {
            "ports": [
              "S00_ARESETN",
              "s00_couplers/S_ARESETN"
            ]
          },
          "S01_ACLK_1": {
            "ports": [
              "S01_ACLK",
              "s01_couplers/S_ACLK"
            ]
          },
          "S01_ARESETN_1": {
            "ports": [
              "S01_ARESETN",
              "s01_couplers/S_ARESETN"
            ]
          },
          "microblaze_0_axi_periph_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/M_ACLK",
              "s01_couplers/M_ACLK",
              "m00_couplers/S_ACLK",
              "m01_couplers/S_ACLK",
              "m02_couplers/S_ACLK",
              "m03_couplers/S_ACLK",
              "m04_couplers/S_ACLK",
              "m05_couplers/S_ACLK",
              "m06_couplers/S_ACLK"
            ]
          },
          "microblaze_0_axi_periph_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/M_ARESETN",
              "s01_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN",
              "m01_couplers/S_ARESETN",
              "m02_couplers/S_ARESETN",
              "m03_couplers/S_ARESETN",
              "m04_couplers/S_ARESETN",
              "m05_couplers/S_ARESETN",
              "m06_couplers/S_ARESETN"
            ]
          }
        }
      },
      "microblaze_0_local_memory": {
        "interface_ports": {
          "DLMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          },
          "ILMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          }
        },
        "ports": {
          "LMB_Clk": {
            "type": "clk",
            "direction": "I"
          },
          "SYS_Rst": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "dlmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "design_1_dlmb_bram_if_cntlr_0",
            "xci_path": "ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            },
            "hdl_attributes": {
              "BMM_INFO_ADDRESS_SPACE": {
                "value": "byte  0x00000000 32 > design_1 microblaze_0_local_memory/lmb_bram",
                "value_src": "default"
              },
              "KEEP_HIERARCHY": {
                "value": "yes",
                "value_src": "default"
              }
            }
          },
          "dlmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "design_1_dlmb_v10_0",
            "xci_path": "ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "ilmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "design_1_ilmb_bram_if_cntlr_0",
            "xci_path": "ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            }
          },
          "ilmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "design_1_ilmb_v10_0",
            "xci_path": "ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "lmb_bram": {
            "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
            "xci_name": "design_1_lmb_bram_0",
            "xci_path": "ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/lmb_bram",
            "parameters": {
              "Enable_B": {
                "value": "Use_ENB_Pin"
              },
              "Memory_Type": {
                "value": "True_Dual_Port_RAM"
              },
              "Port_B_Clock": {
                "value": "100"
              },
              "Port_B_Enable_Rate": {
                "value": "100"
              },
              "Port_B_Write_Rate": {
                "value": "50"
              },
              "Use_RSTB_Pin": {
                "value": "true"
              },
              "use_bram_block": {
                "value": "BRAM_Controller"
              }
            }
          }
        },
        "interface_nets": {
          "microblaze_0_dlmb": {
            "interface_ports": [
              "DLMB",
              "dlmb_v10/LMB_M"
            ]
          },
          "microblaze_0_dlmb_bus": {
            "interface_ports": [
              "dlmb_bram_if_cntlr/SLMB",
              "dlmb_v10/LMB_Sl_0"
            ]
          },
          "microblaze_0_dlmb_cntlr": {
            "interface_ports": [
              "dlmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTA"
            ]
          },
          "microblaze_0_ilmb": {
            "interface_ports": [
              "ILMB",
              "ilmb_v10/LMB_M"
            ]
          },
          "microblaze_0_ilmb_bus": {
            "interface_ports": [
              "ilmb_bram_if_cntlr/SLMB",
              "ilmb_v10/LMB_Sl_0"
            ]
          },
          "microblaze_0_ilmb_cntlr": {
            "interface_ports": [
              "ilmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTB"
            ]
          }
        },
        "nets": {
          "SYS_Rst_1": {
            "ports": [
              "SYS_Rst",
              "dlmb_bram_if_cntlr/LMB_Rst",
              "dlmb_v10/SYS_Rst",
              "ilmb_bram_if_cntlr/LMB_Rst",
              "ilmb_v10/SYS_Rst"
            ]
          },
          "microblaze_0_Clk": {
            "ports": [
              "LMB_Clk",
              "dlmb_bram_if_cntlr/LMB_Clk",
              "dlmb_v10/LMB_Clk",
              "ilmb_bram_if_cntlr/LMB_Clk",
              "ilmb_v10/LMB_Clk"
            ]
          }
        }
      },
      "microblaze_0_xlconcat": {
        "vlnv": "xilinx.com:ip:xlconcat:2.1",
        "xci_name": "design_1_microblaze_0_xlconcat_0",
        "xci_path": "ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci",
        "inst_hier_path": "microblaze_0_xlconcat",
        "parameters": {
          "NUM_PORTS": {
            "value": "3"
          }
        }
      },
      "rst_clk_wiz_1_100M": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "design_1_rst_clk_wiz_1_100M_0",
        "xci_path": "ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xci",
        "inst_hier_path": "rst_clk_wiz_1_100M",
        "parameters": {
          "C_AUX_RESET_HIGH": {
            "value": "0"
          }
        }
      },
      "system_management_wiz_0": {
        "vlnv": "xilinx.com:ip:system_management_wiz:1.3",
        "xci_name": "design_1_system_management_wiz_0_0",
        "xci_path": "ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci",
        "inst_hier_path": "system_management_wiz_0",
        "parameters": {
          "CHANNEL_AVERAGING": {
            "value": "16"
          },
          "CHANNEL_ENABLE_VP_VN": {
            "value": "true"
          },
          "ENABLE_TEMP_BUS": {
            "value": "false"
          },
          "ENABLE_VCCPSAUX_ALARM": {
            "value": "false"
          },
          "ENABLE_VCCPSINTFP_ALARM": {
            "value": "false"
          },
          "ENABLE_VCCPSINTLP_ALARM": {
            "value": "false"
          },
          "OT_ALARM": {
            "value": "false"
          },
          "SYSMONE1_STARUP_SELECTION": {
            "value": "channel_sequencer"
          },
          "USER_TEMP_ALARM": {
            "value": "false"
          },
          "VCCAUX_ALARM": {
            "value": "false"
          },
          "VCCINT_ALARM": {
            "value": "false"
          }
        }
      },
      "util_ds_buf_0": {
        "vlnv": "xilinx.com:ip:util_ds_buf:2.2",
        "xci_name": "design_1_util_ds_buf_0_0",
        "xci_path": "ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci",
        "inst_hier_path": "util_ds_buf_0",
        "parameters": {
          "C_BUF_TYPE": {
            "value": "IBUFDSGTE"
          }
        }
      },
      "xdma_0": {
        "vlnv": "xilinx.com:ip:xdma:4.1",
        "xci_name": "design_1_xdma_0_0",
        "xci_path": "ip/design_1_xdma_0_0/design_1_xdma_0_0.xci",
        "inst_hier_path": "xdma_0",
        "parameters": {
          "axi_addr_width": {
            "value": "40"
          },
          "c_s_axi_supports_narrow_burst": {
            "value": "true"
          },
          "en_axi_master_if": {
            "value": "true"
          },
          "en_axi_slave_if": {
            "value": "true"
          },
          "en_gt_selection": {
            "value": "false"
          },
          "enable_auto_rxeq": {
            "value": "False"
          },
          "functional_mode": {
            "value": "AXI_Bridge"
          },
          "mode_selection": {
            "value": "Advanced"
          },
          "pcie_blk_locn": {
            "value": "X0Y0"
          },
          "pcie_id_if": {
            "value": "false"
          },
          "pciebar2axibar_0": {
            "value": "0x0000000080000000"
          },
          "pf0_bar0_scale": {
            "value": "Megabytes"
          },
          "pf0_bar0_size": {
            "value": "32"
          },
          "pf0_base_class_menu": {
            "value": "Memory_controller"
          },
          "pf0_sub_class_interface_menu": {
            "value": "Other_memory_controller"
          },
          "pl_link_cap_max_link_speed": {
            "value": "8.0_GT/s"
          },
          "pl_link_cap_max_link_width": {
            "value": "X8"
          },
          "sys_reset_polarity": {
            "value": "ACTIVE_LOW"
          }
        },
        "interface_ports": {
          "S_AXI_B": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Slave",
            "memory_map_ref": "S_AXI_B"
          },
          "M_AXI_B": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "M_AXI_B",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0x00FFFFFFFFFF",
              "width": "40"
            }
          },
          "S_AXI_LITE": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Slave",
            "memory_map_ref": "S_AXI_LITE"
          }
        },
        "addressing": {
          "memory_maps": {
            "S_AXI_B": {
              "address_blocks": {
                "BAR0": {
                  "base_address": "0",
                  "range": "1M",
                  "width": "20",
                  "usage": "memory",
                  "offset_base_param": "axibar_0",
                  "offset_high_param": "axibar_highaddr_0"
                }
              }
            },
            "S_AXI_LITE": {
              "address_blocks": {
                "CTL0": {
                  "base_address": "0",
                  "range": "512M",
                  "width": "29",
                  "usage": "memory",
                  "offset_base_param": "baseaddr",
                  "offset_high_param": "highaddr"
                }
              }
            }
          },
          "address_spaces": {
            "M_AXI_B": {
              "range": "1T",
              "width": "40"
            }
          }
        }
      },
      "xlconstant_0": {
        "vlnv": "xilinx.com:ip:xlconstant:1.1",
        "xci_name": "design_1_xlconstant_0_0",
        "xci_path": "ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci",
        "inst_hier_path": "xlconstant_0"
      },
      "zynq_ultra_ps_e_0": {
        "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.4",
        "xci_name": "design_1_zynq_ultra_ps_e_0_0",
        "xci_path": "ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xci",
        "inst_hier_path": "zynq_ultra_ps_e_0",
        "parameters": {
          "CAN0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "CAN1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "CSU_BOARD_INTERFACE": {
            "value": "custom"
          },
          "DP_BOARD_INTERFACE": {
            "value": "custom"
          },
          "GEM0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "GEM1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "GEM2_BOARD_INTERFACE": {
            "value": "custom"
          },
          "GEM3_BOARD_INTERFACE": {
            "value": "custom"
          },
          "GPIO_BOARD_INTERFACE": {
            "value": "custom"
          },
          "IIC0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "IIC1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "NAND_BOARD_INTERFACE": {
            "value": "custom"
          },
          "PCIE_BOARD_INTERFACE": {
            "value": "custom"
          },
          "PJTAG_BOARD_INTERFACE": {
            "value": "custom"
          },
          "PMU_BOARD_INTERFACE": {
            "value": "custom"
          },
          "PSU_BANK_0_IO_STANDARD": {
            "value": "LVCMOS33"
          },
          "PSU_BANK_1_IO_STANDARD": {
            "value": "LVCMOS33"
          },
          "PSU_BANK_2_IO_STANDARD": {
            "value": "LVCMOS33"
          },
          "PSU_BANK_3_IO_STANDARD": {
            "value": "LVCMOS33"
          },
          "PSU_DDR_RAM_HIGHADDR": {
            "value": "0xFFFFFFFF"
          },
          "PSU_DDR_RAM_HIGHADDR_OFFSET": {
            "value": "0x800000000"
          },
          "PSU_DDR_RAM_LOWADDR_OFFSET": {
            "value": "0x80000000"
          },
          "PSU_MIO_0_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_0_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_0_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_10_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_10_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_10_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_10_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_11_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_11_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_11_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_11_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_12_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_12_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_12_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_13_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_13_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_13_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_13_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_14_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_14_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_14_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_14_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_15_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_15_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_15_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_15_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_16_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_16_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_16_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_16_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_17_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_17_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_17_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_17_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_18_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_18_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_18_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_18_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_19_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_19_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_19_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_19_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_1_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_1_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_1_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_1_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_20_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_20_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_20_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_20_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_21_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_21_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_21_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_21_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_22_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_22_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_22_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_22_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_23_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_23_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_23_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_23_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_24_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_24_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_24_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_24_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_25_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_25_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_25_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_25_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_26_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_26_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_26_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_26_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_27_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_27_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_27_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_27_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_28_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_28_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_28_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_28_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_29_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_29_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_29_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_29_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_2_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_2_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_2_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_2_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_30_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_30_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_30_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_30_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_31_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_31_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_31_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_31_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_32_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_32_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_32_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_32_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_33_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_33_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_33_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_33_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_34_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_34_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_34_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_34_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_35_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_35_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_35_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_35_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_36_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_36_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_36_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_36_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_37_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_37_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_37_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_37_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_38_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_38_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_38_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_38_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_39_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_39_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_39_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_39_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_3_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_3_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_3_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_3_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_40_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_40_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_40_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_40_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_41_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_41_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_41_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_41_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_42_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_42_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_43_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_43_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_43_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_44_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_44_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_44_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_44_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_45_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_45_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_45_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_45_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_46_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_46_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_46_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_46_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_47_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_47_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_47_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_47_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_48_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_48_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_48_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_48_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_49_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_49_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_49_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_49_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_4_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_4_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_4_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_4_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_50_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_50_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_50_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_50_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_51_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_51_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_51_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_51_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_52_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_52_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_52_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_52_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_53_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_53_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_53_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_53_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_54_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_54_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_54_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_54_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_55_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_55_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_55_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_55_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_56_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_56_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_56_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_56_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_57_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_57_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_57_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_57_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_58_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_58_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_58_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_58_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_59_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_59_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_59_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_59_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_5_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_5_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_5_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_60_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_60_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_60_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_60_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_61_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_61_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_61_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_61_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_62_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_62_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_62_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_62_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_63_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_63_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_63_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_63_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_64_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_64_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_64_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_64_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_65_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_65_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_65_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_65_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_66_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_66_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_66_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_66_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_67_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_67_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_67_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_67_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_68_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_68_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_68_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_68_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_69_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_69_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_69_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_69_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_6_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_6_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_6_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_6_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_70_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_70_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_70_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_70_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_71_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_71_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_71_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_71_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_72_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_72_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_72_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_72_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_73_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_73_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_73_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_73_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_74_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_74_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_74_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_74_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_75_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_75_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_75_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_75_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_76_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_76_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_76_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_76_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_77_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_77_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_77_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_77_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_7_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_7_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_7_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_8_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_8_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_8_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_8_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_9_DRIVE_STRENGTH": {
            "value": "12"
          },
          "PSU_MIO_9_INPUT_TYPE": {
            "value": "cmos"
          },
          "PSU_MIO_9_PULLUPDOWN": {
            "value": "pullup"
          },
          "PSU_MIO_9_SLEW": {
            "value": "fast"
          },
          "PSU_MIO_TREE_PERIPHERALS": {
            "value": [
              "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash##Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI",
              "Flash##############################UART 0#UART 0##################################"
            ]
          },
          "PSU_MIO_TREE_SIGNALS": {
            "value": "sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out##n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper##############################rxd#txd##################################"
          },
          "PSU_SD0_INTERNAL_BUS_WIDTH": {
            "value": "8"
          },
          "PSU_SD1_INTERNAL_BUS_WIDTH": {
            "value": "8"
          },
          "PSU_SMC_CYCLE_T0": {
            "value": "NA"
          },
          "PSU_SMC_CYCLE_T1": {
            "value": "NA"
          },
          "PSU_SMC_CYCLE_T2": {
            "value": "NA"
          },
          "PSU_SMC_CYCLE_T3": {
            "value": "NA"
          },
          "PSU_SMC_CYCLE_T4": {
            "value": "NA"
          },
          "PSU_SMC_CYCLE_T5": {
            "value": "NA"
          },
          "PSU_SMC_CYCLE_T6": {
            "value": "NA"
          },
          "PSU_USB3__DUAL_CLOCK_ENABLE": {
            "value": "0"
          },
          "PSU_VALUE_SILVERSION": {
            "value": "3"
          },
          "PSU__ACPU0__POWER__ON": {
            "value": "1"
          },
          "PSU__ACPU1__POWER__ON": {
            "value": "1"
          },
          "PSU__ACPU2__POWER__ON": {
            "value": "1"
          },
          "PSU__ACPU3__POWER__ON": {
            "value": "1"
          },
          "PSU__ACTUAL__IP": {
            "value": "1"
          },
          "PSU__ACT_DDR_FREQ_MHZ": {
            "value": "1199.988037"
          },
          "PSU__AUX_REF_CLK__FREQMHZ": {
            "value": "33.333"
          },
          "PSU__CAN0_LOOP_CAN1__ENABLE": {
            "value": "0"
          },
          "PSU__CAN0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__CAN1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ": {
            "value": "1333.320068"
          },
          "PSU__CRF_APB__ACPU_CTRL__FREQMHZ": {
            "value": "1333.333"
          },
          "PSU__CRF_APB__ACPU_CTRL__SRCSEL": {
            "value": "APLL"
          },
          "PSU__CRF_APB__ACPU__FRAC_ENABLED": {
            "value": "0"
          },
          "PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0": {
            "value": "2"
          },
          "PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__AFI0_REF__ENABLE": {
            "value": "0"
          },
          "PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0": {
            "value": "2"
          },
          "PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__AFI1_REF__ENABLE": {
            "value": "0"
          },
          "PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0": {
            "value": "2"
          },
          "PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__AFI2_REF__ENABLE": {
            "value": "0"
          },
          "PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0": {
            "value": "2"
          },
          "PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__AFI3_REF__ENABLE": {
            "value": "0"
          },
          "PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0": {
            "value": "2"
          },
          "PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__AFI4_REF__ENABLE": {
            "value": "0"
          },
          "PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0": {
            "value": "2"
          },
          "PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ": {
            "value": "667"
          },
          "PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__AFI5_REF__ENABLE": {
            "value": "0"
          },
          "PSU__CRF_APB__APLL_CTRL__FRACFREQ": {
            "value": "27.138"
          },
          "PSU__CRF_APB__APLL_CTRL__SRCSEL": {
            "value": "PSS_REF_CLK"
          },
          "PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ": {
            "value": "1"
          },
          "PSU__CRF_APB__APM_CTRL__DIVISOR0": {
            "value": "1"
          },
          "PSU__CRF_APB__APM_CTRL__FREQMHZ": {
            "value": "1"
          },
          "PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ": {
            "value": "249.997498"
          },
          "PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ": {
            "value": "250"
          },
          "PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ": {
            "value": "250"
          },
          "PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ": {
            "value": "250"
          },
          "PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ": {
            "value": "249.997498"
          },
          "PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ": {
            "value": "250"
          },
          "PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ": {
            "value": "599.994019"
          },
          "PSU__CRF_APB__DDR_CTRL__FREQMHZ": {
            "value": "1200"
          },
          "PSU__CRF_APB__DDR_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ": {
            "value": "599.994019"
          },
          "PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ": {
            "value": "600"
          },
          "PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__DPLL_CTRL__FRACFREQ": {
            "value": "27.138"
          },
          "PSU__CRF_APB__DPLL_CTRL__SRCSEL": {
            "value": "PSS_REF_CLK"
          },
          "PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ": {
            "value": "25"
          },
          "PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ": {
            "value": "25"
          },
          "PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL": {
            "value": "VPLL"
          },
          "PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ": {
            "value": "27"
          },
          "PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ": {
            "value": "27"
          },
          "PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL": {
            "value": "VPLL"
          },
          "PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ": {
            "value": "320"
          },
          "PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ": {
            "value": "300"
          },
          "PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ": {
            "value": "599.994019"
          },
          "PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ": {
            "value": "600"
          },
          "PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ": {
            "value": "599.994019"
          },
          "PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ": {
            "value": "600"
          },
          "PSU__CRF_APB__GPU_REF_CTRL__SRCSEL": {
            "value": "DPLL"
          },
          "PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ": {
            "value": "-1"
          },
          "PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0": {
            "value": "-1"
          },
          "PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ": {
            "value": "-1"
          },
          "PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL": {
            "value": "NA"
          },
          "PSU__CRF_APB__GTGREF0__ENABLE": {
            "value": "NA"
          },
          "PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ": {
            "value": "250"
          },
          "PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ": {
            "value": "250"
          },
          "PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ": {
            "value": "99.999001"
          },
          "PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ": {
            "value": "533.328003"
          },
          "PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ": {
            "value": "533.333"
          },
          "PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL": {
            "value": "VPLL"
          },
          "PSU__CRF_APB__VPLL_CTRL__FRACFREQ": {
            "value": "27.138"
          },
          "PSU__CRF_APB__VPLL_CTRL__SRCSEL": {
            "value": "PSS_REF_CLK"
          },
          "PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ": {
            "value": "533.328003"
          },
          "PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ": {
            "value": "533.333"
          },
          "PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ": {
            "value": "500"
          },
          "PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ": {
            "value": "500"
          },
          "PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__AFI6__ENABLE": {
            "value": "0"
          },
          "PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ": {
            "value": "49.999500"
          },
          "PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ": {
            "value": "50"
          },
          "PSU__CRL_APB__AMS_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ": {
            "value": "533.328003"
          },
          "PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ": {
            "value": "533.333"
          },
          "PSU__CRL_APB__CPU_R5_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ": {
            "value": "180"
          },
          "PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0": {
            "value": "3"
          },
          "PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL": {
            "value": "SysOsc"
          },
          "PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ": {
            "value": "249.997498"
          },
          "PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ": {
            "value": "250"
          },
          "PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ": {
            "value": "1000"
          },
          "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0": {
            "value": "6"
          },
          "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ": {
            "value": "1000"
          },
          "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ": {
            "value": "1499.984985"
          },
          "PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ": {
            "value": "1500"
          },
          "PSU__CRL_APB__DLL_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ": {
            "value": "125"
          },
          "PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ": {
            "value": "250"
          },
          "PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ": {
            "value": "250"
          },
          "PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__IOPLL_CTRL__FRACFREQ": {
            "value": "27.138"
          },
          "PSU__CRL_APB__IOPLL_CTRL__SRCSEL": {
            "value": "PSS_REF_CLK"
          },
          "PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ": {
            "value": "266.664001"
          },
          "PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ": {
            "value": "267"
          },
          "PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ": {
            "value": "99.999001"
          },
          "PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ": {
            "value": "533.328003"
          },
          "PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ": {
            "value": "533.333"
          },
          "PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__NAND_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ": {
            "value": "500"
          },
          "PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0": {
            "value": "3"
          },
          "PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ": {
            "value": "500"
          },
          "PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ": {
            "value": "187.498123"
          },
          "PSU__CRL_APB__PCAP_CTRL__FREQMHZ": {
            "value": "200"
          },
          "PSU__CRL_APB__PCAP_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ": {
            "value": "96.968727"
          },
          "PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__PL0_REF_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ": {
            "value": "299.997009"
          },
          "PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ": {
            "value": "300"
          },
          "PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__RPLL_CTRL__FRACFREQ": {
            "value": "27.138"
          },
          "PSU__CRL_APB__RPLL_CTRL__SRCSEL": {
            "value": "PSS_REF_CLK"
          },
          "PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ": {
            "value": "200"
          },
          "PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ": {
            "value": "200"
          },
          "PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ": {
            "value": "200"
          },
          "PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ": {
            "value": "200"
          },
          "PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ": {
            "value": "214"
          },
          "PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ": {
            "value": "200"
          },
          "PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ": {
            "value": "214"
          },
          "PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ": {
            "value": "200"
          },
          "PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL": {
            "value": "RPLL"
          },
          "PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ": {
            "value": "33.333000"
          },
          "PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL": {
            "value": "PSS_REF_CLK"
          },
          "PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ": {
            "value": "99.999001"
          },
          "PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__UART0_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ": {
            "value": "100"
          },
          "PSU__CRL_APB__UART1_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ": {
            "value": "250"
          },
          "PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ": {
            "value": "250"
          },
          "PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ": {
            "value": "250"
          },
          "PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ": {
            "value": "250"
          },
          "PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ": {
            "value": "20"
          },
          "PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ": {
            "value": "20"
          },
          "PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL": {
            "value": "IOPLL"
          },
          "PSU__CRL_APB__USB3__ENABLE": {
            "value": "0"
          },
          "PSU__CSUPMU__PERIPHERAL__VALID": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_0__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_10__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_11__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_12__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_1__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_2__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_3__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_4__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_5__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_6__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_7__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_8__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__CSU_TAMPER_9__ENABLE": {
            "value": "0"
          },
          "PSU__CSU__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__DDRC__AL": {
            "value": "0"
          },
          "PSU__DDRC__BG_ADDR_COUNT": {
            "value": "1"
          },
          "PSU__DDRC__BRC_MAPPING": {
            "value": "ROW_BANK_COL"
          },
          "PSU__DDRC__BUS_WIDTH": {
            "value": "64 Bit"
          },
          "PSU__DDRC__CL": {
            "value": "16"
          },
          "PSU__DDRC__CLOCK_STOP_EN": {
            "value": "0"
          },
          "PSU__DDRC__COMPONENTS": {
            "value": "Components"
          },
          "PSU__DDRC__CWL": {
            "value": "12"
          },
          "PSU__DDRC__DDR4_ADDR_MAPPING": {
            "value": "0"
          },
          "PSU__DDRC__DDR4_CAL_MODE_ENABLE": {
            "value": "0"
          },
          "PSU__DDRC__DDR4_CRC_CONTROL": {
            "value": "0"
          },
          "PSU__DDRC__DDR4_MAXPWR_SAVING_EN": {
            "value": "0"
          },
          "PSU__DDRC__DDR4_T_REF_MODE": {
            "value": "0"
          },
          "PSU__DDRC__DDR4_T_REF_RANGE": {
            "value": "Normal (0-85)"
          },
          "PSU__DDRC__DEVICE_CAPACITY": {
            "value": "8192 MBits"
          },
          "PSU__DDRC__DM_DBI": {
            "value": "DM_NO_DBI"
          },
          "PSU__DDRC__DRAM_WIDTH": {
            "value": "16 Bits"
          },
          "PSU__DDRC__ECC": {
            "value": "Disabled"
          },
          "PSU__DDRC__ECC_SCRUB": {
            "value": "0"
          },
          "PSU__DDRC__ENABLE": {
            "value": "1"
          },
          "PSU__DDRC__ENABLE_2T_TIMING": {
            "value": "0"
          },
          "PSU__DDRC__ENABLE_DP_SWITCH": {
            "value": "0"
          },
          "PSU__DDRC__EN_2ND_CLK": {
            "value": "0"
          },
          "PSU__DDRC__FGRM": {
            "value": "1X"
          },
          "PSU__DDRC__FREQ_MHZ": {
            "value": "1"
          },
          "PSU__DDRC__LPDDR3_DUALRANK_SDP": {
            "value": "0"
          },
          "PSU__DDRC__LP_ASR": {
            "value": "manual normal"
          },
          "PSU__DDRC__MEMORY_TYPE": {
            "value": "DDR 4"
          },
          "PSU__DDRC__PARITY_ENABLE": {
            "value": "0"
          },
          "PSU__DDRC__PER_BANK_REFRESH": {
            "value": "0"
          },
          "PSU__DDRC__PHY_DBI_MODE": {
            "value": "0"
          },
          "PSU__DDRC__PLL_BYPASS": {
            "value": "0"
          },
          "PSU__DDRC__PWR_DOWN_EN": {
            "value": "0"
          },
          "PSU__DDRC__RANK_ADDR_COUNT": {
            "value": "0"
          },
          "PSU__DDRC__RD_DQS_CENTER": {
            "value": "0"
          },
          "PSU__DDRC__ROW_ADDR_COUNT": {
            "value": "16"
          },
          "PSU__DDRC__SELF_REF_ABORT": {
            "value": "0"
          },
          "PSU__DDRC__SPEED_BIN": {
            "value": "DDR4_2400P"
          },
          "PSU__DDRC__STATIC_RD_MODE": {
            "value": "0"
          },
          "PSU__DDRC__TRAIN_DATA_EYE": {
            "value": "1"
          },
          "PSU__DDRC__TRAIN_READ_GATE": {
            "value": "1"
          },
          "PSU__DDRC__TRAIN_WRITE_LEVEL": {
            "value": "1"
          },
          "PSU__DDRC__T_FAW": {
            "value": "30.0"
          },
          "PSU__DDRC__T_RAS_MIN": {
            "value": "32"
          },
          "PSU__DDRC__T_RC": {
            "value": "45.32"
          },
          "PSU__DDRC__T_RCD": {
            "value": "16"
          },
          "PSU__DDRC__T_RP": {
            "value": "16"
          },
          "PSU__DDRC__VIDEO_BUFFER_SIZE": {
            "value": "0"
          },
          "PSU__DDRC__VREF": {
            "value": "1"
          },
          "PSU__DDR_HIGH_ADDRESS_GUI_ENABLE": {
            "value": "1"
          },
          "PSU__DDR_QOS_ENABLE": {
            "value": "0"
          },
          "PSU__DDR_SW_REFRESH_ENABLED": {
            "value": "1"
          },
          "PSU__DDR__INTERFACE__FREQMHZ": {
            "value": "600.000"
          },
          "PSU__DEVICE_TYPE": {
            "value": "EV"
          },
          "PSU__DISPLAYPORT__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__DLL__ISUSED": {
            "value": "0"
          },
          "PSU__ENABLE__DDR__REFRESH__SIGNALS": {
            "value": "0"
          },
          "PSU__ENET0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__ENET1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__ENET2__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__ENET3__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__EN_AXI_STATUS_PORTS": {
            "value": "0"
          },
          "PSU__EN_EMIO_TRACE": {
            "value": "0"
          },
          "PSU__EP__IP": {
            "value": "0"
          },
          "PSU__EXPAND__CORESIGHT": {
            "value": "0"
          },
          "PSU__EXPAND__FPD_SLAVES": {
            "value": "0"
          },
          "PSU__EXPAND__GIC": {
            "value": "0"
          },
          "PSU__EXPAND__LOWER_LPS_SLAVES": {
            "value": "0"
          },
          "PSU__EXPAND__UPPER_LPS_SLAVES": {
            "value": "0"
          },
          "PSU__FPD_SLCR__WDT1__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__FPD_SLCR__WDT1__FREQMHZ": {
            "value": "100"
          },
          "PSU__FPGA_PL0_ENABLE": {
            "value": "1"
          },
          "PSU__FPGA_PL1_ENABLE": {
            "value": "0"
          },
          "PSU__FPGA_PL2_ENABLE": {
            "value": "0"
          },
          "PSU__FPGA_PL3_ENABLE": {
            "value": "0"
          },
          "PSU__FP__POWER__ON": {
            "value": "1"
          },
          "PSU__FTM__CTI_IN_0": {
            "value": "0"
          },
          "PSU__FTM__CTI_IN_1": {
            "value": "0"
          },
          "PSU__FTM__CTI_IN_2": {
            "value": "0"
          },
          "PSU__FTM__CTI_IN_3": {
            "value": "0"
          },
          "PSU__FTM__CTI_OUT_0": {
            "value": "0"
          },
          "PSU__FTM__CTI_OUT_1": {
            "value": "0"
          },
          "PSU__FTM__CTI_OUT_2": {
            "value": "0"
          },
          "PSU__FTM__CTI_OUT_3": {
            "value": "0"
          },
          "PSU__FTM__GPI": {
            "value": "0"
          },
          "PSU__FTM__GPO": {
            "value": "0"
          },
          "PSU__GEN_IPI_0__MASTER": {
            "value": "APU"
          },
          "PSU__GEN_IPI_10__MASTER": {
            "value": "NONE"
          },
          "PSU__GEN_IPI_1__MASTER": {
            "value": "RPU0"
          },
          "PSU__GEN_IPI_2__MASTER": {
            "value": "RPU1"
          },
          "PSU__GEN_IPI_3__MASTER": {
            "value": "PMU"
          },
          "PSU__GEN_IPI_4__MASTER": {
            "value": "PMU"
          },
          "PSU__GEN_IPI_5__MASTER": {
            "value": "PMU"
          },
          "PSU__GEN_IPI_6__MASTER": {
            "value": "PMU"
          },
          "PSU__GEN_IPI_7__MASTER": {
            "value": "NONE"
          },
          "PSU__GEN_IPI_8__MASTER": {
            "value": "NONE"
          },
          "PSU__GEN_IPI_9__MASTER": {
            "value": "NONE"
          },
          "PSU__GPIO0_MIO__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__GPIO1_MIO__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__GPIO2_MIO__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__GPIO_EMIO_WIDTH": {
            "value": "1"
          },
          "PSU__GPIO_EMIO__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__GPIO_EMIO__WIDTH": {
            "value": "[94:0]"
          },
          "PSU__GPU_PP0__POWER__ON": {
            "value": "1"
          },
          "PSU__GPU_PP1__POWER__ON": {
            "value": "1"
          },
          "PSU__GT_REF_CLK__FREQMHZ": {
            "value": "33.333"
          },
          "PSU__HPM0_FPD__NUM_READ_THREADS": {
            "value": "4"
          },
          "PSU__HPM0_FPD__NUM_WRITE_THREADS": {
            "value": "4"
          },
          "PSU__HPM0_LPD__NUM_READ_THREADS": {
            "value": "4"
          },
          "PSU__HPM0_LPD__NUM_WRITE_THREADS": {
            "value": "4"
          },
          "PSU__HPM1_FPD__NUM_READ_THREADS": {
            "value": "4"
          },
          "PSU__HPM1_FPD__NUM_WRITE_THREADS": {
            "value": "4"
          },
          "PSU__I2C0_LOOP_I2C1__ENABLE": {
            "value": "0"
          },
          "PSU__I2C0__GRP_INT__ENABLE": {
            "value": "0"
          },
          "PSU__I2C0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__I2C1__GRP_INT__ENABLE": {
            "value": "0"
          },
          "PSU__I2C1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL": {
            "value": "APB"
          },
          "PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL": {
            "value": "APB"
          },
          "PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL": {
            "value": "APB"
          },
          "PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL": {
            "value": "APB"
          },
          "PSU__IOU_SLCR__TTC0__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__TTC0__FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__TTC1__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__TTC1__FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__TTC2__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__TTC2__FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__TTC3__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__TTC3__FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__WDT0__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__IOU_SLCR__WDT0__FREQMHZ": {
            "value": "100"
          },
          "PSU__IRQ_P2F_ADMA_CHAN__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_AIB_AXI__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_AMS__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APM_FPD__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_COMM__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_CPUMNT__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_CTI__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_EXTERR__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_IPI__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_L2ERR__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_PMU__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_APU_REGS__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_ATB_LPD__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_CLKMON__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_DDR_SS__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_DPDMA__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_EFUSE__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_FPD_APB__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_FPD_ATB_ERR__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_FP_WDT__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_GDMA_CHAN__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_GPIO__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_GPU__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_LPD_APB__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_LPD_APM__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_LP_WDT__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_OCM_ERR__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_PCIE_DMA__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_PCIE_LEGACY__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_PCIE_MSC__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_PCIE_MSI__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_PL_IPI__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_QSPI__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_RPU_IPI__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_RPU_PERMON__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_RTC_ALARM__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_RTC_SECONDS__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_SATA__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_UART0__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_USB3_ENDPOINT__INT0": {
            "value": "0"
          },
          "PSU__IRQ_P2F_USB3_ENDPOINT__INT1": {
            "value": "0"
          },
          "PSU__IRQ_P2F_USB3_OTG__INT0": {
            "value": "0"
          },
          "PSU__IRQ_P2F_USB3_OTG__INT1": {
            "value": "0"
          },
          "PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_XMPU_FPD__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F_XMPU_LPD__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F__INTF_FPD_SMMU__INT": {
            "value": "0"
          },
          "PSU__IRQ_P2F__INTF_PPD_CCI__INT": {
            "value": "0"
          },
          "PSU__L2_BANK0__POWER__ON": {
            "value": "1"
          },
          "PSU__LPDMA0_COHERENCY": {
            "value": "0"
          },
          "PSU__LPDMA1_COHERENCY": {
            "value": "0"
          },
          "PSU__LPDMA2_COHERENCY": {
            "value": "0"
          },
          "PSU__LPDMA3_COHERENCY": {
            "value": "0"
          },
          "PSU__LPDMA4_COHERENCY": {
            "value": "0"
          },
          "PSU__LPDMA5_COHERENCY": {
            "value": "0"
          },
          "PSU__LPDMA6_COHERENCY": {
            "value": "0"
          },
          "PSU__LPDMA7_COHERENCY": {
            "value": "0"
          },
          "PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT": {
            "value": "APB"
          },
          "PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ": {
            "value": "100"
          },
          "PSU__LPD_SLCR__CSUPMU__FREQMHZ": {
            "value": "100"
          },
          "PSU__MAXIGP2__DATA_WIDTH": {
            "value": "32"
          },
          "PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "PSU__NAND__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__NAND__READY_BUSY__ENABLE": {
            "value": "0"
          },
          "PSU__NUM_FABRIC_RESETS": {
            "value": "1"
          },
          "PSU__OCM_BANK0__POWER__ON": {
            "value": "1"
          },
          "PSU__OCM_BANK1__POWER__ON": {
            "value": "1"
          },
          "PSU__OCM_BANK2__POWER__ON": {
            "value": "1"
          },
          "PSU__OCM_BANK3__POWER__ON": {
            "value": "1"
          },
          "PSU__OVERRIDE_HPX_QOS": {
            "value": "0"
          },
          "PSU__OVERRIDE__BASIC_CLOCK": {
            "value": "0"
          },
          "PSU__PCIE__ACS_VIOLAION": {
            "value": "0"
          },
          "PSU__PCIE__AER_CAPABILITY": {
            "value": "0"
          },
          "PSU__PCIE__INTX_GENERATION": {
            "value": "0"
          },
          "PSU__PCIE__MSIX_CAPABILITY": {
            "value": "0"
          },
          "PSU__PCIE__MSI_CAPABILITY": {
            "value": "0"
          },
          "PSU__PCIE__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE": {
            "value": "1"
          },
          "PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE": {
            "value": "0"
          },
          "PSU__PCIE__RESET__POLARITY": {
            "value": "Active Low"
          },
          "PSU__PJTAG__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__PL_CLK0_BUF": {
            "value": "TRUE"
          },
          "PSU__PL__POWER__ON": {
            "value": "1"
          },
          "PSU__PMU__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__PRESET_APPLIED": {
            "value": "0"
          },
          "PSU__PROTECTION__DDR_SEGMENTS": {
            "value": "NONE"
          },
          "PSU__PROTECTION__ENABLE": {
            "value": "0"
          },
          "PSU__PROTECTION__FPD_SEGMENTS": {
            "value": [
              "SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|",
              "SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|",
              "SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|",
              "SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|",
              "SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem"
            ]
          },
          "PSU__PROTECTION__LPD_SEGMENTS": {
            "value": [
              "SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|",
              "SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|",
              "SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|",
              "SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure",
              "Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;",
              "subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem"
            ]
          },
          "PSU__PROTECTION__MASTERS": {
            "value": "USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;0|SD0:NonSecure;0|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1"
          },
          "PSU__PROTECTION__MASTERS_TZ": {
            "value": "GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure"
          },
          "PSU__PROTECTION__OCM_SEGMENTS": {
            "value": "NONE"
          },
          "PSU__PROTECTION__PRESUBSYSTEMS": {
            "value": "NONE"
          },
          "PSU__PROTECTION__SLAVES": {
            "value": [
              "LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;0|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;0|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display",
              "Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1"
            ]
          },
          "PSU__PROTECTION__SUBSYSTEMS": {
            "value": "PMU Firmware:PMU|Secure Subsystem:"
          },
          "PSU__PSS_ALT_REF_CLK__ENABLE": {
            "value": "0"
          },
          "PSU__PSS_ALT_REF_CLK__FREQMHZ": {
            "value": "33.333"
          },
          "PSU__PSS_REF_CLK__FREQMHZ": {
            "value": "33.333"
          },
          "PSU__QSPI_COHERENCY": {
            "value": "0"
          },
          "PSU__QSPI_ROUTE_THROUGH_FPD": {
            "value": "0"
          },
          "PSU__QSPI__GRP_FBCLK__ENABLE": {
            "value": "0"
          },
          "PSU__QSPI__PERIPHERAL__DATA_MODE": {
            "value": "x4"
          },
          "PSU__QSPI__PERIPHERAL__ENABLE": {
            "value": "1"
          },
          "PSU__QSPI__PERIPHERAL__IO": {
            "value": "MIO 0 .. 12"
          },
          "PSU__QSPI__PERIPHERAL__MODE": {
            "value": "Dual Parallel"
          },
          "PSU__REPORT__DBGLOG": {
            "value": "0"
          },
          "PSU__RPU_COHERENCY": {
            "value": "0"
          },
          "PSU__RPU__POWER__ON": {
            "value": "1"
          },
          "PSU__SATA__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__SD0__CLK_100_SDR_OTAP_DLY": {
            "value": "0x3"
          },
          "PSU__SD0__CLK_200_SDR_OTAP_DLY": {
            "value": "0x3"
          },
          "PSU__SD0__CLK_50_DDR_ITAP_DLY": {
            "value": "0x3D"
          },
          "PSU__SD0__CLK_50_DDR_OTAP_DLY": {
            "value": "0x4"
          },
          "PSU__SD0__CLK_50_SDR_ITAP_DLY": {
            "value": "0x15"
          },
          "PSU__SD0__CLK_50_SDR_OTAP_DLY": {
            "value": "0x5"
          },
          "PSU__SD0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__SD0__RESET__ENABLE": {
            "value": "0"
          },
          "PSU__SD1__CLK_100_SDR_OTAP_DLY": {
            "value": "0x3"
          },
          "PSU__SD1__CLK_200_SDR_OTAP_DLY": {
            "value": "0x3"
          },
          "PSU__SD1__CLK_50_DDR_ITAP_DLY": {
            "value": "0x3D"
          },
          "PSU__SD1__CLK_50_DDR_OTAP_DLY": {
            "value": "0x4"
          },
          "PSU__SD1__CLK_50_SDR_ITAP_DLY": {
            "value": "0x15"
          },
          "PSU__SD1__CLK_50_SDR_OTAP_DLY": {
            "value": "0x5"
          },
          "PSU__SD1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__SD1__RESET__ENABLE": {
            "value": "0"
          },
          "PSU__SPI0_LOOP_SPI1__ENABLE": {
            "value": "0"
          },
          "PSU__SPI0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__SPI1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__SWDT0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__SWDT0__PERIPHERAL__IO": {
            "value": "NA"
          },
          "PSU__SWDT1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__SWDT1__PERIPHERAL__IO": {
            "value": "NA"
          },
          "PSU__TCM0A__POWER__ON": {
            "value": "1"
          },
          "PSU__TCM0B__POWER__ON": {
            "value": "1"
          },
          "PSU__TCM1A__POWER__ON": {
            "value": "1"
          },
          "PSU__TCM1B__POWER__ON": {
            "value": "1"
          },
          "PSU__TESTSCAN__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__TRACE__INTERNAL_WIDTH": {
            "value": "32"
          },
          "PSU__TRACE__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__TRISTATE__INVERTED": {
            "value": "1"
          },
          "PSU__TTC0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__TTC0__PERIPHERAL__IO": {
            "value": "NA"
          },
          "PSU__TTC1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__TTC1__PERIPHERAL__IO": {
            "value": "NA"
          },
          "PSU__TTC2__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__TTC2__PERIPHERAL__IO": {
            "value": "NA"
          },
          "PSU__TTC3__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__TTC3__PERIPHERAL__IO": {
            "value": "NA"
          },
          "PSU__UART0_LOOP_UART1__ENABLE": {
            "value": "0"
          },
          "PSU__UART0__BAUD_RATE": {
            "value": "115200"
          },
          "PSU__UART0__MODEM__ENABLE": {
            "value": "0"
          },
          "PSU__UART0__PERIPHERAL__ENABLE": {
            "value": "1"
          },
          "PSU__UART0__PERIPHERAL__IO": {
            "value": "MIO 42 .. 43"
          },
          "PSU__UART1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__USB0__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__USB0__RESET__ENABLE": {
            "value": "0"
          },
          "PSU__USB1__PERIPHERAL__ENABLE": {
            "value": "0"
          },
          "PSU__USB1__RESET__ENABLE": {
            "value": "0"
          },
          "PSU__USE__ADMA": {
            "value": "0"
          },
          "PSU__USE__APU_LEGACY_INTERRUPT": {
            "value": "0"
          },
          "PSU__USE__AUDIO": {
            "value": "0"
          },
          "PSU__USE__CLK": {
            "value": "0"
          },
          "PSU__USE__CLK0": {
            "value": "0"
          },
          "PSU__USE__CLK1": {
            "value": "0"
          },
          "PSU__USE__CLK2": {
            "value": "0"
          },
          "PSU__USE__CLK3": {
            "value": "0"
          },
          "PSU__USE__CROSS_TRIGGER": {
            "value": "0"
          },
          "PSU__USE__DDR_INTF_REQUESTED": {
            "value": "0"
          },
          "PSU__USE__DEBUG__TEST": {
            "value": "0"
          },
          "PSU__USE__EVENT_RPU": {
            "value": "0"
          },
          "PSU__USE__FABRIC__RST": {
            "value": "1"
          },
          "PSU__USE__FTM": {
            "value": "0"
          },
          "PSU__USE__GDMA": {
            "value": "0"
          },
          "PSU__USE__IRQ": {
            "value": "0"
          },
          "PSU__USE__IRQ0": {
            "value": "0"
          },
          "PSU__USE__IRQ1": {
            "value": "0"
          },
          "PSU__USE__M_AXI_GP0": {
            "value": "0"
          },
          "PSU__USE__M_AXI_GP1": {
            "value": "0"
          },
          "PSU__USE__M_AXI_GP2": {
            "value": "1"
          },
          "PSU__USE__PROC_EVENT_BUS": {
            "value": "0"
          },
          "PSU__USE__RPU_LEGACY_INTERRUPT": {
            "value": "0"
          },
          "PSU__USE__RST0": {
            "value": "0"
          },
          "PSU__USE__RST1": {
            "value": "0"
          },
          "PSU__USE__RST2": {
            "value": "0"
          },
          "PSU__USE__RST3": {
            "value": "0"
          },
          "PSU__USE__RTC": {
            "value": "0"
          },
          "PSU__USE__STM": {
            "value": "0"
          },
          "PSU__USE__S_AXI_ACE": {
            "value": "0"
          },
          "PSU__USE__S_AXI_ACP": {
            "value": "0"
          },
          "PSU__USE__S_AXI_GP0": {
            "value": "0"
          },
          "PSU__USE__S_AXI_GP1": {
            "value": "0"
          },
          "PSU__USE__S_AXI_GP2": {
            "value": "0"
          },
          "PSU__USE__S_AXI_GP3": {
            "value": "0"
          },
          "PSU__USE__S_AXI_GP4": {
            "value": "0"
          },
          "PSU__USE__S_AXI_GP5": {
            "value": "0"
          },
          "PSU__USE__S_AXI_GP6": {
            "value": "0"
          },
          "PSU__USE__USB3_0_HUB": {
            "value": "0"
          },
          "PSU__USE__USB3_1_HUB": {
            "value": "0"
          },
          "PSU__USE__VIDEO": {
            "value": "0"
          },
          "PSU__VIDEO_REF_CLK__ENABLE": {
            "value": "0"
          },
          "PSU__VIDEO_REF_CLK__FREQMHZ": {
            "value": "33.333"
          },
          "QSPI_BOARD_INTERFACE": {
            "value": "custom"
          },
          "SATA_BOARD_INTERFACE": {
            "value": "custom"
          },
          "SD0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "SD1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "SPI0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "SPI1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "SUBPRESET1": {
            "value": "Custom"
          },
          "SUBPRESET2": {
            "value": "Custom"
          },
          "SWDT0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "SWDT1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "TRACE_BOARD_INTERFACE": {
            "value": "custom"
          },
          "TTC0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "TTC1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "TTC2_BOARD_INTERFACE": {
            "value": "custom"
          },
          "TTC3_BOARD_INTERFACE": {
            "value": "custom"
          },
          "UART0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "UART1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "USB0_BOARD_INTERFACE": {
            "value": "custom"
          },
          "USB1_BOARD_INTERFACE": {
            "value": "custom"
          },
          "preset": {
            "value": "None"
          }
        },
        "interface_ports": {
          "M_AXI_HPM0_LPD": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x80000000",
              "maximum": "0x9FFFFFFF",
              "width": "40"
            }
          }
        },
        "addressing": {
          "address_spaces": {
            "Data": {
              "range": "1T",
              "width": "40",
              "local_memory_map": {
                "name": "Data",
                "description": "Address Space Segments",
                "address_blocks": {
                  "M_AXI_HPM0_LPD:LPD_AFI_FS": {
                    "name": "M_AXI_HPM0_LPD:LPD_AFI_FS",
                    "display_name": "M_AXI_HPM0_LPD/LPD_AFI_FS",
                    "base_address": "0x80000000",
                    "range": "512M",
                    "width": "32",
                    "usage": "register"
                  },
                  "M_AXI_HPM1_FPD:FPD_AFI_FS0_00": {
                    "name": "M_AXI_HPM1_FPD:FPD_AFI_FS0_00",
                    "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_00",
                    "base_address": "0xB0000000",
                    "range": "256M",
                    "width": "32",
                    "usage": "register"
                  },
                  "M_AXI_HPM1_FPD:FPD_AFI_FS0_01": {
                    "name": "M_AXI_HPM1_FPD:FPD_AFI_FS0_01",
                    "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_01",
                    "base_address": "0x000500000000",
                    "range": "4G",
                    "width": "35",
                    "usage": "register"
                  },
                  "M_AXI_HPM1_FPD:FPD_AFI_FS0_10": {
                    "name": "M_AXI_HPM1_FPD:FPD_AFI_FS0_10",
                    "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_10",
                    "base_address": "0x004800000000",
                    "range": "224G",
                    "width": "39",
                    "usage": "register"
                  },
                  "M_AXI_HPM0_FPD:FPD_AFI_FS1_00": {
                    "name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_00",
                    "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_00",
                    "base_address": "0xA0000000",
                    "range": "256M",
                    "width": "32",
                    "usage": "register"
                  },
                  "M_AXI_HPM0_FPD:FPD_AFI_FS1_01": {
                    "name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_01",
                    "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_01",
                    "base_address": "0x000400000000",
                    "range": "4G",
                    "width": "35",
                    "usage": "register"
                  },
                  "M_AXI_HPM0_FPD:FPD_AFI_FS1_10": {
                    "name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_10",
                    "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_10",
                    "base_address": "0x001000000000",
                    "range": "224G",
                    "width": "39",
                    "usage": "register"
                  }
                }
              }
            }
          }
        }
      },
      "axi_interconnect_1": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci",
        "inst_hier_path": "axi_interconnect_1",
        "xci_name": "design_1_axi_interconnect_1_0",
        "parameters": {
          "M00_HAS_DATA_FIFO": {
            "value": "1"
          },
          "NUM_MI": {
            "value": "1"
          },
          "NUM_SI": {
            "value": "2"
          },
          "S00_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S01_HAS_DATA_FIFO": {
            "value": "1"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "S01_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S01_ARESETN"
              }
            }
          },
          "S01_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "design_1_xbar_2",
            "xci_path": "ip/design_1_xbar_2/design_1_xbar_2.xci",
            "inst_hier_path": "axi_interconnect_1/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "1"
              },
              "NUM_SI": {
                "value": "2"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S01_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s00_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "design_1_s00_data_fifo_0",
                "xci_path": "ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_1/s00_couplers/s00_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "s00_couplers_to_s00_data_fifo": {
                "interface_ports": [
                  "S_AXI",
                  "s00_data_fifo/S_AXI"
                ]
              },
              "s00_data_fifo_to_s00_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s00_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s00_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s00_data_fifo/aresetn"
                ]
              }
            }
          },
          "s01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s01_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "design_1_s01_data_fifo_0",
                "xci_path": "ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_1/s01_couplers/s01_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "s01_couplers_to_s01_data_fifo": {
                "interface_ports": [
                  "S_AXI",
                  "s01_data_fifo/S_AXI"
                ]
              },
              "s01_data_fifo_to_s01_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s01_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s01_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s01_data_fifo/aresetn"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "m00_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "design_1_m00_data_fifo_0",
                "xci_path": "ip/design_1_m00_data_fifo_0/design_1_m00_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_1/m00_couplers/m00_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_data_fifo": {
                "interface_ports": [
                  "S_AXI",
                  "m00_data_fifo/S_AXI"
                ]
              },
              "m00_data_fifo_to_m00_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "m00_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "m00_data_fifo/aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "m00_data_fifo/aresetn"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "axi_interconnect_1_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "axi_interconnect_1_to_s01_couplers": {
            "interface_ports": [
              "S01_AXI",
              "s01_couplers/S_AXI"
            ]
          },
          "m00_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "s01_couplers_to_xbar": {
            "interface_ports": [
              "s01_couplers/M_AXI",
              "xbar/S01_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "axi_interconnect_1_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/S_ACLK",
              "s01_couplers/S_ACLK",
              "s00_couplers/M_ACLK",
              "s01_couplers/M_ACLK",
              "m00_couplers/M_ACLK",
              "m00_couplers/S_ACLK"
            ]
          },
          "axi_interconnect_1_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/S_ARESETN",
              "s01_couplers/S_ARESETN",
              "s00_couplers/M_ARESETN",
              "s01_couplers/M_ARESETN",
              "m00_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN"
            ]
          }
        }
      }
    },
    "interface_nets": {
      "CLK_IN1_D_0_1": {
        "interface_ports": [
          "sys_clk",
          "clk_wiz_1/CLK_IN1_D"
        ]
      },
      "CLK_IN_D_0_1": {
        "interface_ports": [
          "pcie_refclk",
          "util_ds_buf_0/CLK_IN_D"
        ]
      },
      "S00_AXI_0_1": {
        "interface_ports": [
          "pcie_m_axi0",
          "axi_interconnect_1/S00_AXI"
        ]
      },
      "S00_AXI_1": {
        "interface_ports": [
          "axi_interconnect_0/S00_AXI",
          "microblaze_0/M_AXI_DP"
        ]
      },
      "S01_AXI_0_1": {
        "interface_ports": [
          "pcie_m_axi1",
          "axi_interconnect_1/S01_AXI"
        ]
      },
      "axi_interconnect_0_M00_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M00_AXI",
          "microblaze_0_axi_intc/s_axi"
        ]
      },
      "axi_interconnect_0_M01_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M01_AXI",
          "axi_timer_0/S_AXI"
        ]
      },
      "axi_interconnect_0_M02_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M02_AXI",
          "axi_uartlite_0/S_AXI"
        ]
      },
      "axi_interconnect_0_M03_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M03_AXI",
          "system_management_wiz_0/S_AXI_LITE"
        ]
      },
      "axi_interconnect_0_M04_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M04_AXI",
          "microblaze_0_axi_periph/S00_AXI"
        ]
      },
      "axi_interconnect_1_M00_AXI": {
        "interface_ports": [
          "axi_interconnect_1/M00_AXI",
          "xdma_0/S_AXI_B"
        ]
      },
      "axi_uartlite_0_UART": {
        "interface_ports": [
          "UART_0",
          "axi_uartlite_0/UART"
        ]
      },
      "microblaze_0_axi_periph_M00_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M00_AXI",
          "xdma_0/S_AXI_LITE"
        ]
      },
      "microblaze_0_axi_periph_M01_AXI": {
        "interface_ports": [
          "axil_descriptors",
          "microblaze_0_axi_periph/M01_AXI"
        ]
      },
      "microblaze_0_axi_periph_M02_AXI": {
        "interface_ports": [
          "axil_dma_ctrl0",
          "microblaze_0_axi_periph/M02_AXI"
        ]
      },
      "microblaze_0_axi_periph_M03_AXI": {
        "interface_ports": [
          "axil_dma_ctrl1",
          "microblaze_0_axi_periph/M03_AXI"
        ]
      },
      "microblaze_0_axi_periph_M04_AXI": {
        "interface_ports": [
          "axil_util",
          "microblaze_0_axi_periph/M04_AXI"
        ]
      },
      "microblaze_0_axi_periph_M05_AXI": {
        "interface_ports": [
          "axil_timing",
          "microblaze_0_axi_periph/M05_AXI"
        ]
      },
      "microblaze_0_axi_periph_M06_AXI": {
        "interface_ports": [
          "axil_data_gen",
          "microblaze_0_axi_periph/M06_AXI"
        ]
      },
      "microblaze_0_debug": {
        "interface_ports": [
          "mdm_1/MBDEBUG_0",
          "microblaze_0/DEBUG"
        ]
      },
      "microblaze_0_dlmb_1": {
        "interface_ports": [
          "microblaze_0/DLMB",
          "microblaze_0_local_memory/DLMB"
        ]
      },
      "microblaze_0_ilmb_1": {
        "interface_ports": [
          "microblaze_0/ILMB",
          "microblaze_0_local_memory/ILMB"
        ]
      },
      "microblaze_0_interrupt": {
        "interface_ports": [
          "microblaze_0/INTERRUPT",
          "microblaze_0_axi_intc/interrupt"
        ]
      },
      "xdma_0_M_AXI_B": {
        "interface_ports": [
          "microblaze_0_axi_periph/S01_AXI",
          "xdma_0/M_AXI_B"
        ]
      },
      "xdma_0_pcie_mgt": {
        "interface_ports": [
          "pcie_mgt_0",
          "xdma_0/pcie_mgt"
        ]
      }
    },
    "nets": {
      "S01_ARESETN_1": {
        "ports": [
          "xdma_0/axi_aresetn",
          "axi_pcie_aresetn",
          "microblaze_0_axi_periph/M01_ARESETN",
          "microblaze_0_axi_periph/M02_ARESETN",
          "microblaze_0_axi_periph/M03_ARESETN",
          "microblaze_0_axi_periph/S01_ARESETN",
          "microblaze_0_axi_periph/M05_ARESETN",
          "microblaze_0_axi_periph/M06_ARESETN",
          "microblaze_0_axi_periph/M04_ARESETN",
          "axi_interconnect_1/ARESETN",
          "axi_interconnect_1/S00_ARESETN",
          "axi_interconnect_1/M00_ARESETN",
          "axi_interconnect_1/S01_ARESETN"
        ]
      },
      "axi_timer_0_interrupt": {
        "ports": [
          "axi_timer_0/interrupt",
          "microblaze_0_xlconcat/In1"
        ]
      },
      "axi_uartlite_0_interrupt": {
        "ports": [
          "axi_uartlite_0/interrupt",
          "microblaze_0_xlconcat/In0"
        ]
      },
      "clk_wiz_1_locked": {
        "ports": [
          "clk_wiz_1/locked",
          "rst_clk_wiz_1_100M/dcm_locked"
        ]
      },
      "mdm_1_debug_sys_rst": {
        "ports": [
          "mdm_1/Debug_SYS_Rst",
          "rst_clk_wiz_1_100M/mb_debug_sys_rst"
        ]
      },
      "microblaze_0_Clk": {
        "ports": [
          "clk_wiz_1/clk_out1",
          "axil_clk",
          "axi_interconnect_0/ACLK",
          "axi_interconnect_0/M00_ACLK",
          "axi_interconnect_0/M01_ACLK",
          "axi_interconnect_0/M02_ACLK",
          "axi_interconnect_0/M03_ACLK",
          "axi_interconnect_0/M04_ACLK",
          "axi_interconnect_0/S00_ACLK",
          "axi_timer_0/s_axi_aclk",
          "axi_uartlite_0/s_axi_aclk",
          "microblaze_0/Clk",
          "microblaze_0_axi_intc/processor_clk",
          "microblaze_0_axi_intc/s_axi_aclk",
          "microblaze_0_axi_periph/S00_ACLK",
          "microblaze_0_local_memory/LMB_Clk",
          "rst_clk_wiz_1_100M/slowest_sync_clk",
          "system_management_wiz_0/s_axi_aclk"
        ]
      },
      "microblaze_0_intr": {
        "ports": [
          "microblaze_0_xlconcat/dout",
          "microblaze_0_axi_intc/intr"
        ]
      },
      "rst_clk_wiz_1_100M_bus_struct_reset": {
        "ports": [
          "rst_clk_wiz_1_100M/bus_struct_reset",
          "microblaze_0_local_memory/SYS_Rst"
        ]
      },
      "rst_clk_wiz_1_100M_mb_reset": {
        "ports": [
          "rst_clk_wiz_1_100M/mb_reset",
          "microblaze_0/Reset",
          "microblaze_0_axi_intc/processor_rst"
        ]
      },
      "rst_clk_wiz_1_100M_peripheral_aresetn": {
        "ports": [
          "rst_clk_wiz_1_100M/peripheral_aresetn",
          "axil_resetn",
          "axi_interconnect_0/ARESETN",
          "axi_interconnect_0/M00_ARESETN",
          "axi_interconnect_0/M01_ARESETN",
          "axi_interconnect_0/M02_ARESETN",
          "axi_interconnect_0/M03_ARESETN",
          "axi_interconnect_0/M04_ARESETN",
          "axi_interconnect_0/S00_ARESETN",
          "axi_timer_0/s_axi_aresetn",
          "axi_uartlite_0/s_axi_aresetn",
          "microblaze_0_axi_intc/s_axi_aresetn",
          "microblaze_0_axi_periph/S00_ARESETN",
          "system_management_wiz_0/s_axi_aresetn"
        ]
      },
      "sys_rst_n_0_1": {
        "ports": [
          "pcie_rstn",
          "xdma_0/sys_rst_n"
        ]
      },
      "system_management_wiz_0_ip2intc_irpt": {
        "ports": [
          "system_management_wiz_0/ip2intc_irpt",
          "microblaze_0_xlconcat/In2"
        ]
      },
      "usr_irq_req_0_1": {
        "ports": [
          "usr_irq_req",
          "xdma_0/usr_irq_req"
        ]
      },
      "util_ds_buf_0_IBUF_DS_ODIV2": {
        "ports": [
          "util_ds_buf_0/IBUF_DS_ODIV2",
          "xdma_0/sys_clk"
        ]
      },
      "util_ds_buf_0_IBUF_OUT": {
        "ports": [
          "util_ds_buf_0/IBUF_OUT",
          "xdma_0/sys_clk_gt"
        ]
      },
      "xdma_0_axi_aclk": {
        "ports": [
          "xdma_0/axi_aclk",
          "axi_pcie_clk",
          "microblaze_0_axi_periph/M00_ACLK",
          "microblaze_0_axi_periph/M01_ACLK",
          "microblaze_0_axi_periph/M02_ACLK",
          "microblaze_0_axi_periph/M03_ACLK",
          "microblaze_0_axi_periph/S01_ACLK",
          "microblaze_0_axi_periph/M05_ACLK",
          "microblaze_0_axi_periph/M06_ACLK",
          "microblaze_0_axi_periph/M04_ACLK",
          "microblaze_0_axi_periph/ACLK",
          "axi_interconnect_1/ACLK",
          "axi_interconnect_1/S00_ACLK",
          "axi_interconnect_1/M00_ACLK",
          "axi_interconnect_1/S01_ACLK"
        ]
      },
      "xdma_0_axi_ctl_aresetn": {
        "ports": [
          "xdma_0/axi_ctl_aresetn",
          "microblaze_0_axi_periph/M00_ARESETN",
          "microblaze_0_axi_periph/ARESETN"
        ]
      },
      "xdma_0_cfg_ltssm_state": {
        "ports": [
          "xdma_0/cfg_ltssm_state",
          "pcie_cfg_ltssm_state"
        ]
      },
      "xdma_0_user_lnk_up": {
        "ports": [
          "xdma_0/user_lnk_up",
          "pcie_user_lnk_up"
        ]
      },
      "xlconstant_0_dout": {
        "ports": [
          "xlconstant_0/dout",
          "rst_clk_wiz_1_100M/aux_reset_in",
          "rst_clk_wiz_1_100M/ext_reset_in"
        ]
      },
      "zynq_ultra_ps_e_0_pl_clk0": {
        "ports": [
          "zynq_ultra_ps_e_0/pl_clk0",
          "zynq_ultra_ps_e_0/maxihpm0_lpd_aclk"
        ]
      }
    },
    "addressing": {
      "/": {
        "address_spaces": {
          "pcie_m_axi0": {
            "range": "1T",
            "width": "40",
            "segments": {
              "SEG_xdma_0_BAR0": {
                "address_block": "/xdma_0/S_AXI_B/BAR0",
                "offset": "0x0000000000",
                "range": "1T",
                "offset_base_param": "axibar_0",
                "offset_high_param": "axibar_highaddr_0"
              }
            }
          },
          "pcie_m_axi1": {
            "range": "1T",
            "width": "40",
            "segments": {
              "SEG_xdma_0_BAR0": {
                "address_block": "/xdma_0/S_AXI_B/BAR0",
                "offset": "0x0000000000",
                "range": "1T",
                "offset_base_param": "axibar_0",
                "offset_high_param": "axibar_highaddr_0"
              }
            }
          }
        },
        "memory_maps": {
          "axil_data_gen": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_descriptors": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_dma_ctrl0": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_dma_ctrl1": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_timing": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_util": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          }
        }
      },
      "/microblaze_0": {
        "address_spaces": {
          "Data": {
            "segments": {
              "SEG_axi_timer_0_Reg": {
                "address_block": "/axi_timer_0/S_AXI/Reg",
                "offset": "0x40000000",
                "range": "64K"
              },
              "SEG_axi_uartlite_0_Reg": {
                "address_block": "/axi_uartlite_0/S_AXI/Reg",
                "offset": "0x40010000",
                "range": "64K"
              },
              "SEG_axil_data_gen_Reg": {
                "address_block": "/axil_data_gen/Reg",
                "offset": "0x80120000",
                "range": "64K"
              },
              "SEG_axil_descriptors_Reg": {
                "address_block": "/axil_descriptors/Reg",
                "offset": "0x80000000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl0_Reg": {
                "address_block": "/axil_dma_ctrl0/Reg",
                "offset": "0x81000000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl1_Reg": {
                "address_block": "/axil_dma_ctrl1/Reg",
                "offset": "0x81010000",
                "range": "64K"
              },
              "SEG_axil_timing_Reg": {
                "address_block": "/axil_timing/Reg",
                "offset": "0x80110000",
                "range": "64K"
              },
              "SEG_axil_util_Reg": {
                "address_block": "/axil_util/Reg",
                "offset": "0x80100000",
                "range": "64K"
              },
              "SEG_dlmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x00000000",
                "range": "32K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_microblaze_0_axi_intc_Reg": {
                "address_block": "/microblaze_0_axi_intc/S_AXI/Reg",
                "offset": "0x40020000",
                "range": "64K"
              },
              "SEG_system_management_wiz_0_Reg": {
                "address_block": "/system_management_wiz_0/S_AXI_LITE/Reg",
                "offset": "0x40030000",
                "range": "64K"
              },
              "SEG_xdma_0_CTL0": {
                "address_block": "/xdma_0/S_AXI_LITE/CTL0",
                "offset": "0x83000000",
                "range": "16M",
                "offset_base_param": "baseaddr",
                "offset_high_param": "highaddr"
              }
            }
          },
          "Instruction": {
            "segments": {
              "SEG_ilmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x00000000",
                "range": "32K",
                "offset_high_param": "C_HIGHADDR"
              }
            }
          }
        }
      },
      "/xdma_0": {
        "address_spaces": {
          "M_AXI_B": {
            "segments": {
              "SEG_axil_data_gen_Reg": {
                "address_block": "/axil_data_gen/Reg",
                "offset": "0x0080120000",
                "range": "64K"
              },
              "SEG_axil_descriptors_Reg": {
                "address_block": "/axil_descriptors/Reg",
                "offset": "0x0080000000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl0_Reg": {
                "address_block": "/axil_dma_ctrl0/Reg",
                "offset": "0x0081000000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl1_Reg": {
                "address_block": "/axil_dma_ctrl1/Reg",
                "offset": "0x0081010000",
                "range": "64K"
              },
              "SEG_axil_timing_Reg": {
                "address_block": "/axil_timing/Reg",
                "offset": "0x0080110000",
                "range": "64K"
              },
              "SEG_axil_util_Reg": {
                "address_block": "/axil_util/Reg",
                "offset": "0x0080100000",
                "range": "64K"
              },
              "SEG_xdma_0_CTL0": {
                "address_block": "/xdma_0/S_AXI_LITE/CTL0",
                "offset": "0x0083000000",
                "range": "16M",
                "offset_base_param": "baseaddr",
                "offset_high_param": "highaddr"
              }
            }
          }
        }
      }
    },
    "elf_association": {
      "file": {
        "name": "/home/bkiedinger/project_1/vitis/app/Debug/app.elf",
        "type": "ELF",
        "checksum": "3422405275",
        "IsVisible": "1",
        "ScopedToRef": "design_1",
        "ScopedToCell": [
          "microblaze_0"
        ],
        "UsedIn": [
          "implementation"
        ]
      }
    }
  }
}