{
  "design": {
    "design_info": {
      "boundary_crc": "0x7C180B25792A5F3F",
      "device": "xcku15p-ffve1517-2-i",
      "gen_directory": "../../../../project_1.gen/sources_1/bd/design_1",
      "name": "design_1",
      "rev_ctrl_bd_flag": "RevCtrlBdOff",
      "synth_flow_mode": "Singular",
      "tool_version": "2022.2",
      "validated": "true"
    },
    "design_tree": {
      "microblaze_0_local_memory": {
        "dlmb_bram_if_cntlr": "",
        "dlmb_v10": "",
        "ilmb_bram_if_cntlr": "",
        "ilmb_v10": "",
        "lmb_bram": ""
      },
      "axi_interconnect_0": {
        "xbar": "",
        "s00_couplers": {},
        "m00_couplers": {},
        "m01_couplers": {},
        "m02_couplers": {},
        "m03_couplers": {},
        "m04_couplers": {}
      },
      "axi_interconnect_1": {
        "xbar": "",
        "s00_couplers": {
          "s00_data_fifo": "",
          "auto_us": ""
        },
        "s01_couplers": {
          "s01_data_fifo": "",
          "auto_us": ""
        },
        "s02_couplers": {
          "s02_data_fifo": "",
          "auto_us": ""
        },
        "s03_couplers": {
          "s03_data_fifo": "",
          "auto_us": ""
        },
        "m00_couplers": {}
      },
      "axi_timer_0": "",
      "clk_wiz_1": "",
      "mdm_1": "",
      "microblaze_0": "",
      "microblaze_0_axi_intc": "",
      "microblaze_0_axi_periph": {
        "xbar": "",
        "s00_couplers": {
          "auto_cc": ""
        },
        "s01_couplers": {
          "auto_ds": "",
          "auto_pc": ""
        },
        "m00_couplers": {},
        "m01_couplers": {},
        "m02_couplers": {},
        "m03_couplers": {},
        "m04_couplers": {},
        "m05_couplers": {},
        "m06_couplers": {},
        "m07_couplers": {},
        "m08_couplers": {}
      },
      "microblaze_0_xlconcat": "",
      "rst_clk_wiz_1_100M": "",
      "system_management_wiz_0": "",
      "util_ds_buf_0": "",
      "xdma_0": "",
      "xlconstant_0": ""
    },
    "interface_ports": {
      "axil_descriptors": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_descriptors",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_descriptors_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_descriptors_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_descriptors_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_descriptors_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_descriptors_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_descriptors_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_descriptors_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_descriptors_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_descriptors_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_descriptors_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_descriptors_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_descriptors_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_descriptors_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_descriptors_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_descriptors_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_descriptors_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_descriptors_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_descriptors_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_descriptors_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_dma_ctrl0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_dma_ctrl0",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_dma_ctrl0_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_dma_ctrl0_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_dma_ctrl0_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_dma_ctrl0_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_dma_ctrl0_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_dma_ctrl0_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_dma_ctrl0_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_dma_ctrl0_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_dma_ctrl0_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_dma_ctrl0_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_dma_ctrl0_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_dma_ctrl0_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_dma_ctrl0_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_dma_ctrl0_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_dma_ctrl0_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_dma_ctrl0_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_dma_ctrl0_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_dma_ctrl0_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_dma_ctrl0_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_dma_ctrl1": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_dma_ctrl1",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_dma_ctrl1_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_dma_ctrl1_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_dma_ctrl1_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_dma_ctrl1_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_dma_ctrl1_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_dma_ctrl1_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_dma_ctrl1_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_dma_ctrl1_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_dma_ctrl1_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_dma_ctrl1_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_dma_ctrl1_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_dma_ctrl1_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_dma_ctrl1_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_dma_ctrl1_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_dma_ctrl1_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_dma_ctrl1_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_dma_ctrl1_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_dma_ctrl1_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_dma_ctrl1_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_util": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_util",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_util_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_util_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_util_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_util_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_util_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_util_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_util_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_util_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_util_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_util_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_util_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_util_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_util_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_util_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_util_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_util_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_util_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_util_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_util_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "pcie_mgt_0": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:pcie_7x_mgt:1.0",
        "vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0",
        "port_maps": {
          "rxn": {
            "physical_name": "pcie_mgt_0_rxn",
            "direction": "I",
            "left": "15",
            "right": "0"
          },
          "rxp": {
            "physical_name": "pcie_mgt_0_rxp",
            "direction": "I",
            "left": "15",
            "right": "0"
          },
          "txn": {
            "physical_name": "pcie_mgt_0_txn",
            "direction": "O",
            "left": "15",
            "right": "0"
          },
          "txp": {
            "physical_name": "pcie_mgt_0_txp",
            "direction": "O",
            "left": "15",
            "right": "0"
          }
        }
      },
      "pcie_refclk": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "default"
          }
        },
        "port_maps": {
          "CLK_P": {
            "physical_name": "pcie_refclk_clk_p",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "CLK_N": {
            "physical_name": "pcie_refclk_clk_n",
            "direction": "I",
            "left": "0",
            "right": "0"
          }
        }
      },
      "sys_clk": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000"
          }
        },
        "port_maps": {
          "CLK_N": {
            "physical_name": "sys_clk_clk_n",
            "direction": "I"
          },
          "CLK_P": {
            "physical_name": "sys_clk_clk_p",
            "direction": "I"
          }
        }
      },
      "axil_timing": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_timing",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_timing_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_timing_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_timing_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_timing_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_timing_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_timing_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_timing_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_timing_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_timing_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_timing_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_timing_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_timing_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_timing_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_timing_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_timing_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_timing_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_timing_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_timing_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_timing_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_data_gen": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "32"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2",
            "value_src": "default_prop"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_data_gen",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_data_gen_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_data_gen_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_data_gen_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_data_gen_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_data_gen_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_data_gen_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_data_gen_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_data_gen_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_data_gen_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_data_gen_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_data_gen_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_data_gen_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_data_gen_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_data_gen_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_data_gen_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_data_gen_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_data_gen_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_data_gen_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_data_gen_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "pcie_m_axi0": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0"
          },
          "AWUSER_WIDTH": {
            "value": "0"
          },
          "BUSER_WIDTH": {
            "value": "0"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "256"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1"
          },
          "HAS_BURST": {
            "value": "1"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "0"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1"
          },
          "HAS_WSTRB": {
            "value": "1"
          },
          "ID_WIDTH": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "256"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "16"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4"
          },
          "READ_WRITE_MODE": {
            "value": "WRITE_ONLY"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "RUSER_WIDTH": {
            "value": "0"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_WIDTH": {
            "value": "0"
          }
        },
        "address_space_ref": "pcie_m_axi0",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x00FFFFFFFFFF",
          "width": "40"
        },
        "port_maps": {
          "AWADDR": {
            "physical_name": "pcie_m_axi0_awaddr",
            "direction": "I",
            "left": "39",
            "right": "0"
          },
          "AWLEN": {
            "physical_name": "pcie_m_axi0_awlen",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "AWSIZE": {
            "physical_name": "pcie_m_axi0_awsize",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWBURST": {
            "physical_name": "pcie_m_axi0_awburst",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "AWLOCK": {
            "physical_name": "pcie_m_axi0_awlock",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWCACHE": {
            "physical_name": "pcie_m_axi0_awcache",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "pcie_m_axi0_awprot",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWQOS": {
            "physical_name": "pcie_m_axi0_awqos",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "pcie_m_axi0_awvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "pcie_m_axi0_awready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "pcie_m_axi0_wdata",
            "direction": "I",
            "left": "255",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "pcie_m_axi0_wstrb",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "WLAST": {
            "physical_name": "pcie_m_axi0_wlast",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "pcie_m_axi0_wvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "pcie_m_axi0_wready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "pcie_m_axi0_bresp",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "pcie_m_axi0_bvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "pcie_m_axi0_bready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREGION": {
            "physical_name": "pcie_m_axi0_awregion",
            "direction": "I",
            "left": "3",
            "right": "0"
          }
        }
      },
      "pcie_m_axi1": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0"
          },
          "AWUSER_WIDTH": {
            "value": "0"
          },
          "BUSER_WIDTH": {
            "value": "0"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "256"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1"
          },
          "HAS_BURST": {
            "value": "1"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "0"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1"
          },
          "HAS_WSTRB": {
            "value": "1"
          },
          "ID_WIDTH": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "256"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "16"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4"
          },
          "READ_WRITE_MODE": {
            "value": "WRITE_ONLY"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "RUSER_WIDTH": {
            "value": "0"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_WIDTH": {
            "value": "0"
          }
        },
        "address_space_ref": "pcie_m_axi1",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x00FFFFFFFFFF",
          "width": "40"
        },
        "port_maps": {
          "AWADDR": {
            "physical_name": "pcie_m_axi1_awaddr",
            "direction": "I",
            "left": "39",
            "right": "0"
          },
          "AWLEN": {
            "physical_name": "pcie_m_axi1_awlen",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "AWSIZE": {
            "physical_name": "pcie_m_axi1_awsize",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWBURST": {
            "physical_name": "pcie_m_axi1_awburst",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "AWLOCK": {
            "physical_name": "pcie_m_axi1_awlock",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWCACHE": {
            "physical_name": "pcie_m_axi1_awcache",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "pcie_m_axi1_awprot",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWQOS": {
            "physical_name": "pcie_m_axi1_awqos",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "pcie_m_axi1_awvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "pcie_m_axi1_awready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "pcie_m_axi1_wdata",
            "direction": "I",
            "left": "255",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "pcie_m_axi1_wstrb",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "WLAST": {
            "physical_name": "pcie_m_axi1_wlast",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "pcie_m_axi1_wvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "pcie_m_axi1_wready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "pcie_m_axi1_bresp",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "pcie_m_axi1_bvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "pcie_m_axi1_bready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWREGION": {
            "physical_name": "pcie_m_axi1_awregion",
            "direction": "I",
            "left": "3",
            "right": "0"
          }
        }
      },
      "pcie_m_axi2": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0"
          },
          "AWUSER_WIDTH": {
            "value": "0"
          },
          "BUSER_WIDTH": {
            "value": "0"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "256"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1"
          },
          "HAS_BURST": {
            "value": "1"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "0"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1"
          },
          "HAS_WSTRB": {
            "value": "1"
          },
          "ID_WIDTH": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "256"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "16"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4"
          },
          "READ_WRITE_MODE": {
            "value": "WRITE_ONLY"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "RUSER_WIDTH": {
            "value": "0"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_WIDTH": {
            "value": "0"
          }
        },
        "address_space_ref": "pcie_m_axi2",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x00FFFFFFFFFF",
          "width": "40"
        },
        "port_maps": {
          "AWADDR": {
            "physical_name": "pcie_m_axi2_awaddr",
            "direction": "I",
            "left": "39",
            "right": "0"
          },
          "AWLEN": {
            "physical_name": "pcie_m_axi2_awlen",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "AWSIZE": {
            "physical_name": "pcie_m_axi2_awsize",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWBURST": {
            "physical_name": "pcie_m_axi2_awburst",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "AWLOCK": {
            "physical_name": "pcie_m_axi2_awlock",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWCACHE": {
            "physical_name": "pcie_m_axi2_awcache",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "pcie_m_axi2_awprot",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWQOS": {
            "physical_name": "pcie_m_axi2_awqos",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "pcie_m_axi2_awvalid",
            "direction": "I"
          },
          "AWREADY": {
            "physical_name": "pcie_m_axi2_awready",
            "direction": "O"
          },
          "WDATA": {
            "physical_name": "pcie_m_axi2_wdata",
            "direction": "I",
            "left": "255",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "pcie_m_axi2_wstrb",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "WLAST": {
            "physical_name": "pcie_m_axi2_wlast",
            "direction": "I"
          },
          "WVALID": {
            "physical_name": "pcie_m_axi2_wvalid",
            "direction": "I"
          },
          "WREADY": {
            "physical_name": "pcie_m_axi2_wready",
            "direction": "O"
          },
          "BRESP": {
            "physical_name": "pcie_m_axi2_bresp",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "pcie_m_axi2_bvalid",
            "direction": "O"
          },
          "BREADY": {
            "physical_name": "pcie_m_axi2_bready",
            "direction": "I"
          },
          "AWREGION": {
            "physical_name": "pcie_m_axi2_awregion",
            "direction": "I",
            "left": "3",
            "right": "0"
          }
        }
      },
      "pcie_m_axi3": {
        "mode": "Slave",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0"
          },
          "AWUSER_WIDTH": {
            "value": "0"
          },
          "BUSER_WIDTH": {
            "value": "0"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "256"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1"
          },
          "HAS_BURST": {
            "value": "1"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "0"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1"
          },
          "HAS_WSTRB": {
            "value": "1"
          },
          "ID_WIDTH": {
            "value": "0"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "256"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "16"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4"
          },
          "READ_WRITE_MODE": {
            "value": "WRITE_ONLY"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "RUSER_WIDTH": {
            "value": "0"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_WIDTH": {
            "value": "0"
          }
        },
        "address_space_ref": "pcie_m_axi3",
        "base_address": {
          "minimum": "0x00000000",
          "maximum": "0x00FFFFFFFFFF",
          "width": "40"
        },
        "port_maps": {
          "AWADDR": {
            "physical_name": "pcie_m_axi3_awaddr",
            "direction": "I",
            "left": "39",
            "right": "0"
          },
          "AWLEN": {
            "physical_name": "pcie_m_axi3_awlen",
            "direction": "I",
            "left": "7",
            "right": "0"
          },
          "AWSIZE": {
            "physical_name": "pcie_m_axi3_awsize",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWBURST": {
            "physical_name": "pcie_m_axi3_awburst",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "AWLOCK": {
            "physical_name": "pcie_m_axi3_awlock",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "AWCACHE": {
            "physical_name": "pcie_m_axi3_awcache",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "pcie_m_axi3_awprot",
            "direction": "I",
            "left": "2",
            "right": "0"
          },
          "AWQOS": {
            "physical_name": "pcie_m_axi3_awqos",
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "pcie_m_axi3_awvalid",
            "direction": "I"
          },
          "AWREADY": {
            "physical_name": "pcie_m_axi3_awready",
            "direction": "O"
          },
          "WDATA": {
            "physical_name": "pcie_m_axi3_wdata",
            "direction": "I",
            "left": "255",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "pcie_m_axi3_wstrb",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "WLAST": {
            "physical_name": "pcie_m_axi3_wlast",
            "direction": "I"
          },
          "WVALID": {
            "physical_name": "pcie_m_axi3_wvalid",
            "direction": "I"
          },
          "WREADY": {
            "physical_name": "pcie_m_axi3_wready",
            "direction": "O"
          },
          "BRESP": {
            "physical_name": "pcie_m_axi3_bresp",
            "direction": "O",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "pcie_m_axi3_bvalid",
            "direction": "O"
          },
          "BREADY": {
            "physical_name": "pcie_m_axi3_bready",
            "direction": "I"
          },
          "AWREGION": {
            "physical_name": "pcie_m_axi3_awregion",
            "direction": "I",
            "left": "3",
            "right": "0"
          }
        }
      },
      "axil_dma_ctrl2": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_dma_ctrl2",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_dma_ctrl2_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_dma_ctrl2_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_dma_ctrl2_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_dma_ctrl2_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_dma_ctrl2_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_dma_ctrl2_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_dma_ctrl2_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_dma_ctrl2_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_dma_ctrl2_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_dma_ctrl2_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_dma_ctrl2_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_dma_ctrl2_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_dma_ctrl2_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_dma_ctrl2_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_dma_ctrl2_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_dma_ctrl2_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_dma_ctrl2_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_dma_ctrl2_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_dma_ctrl2_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      },
      "axil_dma_ctrl3": {
        "mode": "Master",
        "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
          "ADDR_WIDTH": {
            "value": "40"
          },
          "ARUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "AWUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "BUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "DATA_WIDTH": {
            "value": "32"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "HAS_BRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_BURST": {
            "value": "0"
          },
          "HAS_CACHE": {
            "value": "0"
          },
          "HAS_LOCK": {
            "value": "0"
          },
          "HAS_PROT": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_QOS": {
            "value": "0"
          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_RRESP": {
            "value": "1",
            "value_src": "const_prop"
          },
          "HAS_WSTRB": {
            "value": "1",
            "value_src": "const_prop"
          },
          "ID_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "MAX_BURST_LENGTH": {
            "value": "1",
            "value_src": "ip_prop"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_READ_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "1",
            "value_src": "default"
          },
          "NUM_WRITE_THREADS": {
            "value": "1",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          },
          "PROTOCOL": {
            "value": "AXI4LITE"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE",
            "value_src": "default"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "RUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          },
          "SUPPORTS_NARROW_BURST": {
            "value": "0",
            "value_src": "ip_prop"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0",
            "value_src": "default"
          },
          "WUSER_WIDTH": {
            "value": "0",
            "value_src": "default"
          }
        },
        "memory_map_ref": "axil_dma_ctrl3",
        "port_maps": {
          "AWADDR": {
            "physical_name": "axil_dma_ctrl3_awaddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "AWPROT": {
            "physical_name": "axil_dma_ctrl3_awprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "AWVALID": {
            "physical_name": "axil_dma_ctrl3_awvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "AWREADY": {
            "physical_name": "axil_dma_ctrl3_awready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "WDATA": {
            "physical_name": "axil_dma_ctrl3_wdata",
            "direction": "O",
            "left": "31",
            "right": "0"
          },
          "WSTRB": {
            "physical_name": "axil_dma_ctrl3_wstrb",
            "direction": "O",
            "left": "3",
            "right": "0"
          },
          "WVALID": {
            "physical_name": "axil_dma_ctrl3_wvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "WREADY": {
            "physical_name": "axil_dma_ctrl3_wready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BRESP": {
            "physical_name": "axil_dma_ctrl3_bresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "BVALID": {
            "physical_name": "axil_dma_ctrl3_bvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "BREADY": {
            "physical_name": "axil_dma_ctrl3_bready",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARADDR": {
            "physical_name": "axil_dma_ctrl3_araddr",
            "direction": "O",
            "left": "39",
            "right": "0"
          },
          "ARPROT": {
            "physical_name": "axil_dma_ctrl3_arprot",
            "direction": "O",
            "left": "2",
            "right": "0"
          },
          "ARVALID": {
            "physical_name": "axil_dma_ctrl3_arvalid",
            "direction": "O",
            "left": "0",
            "right": "0"
          },
          "ARREADY": {
            "physical_name": "axil_dma_ctrl3_arready",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RDATA": {
            "physical_name": "axil_dma_ctrl3_rdata",
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "RRESP": {
            "physical_name": "axil_dma_ctrl3_rresp",
            "direction": "I",
            "left": "1",
            "right": "0"
          },
          "RVALID": {
            "physical_name": "axil_dma_ctrl3_rvalid",
            "direction": "I",
            "left": "0",
            "right": "0"
          },
          "RREADY": {
            "physical_name": "axil_dma_ctrl3_rready",
            "direction": "O",
            "left": "0",
            "right": "0"
          }
        }
      }
    },
    "ports": {
      "axi_pcie_aresetn": {
        "type": "rst",
        "direction": "O",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "const_prop"
          }
        }
      },
      "axi_pcie_clk": {
        "type": "clk",
        "direction": "O",
        "parameters": {
          "ASSOCIATED_BUSIF": {
            "value": "axil_dma_ctrl1:axil_dma_ctrl0:axil_descriptors:axil_timing:axil_data_gen:axil_util:pcie_m_axi0:pcie_m_axi1:pcie_m_axi2:pcie_m_axi3:axil_dma_ctrl2:axil_dma_ctrl3"
          },
          "CLK_DOMAIN": {
            "value": "design_1_xdma_0_0_axi_aclk",
            "value_src": "default_prop"
          },
          "FREQ_HZ": {
            "value": "250000000",
            "value_src": "user_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "default"
          }
        }
      },
      "axil_clk": {
        "type": "clk",
        "direction": "O",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "design_1_clk_wiz_1_0_clk_out1",
            "value_src": "default_prop"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "ip_prop"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.0",
            "value_src": "ip_prop"
          }
        }
      },
      "axil_resetn": {
        "type": "rst",
        "direction": "O",
        "left": "0",
        "right": "0",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "const_prop"
          }
        }
      },
      "pcie_cfg_ltssm_state": {
        "direction": "O",
        "left": "5",
        "right": "0"
      },
      "pcie_rstn": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW"
          }
        }
      },
      "pcie_user_lnk_up": {
        "direction": "O"
      },
      "usr_irq_req": {
        "direction": "I",
        "left": "0",
        "right": "0"
      }
    },
    "components": {
      "microblaze_0_local_memory": {
        "interface_ports": {
          "DLMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          },
          "ILMB": {
            "mode": "MirroredMaster",
            "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0",
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0"
          }
        },
        "ports": {
          "LMB_Clk": {
            "type": "clk",
            "direction": "I"
          },
          "SYS_Rst": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "dlmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "design_1_dlmb_bram_if_cntlr_0",
            "xci_path": "ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            },
            "hdl_attributes": {
              "BMM_INFO_ADDRESS_SPACE": {
                "value": "byte  0x00000000 32 > design_1 microblaze_0_local_memory/lmb_bram",
                "value_src": "default"
              },
              "KEEP_HIERARCHY": {
                "value": "yes",
                "value_src": "default"
              }
            }
          },
          "dlmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "design_1_dlmb_v10_0",
            "xci_path": "ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/dlmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "ilmb_bram_if_cntlr": {
            "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
            "xci_name": "design_1_ilmb_bram_if_cntlr_0",
            "xci_path": "ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_bram_if_cntlr",
            "parameters": {
              "C_ECC": {
                "value": "0"
              }
            }
          },
          "ilmb_v10": {
            "vlnv": "xilinx.com:ip:lmb_v10:3.0",
            "xci_name": "design_1_ilmb_v10_0",
            "xci_path": "ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/ilmb_v10",
            "interface_ports": {
              "LMB_M": {
                "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
                "mode": "MirroredMaster",
                "bridges": [
                  "LMB_Sl_0"
                ]
              }
            }
          },
          "lmb_bram": {
            "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
            "xci_name": "design_1_lmb_bram_0",
            "xci_path": "ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci",
            "inst_hier_path": "microblaze_0_local_memory/lmb_bram",
            "parameters": {
              "Enable_B": {
                "value": "Use_ENB_Pin"
              },
              "Memory_Type": {
                "value": "True_Dual_Port_RAM"
              },
              "Port_B_Clock": {
                "value": "100"
              },
              "Port_B_Enable_Rate": {
                "value": "100"
              },
              "Port_B_Write_Rate": {
                "value": "50"
              },
              "Use_RSTB_Pin": {
                "value": "true"
              },
              "use_bram_block": {
                "value": "BRAM_Controller"
              }
            }
          }
        },
        "interface_nets": {
          "microblaze_0_dlmb": {
            "interface_ports": [
              "DLMB",
              "dlmb_v10/LMB_M"
            ]
          },
          "microblaze_0_dlmb_bus": {
            "interface_ports": [
              "dlmb_bram_if_cntlr/SLMB",
              "dlmb_v10/LMB_Sl_0"
            ]
          },
          "microblaze_0_dlmb_cntlr": {
            "interface_ports": [
              "dlmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTA"
            ]
          },
          "microblaze_0_ilmb": {
            "interface_ports": [
              "ILMB",
              "ilmb_v10/LMB_M"
            ]
          },
          "microblaze_0_ilmb_bus": {
            "interface_ports": [
              "ilmb_bram_if_cntlr/SLMB",
              "ilmb_v10/LMB_Sl_0"
            ]
          },
          "microblaze_0_ilmb_cntlr": {
            "interface_ports": [
              "ilmb_bram_if_cntlr/BRAM_PORT",
              "lmb_bram/BRAM_PORTB"
            ]
          }
        },
        "nets": {
          "SYS_Rst_1": {
            "ports": [
              "SYS_Rst",
              "dlmb_bram_if_cntlr/LMB_Rst",
              "dlmb_v10/SYS_Rst",
              "ilmb_bram_if_cntlr/LMB_Rst",
              "ilmb_v10/SYS_Rst"
            ]
          },
          "microblaze_0_Clk": {
            "ports": [
              "LMB_Clk",
              "dlmb_bram_if_cntlr/LMB_Clk",
              "dlmb_v10/LMB_Clk",
              "ilmb_bram_if_cntlr/LMB_Clk",
              "ilmb_v10/LMB_Clk"
            ]
          }
        }
      },
      "axi_interconnect_0": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci",
        "inst_hier_path": "axi_interconnect_0",
        "xci_name": "design_1_axi_interconnect_0_0",
        "parameters": {
          "NUM_MI": {
            "value": "5"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M02_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M03_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M04_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M01_ARESETN"
              }
            }
          },
          "M01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M02_ARESETN"
              }
            }
          },
          "M02_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M03_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M03_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M03_ARESETN"
              }
            }
          },
          "M03_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M04_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M04_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M04_ARESETN"
              }
            }
          },
          "M04_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "design_1_xbar_3",
            "xci_path": "ip/design_1_xbar_3/design_1_xbar_3.xci",
            "inst_hier_path": "axi_interconnect_0/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "5"
              },
              "NUM_SI": {
                "value": "1"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI",
                  "M01_AXI",
                  "M02_AXI",
                  "M03_AXI",
                  "M04_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "s00_couplers_to_s00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m01_couplers_to_m01_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m02_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m02_couplers_to_m02_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m03_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m03_couplers_to_m03_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m04_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m04_couplers_to_m04_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "axi_interconnect_0_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "m00_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "m01_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M01_AXI",
              "m01_couplers/M_AXI"
            ]
          },
          "m02_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M02_AXI",
              "m02_couplers/M_AXI"
            ]
          },
          "m03_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M03_AXI",
              "m03_couplers/M_AXI"
            ]
          },
          "m04_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M04_AXI",
              "m04_couplers/M_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "xbar_to_m01_couplers": {
            "interface_ports": [
              "xbar/M01_AXI",
              "m01_couplers/S_AXI"
            ]
          },
          "xbar_to_m02_couplers": {
            "interface_ports": [
              "xbar/M02_AXI",
              "m02_couplers/S_AXI"
            ]
          },
          "xbar_to_m03_couplers": {
            "interface_ports": [
              "xbar/M03_AXI",
              "m03_couplers/S_AXI"
            ]
          },
          "xbar_to_m04_couplers": {
            "interface_ports": [
              "xbar/M04_AXI",
              "m04_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "axi_interconnect_0_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/S_ACLK",
              "s00_couplers/M_ACLK",
              "m00_couplers/M_ACLK",
              "m01_couplers/M_ACLK",
              "m02_couplers/M_ACLK",
              "m03_couplers/M_ACLK",
              "m04_couplers/M_ACLK",
              "m00_couplers/S_ACLK",
              "m01_couplers/S_ACLK",
              "m02_couplers/S_ACLK",
              "m03_couplers/S_ACLK",
              "m04_couplers/S_ACLK"
            ]
          },
          "axi_interconnect_0_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/S_ARESETN",
              "s00_couplers/M_ARESETN",
              "m00_couplers/M_ARESETN",
              "m01_couplers/M_ARESETN",
              "m02_couplers/M_ARESETN",
              "m03_couplers/M_ARESETN",
              "m04_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN",
              "m01_couplers/S_ARESETN",
              "m02_couplers/S_ARESETN",
              "m03_couplers/S_ARESETN",
              "m04_couplers/S_ARESETN"
            ]
          }
        }
      },
      "axi_interconnect_1": {
        "vlnv": "xilinx.com:ip:axi_interconnect:2.1",
        "xci_path": "ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci",
        "inst_hier_path": "axi_interconnect_1",
        "xci_name": "design_1_axi_interconnect_1_0",
        "parameters": {
          "M00_HAS_DATA_FIFO": {
            "value": "0"
          },
          "NUM_MI": {
            "value": "1"
          },
          "NUM_SI": {
            "value": "4"
          },
          "S00_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S01_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S02_HAS_DATA_FIFO": {
            "value": "1"
          },
          "S03_HAS_DATA_FIFO": {
            "value": "1"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "S01_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "S02_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          },
          "S03_AXI": {
            "mode": "Slave",
            "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "design_1_xdma_0_0_axi_aclk",
                "value_src": "undefined"
              }
            }
          }
        },
        "ports": {
          "ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_RESET": {
                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S01_ARESETN"
              }
            }
          },
          "S01_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
              }
            }
          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S02_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S02_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S02_ARESETN"
              }
            }
          },
          "S02_ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S03_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S03_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S03_ARESETN"
              }
            }
          },
          "S03_ARESETN": {
            "type": "rst",
            "direction": "I"
          }
        },
        "components": {
          "xbar": {
            "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
            "xci_name": "design_1_xbar_4",
            "xci_path": "ip/design_1_xbar_4/design_1_xbar_4.xci",
            "inst_hier_path": "axi_interconnect_1/xbar",
            "parameters": {
              "NUM_MI": {
                "value": "1"
              },
              "NUM_SI": {
                "value": "4"
              },
              "STRATEGY": {
                "value": "0"
              }
            },
            "interface_ports": {
              "S00_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S01_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S02_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              },
              "S03_AXI": {
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                "mode": "Slave",
                "bridges": [
                  "M00_AXI"
                ]
              }
            }
          },
          "s00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s00_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "design_1_s00_data_fifo_0",
                "xci_path": "ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_1/s00_couplers/s00_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_us": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "design_1_auto_us_0",
                "xci_path": "ip/design_1_auto_us_0/design_1_auto_us_0.xci",
                "inst_hier_path": "axi_interconnect_1/s00_couplers/auto_us",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "512"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "256"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_us_to_s00_data_fifo": {
                "interface_ports": [
                  "s00_data_fifo/S_AXI",
                  "auto_us/M_AXI"
                ]
              },
              "s00_couplers_to_auto_us": {
                "interface_ports": [
                  "S_AXI",
                  "auto_us/S_AXI"
                ]
              },
              "s00_data_fifo_to_s00_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s00_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s00_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s00_data_fifo/aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_us/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_us/s_axi_aresetn"
                ]
              }
            }
          },
          "s01_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s01_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "design_1_s01_data_fifo_0",
                "xci_path": "ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_1/s01_couplers/s01_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_us": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "design_1_auto_us_1",
                "xci_path": "ip/design_1_auto_us_1/design_1_auto_us_1.xci",
                "inst_hier_path": "axi_interconnect_1/s01_couplers/auto_us",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "512"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "256"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_us_to_s01_data_fifo": {
                "interface_ports": [
                  "s01_data_fifo/S_AXI",
                  "auto_us/M_AXI"
                ]
              },
              "s01_couplers_to_auto_us": {
                "interface_ports": [
                  "S_AXI",
                  "auto_us/S_AXI"
                ]
              },
              "s01_data_fifo_to_s01_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s01_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s01_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s01_data_fifo/aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_us/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_us/s_axi_aresetn"
                ]
              }
            }
          },
          "s02_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s02_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "design_1_s02_data_fifo_0",
                "xci_path": "ip/design_1_s02_data_fifo_0/design_1_s02_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_1/s02_couplers/s02_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_us": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "design_1_auto_us_2",
                "xci_path": "ip/design_1_auto_us_2/design_1_auto_us_2.xci",
                "inst_hier_path": "axi_interconnect_1/s02_couplers/auto_us",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "512"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "256"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_us_to_s02_data_fifo": {
                "interface_ports": [
                  "s02_data_fifo/S_AXI",
                  "auto_us/M_AXI"
                ]
              },
              "s02_couplers_to_auto_us": {
                "interface_ports": [
                  "S_AXI",
                  "auto_us/S_AXI"
                ]
              },
              "s02_data_fifo_to_s02_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s02_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s02_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s02_data_fifo/aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_us/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_us/s_axi_aresetn"
                ]
              }
            }
          },
          "s03_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
              "s03_data_fifo": {
                "vlnv": "xilinx.com:ip:axi_data_fifo:2.1",
                "xci_name": "design_1_s03_data_fifo_0",
                "xci_path": "ip/design_1_s03_data_fifo_0/design_1_s03_data_fifo_0.xci",
                "inst_hier_path": "axi_interconnect_1/s03_couplers/s03_data_fifo",
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              },
              "auto_us": {
                "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
                "xci_name": "design_1_auto_us_3",
                "xci_path": "ip/design_1_auto_us_3/design_1_auto_us_3.xci",
                "inst_hier_path": "axi_interconnect_1/s03_couplers/auto_us",
                "parameters": {
                  "MI_DATA_WIDTH": {
                    "value": "512"
                  },
                  "SI_DATA_WIDTH": {
                    "value": "256"
                  }
                },
                "interface_ports": {
                  "S_AXI": {
                    "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
                    "mode": "Slave",
                    "bridges": [
                      "M_AXI"
                    ]
                  }
                }
              }
            },
            "interface_nets": {
              "auto_us_to_s03_data_fifo": {
                "interface_ports": [
                  "s03_data_fifo/S_AXI",
                  "auto_us/M_AXI"
                ]
              },
              "s03_couplers_to_auto_us": {
                "interface_ports": [
                  "S_AXI",
                  "auto_us/S_AXI"
                ]
              },
              "s03_data_fifo_to_s03_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "s03_data_fifo/M_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "s03_data_fifo/aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "s03_data_fifo/aresetn"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_us/s_axi_aclk"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_us/s_axi_aresetn"
                ]
              }
            }
          },
          "m00_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m00_couplers_to_m00_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "axi_interconnect_1_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "axi_interconnect_1_to_s01_couplers": {
            "interface_ports": [
              "S01_AXI",
              "s01_couplers/S_AXI"
            ]
          },
          "axi_interconnect_1_to_s02_couplers": {
            "interface_ports": [
              "S02_AXI",
              "s02_couplers/S_AXI"
            ]
          },
          "axi_interconnect_1_to_s03_couplers": {
            "interface_ports": [
              "S03_AXI",
              "s03_couplers/S_AXI"
            ]
          },
          "m00_couplers_to_axi_interconnect_1": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "s01_couplers_to_xbar": {
            "interface_ports": [
              "s01_couplers/M_AXI",
              "xbar/S01_AXI"
            ]
          },
          "s02_couplers_to_xbar": {
            "interface_ports": [
              "s02_couplers/M_AXI",
              "xbar/S02_AXI"
            ]
          },
          "s03_couplers_to_xbar": {
            "interface_ports": [
              "s03_couplers/M_AXI",
              "xbar/S03_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "axi_interconnect_1_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/S_ACLK",
              "s01_couplers/S_ACLK",
              "s02_couplers/S_ACLK",
              "s03_couplers/S_ACLK",
              "s00_couplers/M_ACLK",
              "s01_couplers/M_ACLK",
              "s02_couplers/M_ACLK",
              "s03_couplers/M_ACLK",
              "m00_couplers/M_ACLK",
              "m00_couplers/S_ACLK"
            ]
          },
          "axi_interconnect_1_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/S_ARESETN",
              "s01_couplers/S_ARESETN",
              "s02_couplers/S_ARESETN",
              "s03_couplers/S_ARESETN",
              "s00_couplers/M_ARESETN",
              "s01_couplers/M_ARESETN",
              "s02_couplers/M_ARESETN",
              "s03_couplers/M_ARESETN",
              "m00_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN"
            ]
          }
        }
      },
      "axi_timer_0": {
        "vlnv": "xilinx.com:ip:axi_timer:2.0",
        "xci_name": "design_1_axi_timer_0_0",
        "xci_path": "ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci",
        "inst_hier_path": "axi_timer_0"
      },
      "clk_wiz_1": {
        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
        "xci_name": "design_1_clk_wiz_1_0",
        "xci_path": "ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xci",
        "inst_hier_path": "clk_wiz_1",
        "parameters": {
          "CLKIN1_JITTER_PS": {
            "value": "100.0"
          },
          "CLKOUT1_JITTER": {
            "value": "115.831"
          },
          "CLKOUT1_PHASE_ERROR": {
            "value": "87.180"
          },
          "MMCM_CLKFBOUT_MULT_F": {
            "value": "12.000"
          },
          "MMCM_CLKIN1_PERIOD": {
            "value": "10.000"
          },
          "MMCM_CLKIN2_PERIOD": {
            "value": "10.000"
          },
          "PRIM_IN_FREQ": {
            "value": "100"
          },
          "PRIM_SOURCE": {
            "value": "Differential_clock_capable_pin"
          },
          "USE_LOCKED": {
            "value": "true"
          },
          "USE_RESET": {
            "value": "false"
          }
        }
      },
      "mdm_1": {
        "vlnv": "xilinx.com:ip:mdm:3.2",
        "xci_name": "design_1_mdm_1_0",
        "xci_path": "ip/design_1_mdm_1_0/design_1_mdm_1_0.xci",
        "inst_hier_path": "mdm_1",
        "parameters": {
          "C_ADDR_SIZE": {
            "value": "32"
          },
          "C_M_AXI_ADDR_WIDTH": {
            "value": "32"
          },
          "C_USE_UART": {
            "value": "1"
          }
        }
      },
      "microblaze_0": {
        "vlnv": "xilinx.com:ip:microblaze:11.0",
        "xci_name": "design_1_microblaze_0_0",
        "xci_path": "ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci",
        "inst_hier_path": "microblaze_0",
        "parameters": {
          "C_ADDR_TAG_BITS": {
            "value": "0"
          },
          "C_DCACHE_ADDR_TAG": {
            "value": "0"
          },
          "C_DEBUG_ENABLED": {
            "value": "1"
          },
          "C_D_AXI": {
            "value": "1"
          },
          "C_D_LMB": {
            "value": "1"
          },
          "C_I_LMB": {
            "value": "1"
          },
          "C_USE_BARREL": {
            "value": "1"
          },
          "C_USE_DIV": {
            "value": "1"
          },
          "C_USE_HW_MUL": {
            "value": "1"
          },
          "C_USE_PCMP_INSTR": {
            "value": "1"
          },
          "C_USE_STACK_PROTECTION": {
            "value": "1"
          },
          "G_TEMPLATE_LIST": {
            "value": "0"
          }
        },
        "interface_ports": {
          "DLMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "ILMB": {
            "vlnv": "xilinx.com:interface:lmb_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Instruction",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
              "width": "32"
            }
          },
          "M_AXI_DP": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "Data",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0xFFFFFFFF",
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              "S_ARESETN": {
                "type": "rst",
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                "parameters": {
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                    "value": "S_AXI"
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              "S_ARESETN": {
                "type": "rst",
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            "interface_nets": {
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                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m03_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m03_couplers_to_m03_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m04_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m04_couplers_to_m04_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m05_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m05_couplers_to_m05_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m06_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m06_couplers_to_m06_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m07_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m07_couplers_to_m07_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          },
          "m08_couplers": {
            "interface_ports": {
              "M_AXI": {
                "mode": "Master",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "interface_nets": {
              "m08_couplers_to_m08_couplers": {
                "interface_ports": [
                  "S_AXI",
                  "M_AXI"
                ]
              }
            }
          }
        },
        "interface_nets": {
          "m00_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "m01_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M01_AXI",
              "m01_couplers/M_AXI"
            ]
          },
          "m02_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M02_AXI",
              "m02_couplers/M_AXI"
            ]
          },
          "m03_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M03_AXI",
              "m03_couplers/M_AXI"
            ]
          },
          "m04_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M04_AXI",
              "m04_couplers/M_AXI"
            ]
          },
          "m05_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M05_AXI",
              "m05_couplers/M_AXI"
            ]
          },
          "m06_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M06_AXI",
              "m06_couplers/M_AXI"
            ]
          },
          "m07_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M07_AXI",
              "m07_couplers/M_AXI"
            ]
          },
          "m08_couplers_to_microblaze_0_axi_periph": {
            "interface_ports": [
              "M08_AXI",
              "m08_couplers/M_AXI"
            ]
          },
          "microblaze_0_axi_periph_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "microblaze_0_axi_periph_to_s01_couplers": {
            "interface_ports": [
              "S01_AXI",
              "s01_couplers/S_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          },
          "s01_couplers_to_xbar": {
            "interface_ports": [
              "s01_couplers/M_AXI",
              "xbar/S01_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "xbar_to_m01_couplers": {
            "interface_ports": [
              "xbar/M01_AXI",
              "m01_couplers/S_AXI"
            ]
          },
          "xbar_to_m02_couplers": {
            "interface_ports": [
              "xbar/M02_AXI",
              "m02_couplers/S_AXI"
            ]
          },
          "xbar_to_m03_couplers": {
            "interface_ports": [
              "xbar/M03_AXI",
              "m03_couplers/S_AXI"
            ]
          },
          "xbar_to_m04_couplers": {
            "interface_ports": [
              "xbar/M04_AXI",
              "m04_couplers/S_AXI"
            ]
          },
          "xbar_to_m05_couplers": {
            "interface_ports": [
              "xbar/M05_AXI",
              "m05_couplers/S_AXI"
            ]
          },
          "xbar_to_m06_couplers": {
            "interface_ports": [
              "xbar/M06_AXI",
              "m06_couplers/S_AXI"
            ]
          },
          "xbar_to_m07_couplers": {
            "interface_ports": [
              "xbar/M07_AXI",
              "m07_couplers/S_AXI"
            ]
          },
          "xbar_to_m08_couplers": {
            "interface_ports": [
              "xbar/M08_AXI",
              "m08_couplers/S_AXI"
            ]
          }
        },
        "nets": {
          "M00_ACLK_1": {
            "ports": [
              "M00_ACLK",
              "m00_couplers/M_ACLK"
            ]
          },
          "M00_ARESETN_1": {
            "ports": [
              "M00_ARESETN",
              "m00_couplers/M_ARESETN"
            ]
          },
          "M01_ACLK_1": {
            "ports": [
              "M01_ACLK",
              "m01_couplers/M_ACLK"
            ]
          },
          "M01_ARESETN_1": {
            "ports": [
              "M01_ARESETN",
              "m01_couplers/M_ARESETN"
            ]
          },
          "M02_ACLK_1": {
            "ports": [
              "M02_ACLK",
              "m02_couplers/M_ACLK"
            ]
          },
          "M02_ARESETN_1": {
            "ports": [
              "M02_ARESETN",
              "m02_couplers/M_ARESETN"
            ]
          },
          "M03_ACLK_1": {
            "ports": [
              "M03_ACLK",
              "m03_couplers/M_ACLK"
            ]
          },
          "M03_ARESETN_1": {
            "ports": [
              "M03_ARESETN",
              "m03_couplers/M_ARESETN"
            ]
          },
          "M04_ACLK_1": {
            "ports": [
              "M04_ACLK",
              "m04_couplers/M_ACLK"
            ]
          },
          "M04_ARESETN_1": {
            "ports": [
              "M04_ARESETN",
              "m04_couplers/M_ARESETN"
            ]
          },
          "M05_ACLK_1": {
            "ports": [
              "M05_ACLK",
              "m05_couplers/M_ACLK"
            ]
          },
          "M05_ARESETN_1": {
            "ports": [
              "M05_ARESETN",
              "m05_couplers/M_ARESETN"
            ]
          },
          "M06_ACLK_1": {
            "ports": [
              "M06_ACLK",
              "m06_couplers/M_ACLK"
            ]
          },
          "M06_ARESETN_1": {
            "ports": [
              "M06_ARESETN",
              "m06_couplers/M_ARESETN"
            ]
          },
          "M07_ACLK_1": {
            "ports": [
              "M07_ACLK",
              "m07_couplers/M_ACLK"
            ]
          },
          "M07_ARESETN_1": {
            "ports": [
              "M07_ARESETN",
              "m07_couplers/M_ARESETN"
            ]
          },
          "M08_ACLK_1": {
            "ports": [
              "M08_ACLK",
              "m08_couplers/M_ACLK"
            ]
          },
          "M08_ARESETN_1": {
            "ports": [
              "M08_ARESETN",
              "m08_couplers/M_ARESETN"
            ]
          },
          "S00_ACLK_1": {
            "ports": [
              "S00_ACLK",
              "s00_couplers/S_ACLK"
            ]
          },
          "S00_ARESETN_1": {
            "ports": [
              "S00_ARESETN",
              "s00_couplers/S_ARESETN"
            ]
          },
          "S01_ACLK_1": {
            "ports": [
              "S01_ACLK",
              "s01_couplers/S_ACLK"
            ]
          },
          "S01_ARESETN_1": {
            "ports": [
              "S01_ARESETN",
              "s01_couplers/S_ARESETN"
            ]
          },
          "microblaze_0_axi_periph_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/M_ACLK",
              "s01_couplers/M_ACLK",
              "m00_couplers/S_ACLK",
              "m01_couplers/S_ACLK",
              "m02_couplers/S_ACLK",
              "m03_couplers/S_ACLK",
              "m04_couplers/S_ACLK",
              "m05_couplers/S_ACLK",
              "m06_couplers/S_ACLK",
              "m07_couplers/S_ACLK",
              "m08_couplers/S_ACLK"
            ]
          },
          "microblaze_0_axi_periph_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/M_ARESETN",
              "s01_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN",
              "m01_couplers/S_ARESETN",
              "m02_couplers/S_ARESETN",
              "m03_couplers/S_ARESETN",
              "m04_couplers/S_ARESETN",
              "m05_couplers/S_ARESETN",
              "m06_couplers/S_ARESETN",
              "m07_couplers/S_ARESETN",
              "m08_couplers/S_ARESETN"
            ]
          }
        }
      },
      "microblaze_0_xlconcat": {
        "vlnv": "xilinx.com:ip:xlconcat:2.1",
        "xci_name": "design_1_microblaze_0_xlconcat_0",
        "xci_path": "ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci",
        "inst_hier_path": "microblaze_0_xlconcat",
        "parameters": {
          "NUM_PORTS": {
            "value": "3"
          },
          "dout_width": {
            "value": "3"
          }
        }
      },
      "rst_clk_wiz_1_100M": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "design_1_rst_clk_wiz_1_100M_0",
        "xci_path": "ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xci",
        "inst_hier_path": "rst_clk_wiz_1_100M",
        "parameters": {
          "C_AUX_RESET_HIGH": {
            "value": "0"
          }
        }
      },
      "system_management_wiz_0": {
        "vlnv": "xilinx.com:ip:system_management_wiz:1.3",
        "xci_name": "design_1_system_management_wiz_0_0",
        "xci_path": "ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci",
        "inst_hier_path": "system_management_wiz_0",
        "parameters": {
          "ANALOG_BANK_SELECTION": {
            "value": "64"
          },
          "CHANNEL_AVERAGING": {
            "value": "16"
          },
          "CHANNEL_ENABLE_VP_VN": {
            "value": "true"
          },
          "ENABLE_TEMP_BUS": {
            "value": "false"
          },
          "I2C_SCLK_LOC": {
            "value": "AC18"
          },
          "I2C_SDA_LOC": {
            "value": "AA19"
          },
          "INTERFACE_SELECTION": {
            "value": "Enable_AXI"
          },
          "OT_ALARM": {
            "value": "false"
          },
          "SYSMONE1_STARUP_SELECTION": {
            "value": "channel_sequencer"
          },
          "USER_TEMP_ALARM": {
            "value": "false"
          },
          "VAUXN0_LOC": {
            "value": "B19"
          },
          "VAUXN10_LOC": {
            "value": "C23"
          },
          "VAUXN11_LOC": {
            "value": "C22"
          },
          "VAUXN12_LOC": {
            "value": "D21"
          },
          "VAUXN13_LOC": {
            "value": "D19"
          },
          "VAUXN14_LOC": {
            "value": "H26"
          },
          "VAUXN15_LOC": {
            "value": "J22"
          },
          "VAUXN1_LOC": {
            "value": "C19"
          },
          "VAUXN2_LOC": {
            "value": "G26"
          },
          "VAUXN3_LOC": {
            "value": "D24"
          },
          "VAUXN4_LOC": {
            "value": "F20"
          },
          "VAUXN5_LOC": {
            "value": "H22"
          },
          "VAUXN6_LOC": {
            "value": "H24"
          },
          "VAUXN7_LOC": {
            "value": "K23"
          },
          "VAUXN8_LOC": {
            "value": "A21"
          },
          "VAUXN9_LOC": {
            "value": "A19"
          },
          "VAUXP0_LOC": {
            "value": "B18"
          },
          "VAUXP10_LOC": {
            "value": "D22"
          },
          "VAUXP11_LOC": {
            "value": "C21"
          },
          "VAUXP12_LOC": {
            "value": "D20"
          },
          "VAUXP13_LOC": {
            "value": "E19"
          },
          "VAUXP14_LOC": {
            "value": "J25"
          },
          "VAUXP15_LOC": {
            "value": "J21"
          },
          "VAUXP1_LOC": {
            "value": "C18"
          },
          "VAUXP2_LOC": {
            "value": "G25"
          },
          "VAUXP3_LOC": {
            "value": "E24"
          },
          "VAUXP4_LOC": {
            "value": "G20"
          },
          "VAUXP5_LOC": {
            "value": "H21"
          },
          "VAUXP6_LOC": {
            "value": "J24"
          },
          "VAUXP7_LOC": {
            "value": "K22"
          },
          "VAUXP8_LOC": {
            "value": "A20"
          },
          "VAUXP9_LOC": {
            "value": "A18"
          },
          "VCCAUX_ALARM": {
            "value": "false"
          },
          "VCCINT_ALARM": {
            "value": "false"
          }
        }
      },
      "util_ds_buf_0": {
        "vlnv": "xilinx.com:ip:util_ds_buf:2.2",
        "xci_name": "design_1_util_ds_buf_0_0",
        "xci_path": "ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci",
        "inst_hier_path": "util_ds_buf_0",
        "parameters": {
          "C_BUF_TYPE": {
            "value": "IBUFDSGTE"
          }
        }
      },
      "xdma_0": {
        "vlnv": "xilinx.com:ip:xdma:4.1",
        "xci_name": "design_1_xdma_0_0",
        "xci_path": "ip/design_1_xdma_0_0/design_1_xdma_0_0.xci",
        "inst_hier_path": "xdma_0",
        "parameters": {
          "PF0_DEVICE_ID_mqdma": {
            "value": "903F"
          },
          "PF0_SRIOV_VF_DEVICE_ID": {
            "value": "A03F"
          },
          "PF2_DEVICE_ID_mqdma": {
            "value": "923F"
          },
          "PF3_DEVICE_ID_mqdma": {
            "value": "933F"
          },
          "axi_addr_width": {
            "value": "40"
          },
          "axi_data_width": {
            "value": "512_bit"
          },
          "axisten_freq": {
            "value": "250"
          },
          "bridge_burst": {
            "value": "true"
          },
          "c_s_axi_supports_narrow_burst": {
            "value": "true"
          },
          "en_axi_master_if": {
            "value": "true"
          },
          "en_axi_slave_if": {
            "value": "true"
          },
          "en_gt_selection": {
            "value": "false"
          },
          "enable_auto_rxeq": {
            "value": "False"
          },
          "functional_mode": {
            "value": "AXI_Bridge"
          },
          "mode_selection": {
            "value": "Advanced"
          },
          "pcie_blk_locn": {
            "value": "X0Y2"
          },
          "pcie_id_if": {
            "value": "false"
          },
          "pciebar2axibar_0": {
            "value": "0x0000000080000000"
          },
          "pf0_bar0_64bit": {
            "value": "false"
          },
          "pf0_bar0_scale": {
            "value": "Megabytes"
          },
          "pf0_bar0_size": {
            "value": "2"
          },
          "pf0_base_class_menu": {
            "value": "Memory_controller"
          },
          "pf0_class_code_base": {
            "value": "05"
          },
          "pf0_class_code_interface": {
            "value": "00"
          },
          "pf0_class_code_sub": {
            "value": "80"
          },
          "pf0_device_id": {
            "value": "903F"
          },
          "pf0_sub_class_interface_menu": {
            "value": "Other_memory_controller"
          },
          "pl_link_cap_max_link_speed": {
            "value": "8.0_GT/s"
          },
          "pl_link_cap_max_link_width": {
            "value": "X16"
          },
          "plltype": {
            "value": "QPLL1"
          },
          "sys_reset_polarity": {
            "value": "ACTIVE_LOW"
          }
        },
        "interface_ports": {
          "S_AXI_B": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Slave",
            "memory_map_ref": "S_AXI_B"
          },
          "M_AXI_B": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Master",
            "address_space_ref": "M_AXI_B",
            "base_address": {
              "minimum": "0x00000000",
              "maximum": "0x00FFFFFFFFFF",
              "width": "40"
            }
          },
          "S_AXI_LITE": {
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "mode": "Slave",
            "memory_map_ref": "S_AXI_LITE"
          }
        },
        "addressing": {
          "memory_maps": {
            "S_AXI_B": {
              "address_blocks": {
                "BAR0": {
                  "base_address": "0",
                  "range": "1M",
                  "width": "20",
                  "usage": "memory",
                  "offset_base_param": "axibar_0",
                  "offset_high_param": "axibar_highaddr_0"
                }
              }
            },
            "S_AXI_LITE": {
              "address_blocks": {
                "CTL0": {
                  "base_address": "0",
                  "range": "512M",
                  "width": "29",
                  "usage": "memory",
                  "offset_base_param": "baseaddr",
                  "offset_high_param": "highaddr"
                }
              }
            }
          },
          "address_spaces": {
            "M_AXI_B": {
              "range": "1T",
              "width": "40"
            }
          }
        }
      },
      "xlconstant_0": {
        "vlnv": "xilinx.com:ip:xlconstant:1.1",
        "xci_name": "design_1_xlconstant_0_0",
        "xci_path": "ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci",
        "inst_hier_path": "xlconstant_0"
      }
    },
    "interface_nets": {
      "CLK_IN1_D_0_1": {
        "interface_ports": [
          "sys_clk",
          "clk_wiz_1/CLK_IN1_D"
        ]
      },
      "CLK_IN_D_0_1": {
        "interface_ports": [
          "pcie_refclk",
          "util_ds_buf_0/CLK_IN_D"
        ]
      },
      "S00_AXI_0_1": {
        "interface_ports": [
          "pcie_m_axi0",
          "axi_interconnect_1/S00_AXI"
        ]
      },
      "S00_AXI_1": {
        "interface_ports": [
          "axi_interconnect_0/S00_AXI",
          "microblaze_0/M_AXI_DP"
        ]
      },
      "S01_AXI_0_1": {
        "interface_ports": [
          "pcie_m_axi1",
          "axi_interconnect_1/S01_AXI"
        ]
      },
      "S02_AXI_0_1": {
        "interface_ports": [
          "pcie_m_axi2",
          "axi_interconnect_1/S02_AXI"
        ]
      },
      "S03_AXI_0_1": {
        "interface_ports": [
          "pcie_m_axi3",
          "axi_interconnect_1/S03_AXI"
        ]
      },
      "axi_interconnect_0_M00_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M00_AXI",
          "microblaze_0_axi_intc/s_axi"
        ]
      },
      "axi_interconnect_0_M01_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M01_AXI",
          "axi_timer_0/S_AXI"
        ]
      },
      "axi_interconnect_0_M02_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M02_AXI",
          "mdm_1/S_AXI"
        ]
      },
      "axi_interconnect_0_M03_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M03_AXI",
          "system_management_wiz_0/S_AXI_LITE"
        ]
      },
      "axi_interconnect_0_M04_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M04_AXI",
          "microblaze_0_axi_periph/S00_AXI"
        ]
      },
      "axi_interconnect_1_M00_AXI": {
        "interface_ports": [
          "axi_interconnect_1/M00_AXI",
          "xdma_0/S_AXI_B"
        ]
      },
      "microblaze_0_axi_periph_M00_AXI": {
        "interface_ports": [
          "microblaze_0_axi_periph/M00_AXI",
          "xdma_0/S_AXI_LITE"
        ]
      },
      "microblaze_0_axi_periph_M01_AXI": {
        "interface_ports": [
          "axil_descriptors",
          "microblaze_0_axi_periph/M01_AXI"
        ]
      },
      "microblaze_0_axi_periph_M02_AXI": {
        "interface_ports": [
          "axil_dma_ctrl0",
          "microblaze_0_axi_periph/M02_AXI"
        ]
      },
      "microblaze_0_axi_periph_M03_AXI": {
        "interface_ports": [
          "axil_dma_ctrl1",
          "microblaze_0_axi_periph/M03_AXI"
        ]
      },
      "microblaze_0_axi_periph_M04_AXI": {
        "interface_ports": [
          "axil_util",
          "microblaze_0_axi_periph/M04_AXI"
        ]
      },
      "microblaze_0_axi_periph_M05_AXI": {
        "interface_ports": [
          "axil_timing",
          "microblaze_0_axi_periph/M05_AXI"
        ]
      },
      "microblaze_0_axi_periph_M06_AXI": {
        "interface_ports": [
          "axil_data_gen",
          "microblaze_0_axi_periph/M06_AXI"
        ]
      },
      "microblaze_0_axi_periph_M07_AXI": {
        "interface_ports": [
          "axil_dma_ctrl2",
          "microblaze_0_axi_periph/M07_AXI"
        ]
      },
      "microblaze_0_axi_periph_M08_AXI": {
        "interface_ports": [
          "axil_dma_ctrl3",
          "microblaze_0_axi_periph/M08_AXI"
        ]
      },
      "microblaze_0_debug": {
        "interface_ports": [
          "mdm_1/MBDEBUG_0",
          "microblaze_0/DEBUG"
        ]
      },
      "microblaze_0_dlmb_1": {
        "interface_ports": [
          "microblaze_0/DLMB",
          "microblaze_0_local_memory/DLMB"
        ]
      },
      "microblaze_0_ilmb_1": {
        "interface_ports": [
          "microblaze_0/ILMB",
          "microblaze_0_local_memory/ILMB"
        ]
      },
      "microblaze_0_interrupt": {
        "interface_ports": [
          "microblaze_0/INTERRUPT",
          "microblaze_0_axi_intc/interrupt"
        ]
      },
      "xdma_0_M_AXI_B": {
        "interface_ports": [
          "microblaze_0_axi_periph/S01_AXI",
          "xdma_0/M_AXI_B"
        ]
      },
      "xdma_0_pcie_mgt": {
        "interface_ports": [
          "pcie_mgt_0",
          "xdma_0/pcie_mgt"
        ]
      }
    },
    "nets": {
      "S01_ARESETN_1": {
        "ports": [
          "xdma_0/axi_aresetn",
          "axi_pcie_aresetn",
          "axi_interconnect_1/ARESETN",
          "axi_interconnect_1/S00_ARESETN",
          "axi_interconnect_1/M00_ARESETN",
          "axi_interconnect_1/S01_ARESETN",
          "microblaze_0_axi_periph/M01_ARESETN",
          "microblaze_0_axi_periph/S01_ARESETN",
          "microblaze_0_axi_periph/M02_ARESETN",
          "microblaze_0_axi_periph/M03_ARESETN",
          "microblaze_0_axi_periph/M04_ARESETN",
          "microblaze_0_axi_periph/M05_ARESETN",
          "microblaze_0_axi_periph/M06_ARESETN",
          "axi_interconnect_1/S02_ARESETN",
          "axi_interconnect_1/S03_ARESETN",
          "microblaze_0_axi_periph/M07_ARESETN",
          "microblaze_0_axi_periph/M08_ARESETN"
        ]
      },
      "axi_timer_0_interrupt": {
        "ports": [
          "axi_timer_0/interrupt",
          "microblaze_0_xlconcat/In1"
        ]
      },
      "clk_wiz_1_locked": {
        "ports": [
          "clk_wiz_1/locked",
          "rst_clk_wiz_1_100M/dcm_locked"
        ]
      },
      "mdm_1_debug_sys_rst": {
        "ports": [
          "mdm_1/Debug_SYS_Rst",
          "rst_clk_wiz_1_100M/mb_debug_sys_rst"
        ]
      },
      "microblaze_0_Clk": {
        "ports": [
          "clk_wiz_1/clk_out1",
          "axil_clk",
          "microblaze_0_local_memory/LMB_Clk",
          "axi_interconnect_0/ACLK",
          "axi_interconnect_0/S00_ACLK",
          "axi_interconnect_0/M00_ACLK",
          "axi_interconnect_0/M01_ACLK",
          "axi_interconnect_0/M02_ACLK",
          "axi_interconnect_0/M03_ACLK",
          "axi_interconnect_0/M04_ACLK",
          "axi_timer_0/s_axi_aclk",
          "microblaze_0/Clk",
          "microblaze_0_axi_intc/s_axi_aclk",
          "microblaze_0_axi_intc/processor_clk",
          "microblaze_0_axi_periph/S00_ACLK",
          "rst_clk_wiz_1_100M/slowest_sync_clk",
          "system_management_wiz_0/s_axi_aclk",
          "mdm_1/S_AXI_ACLK"
        ]
      },
      "microblaze_0_intr": {
        "ports": [
          "microblaze_0_xlconcat/dout",
          "microblaze_0_axi_intc/intr"
        ]
      },
      "rst_clk_wiz_1_100M_bus_struct_reset": {
        "ports": [
          "rst_clk_wiz_1_100M/bus_struct_reset",
          "microblaze_0_local_memory/SYS_Rst"
        ]
      },
      "rst_clk_wiz_1_100M_mb_reset": {
        "ports": [
          "rst_clk_wiz_1_100M/mb_reset",
          "microblaze_0/Reset",
          "microblaze_0_axi_intc/processor_rst"
        ]
      },
      "rst_clk_wiz_1_100M_peripheral_aresetn": {
        "ports": [
          "rst_clk_wiz_1_100M/peripheral_aresetn",
          "axil_resetn",
          "axi_interconnect_0/ARESETN",
          "axi_interconnect_0/S00_ARESETN",
          "axi_interconnect_0/M00_ARESETN",
          "axi_interconnect_0/M01_ARESETN",
          "axi_interconnect_0/M02_ARESETN",
          "axi_interconnect_0/M03_ARESETN",
          "axi_interconnect_0/M04_ARESETN",
          "axi_timer_0/s_axi_aresetn",
          "microblaze_0_axi_intc/s_axi_aresetn",
          "microblaze_0_axi_periph/S00_ARESETN",
          "system_management_wiz_0/s_axi_aresetn",
          "mdm_1/S_AXI_ARESETN"
        ]
      },
      "sys_rst_n_0_1": {
        "ports": [
          "pcie_rstn",
          "xdma_0/sys_rst_n"
        ]
      },
      "system_management_wiz_0_ip2intc_irpt": {
        "ports": [
          "system_management_wiz_0/ip2intc_irpt",
          "microblaze_0_xlconcat/In2"
        ]
      },
      "usr_irq_req_0_1": {
        "ports": [
          "usr_irq_req",
          "xdma_0/usr_irq_req"
        ]
      },
      "util_ds_buf_0_IBUF_DS_ODIV2": {
        "ports": [
          "util_ds_buf_0/IBUF_DS_ODIV2",
          "xdma_0/sys_clk"
        ]
      },
      "util_ds_buf_0_IBUF_OUT": {
        "ports": [
          "util_ds_buf_0/IBUF_OUT",
          "xdma_0/sys_clk_gt"
        ]
      },
      "xdma_0_axi_aclk": {
        "ports": [
          "xdma_0/axi_aclk",
          "axi_pcie_clk",
          "axi_interconnect_1/ACLK",
          "axi_interconnect_1/S00_ACLK",
          "axi_interconnect_1/M00_ACLK",
          "axi_interconnect_1/S01_ACLK",
          "microblaze_0_axi_periph/ACLK",
          "microblaze_0_axi_periph/M00_ACLK",
          "microblaze_0_axi_periph/M01_ACLK",
          "microblaze_0_axi_periph/S01_ACLK",
          "microblaze_0_axi_periph/M02_ACLK",
          "microblaze_0_axi_periph/M03_ACLK",
          "microblaze_0_axi_periph/M04_ACLK",
          "microblaze_0_axi_periph/M05_ACLK",
          "microblaze_0_axi_periph/M06_ACLK",
          "axi_interconnect_1/S02_ACLK",
          "axi_interconnect_1/S03_ACLK",
          "microblaze_0_axi_periph/M07_ACLK",
          "microblaze_0_axi_periph/M08_ACLK"
        ]
      },
      "xdma_0_axi_ctl_aresetn": {
        "ports": [
          "xdma_0/axi_ctl_aresetn",
          "microblaze_0_axi_periph/ARESETN",
          "microblaze_0_axi_periph/M00_ARESETN"
        ]
      },
      "xdma_0_cfg_ltssm_state": {
        "ports": [
          "xdma_0/cfg_ltssm_state",
          "pcie_cfg_ltssm_state"
        ]
      },
      "xdma_0_user_lnk_up": {
        "ports": [
          "xdma_0/user_lnk_up",
          "pcie_user_lnk_up"
        ]
      },
      "xlconstant_0_dout": {
        "ports": [
          "xlconstant_0/dout",
          "rst_clk_wiz_1_100M/ext_reset_in",
          "rst_clk_wiz_1_100M/aux_reset_in"
        ]
      }
    },
    "addressing": {
      "/": {
        "address_spaces": {
          "pcie_m_axi0": {
            "range": "1T",
            "width": "40",
            "segments": {
              "SEG_xdma_0_BAR0": {
                "address_block": "/xdma_0/S_AXI_B/BAR0",
                "offset": "0x0000000000",
                "range": "1T",
                "offset_base_param": "axibar_0",
                "offset_high_param": "axibar_highaddr_0"
              }
            }
          },
          "pcie_m_axi1": {
            "range": "1T",
            "width": "40",
            "segments": {
              "SEG_xdma_0_BAR0": {
                "address_block": "/xdma_0/S_AXI_B/BAR0",
                "offset": "0x0000000000",
                "range": "1T",
                "offset_base_param": "axibar_0",
                "offset_high_param": "axibar_highaddr_0"
              }
            }
          },
          "pcie_m_axi2": {
            "range": "1T",
            "width": "40",
            "segments": {
              "SEG_xdma_0_BAR0": {
                "address_block": "/xdma_0/S_AXI_B/BAR0",
                "offset": "0x0000000000",
                "range": "1T",
                "offset_base_param": "axibar_0",
                "offset_high_param": "axibar_highaddr_0"
              }
            }
          },
          "pcie_m_axi3": {
            "range": "1T",
            "width": "40",
            "segments": {
              "SEG_xdma_0_BAR0": {
                "address_block": "/xdma_0/S_AXI_B/BAR0",
                "offset": "0x0000000000",
                "range": "1T",
                "offset_base_param": "axibar_0",
                "offset_high_param": "axibar_highaddr_0"
              }
            }
          }
        },
        "memory_maps": {
          "axil_data_gen": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_descriptors": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_dma_ctrl0": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_dma_ctrl1": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_dma_ctrl2": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_dma_ctrl3": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_timing": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          },
          "axil_util": {
            "address_blocks": {
              "Reg": {
                "base_address": "0",
                "range": "64K",
                "width": "16",
                "usage": "register"
              }
            }
          }
        }
      },
      "/microblaze_0": {
        "address_spaces": {
          "Data": {
            "segments": {
              "SEG_axi_timer_0_Reg": {
                "address_block": "/axi_timer_0/S_AXI/Reg",
                "offset": "0x40000000",
                "range": "64K"
              },
              "SEG_axil_data_gen_Reg": {
                "address_block": "/axil_data_gen/Reg",
                "offset": "0x80030000",
                "range": "64K"
              },
              "SEG_axil_descriptors_Reg": {
                "address_block": "/axil_descriptors/Reg",
                "offset": "0x80000000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl0_Reg": {
                "address_block": "/axil_dma_ctrl0/Reg",
                "offset": "0x80100000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl1_Reg": {
                "address_block": "/axil_dma_ctrl1/Reg",
                "offset": "0x80110000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl2_Reg": {
                "address_block": "/axil_dma_ctrl2/Reg",
                "offset": "0x80120000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl3_Reg": {
                "address_block": "/axil_dma_ctrl3/Reg",
                "offset": "0x80130000",
                "range": "64K"
              },
              "SEG_axil_timing_Reg": {
                "address_block": "/axil_timing/Reg",
                "offset": "0x80020000",
                "range": "64K"
              },
              "SEG_axil_util_Reg": {
                "address_block": "/axil_util/Reg",
                "offset": "0x80010000",
                "range": "64K"
              },
              "SEG_dlmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x00000000",
                "range": "32K",
                "offset_high_param": "C_HIGHADDR"
              },
              "SEG_mdm_1_Reg": {
                "address_block": "/mdm_1/S_AXI/Reg",
                "offset": "0x40010000",
                "range": "4K"
              },
              "SEG_microblaze_0_axi_intc_Reg": {
                "address_block": "/microblaze_0_axi_intc/S_AXI/Reg",
                "offset": "0x40020000",
                "range": "64K"
              },
              "SEG_system_management_wiz_0_Reg": {
                "address_block": "/system_management_wiz_0/S_AXI_LITE/Reg",
                "offset": "0x40030000",
                "range": "64K"
              },
              "SEG_xdma_0_CTL0": {
                "address_block": "/xdma_0/S_AXI_LITE/CTL0",
                "offset": "0x83000000",
                "range": "16M",
                "offset_base_param": "baseaddr",
                "offset_high_param": "highaddr"
              }
            }
          },
          "Instruction": {
            "segments": {
              "SEG_ilmb_bram_if_cntlr_Mem": {
                "address_block": "/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem",
                "offset": "0x00000000",
                "range": "32K",
                "offset_high_param": "C_HIGHADDR"
              }
            }
          }
        }
      },
      "/xdma_0": {
        "address_spaces": {
          "M_AXI_B": {
            "segments": {
              "SEG_axil_data_gen_Reg": {
                "address_block": "/axil_data_gen/Reg",
                "offset": "0x0080030000",
                "range": "64K"
              },
              "SEG_axil_descriptors_Reg": {
                "address_block": "/axil_descriptors/Reg",
                "offset": "0x0080000000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl0_Reg": {
                "address_block": "/axil_dma_ctrl0/Reg",
                "offset": "0x0080100000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl1_Reg": {
                "address_block": "/axil_dma_ctrl1/Reg",
                "offset": "0x0080110000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl2_Reg": {
                "address_block": "/axil_dma_ctrl2/Reg",
                "offset": "0x0080120000",
                "range": "64K"
              },
              "SEG_axil_dma_ctrl3_Reg": {
                "address_block": "/axil_dma_ctrl3/Reg",
                "offset": "0x0080130000",
                "range": "64K"
              },
              "SEG_axil_timing_Reg": {
                "address_block": "/axil_timing/Reg",
                "offset": "0x0080020000",
                "range": "64K"
              },
              "SEG_axil_util_Reg": {
                "address_block": "/axil_util/Reg",
                "offset": "0x0080010000",
                "range": "64K"
              },
              "SEG_xdma_0_CTL0": {
                "address_block": "/xdma_0/S_AXI_LITE/CTL0",
                "offset": "0x0083000000",
                "range": "16M",
                "offset_base_param": "baseaddr",
                "offset_high_param": "highaddr"
              }
            }
          }
        }
      }
    },
    "elf_association": {
      "file": {
        "name": "/home/bkiedinger/project_1/vitis/app/Debug/app.elf",
        "type": "ELF",
        "checksum": "3422405275",
        "IsVisible": "1",
        "ScopedToRef": "design_1",
        "ScopedToCell": [
          "microblaze_0"
        ],
        "UsedIn": [
          "implementation"
        ]
      }
    }
  }
}