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            "WVALID": [ { "physical_name": "M_AXI_DP_WVALID" } ]
          }
        },
        "DEBUG": {
          "vlnv": "xilinx.com:interface:mbdebug:3.0",
          "abstraction_type": "xilinx.com:interface:mbdebug_rtl:3.0",
          "mode": "slave",
          "port_maps": {
            "CAPTURE": [ { "physical_name": "Dbg_Capture" } ],
            "CLK": [ { "physical_name": "Dbg_Clk" } ],
            "DISABLE": [ { "physical_name": "Dbg_Disable" } ],
            "REG_EN": [ { "physical_name": "Dbg_Reg_En" } ],
            "RST": [ { "physical_name": "Debug_Rst" } ],
            "SHIFT": [ { "physical_name": "Dbg_Shift" } ],
            "TDI": [ { "physical_name": "Dbg_TDI" } ],
            "TDO": [ { "physical_name": "Dbg_TDO" } ],
            "UPDATE": [ { "physical_name": "Dbg_Update" } ]
          }
        }
      },
      "address_spaces": {
        "Data": {
          "range": "4294967296",
          "width": "32"
        },
        "Instruction": {
          "range": "4294967296",
          "width": "32"
        }
      },
      "memory_maps": {
        "S_AXI_DEBUG": {
          "description": "AXI debug memory map",
          "address_blocks": {
            "Reg": {
              "base_address": "0",
              "range": "4096",
              "display_name": "Reg",
              "description": "Debug Register Block",
              "usage": "register",
              "access": "read-write"
            }
          }
        }
      }
    },
    "contents": {
      "cpus": {
        "microblaze": {
          "address_space_refs": "Data",
          "parameters": {
            "endian": [ { "value": "little" } ],
            "elf_class": [ { "value": "32-bit" } ],
            "instance_path": [ { "value": "" } ],
            "bootloop_file": [ { "value": "data/mb_bootloop_le.elf" } ],
            "processor_type": [ { "value": "MICROBLAZE_LE" } ],
            "is_visible": [ { "value": "true" } ]
          }
        }
      }
    }
  }
}