{
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"1.10748",
   "Default View_TopLeft":"939,944",
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
#  -string -flagsOSRD
preplace port UART_0 -pg 1 -lvl 7 -x 2500 -y 470 -defaultsOSRD
preplace port axil_descriptors -pg 1 -lvl 7 -x 2500 -y 1550 -defaultsOSRD
preplace port axil_dma_ctrl0 -pg 1 -lvl 7 -x 2500 -y 1580 -defaultsOSRD
preplace port axil_dma_ctrl1 -pg 1 -lvl 7 -x 2500 -y 1610 -defaultsOSRD
preplace port axil_util -pg 1 -lvl 7 -x 2500 -y 1640 -defaultsOSRD
preplace port pcie_mgt_0 -pg 1 -lvl 7 -x 2500 -y 1100 -defaultsOSRD
preplace port pcie_refclk -pg 1 -lvl 0 -x -30 -y 1350 -defaultsOSRD
preplace port sys_clk -pg 1 -lvl 0 -x -30 -y 800 -defaultsOSRD
preplace port axil_timing -pg 1 -lvl 7 -x 2500 -y 1670 -defaultsOSRD
preplace port axil_data_gen -pg 1 -lvl 7 -x 2500 -y 1700 -defaultsOSRD
preplace port pcie_m_axi0 -pg 1 -lvl 0 -x -30 -y 1030 -defaultsOSRD
preplace port pcie_m_axi1 -pg 1 -lvl 0 -x -30 -y 1060 -defaultsOSRD
preplace port port-id_axi_pcie_aresetn -pg 1 -lvl 7 -x 2500 -y 1190 -defaultsOSRD
preplace port port-id_axi_pcie_clk -pg 1 -lvl 7 -x 2500 -y 1880 -defaultsOSRD
preplace port port-id_axil_clk -pg 1 -lvl 7 -x 2500 -y 790 -defaultsOSRD
preplace port port-id_pcie_rstn -pg 1 -lvl 0 -x -30 -y 1400 -defaultsOSRD
preplace port port-id_pcie_user_lnk_up -pg 1 -lvl 7 -x 2500 -y 1160 -defaultsOSRD
preplace portBus axil_resetn -pg 1 -lvl 7 -x 2500 -y 820 -defaultsOSRD
preplace portBus pcie_cfg_ltssm_state -pg 1 -lvl 7 -x 2500 -y 1130 -defaultsOSRD
preplace portBus usr_irq_req -pg 1 -lvl 0 -x -30 -y 1430 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 5 -x 1560 -y 320 -defaultsOSRD
preplace inst axi_timer_0 -pg 1 -lvl 6 -x 2140 -y 290 -defaultsOSRD
preplace inst axi_uartlite_0 -pg 1 -lvl 6 -x 2140 -y 480 -defaultsOSRD
preplace inst clk_wiz_1 -pg 1 -lvl 5 -x 1560 -y 800 -defaultsOSRD
preplace inst mdm_1 -pg 1 -lvl 3 -x 710 -y 870 -defaultsOSRD
preplace inst microblaze_0 -pg 1 -lvl 4 -x 1100 -y 660 -defaultsOSRD
preplace inst microblaze_0_axi_intc -pg 1 -lvl 3 -x 710 -y 640 -defaultsOSRD
preplace inst microblaze_0_axi_periph -pg 1 -lvl 6 -x 2140 -y 1610 -defaultsOSRD
preplace inst microblaze_0_local_memory -pg 1 -lvl 5 -x 1560 -y 670 -defaultsOSRD
preplace inst microblaze_0_xlconcat -pg 1 -lvl 2 -x 370 -y 720 -defaultsOSRD
preplace inst rst_clk_wiz_1_100M -pg 1 -lvl 2 -x 370 -y 920 -defaultsOSRD
preplace inst system_management_wiz_0 -pg 1 -lvl 6 -x 2140 -y 680 -defaultsOSRD
preplace inst util_ds_buf_0 -pg 1 -lvl 4 -x 1100 -y 1350 -defaultsOSRD
preplace inst xdma_0 -pg 1 -lvl 5 -x 1560 -y 1440 -defaultsOSRD
preplace inst xlconstant_0 -pg 1 -lvl 1 -x 70 -y 900 -defaultsOSRD
preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 6 -x 2140 -y 100 -defaultsOSRD
preplace inst axi_interconnect_1 -pg 1 -lvl 4 -x 1100 -y 1130 -defaultsOSRD
preplace netloc S01_ARESETN_1 1 3 4 860 1280 1370J 1270 1720 1300 2480J
preplace netloc axi_timer_0_interrupt 1 1 6 160 500 NJ 500 NJ 500 1360J 520 1790J 560 2480
preplace netloc axi_uartlite_0_interrupt 1 1 6 150 100 NJ 100 NJ 100 NJ 100 1810J 400 2450
preplace netloc clk_wiz_1_locked 1 1 5 170 810 580J 780 NJ 780 1360J 870 1740
preplace netloc mdm_1_debug_sys_rst 1 1 3 190 820 590J 790 830
preplace netloc microblaze_0_Clk 1 1 6 180 640 580 530 850 560 1390 110 1800 790 NJ
preplace netloc microblaze_0_intr 1 2 1 550 650n
preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 2 3 550 940 840J 570 1360J
preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 2 570 520 860J
preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 2 5 560 460 NJ 460 1360 120 1780 820 NJ
preplace netloc sys_rst_n_0_1 1 0 5 NJ 1400 NJ 1400 NJ 1400 830J 1470 NJ
preplace netloc system_management_wiz_0_ip2intc_irpt 1 1 6 170 510 NJ 510 870J 530 NJ 530 1720J 570 2450
preplace netloc usr_irq_req_0_1 1 0 5 NJ 1430 NJ 1430 NJ 1430 NJ 1430 1330J
preplace netloc util_ds_buf_0_IBUF_DS_ODIV2 1 4 1 1340 1360n
preplace netloc util_ds_buf_0_IBUF_OUT 1 4 1 1350 1340n
preplace netloc xdma_0_axi_aclk 1 3 4 840 1420 1380J 1280 1740 1880 NJ
preplace netloc xdma_0_axi_ctl_aresetn 1 5 1 1820 1460n
preplace netloc xdma_0_cfg_ltssm_state 1 5 2 1790J 1280 2460J
preplace netloc xdma_0_user_lnk_up 1 5 2 1730J 1290 2470J
preplace netloc xlconstant_0_dout 1 1 1 150 900n
preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 5 2 1820 10 2480
preplace netloc CLK_IN1_D_0_1 1 0 5 NJ 800 NJ 800 NJ 800 NJ 800 NJ
preplace netloc CLK_IN_D_0_1 1 0 4 NJ 1350 NJ 1350 NJ 1350 NJ
preplace netloc S00_AXI_0_1 1 0 4 NJ 1030 NJ 1030 NJ 1030 850J
preplace netloc S00_AXI_1 1 4 1 1340 180n
preplace netloc S01_AXI_0_1 1 0 4 NJ 1060 NJ 1060 NJ 1060 NJ
preplace netloc axi_interconnect_0_M00_AXI 1 2 4 590 90 NJ 90 NJ 90 1740
preplace netloc axi_interconnect_0_M01_AXI 1 5 1 1770 240n
preplace netloc axi_interconnect_0_M02_AXI 1 5 1 1790 320n
preplace netloc axi_interconnect_0_M03_AXI 1 5 1 1740 340n
preplace netloc axi_interconnect_0_M04_AXI 1 5 1 1770 360n
preplace netloc axi_interconnect_1_M00_AXI 1 4 1 1360 1130n
preplace netloc axi_uartlite_0_UART 1 6 1 NJ 470
preplace netloc microblaze_0_axi_periph_M00_AXI 1 4 3 1390 1260 NJ 1260 2440
preplace netloc microblaze_0_axi_periph_M01_AXI 1 6 1 2470J 1550n
preplace netloc microblaze_0_axi_periph_M02_AXI 1 6 1 2460J 1580n
preplace netloc microblaze_0_axi_periph_M03_AXI 1 6 1 NJ 1610
preplace netloc microblaze_0_axi_periph_M04_AXI 1 6 1 2460J 1630n
preplace netloc microblaze_0_axi_periph_M05_AXI 1 6 1 2470J 1650n
preplace netloc microblaze_0_axi_periph_M06_AXI 1 6 1 2450J 1670n
preplace netloc microblaze_0_debug 1 3 1 870 650n
preplace netloc microblaze_0_dlmb_1 1 4 1 N 640
preplace netloc microblaze_0_ilmb_1 1 4 1 N 660
preplace netloc microblaze_0_interrupt 1 3 1 830 630n
preplace netloc xdma_0_M_AXI_B 1 5 1 1750 1340n
preplace netloc xdma_0_pcie_mgt 1 5 2 1760J 1270 2450J
levelinfo -pg 1 -30 70 370 710 1100 1560 2140 2500
pagesize -pg 1 -db -bbox -sgen -190 0 2720 1970
"
}
0
