diff --git a/project_1.srcs/sources_1/hdl/top.sv b/project_1.srcs/sources_1/hdl/top.sv
index 1b60b25..d020d9b 100644
--- a/project_1.srcs/sources_1/hdl/top.sv
+++ b/project_1.srcs/sources_1/hdl/top.sv
@@ -76,6 +76,7 @@ data_gen_if (
     .resetn(axi_pcie_resetn)
 );
 
+// If you increase NUM_DMA you will also need to create additional AXI interfaces into the BD
 parameter NUM_DMA = 4;
 
 axi4l_intf # (
@@ -411,6 +412,8 @@ data_gen
     .data_out(pcie_dma_axis)
 );       
 
+// The CPU Side driver reads this list to determine how many devices to make
+// Must expand this list to add more DMA channels
 axi_descriptor  
 # (
     .DESCRIPTOR_WIDTH(128), 
@@ -418,14 +421,11 @@ axi_descriptor
 ) axi_descriptor_i 
 (
     .axi(descriptors_if),
-//    .descriptor_list('{{64'b0, 32'h00000000, 32'h10000}, 
-//                       {64'b0, 32'h01000000, 32'h20000},
-//                       {64'b0, 32'h01010000, 32'h20000}})
-    .descriptor_list('{{64'b0, 32'h00000000, 32'h10000}, 
-                       {64'b0, 32'h00100000, 32'h20000},
-                       {64'b0, 32'h00110000, 32'h20000},
-                       {64'b0, 32'h00120000, 32'h20000},
-                       {64'b0, 32'h00130000, 32'h20000}
+    .descriptor_list('{{64'b0, 32'h00000000, 32'h10000},  // AXI Registers
+                       {64'b0, 32'h00100000, 32'h20000},  // DMA 0
+                       {64'b0, 32'h00110000, 32'h20000},  // DMA 1
+                       {64'b0, 32'h00120000, 32'h20000},  // DMA 2
+                       {64'b0, 32'h00130000, 32'h20000}   // DMA 3
                     })
 );