adding more files

project_1.srcs/constrs_1/constraints.xdc

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+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+set_property PACKAGE_PIN M9 [get_ports {leds[0]}]
+set_property PACKAGE_PIN K8 [get_ports {leds[1]}]
+set_property PACKAGE_PIN L8 [get_ports {leds[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
+
+set_property PACKAGE_PIN N8 [get_ports uart_rxd]
+set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd]
+
+set_property PACKAGE_PIN N9 [get_ports uart_txd]
+set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
+
+set_property PACKAGE_PIN AJ9 [get_ports sys_clk_p]
+set_property PACKAGE_PIN AK9 [get_ports sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n]
+create_clock -period 5.000 -name sys_clk_clk_p [get_ports sys_clk_p]
+
+set_property PACKAGE_PIN M8 [get_ports fan_pwm]
+set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm]
+
+#-------------------------------------------
+# PCIE
+#-------------------------------------------
+set_property PACKAGE_PIN AD8 [get_ports pcie_ref_clk_p]
+create_clock -period 10.000 -name pcie_ref_clk_p -waveform {0.000 5.000} [get_ports pcie_ref_clk_p]
+
+set_property PACKAGE_PIN AP4 [get_ports {pcie_mgt_rxp[0]}]
+set_property PACKAGE_PIN AN2 [get_ports {pcie_mgt_rxp[1]}]
+set_property PACKAGE_PIN AL2 [get_ports {pcie_mgt_rxp[2]}]
+set_property PACKAGE_PIN AK4 [get_ports {pcie_mgt_rxp[3]}]
+set_property PACKAGE_PIN AJ2 [get_ports {pcie_mgt_rxp[4]}]
+set_property PACKAGE_PIN AG2 [get_ports {pcie_mgt_rxp[5]}]
+set_property PACKAGE_PIN AF4 [get_ports {pcie_mgt_rxp[6]}]
+set_property PACKAGE_PIN AE2 [get_ports {pcie_mgt_rxp[7]}]
+
+set_property PACKAGE_PIN AN6 [get_ports {pcie_mgt_txp[0]}]
+set_property PACKAGE_PIN AM4 [get_ports {pcie_mgt_txp[1]}]
+set_property PACKAGE_PIN AL6 [get_ports {pcie_mgt_txp[2]}]
+set_property PACKAGE_PIN AJ6 [get_ports {pcie_mgt_txp[3]}]
+set_property PACKAGE_PIN AH4 [get_ports {pcie_mgt_txp[4]}]
+set_property PACKAGE_PIN AG6 [get_ports {pcie_mgt_txp[5]}]
+set_property PACKAGE_PIN AE6 [get_ports {pcie_mgt_txp[6]}]
+set_property PACKAGE_PIN AD4 [get_ports {pcie_mgt_txp[7]}]
+
+set_property PACKAGE_PIN AA20 [get_ports pcie_rst_n]
+set_property IOSTANDARD LVCMOS18 [get_ports pcie_rst_n]
+
+