adding more files
This commit is contained in:
50
project_1.srcs/constrs_1/constraints.xdc
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50
project_1.srcs/constrs_1/constraints.xdc
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property PACKAGE_PIN M9 [get_ports {leds[0]}]
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set_property PACKAGE_PIN K8 [get_ports {leds[1]}]
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set_property PACKAGE_PIN L8 [get_ports {leds[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
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set_property PACKAGE_PIN N8 [get_ports uart_rxd]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd]
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set_property PACKAGE_PIN N9 [get_ports uart_txd]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
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set_property PACKAGE_PIN AJ9 [get_ports sys_clk_p]
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set_property PACKAGE_PIN AK9 [get_ports sys_clk_n]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n]
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create_clock -period 5.000 -name sys_clk_clk_p [get_ports sys_clk_p]
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set_property PACKAGE_PIN M8 [get_ports fan_pwm]
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set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm]
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#-------------------------------------------
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# PCIE
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#-------------------------------------------
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set_property PACKAGE_PIN AD8 [get_ports pcie_ref_clk_p]
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create_clock -period 10.000 -name pcie_ref_clk_p -waveform {0.000 5.000} [get_ports pcie_ref_clk_p]
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set_property PACKAGE_PIN AP4 [get_ports {pcie_mgt_rxp[0]}]
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set_property PACKAGE_PIN AN2 [get_ports {pcie_mgt_rxp[1]}]
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set_property PACKAGE_PIN AL2 [get_ports {pcie_mgt_rxp[2]}]
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set_property PACKAGE_PIN AK4 [get_ports {pcie_mgt_rxp[3]}]
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set_property PACKAGE_PIN AJ2 [get_ports {pcie_mgt_rxp[4]}]
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set_property PACKAGE_PIN AG2 [get_ports {pcie_mgt_rxp[5]}]
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set_property PACKAGE_PIN AF4 [get_ports {pcie_mgt_rxp[6]}]
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set_property PACKAGE_PIN AE2 [get_ports {pcie_mgt_rxp[7]}]
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set_property PACKAGE_PIN AN6 [get_ports {pcie_mgt_txp[0]}]
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set_property PACKAGE_PIN AM4 [get_ports {pcie_mgt_txp[1]}]
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set_property PACKAGE_PIN AL6 [get_ports {pcie_mgt_txp[2]}]
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set_property PACKAGE_PIN AJ6 [get_ports {pcie_mgt_txp[3]}]
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set_property PACKAGE_PIN AH4 [get_ports {pcie_mgt_txp[4]}]
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set_property PACKAGE_PIN AG6 [get_ports {pcie_mgt_txp[5]}]
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set_property PACKAGE_PIN AE6 [get_ports {pcie_mgt_txp[6]}]
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set_property PACKAGE_PIN AD4 [get_ports {pcie_mgt_txp[7]}]
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set_property PACKAGE_PIN AA20 [get_ports pcie_rst_n]
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set_property IOSTANDARD LVCMOS18 [get_ports pcie_rst_n]
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8479
project_1.srcs/sources_1/bd/design_1/design_1.bd
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8479
project_1.srcs/sources_1/bd/design_1/design_1.bd
Normal file
File diff suppressed because it is too large
Load Diff
505
project_1.srcs/sources_1/bd/design_1/design_1.bda
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505
project_1.srcs/sources_1/bd/design_1/design_1.bda
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@@ -0,0 +1,505 @@
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<?xml version="1.0" encoding="utf-8"?>
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<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
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<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
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<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
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<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
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<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
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|
<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
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||||||
|
<key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
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||||||
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<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
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||||||
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<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
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||||||
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<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
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||||||
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<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
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<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
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||||||
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<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
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||||||
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<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
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||||||
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<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
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<key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
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<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
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<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
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||||||
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<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
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<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
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||||||
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<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
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<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
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<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
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<node id="n0">
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||||||
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<data key="BA">0x81010000</data>
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||||||
|
<data key="BP">C_BASEADDR</data>
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||||||
|
<data key="HA">0x8101FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
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||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_axil_dma_ctrl1_Reg</data>
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||||||
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<data key="MV">xilinx.com:ip:microblaze:11.0</data>
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||||||
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<data key="TM">data</data>
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||||||
|
<data key="SX">/</data>
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||||||
|
<data key="SI">axil_dma_ctrl1</data>
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||||||
|
<data key="SS">Reg</data>
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||||||
|
<data key="SV">::design_1_imp:</data>
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||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
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||||||
|
</node>
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||||||
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<node id="n1">
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||||||
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<data key="BA">0x80120000</data>
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||||||
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<data key="BP">C_BASEADDR</data>
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||||||
|
<data key="HA">0x8012FFFF</data>
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||||||
|
<data key="HP">C_HIGHADDR</data>
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||||||
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<data key="MA">Data</data>
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||||||
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<data key="MX">/microblaze_0</data>
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||||||
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<data key="MI">M_AXI_DP</data>
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||||||
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<data key="MS">SEG_axil_data_gen_Reg</data>
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||||||
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<data key="MV">xilinx.com:ip:microblaze:11.0</data>
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||||||
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<data key="TM">data</data>
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||||||
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<data key="SX">/</data>
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||||||
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<data key="SI">axil_data_gen</data>
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||||||
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<data key="SS">Reg</data>
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||||||
|
<data key="SV">::design_1_imp:</data>
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||||||
|
<data key="TU">register</data>
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||||||
|
<data key="VT">AC</data>
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||||||
|
</node>
|
||||||
|
<node id="n2">
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||||||
|
<data key="BA">0x40000000</data>
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||||||
|
<data key="BP">C_BASEADDR</data>
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||||||
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<data key="HA">0x4000FFFF</data>
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||||||
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<data key="HP">C_HIGHADDR</data>
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||||||
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<data key="MA">Data</data>
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||||||
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<data key="MX">/microblaze_0</data>
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||||||
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<data key="MI">M_AXI_DP</data>
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||||||
|
<data key="MS">SEG_axi_timer_0_Reg</data>
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||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
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||||||
|
<data key="TM">data</data>
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||||||
|
<data key="SX">/axi_timer_0</data>
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||||||
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<data key="SI">S_AXI</data>
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||||||
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<data key="SS">Reg</data>
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||||||
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<data key="SV">xilinx.com:ip:axi_timer:2.0</data>
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||||||
|
<data key="TU">register</data>
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||||||
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<data key="VT">AC</data>
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||||||
|
</node>
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||||||
|
<node id="n3">
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||||||
|
<data key="VH">2</data>
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||||||
|
<data key="VM">design_1</data>
|
||||||
|
<data key="VT">VR</data>
|
||||||
|
</node>
|
||||||
|
<node id="n4">
|
||||||
|
<data key="BA">0x0000000000</data>
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||||||
|
<data key="BP">axibar_0</data>
|
||||||
|
<data key="HA">0xFFFFFFFFFF</data>
|
||||||
|
<data key="HP">axibar_highaddr_0</data>
|
||||||
|
<data key="MA">pcie_m_axi1</data>
|
||||||
|
<data key="MX">/</data>
|
||||||
|
<data key="MI">pcie_m_axi1</data>
|
||||||
|
<data key="MS">SEG_xdma_0_BAR0</data>
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||||||
|
<data key="MV">:::</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/xdma_0</data>
|
||||||
|
<data key="SI">S_AXI_B</data>
|
||||||
|
<data key="SS">BAR0</data>
|
||||||
|
<data key="SV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TU">memory</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n5">
|
||||||
|
<data key="BA">0x80000000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x8000FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
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||||||
|
<data key="MX">/microblaze_0</data>
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||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_axil_descriptors_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
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||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_descriptors</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n6">
|
||||||
|
<data key="BA">0x80110000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x8011FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_axil_timing_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_timing</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n7">
|
||||||
|
<data key="BA">0x83000000</data>
|
||||||
|
<data key="BP">baseaddr</data>
|
||||||
|
<data key="HA">0x83FFFFFF</data>
|
||||||
|
<data key="HP">highaddr</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_xdma_0_CTL0</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/xdma_0</data>
|
||||||
|
<data key="SI">S_AXI_LITE</data>
|
||||||
|
<data key="SS">CTL0</data>
|
||||||
|
<data key="SV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TU">memory</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n8">
|
||||||
|
<data key="BA">0x81000000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x8100FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_axil_dma_ctrl0_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_dma_ctrl0</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n9">
|
||||||
|
<data key="BA">0x0080100000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x008010FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">M_AXI_B</data>
|
||||||
|
<data key="MX">/xdma_0</data>
|
||||||
|
<data key="MI">M_AXI_B</data>
|
||||||
|
<data key="MS">SEG_axil_util_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_util</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n10">
|
||||||
|
<data key="BA">0x40030000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x4003FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_system_management_wiz_0_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/system_management_wiz_0</data>
|
||||||
|
<data key="SI">S_AXI_LITE</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">xilinx.com:ip:system_management_wiz:1.3</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n11">
|
||||||
|
<data key="VM">design_1</data>
|
||||||
|
<data key="VT">BC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n12">
|
||||||
|
<data key="BA">0x0081000000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x008100FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">M_AXI_B</data>
|
||||||
|
<data key="MX">/xdma_0</data>
|
||||||
|
<data key="MI">M_AXI_B</data>
|
||||||
|
<data key="MS">SEG_axil_dma_ctrl0_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_dma_ctrl0</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n13">
|
||||||
|
<data key="BA">0x0080000000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x008000FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">M_AXI_B</data>
|
||||||
|
<data key="MX">/xdma_0</data>
|
||||||
|
<data key="MI">M_AXI_B</data>
|
||||||
|
<data key="MS">SEG_axil_descriptors_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_descriptors</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n14">
|
||||||
|
<data key="BA">0x00000000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x00007FFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">DLMB</data>
|
||||||
|
<data key="MS">SEG_dlmb_bram_if_cntlr_Mem</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/microblaze_0_local_memory/dlmb_bram_if_cntlr</data>
|
||||||
|
<data key="SI">SLMB</data>
|
||||||
|
<data key="SS">Mem</data>
|
||||||
|
<data key="SV">xilinx.com:ip:lmb_bram_if_cntlr:4.0</data>
|
||||||
|
<data key="TU">memory</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n15">
|
||||||
|
<data key="TU">active</data>
|
||||||
|
<data key="VH">2</data>
|
||||||
|
<data key="VT">PM</data>
|
||||||
|
</node>
|
||||||
|
<node id="n16">
|
||||||
|
<data key="BA">0x00000000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x00007FFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Instruction</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">ILMB</data>
|
||||||
|
<data key="MS">SEG_ilmb_bram_if_cntlr_Mem</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">instruction</data>
|
||||||
|
<data key="SX">/microblaze_0_local_memory/ilmb_bram_if_cntlr</data>
|
||||||
|
<data key="SI">SLMB</data>
|
||||||
|
<data key="SS">Mem</data>
|
||||||
|
<data key="SV">xilinx.com:ip:lmb_bram_if_cntlr:4.0</data>
|
||||||
|
<data key="TU">memory</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n17">
|
||||||
|
<data key="BA">0x0080110000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x008011FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">M_AXI_B</data>
|
||||||
|
<data key="MX">/xdma_0</data>
|
||||||
|
<data key="MI">M_AXI_B</data>
|
||||||
|
<data key="MS">SEG_axil_timing_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_timing</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n18">
|
||||||
|
<data key="BA">0x0083000000</data>
|
||||||
|
<data key="BP">baseaddr</data>
|
||||||
|
<data key="HA">0x0083FFFFFF</data>
|
||||||
|
<data key="HP">highaddr</data>
|
||||||
|
<data key="MA">M_AXI_B</data>
|
||||||
|
<data key="MX">/xdma_0</data>
|
||||||
|
<data key="MI">M_AXI_B</data>
|
||||||
|
<data key="MS">SEG_xdma_0_CTL0</data>
|
||||||
|
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/xdma_0</data>
|
||||||
|
<data key="SI">S_AXI_LITE</data>
|
||||||
|
<data key="SS">CTL0</data>
|
||||||
|
<data key="SV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TU">memory</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n19">
|
||||||
|
<data key="BA">0x0080120000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x008012FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">M_AXI_B</data>
|
||||||
|
<data key="MX">/xdma_0</data>
|
||||||
|
<data key="MI">M_AXI_B</data>
|
||||||
|
<data key="MS">SEG_axil_data_gen_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_data_gen</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n20">
|
||||||
|
<data key="BA">0x0081010000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x008101FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">M_AXI_B</data>
|
||||||
|
<data key="MX">/xdma_0</data>
|
||||||
|
<data key="MI">M_AXI_B</data>
|
||||||
|
<data key="MS">SEG_axil_dma_ctrl1_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_dma_ctrl1</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n21">
|
||||||
|
<data key="BA">0x80100000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x8010FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_axil_util_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/</data>
|
||||||
|
<data key="SI">axil_util</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">::design_1_imp:</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n22">
|
||||||
|
<data key="BA">0x40010000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x4001FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_axi_uartlite_0_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/axi_uartlite_0</data>
|
||||||
|
<data key="SI">S_AXI</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">xilinx.com:ip:axi_uartlite:2.0</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n23">
|
||||||
|
<data key="BA">0x0000000000</data>
|
||||||
|
<data key="BP">axibar_0</data>
|
||||||
|
<data key="HA">0xFFFFFFFFFF</data>
|
||||||
|
<data key="HP">axibar_highaddr_0</data>
|
||||||
|
<data key="MA">pcie_m_axi0</data>
|
||||||
|
<data key="MX">/</data>
|
||||||
|
<data key="MI">pcie_m_axi0</data>
|
||||||
|
<data key="MS">SEG_xdma_0_BAR0</data>
|
||||||
|
<data key="MV">:::</data>
|
||||||
|
<data key="TM">both</data>
|
||||||
|
<data key="SX">/xdma_0</data>
|
||||||
|
<data key="SI">S_AXI_B</data>
|
||||||
|
<data key="SS">BAR0</data>
|
||||||
|
<data key="SV">xilinx.com:ip:xdma:4.1</data>
|
||||||
|
<data key="TU">memory</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n24">
|
||||||
|
<data key="BA">0x40020000</data>
|
||||||
|
<data key="BP">C_BASEADDR</data>
|
||||||
|
<data key="HA">0x4002FFFF</data>
|
||||||
|
<data key="HP">C_HIGHADDR</data>
|
||||||
|
<data key="MA">Data</data>
|
||||||
|
<data key="MX">/microblaze_0</data>
|
||||||
|
<data key="MI">M_AXI_DP</data>
|
||||||
|
<data key="MS">SEG_microblaze_0_axi_intc_Reg</data>
|
||||||
|
<data key="MV">xilinx.com:ip:microblaze:11.0</data>
|
||||||
|
<data key="TM">data</data>
|
||||||
|
<data key="SX">/microblaze_0_axi_intc</data>
|
||||||
|
<data key="SI">s_axi</data>
|
||||||
|
<data key="MM">S_AXI</data>
|
||||||
|
<data key="SS">Reg</data>
|
||||||
|
<data key="SV">xilinx.com:ip:axi_intc:4.1</data>
|
||||||
|
<data key="TU">register</data>
|
||||||
|
<data key="VT">AC</data>
|
||||||
|
</node>
|
||||||
|
<edge id="e0" source="n11" target="n3"/>
|
||||||
|
<edge id="e1" source="n3" target="n15"/>
|
||||||
|
<edge id="e2" source="n23" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e3" source="n4" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e4" source="n2" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e5" source="n22" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e6" source="n1" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e7" source="n5" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e8" source="n8" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e9" source="n0" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e10" source="n6" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e11" source="n21" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e12" source="n14" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e13" source="n24" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e14" source="n10" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e15" source="n7" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e16" source="n16" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e17" source="n19" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e18" source="n13" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e19" source="n12" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e20" source="n20" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e21" source="n17" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e22" source="n9" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
<edge id="e23" source="n18" target="n15">
|
||||||
|
<data key="EH">2</data>
|
||||||
|
</edge>
|
||||||
|
</graph>
|
||||||
|
</graphml>
|
||||||
@@ -0,0 +1,300 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_auto_cc_0",
|
||||||
|
"cell_name": "microblaze_0_axi_periph/s00_couplers/auto_cc",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_clock_converter:2.1",
|
||||||
|
"ip_revision": "26",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_cc_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ACLK_ASYNC": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ACLK_RATIO": [ { "value": "1:2", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_auto_cc_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "26" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_cc_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"s_axi_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||||
|
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||||
|
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bready": [ { "direction": "out" } ],
|
||||||
|
"m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||||
|
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rready": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||||
|
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||||
|
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||||
|
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||||
|
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SI_CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"MI_CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "M_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "m_axi_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SI_RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"MI_RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "m_axi_aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,337 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_auto_ds_0",
|
||||||
|
"cell_name": "microblaze_0_axi_periph/s01_couplers/auto_ds",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
|
||||||
|
"ip_revision": "27",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_ds_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SI_DATA_WIDTH": [ { "value": "256", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MI_DATA_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SI_ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FIFO_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ACLK_ASYNC": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ACLK_RATIO": [ { "value": "1:2", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_auto_ds_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SUPPORTS_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FIFO_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PACKING_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "27" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_ds_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"s_axi_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
|
||||||
|
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"s_axi_rdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||||
|
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_rlast": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_wlast": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bready": [ { "direction": "out" } ],
|
||||||
|
"m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_arlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_arregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_arqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||||
|
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rready": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "s_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||||
|
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||||
|
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||||
|
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||||
|
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||||
|
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||||
|
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||||
|
"ARREGION": [ { "physical_name": "s_axi_arregion" } ],
|
||||||
|
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||||
|
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||||
|
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||||
|
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||||
|
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "m_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "m_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "m_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "m_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "m_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||||
|
"ARLEN": [ { "physical_name": "m_axi_arlen" } ],
|
||||||
|
"ARSIZE": [ { "physical_name": "m_axi_arsize" } ],
|
||||||
|
"ARBURST": [ { "physical_name": "m_axi_arburst" } ],
|
||||||
|
"ARLOCK": [ { "physical_name": "m_axi_arlock" } ],
|
||||||
|
"ARCACHE": [ { "physical_name": "m_axi_arcache" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||||
|
"ARREGION": [ { "physical_name": "m_axi_arregion" } ],
|
||||||
|
"ARQOS": [ { "physical_name": "m_axi_arqos" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||||
|
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||||
|
"RLAST": [ { "physical_name": "m_axi_rlast" } ],
|
||||||
|
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SI_CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SI_RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,297 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_auto_pc_0",
|
||||||
|
"cell_name": "microblaze_0_axi_periph/s01_couplers/auto_pc",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
|
||||||
|
"ip_revision": "27",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IGNORE_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "27" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"aclk": [ { "direction": "in" } ],
|
||||||
|
"aresetn": [ { "direction": "in" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||||
|
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_rlast": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bready": [ { "direction": "out" } ],
|
||||||
|
"m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||||
|
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rready": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "s_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||||
|
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||||
|
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||||
|
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||||
|
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||||
|
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||||
|
"ARREGION": [ { "physical_name": "s_axi_arregion" } ],
|
||||||
|
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||||
|
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||||
|
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||||
|
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||||
|
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||||
|
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,354 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_axi_interconnect_0_0",
|
||||||
|
"cell_name": "axi_interconnect_0",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
|
||||||
|
"ip_revision": "28",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"NUM_MI": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SYNCHRONIZATION_STAGES": [ { "value": "3", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M16_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M17_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M18_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M19_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M20_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M21_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M22_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M23_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M24_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M25_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M26_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M27_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M28_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M29_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M30_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M31_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M32_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M33_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M34_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M35_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M36_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M37_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M38_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M39_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M40_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M41_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M42_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M43_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M44_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M45_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M46_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M47_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M48_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M49_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M50_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M51_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M52_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M53_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M54_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M55_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M56_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M57_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M58_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M59_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M60_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M61_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M62_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M63_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M16_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M17_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M18_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M19_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
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"M21_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M22_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M23_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M25_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M29_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M30_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M33_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M34_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M35_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M36_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M37_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M38_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M39_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M40_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M42_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M44_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M45_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M46_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M47_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M48_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M49_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M50_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M51_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M52_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M53_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M54_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M55_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M56_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M57_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M58_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M59_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M60_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M61_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M62_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M63_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"S07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
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"S00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"S12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"S13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
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"S14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
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"S15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M62_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M63_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M00_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M01_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M02_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M03_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M04_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M05_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M06_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M07_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M08_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
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"M09_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M10_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M11_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
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"M12_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
|
"M13_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
|
"M14_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
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"M15_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
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}
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}
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@@ -0,0 +1,354 @@
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{
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"M49_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M52_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"M53_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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}
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}
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}
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@@ -0,0 +1,489 @@
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|
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"s_axi_arvalid": [ { "direction": "in" } ],
|
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"s_axi_arready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rready": [ { "direction": "in" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "5", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||||
|
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||||
|
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||||
|
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXI_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXI_RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"INTERRUPT": {
|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"INTERRUPT": [ { "physical_name": "interrupt" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"S_AXI": {
|
||||||
|
"display_name": "S_AXI_MEM",
|
||||||
|
"description": "Memory Map for S_AXI",
|
||||||
|
"address_blocks": {
|
||||||
|
"Reg": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "512",
|
||||||
|
"display_name": "Reg",
|
||||||
|
"description": "Register Block",
|
||||||
|
"usage": "register",
|
||||||
|
"access": "read-write",
|
||||||
|
"registers": {
|
||||||
|
"TCSR0": {
|
||||||
|
"address_offset": "0x0",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Timer 0 Control and Status Register",
|
||||||
|
"description": "Timer 0 Control and Status Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"MDT0": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Timer 0 Mode",
|
||||||
|
"description": "Timer 0 Mode\n0 - Timer mode is generate\n1 - Timer mode is capture\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"UDT0": {
|
||||||
|
"bit_offset": 1,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Timer 0 Up/Down Count",
|
||||||
|
"description": "Up/Down Count Timer 0\n 0 - Timer functions as up counter\n 1 - Timer functions as down counter\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"GENT0": {
|
||||||
|
"bit_offset": 2,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Generate Signal Timer 0",
|
||||||
|
"description": "Enable External Generate Signal Timer 0\n 0 - Disables external generate signal\n 1 - Enables external generate signal\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"CAPT0": {
|
||||||
|
"bit_offset": 3,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Capture Trigger Timer 0",
|
||||||
|
"description": "Enable External Capture Trigger Timer 0\n 0 - Disables external capture trigger\n 1 - Enables external capture trigger\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ARHT0": {
|
||||||
|
"bit_offset": 4,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Auto Reload/Hold Timer 0",
|
||||||
|
"description": "Auto Reload/Hold Timer 0.\nWhen the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. \nIn Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held. 0 = Hold counter or capture value. The TLR must be read before providing the external capture. 1 = Reload generate value or overwrite capture value\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"LOAD0": {
|
||||||
|
"bit_offset": 5,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Load Timer 0",
|
||||||
|
"description": "Load Timer 0 0 = No load 1 = Loads timer with value in TLR0 Setting this bit loads timer/counter register (TCR0) with a specified value in the timer/counter load register (TLR0). This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT0) bit in TCSR0.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ENIT0": {
|
||||||
|
"bit_offset": 6,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Enable Interrupt for Timer 0",
|
||||||
|
"description": "Enable Interrupt for Timer 0\nEnables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T0INT) in TCSR0. 0 - Disable interrupt signal 1 - Enable interrupt signal\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ENT0": {
|
||||||
|
"bit_offset": 7,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Enable Timer 0",
|
||||||
|
"description": "Enable Timer 0\n 0 - Disable timer (counter halts)\n 1 - Enable timer (counter runs)\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"T0INT": {
|
||||||
|
"bit_offset": 8,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Timer 0 Interrupt",
|
||||||
|
"description": "Timer 0 Interrupt\nIndicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.\nRead: 0 - No interrupt has occurred 1 - Interrupt has occurred Write: 0 - No change in state of T0INT 1 - Clear T0INT (clear to 0)\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"PWMA0": {
|
||||||
|
"bit_offset": 9,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Pulse Width Modulation for Timer 0",
|
||||||
|
"description": "Enable Pulse Width Modulation for Timer 0 0 - Disable pulse width modulation 1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0 and C_GEN0_ASSERT and C_GEN1_ASSERT must be 1.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ENALL": {
|
||||||
|
"bit_offset": 10,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Enable All Timers",
|
||||||
|
"description": "Enable All Timers 0 - No effect on timers 1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. \nWriting a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. \n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"CASC": {
|
||||||
|
"bit_offset": 11,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Cascade Mode of Timers",
|
||||||
|
"description": "Enable cascade mode of timers 0 - Disable cascaded operation 1 - Enable cascaded operation Cascaded operation requires using Timer 0 and Timer 1 together as a pair. The counting event for the Timer 1 is when the Timer 0 rolls over from all 1s to all 0s or vice-versa when counting down.\nTLR0 and TLR1 are used for lower 32-bit and higher 32-bit respectively. Similarly, TCR0 contains lower 32-bits for the 64-bit counter and TCR1 contains the higher 32-bits.\nOnly TCSR0 is valid for both the timer/counters in this mode.\nThis CASC bit must be set before enabling the timer/counter.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"TLR0": {
|
||||||
|
"address_offset": "0x4",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Timer 0 Load Register",
|
||||||
|
"description": "Timer 0 Load Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"TCLR0": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 32,
|
||||||
|
"display_name": "Timer/Counter Load Register",
|
||||||
|
"description": "Timer/Counter Load Register\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"TCR0": {
|
||||||
|
"address_offset": "0x8",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Timer 0 Counter Register",
|
||||||
|
"description": "Timer 0 Counter Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"TCR0": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 32,
|
||||||
|
"display_name": "Timer/Counter Register",
|
||||||
|
"description": "Timer/Counter Register\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"TCSR1": {
|
||||||
|
"address_offset": "0x10",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Timer 1 Control and Status Register",
|
||||||
|
"description": "Timer 1 Control and Status Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"MDT1": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Timer 1 Mode",
|
||||||
|
"description": "Timer 1 Mode\n 0 - Timer mode is generate\n 1 - Timer mode is capture\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"UDT1": {
|
||||||
|
"bit_offset": 1,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Timer 1 Up/Down Count",
|
||||||
|
"description": "Up/Down Count Timer 1\n 0 - Timer functions as up counter\n 1 - Timer functions as down counter\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"GENT1": {
|
||||||
|
"bit_offset": 2,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Generate Signal Timer 1",
|
||||||
|
"description": "Enable External Generate Signal Timer 1\n 0 - Disables external generate signal\n 1 - Enables external generate signal\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"CAPT1": {
|
||||||
|
"bit_offset": 3,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Capture Trigger Timer 1",
|
||||||
|
"description": "Enable External Capture Trigger Timer 1\n 0 - Disables external capture trigger\n 1 - Enables external capture trigger\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ARHT1": {
|
||||||
|
"bit_offset": 4,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Auto Reload/Hold Timer 1",
|
||||||
|
"description": "Auto Reload/Hold Timer 1.\nWhen the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. \nIn Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.\n0 = Hold counter or capture value. The TLR must be read before providing the external capture. \n1 = Reload generate value or overwrite capture value\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"LOAD1": {
|
||||||
|
"bit_offset": 5,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Load Timer 1",
|
||||||
|
"description": "Load Timer 1 0 = No load 1 = Loads timer with value in TLR1 Setting this bit loads timer/counter register (TCR1) with a specified value in the timer/counter load register (TLR1). This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT1) bit in TCSR1.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ENIT1": {
|
||||||
|
"bit_offset": 6,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Enable Interrupt for Timer 1",
|
||||||
|
"description": "Enable Interrupt for Timer 1\nEnables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T1INT) in TCSR1. 0 - Disable interrupt signal 1 - Enable interrupt signal\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ENT1": {
|
||||||
|
"bit_offset": 7,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Enable Timer 1",
|
||||||
|
"description": "Enable Timer 1\n 0 - Disable timer (counter halts)\n 1 - Enable timer (counter runs)\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"T1INT": {
|
||||||
|
"bit_offset": 8,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Timer 1 Interrupt",
|
||||||
|
"description": "Timer 1 Interrupt\nIndicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.\nRead: 0 - No interrupt has occurred 1 - Interrupt has occurred Write: 0 - No change in state of T0INT 1 - Clear T1INT (clear to 0)\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"PWMA1": {
|
||||||
|
"bit_offset": 9,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Pulse Width Modulation for Timer 1",
|
||||||
|
"description": "Enable Pulse Width Modulation for Timer 1 0 - Disable pulse width modulation 1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"ENALL": {
|
||||||
|
"bit_offset": 10,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Enable All Timers",
|
||||||
|
"description": "Enable All Timers 0 - No effect on timers 1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. \n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"TLR1": {
|
||||||
|
"address_offset": "0x14",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Timer 1 Load Register",
|
||||||
|
"description": "Timer 1 Load Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"TCLR1": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 32,
|
||||||
|
"display_name": "Timer/Counter Load Register",
|
||||||
|
"description": "Timer/Counter Load Register\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"TCR1": {
|
||||||
|
"address_offset": "0x18",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Timer 1 Counter Register",
|
||||||
|
"description": "Timer 1 Counter Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"TCR1": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 32,
|
||||||
|
"display_name": "Timer/Counter Register",
|
||||||
|
"description": "Timer/Counter Register\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,364 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_axi_uartlite_0_0",
|
||||||
|
"cell_name": "axi_uartlite_0",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_uartlite:2.0",
|
||||||
|
"ip_revision": "31",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_DATA_BITS": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BAUDRATE": [ { "value": "115200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_FREQ_HZ_d": [ { "value": "100.0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_axi_uartlite_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PARITY": [ { "value": "No_Parity", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_USE_PARITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ODD_PARITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"UARTLITE_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ADDR_WIDTH": [ { "value": "4", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BAUDRATE": [ { "value": "115200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DATA_BITS": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_PARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ODD_PARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "31" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||||
|
"interrupt": [ { "direction": "out" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axi_arready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"rx": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"tx": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||||
|
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||||
|
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||||
|
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"INTERRUPT": {
|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"INTERRUPT": [ { "physical_name": "interrupt" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"UART": {
|
||||||
|
"vlnv": "xilinx.com:interface:uart:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:uart_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"BOARD.ASSOCIATED_PARAM": [ { "value": "UARTLITE_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RxD": [ { "physical_name": "rx" } ],
|
||||||
|
"TxD": [ { "physical_name": "tx" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"S_AXI": {
|
||||||
|
"display_name": "S_AXI_MEM",
|
||||||
|
"description": "Memory Map for S_AXI",
|
||||||
|
"address_blocks": {
|
||||||
|
"Reg": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
|
||||||
|
"display_name": "Reg",
|
||||||
|
"description": "Register Block",
|
||||||
|
"usage": "register",
|
||||||
|
"access": "read-write",
|
||||||
|
"registers": {
|
||||||
|
"RX_FIFO": {
|
||||||
|
"address_offset": "0x0",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "RX FIFO",
|
||||||
|
"description": "Receive data FIFO",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"RX_DATA": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 8,
|
||||||
|
"display_name": "Receive Data",
|
||||||
|
"description": "UART Receive Data\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"TX_FIFO": {
|
||||||
|
"address_offset": "0x4",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "TX FIFO",
|
||||||
|
"description": "Transmit data FIFO",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"TX_DATA": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 8,
|
||||||
|
"display_name": "Transmit Data",
|
||||||
|
"description": "UART Transmit Data\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CTRL_REG": {
|
||||||
|
"address_offset": "0xC",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Control Register",
|
||||||
|
"description": "UART Lite control register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"RST_TXFIFO": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Reset Tx FIFO",
|
||||||
|
"description": "Reset/clear the transmit FIFO\nWriting a 1 to this bit position clears the transmit FIFO\n 0 - Do nothing\n 1 - Clear the transmit FIFO\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only"
|
||||||
|
},
|
||||||
|
"RST_RXFIFO": {
|
||||||
|
"bit_offset": 1,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Reset Rx FIFO",
|
||||||
|
"description": "Reset/clear the receive FIFO\nWriting a 1 to this bit position clears the receive FIFO\n 0 - Do nothing\n 1 - Clear the receive FIFO\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only"
|
||||||
|
},
|
||||||
|
"Enable_Intr": {
|
||||||
|
"bit_offset": 4,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Enable interrupt",
|
||||||
|
"description": "Enable interrupt for the AXI UART Lite\n 0 - Disable interrupt signal\n 1 - Enable interrupt signal\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"STAT_REG": {
|
||||||
|
"address_offset": "0x8",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Status Register",
|
||||||
|
"description": "UART Lite status register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"RX_FIFO_Valid_Data": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "RX FIFO Valid Data",
|
||||||
|
"description": "Indicates if the receive FIFO has data.\n 0 - Receive FIFO is empty\n 1 - Receive FIFO has data\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
},
|
||||||
|
"RX_FIFO_Full": {
|
||||||
|
"bit_offset": 1,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "RX FIFO Full",
|
||||||
|
"description": "Indicates if the receive FIFO is full.\n 0 - Receive FIFO is not full\n 1 - Receive FIFO is full\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
},
|
||||||
|
"TX_FIFO_Empty": {
|
||||||
|
"bit_offset": 2,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "TX FIFO Empty",
|
||||||
|
"description": "Indicates if the transmit FIFO is empty.\n 0 - Transmit FIFO is not empty\n 1 - Transmit FIFO is empty\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
},
|
||||||
|
"TX_FIFO_Full": {
|
||||||
|
"bit_offset": 3,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "TX FIFO Full",
|
||||||
|
"description": "Indicates if the transmit FIFO is full.\n 0 - Transmit FIFO is not full\n 1 - Transmit FIFO is full\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
},
|
||||||
|
"Intr_Enabled": {
|
||||||
|
"bit_offset": 4,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Interrupt Enabled",
|
||||||
|
"description": "Indicates that interrupts is enabled.\n 0 - Interrupt is disabled\n 1 - Interrupt is enabled\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
},
|
||||||
|
"Overrun_Error": {
|
||||||
|
"bit_offset": 5,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Overrun Error",
|
||||||
|
"description": "Indicates that a overrun error has occurred after the last time the status register was read. Overrun is when a new character has been received but the receive FIFO is full. The received character is ignored and not written into the receive FIFO. This bit is cleared when the status register is read. 0 - No overrun error has occurred 1 - Overrun error has occurred\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
},
|
||||||
|
"Frame_Error": {
|
||||||
|
"bit_offset": 6,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Frame Error",
|
||||||
|
"description": "Indicates that a frame error has occurred after the last time the status register was read. Frame error is defined as detection of a stop bit with the value 0. The receive character is ignored and not written to the receive FIFO. This bit is cleared when the status register is read. 0 - No frame error has occurred 1 - Frame error has occurred\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
},
|
||||||
|
"Parity_Error": {
|
||||||
|
"bit_offset": 7,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Parity Error",
|
||||||
|
"description": "Indicates that a parity error has occurred after the last time the status register was read. If the UART is configured without any parity handling, this bit is always 0. The received character is written into the receive FIFO. This bit is cleared when the status register is read. 0 - No parity error has occurred 1 - Parity error has occurred\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,655 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_clk_wiz_1_0",
|
||||||
|
"cell_name": "clk_wiz_1",
|
||||||
|
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||||
|
"ip_revision": "11",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "design_1_clk_wiz_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_PHASE_ALIGNMENT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT4_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT5_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT6_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT7_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_LOCKED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "12.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_JITTER": [ { "value": "106.024", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_PHASE_ERROR": [ { "value": "82.655", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"c_component_name": [ { "value": "design_1_clk_wiz_1_0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_PHASE_ALIGNMENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__100.00000______0.000______50.0______106.024_____82.655", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_OUT_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||||
|
"C_MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "12.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE2_AUTO": [ { "value": "0.08333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE3_AUTO": [ { "value": "0.08333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE4_AUTO": [ { "value": "0.08333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE5_AUTO": [ { "value": "0.08333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE6_AUTO": [ { "value": "0.08333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE7_AUTO": [ { "value": "0.08333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_M_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_VCO_MIN": [ { "value": "800.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "11" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"clk_in1_p": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"clk_in1_n": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"clk_out1": [ { "direction": "out" } ],
|
||||||
|
"locked": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"CLK_IN1_D": {
|
||||||
|
"vlnv": "xilinx.com:interface:diff_clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK_N": [ { "physical_name": "clk_in1_n" } ],
|
||||||
|
"CLK_P": [ { "physical_name": "clk_in1_p" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"clock_CLK_OUT1": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,293 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_dlmb_bram_if_cntlr_0",
|
||||||
|
"cell_name": "microblaze_0_local_memory/dlmb_bram_if_cntlr",
|
||||||
|
"component_reference": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
|
||||||
|
"ip_revision": "21",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_BASEADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_HIGHADDR": [ { "value": "0x0000000000007FFF", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_MASK": [ { "value": "0x00000000c0000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_MASK1": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK2": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK3": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_NUM_LMB": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ECC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERCONNECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_dlmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HIGHADDR": [ { "value": "0x0000000000007FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MASK": [ { "value": "0x00000000c0000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_MASK1": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK2": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK3": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERCONNECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_BRAM_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "21" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"LMB_Clk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"LMB_Rst": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"LMB_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_WriteDBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
|
||||||
|
"LMB_AddrStrobe": [ { "direction": "in" } ],
|
||||||
|
"LMB_ReadStrobe": [ { "direction": "in" } ],
|
||||||
|
"LMB_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"LMB_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
|
||||||
|
"Sl_DBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"Sl_Ready": [ { "direction": "out" } ],
|
||||||
|
"Sl_Wait": [ { "direction": "out" } ],
|
||||||
|
"Sl_UE": [ { "direction": "out" } ],
|
||||||
|
"Sl_CE": [ { "direction": "out" } ],
|
||||||
|
"BRAM_Rst_A": [ { "direction": "out" } ],
|
||||||
|
"BRAM_Clk_A": [ { "direction": "out" } ],
|
||||||
|
"BRAM_Addr_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"BRAM_EN_A": [ { "direction": "out" } ],
|
||||||
|
"BRAM_WEN_A": [ { "direction": "out", "size_left": "0", "size_right": "3" } ],
|
||||||
|
"BRAM_Dout_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"BRAM_Din_A": [ { "direction": "in", "size_left": "0", "size_right": "31" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"SLMB": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"memory_map_ref": "SLMB",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "LMB_ABus" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
|
||||||
|
"BE": [ { "physical_name": "LMB_BE" } ],
|
||||||
|
"CE": [ { "physical_name": "Sl_CE" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "Sl_DBus" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
|
||||||
|
"READY": [ { "physical_name": "Sl_Ready" } ],
|
||||||
|
"UE": [ { "physical_name": "Sl_UE" } ],
|
||||||
|
"WAIT": [ { "physical_name": "Sl_Wait" } ],
|
||||||
|
"WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
|
||||||
|
"WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"BRAM_PORT": {
|
||||||
|
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_ECC": [ { "value": "NONE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ADDR": [ { "physical_name": "BRAM_Addr_A" } ],
|
||||||
|
"CLK": [ { "physical_name": "BRAM_Clk_A" } ],
|
||||||
|
"DIN": [ { "physical_name": "BRAM_Dout_A" } ],
|
||||||
|
"DOUT": [ { "physical_name": "BRAM_Din_A" } ],
|
||||||
|
"EN": [ { "physical_name": "BRAM_EN_A" } ],
|
||||||
|
"RST": [ { "physical_name": "BRAM_Rst_A" } ],
|
||||||
|
"WE": [ { "physical_name": "BRAM_WEN_A" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK.LMB_Clk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "SLMB:SLMB1:SLMB2:SLMB3", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "LMB_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "LMB_Clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.LMB_Rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "LMB_Rst" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK.S_AXI_CTRL_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_CTRL", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "S_AXI_CTRL_ARESETN", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.S_AXI_CTRL_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"SLMB": {
|
||||||
|
"description": "SLMB memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SLMB1": {
|
||||||
|
"description": "SLMB1 memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SLMB2": {
|
||||||
|
"description": "SLMB2 memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SLMB3": {
|
||||||
|
"description": "SLMB3 memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXI_CTRL": {
|
||||||
|
"description": "S_AXI_CTRL memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Reg": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
|
||||||
|
"display_name": "Reg",
|
||||||
|
"description": "Register Block",
|
||||||
|
"usage": "register",
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,164 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_dlmb_v10_0",
|
||||||
|
"cell_name": "microblaze_0_local_memory/dlmb_v10",
|
||||||
|
"component_reference": "xilinx.com:ip:lmb_v10:3.0",
|
||||||
|
"ip_revision": "12",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_dlmb_v10_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_dlmb_v10_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "12" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_dlmb_v10_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"LMB_Clk": [ { "direction": "in" } ],
|
||||||
|
"SYS_Rst": [ { "direction": "in" } ],
|
||||||
|
"LMB_Rst": [ { "direction": "out" } ],
|
||||||
|
"M_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"M_ReadStrobe": [ { "direction": "in" } ],
|
||||||
|
"M_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"M_AddrStrobe": [ { "direction": "in" } ],
|
||||||
|
"M_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
|
||||||
|
"M_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
|
||||||
|
"Sl_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"Sl_Ready": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"Sl_Wait": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"Sl_UE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"Sl_CE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"LMB_ABus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_ReadStrobe": [ { "direction": "out" } ],
|
||||||
|
"LMB_WriteStrobe": [ { "direction": "out" } ],
|
||||||
|
"LMB_AddrStrobe": [ { "direction": "out" } ],
|
||||||
|
"LMB_ReadDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_WriteDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_Ready": [ { "direction": "out" } ],
|
||||||
|
"LMB_Wait": [ { "direction": "out" } ],
|
||||||
|
"LMB_UE": [ { "direction": "out" } ],
|
||||||
|
"LMB_CE": [ { "direction": "out" } ],
|
||||||
|
"LMB_BE": [ { "direction": "out", "size_left": "0", "size_right": "3" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"LMB_Sl_0": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "mirroredSlave",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "LMB_ABus" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
|
||||||
|
"BE": [ { "physical_name": "LMB_BE" } ],
|
||||||
|
"CE": [ { "physical_name": "Sl_CE", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "Sl_DBus", "physical_left": "0", "physical_right": "31" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
|
||||||
|
"READY": [ { "physical_name": "Sl_Ready", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"RST": [ { "physical_name": "LMB_Rst" } ],
|
||||||
|
"UE": [ { "physical_name": "Sl_UE", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"WAIT": [ { "physical_name": "Sl_Wait", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
|
||||||
|
"WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"LMB_M": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "mirroredMaster",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "M_ABus" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "M_AddrStrobe" } ],
|
||||||
|
"BE": [ { "physical_name": "M_BE" } ],
|
||||||
|
"CE": [ { "physical_name": "LMB_CE" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "LMB_ReadDBus" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "M_ReadStrobe" } ],
|
||||||
|
"READY": [ { "physical_name": "LMB_Ready" } ],
|
||||||
|
"RST": [ { "physical_name": "LMB_Rst" } ],
|
||||||
|
"UE": [ { "physical_name": "LMB_UE" } ],
|
||||||
|
"WAIT": [ { "physical_name": "LMB_Wait" } ],
|
||||||
|
"WRITEDBUS": [ { "physical_name": "M_DBus" } ],
|
||||||
|
"WRITESTROBE": [ { "physical_name": "M_WriteStrobe" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK.LMB_Clk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "SYS_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "LMB_Clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.SYS_Rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "SYS_Rst" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,293 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_ilmb_bram_if_cntlr_0",
|
||||||
|
"cell_name": "microblaze_0_local_memory/ilmb_bram_if_cntlr",
|
||||||
|
"component_reference": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
|
||||||
|
"ip_revision": "21",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_BASEADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_HIGHADDR": [ { "value": "0x0000000000007FFF", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_MASK": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_MASK1": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK2": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK3": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_NUM_LMB": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ECC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERCONNECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_ilmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HIGHADDR": [ { "value": "0x0000000000007FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MASK": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_MASK1": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK2": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MASK3": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERCONNECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_BRAM_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "21" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"LMB_Clk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"LMB_Rst": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"LMB_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_WriteDBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
|
||||||
|
"LMB_AddrStrobe": [ { "direction": "in" } ],
|
||||||
|
"LMB_ReadStrobe": [ { "direction": "in" } ],
|
||||||
|
"LMB_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"LMB_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
|
||||||
|
"Sl_DBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"Sl_Ready": [ { "direction": "out" } ],
|
||||||
|
"Sl_Wait": [ { "direction": "out" } ],
|
||||||
|
"Sl_UE": [ { "direction": "out" } ],
|
||||||
|
"Sl_CE": [ { "direction": "out" } ],
|
||||||
|
"BRAM_Rst_A": [ { "direction": "out" } ],
|
||||||
|
"BRAM_Clk_A": [ { "direction": "out" } ],
|
||||||
|
"BRAM_Addr_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"BRAM_EN_A": [ { "direction": "out" } ],
|
||||||
|
"BRAM_WEN_A": [ { "direction": "out", "size_left": "0", "size_right": "3" } ],
|
||||||
|
"BRAM_Dout_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"BRAM_Din_A": [ { "direction": "in", "size_left": "0", "size_right": "31" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"SLMB": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"memory_map_ref": "SLMB",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "LMB_ABus" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
|
||||||
|
"BE": [ { "physical_name": "LMB_BE" } ],
|
||||||
|
"CE": [ { "physical_name": "Sl_CE" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "Sl_DBus" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
|
||||||
|
"READY": [ { "physical_name": "Sl_Ready" } ],
|
||||||
|
"UE": [ { "physical_name": "Sl_UE" } ],
|
||||||
|
"WAIT": [ { "physical_name": "Sl_Wait" } ],
|
||||||
|
"WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
|
||||||
|
"WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"BRAM_PORT": {
|
||||||
|
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_ECC": [ { "value": "NONE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ADDR": [ { "physical_name": "BRAM_Addr_A" } ],
|
||||||
|
"CLK": [ { "physical_name": "BRAM_Clk_A" } ],
|
||||||
|
"DIN": [ { "physical_name": "BRAM_Dout_A" } ],
|
||||||
|
"DOUT": [ { "physical_name": "BRAM_Din_A" } ],
|
||||||
|
"EN": [ { "physical_name": "BRAM_EN_A" } ],
|
||||||
|
"RST": [ { "physical_name": "BRAM_Rst_A" } ],
|
||||||
|
"WE": [ { "physical_name": "BRAM_WEN_A" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK.LMB_Clk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "SLMB:SLMB1:SLMB2:SLMB3", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "LMB_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "LMB_Clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.LMB_Rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "LMB_Rst" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK.S_AXI_CTRL_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI_CTRL", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "S_AXI_CTRL_ARESETN", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.S_AXI_CTRL_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"SLMB": {
|
||||||
|
"description": "SLMB memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SLMB1": {
|
||||||
|
"description": "SLMB1 memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SLMB2": {
|
||||||
|
"description": "SLMB2 memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SLMB3": {
|
||||||
|
"description": "SLMB3 memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "8192",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXI_CTRL": {
|
||||||
|
"description": "S_AXI_CTRL memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Reg": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
|
||||||
|
"display_name": "Reg",
|
||||||
|
"description": "Register Block",
|
||||||
|
"usage": "register",
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,164 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_ilmb_v10_0",
|
||||||
|
"cell_name": "microblaze_0_local_memory/ilmb_v10",
|
||||||
|
"component_reference": "xilinx.com:ip:lmb_v10:3.0",
|
||||||
|
"ip_revision": "12",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_ilmb_v10_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_ilmb_v10_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "12" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_ilmb_v10_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"LMB_Clk": [ { "direction": "in" } ],
|
||||||
|
"SYS_Rst": [ { "direction": "in" } ],
|
||||||
|
"LMB_Rst": [ { "direction": "out" } ],
|
||||||
|
"M_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"M_ReadStrobe": [ { "direction": "in" } ],
|
||||||
|
"M_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"M_AddrStrobe": [ { "direction": "in" } ],
|
||||||
|
"M_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
|
||||||
|
"M_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
|
||||||
|
"Sl_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"Sl_Ready": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"Sl_Wait": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"Sl_UE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"Sl_CE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"LMB_ABus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_ReadStrobe": [ { "direction": "out" } ],
|
||||||
|
"LMB_WriteStrobe": [ { "direction": "out" } ],
|
||||||
|
"LMB_AddrStrobe": [ { "direction": "out" } ],
|
||||||
|
"LMB_ReadDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_WriteDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"LMB_Ready": [ { "direction": "out" } ],
|
||||||
|
"LMB_Wait": [ { "direction": "out" } ],
|
||||||
|
"LMB_UE": [ { "direction": "out" } ],
|
||||||
|
"LMB_CE": [ { "direction": "out" } ],
|
||||||
|
"LMB_BE": [ { "direction": "out", "size_left": "0", "size_right": "3" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"LMB_Sl_0": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "mirroredSlave",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "LMB_ABus" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
|
||||||
|
"BE": [ { "physical_name": "LMB_BE" } ],
|
||||||
|
"CE": [ { "physical_name": "Sl_CE", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "Sl_DBus", "physical_left": "0", "physical_right": "31" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
|
||||||
|
"READY": [ { "physical_name": "Sl_Ready", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"RST": [ { "physical_name": "LMB_Rst" } ],
|
||||||
|
"UE": [ { "physical_name": "Sl_UE", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"WAIT": [ { "physical_name": "Sl_Wait", "physical_left": "0", "physical_right": "0" } ],
|
||||||
|
"WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
|
||||||
|
"WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"LMB_M": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "mirroredMaster",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "M_ABus" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "M_AddrStrobe" } ],
|
||||||
|
"BE": [ { "physical_name": "M_BE" } ],
|
||||||
|
"CE": [ { "physical_name": "LMB_CE" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "LMB_ReadDBus" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "M_ReadStrobe" } ],
|
||||||
|
"READY": [ { "physical_name": "LMB_Ready" } ],
|
||||||
|
"RST": [ { "physical_name": "LMB_Rst" } ],
|
||||||
|
"UE": [ { "physical_name": "LMB_UE" } ],
|
||||||
|
"WAIT": [ { "physical_name": "LMB_Wait" } ],
|
||||||
|
"WRITEDBUS": [ { "physical_name": "M_DBus" } ],
|
||||||
|
"WRITESTROBE": [ { "physical_name": "M_WriteStrobe" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK.LMB_Clk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "SYS_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "LMB_Clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.SYS_Rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "SYS_Rst" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,294 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_lmb_bram_0",
|
||||||
|
"cell_name": "microblaze_0_local_memory/lmb_bram",
|
||||||
|
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||||
|
"ip_revision": "5",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_lmb_bram_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "design_1_lmb_bram_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_32bit_Address": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_Byte_Write_Enable": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Byte_Size": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Write_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Write_Depth_A": [ { "value": "8192", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Read_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Write_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Read_Width_B": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_RSTA_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Use_RSTB_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_B_Clock": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_B_Write_Rate": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Port_B_Enable_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"use_bram_block": [ { "value": "BRAM_Controller", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MEM_FILE": [ { "value": "design_1_lmb_bram_0.mem", "value_src": "ip_propagated", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CTRL_ECC_ALGO": [ { "value": "NONE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"EN_SAFETY_CKT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BRAM_BLOCK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_32BIT_ADDRESS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MEM_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BYTE_SIZE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INIT_FILE": [ { "value": "design_1_lmb_bram_0.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_RSTA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WEA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADDRA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_RSTB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WEB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WRITE_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADDRB_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_SAFETY_CKT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_COUNT_36K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 17.246228 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "5" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_lmb_bram_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"rsta": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"ena": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"addra": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"clkb": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"rstb": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"enb": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"web": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"addrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"dinb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"doutb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"rsta_busy": [ { "direction": "out" } ],
|
||||||
|
"rstb_busy": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"CLK.ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"BRAM_PORTA": {
|
||||||
|
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"MEM_SIZE": [ { "value": "32768", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_ECC": [ { "value": "NONE", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ADDR": [ { "physical_name": "addra" } ],
|
||||||
|
"CLK": [ { "physical_name": "clka" } ],
|
||||||
|
"DIN": [ { "physical_name": "dina" } ],
|
||||||
|
"DOUT": [ { "physical_name": "douta" } ],
|
||||||
|
"EN": [ { "physical_name": "ena" } ],
|
||||||
|
"RST": [ { "physical_name": "rsta" } ],
|
||||||
|
"WE": [ { "physical_name": "wea" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"BRAM_PORTB": {
|
||||||
|
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"MEM_SIZE": [ { "value": "32768", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MEM_ECC": [ { "value": "NONE", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ADDR": [ { "physical_name": "addrb" } ],
|
||||||
|
"CLK": [ { "physical_name": "clkb" } ],
|
||||||
|
"DIN": [ { "physical_name": "dinb" } ],
|
||||||
|
"DOUT": [ { "physical_name": "doutb" } ],
|
||||||
|
"EN": [ { "physical_name": "enb" } ],
|
||||||
|
"RST": [ { "physical_name": "rstb" } ],
|
||||||
|
"WE": [ { "physical_name": "web" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"S_1": {
|
||||||
|
"address_blocks": {
|
||||||
|
"Mem0": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
|
||||||
|
"usage": "memory",
|
||||||
|
"access": "read-write",
|
||||||
|
"parameters": {
|
||||||
|
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||||
|
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,348 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_m00_data_fifo_0",
|
||||||
|
"cell_name": "axi_interconnect_1/m00_couplers/m00_data_fifo",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_data_fifo:2.1",
|
||||||
|
"ip_revision": "26",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_m00_data_fifo_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WRITE_FIFO_DEPTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"READ_FIFO_DEPTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WRITE_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"READ_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_m00_data_fifo_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "26" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_m00_data_fifo_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"aclk": [ { "direction": "in" } ],
|
||||||
|
"aresetn": [ { "direction": "in" } ],
|
||||||
|
"s_axi_awid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
|
||||||
|
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_arready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"s_axi_rdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||||
|
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_rlast": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_awid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||||
|
"m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_wlast": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bready": [ { "direction": "out" } ],
|
||||||
|
"m_axi_arid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_arlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_arregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_arqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||||
|
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_rready": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "s_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||||
|
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||||
|
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||||
|
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||||
|
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||||
|
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||||
|
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||||
|
"ARREGION": [ { "physical_name": "s_axi_arregion" } ],
|
||||||
|
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||||
|
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||||
|
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||||
|
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||||
|
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWID": [ { "physical_name": "m_axi_awid" } ],
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "m_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "m_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "m_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "m_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "m_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||||
|
"BID": [ { "physical_name": "m_axi_bid" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||||
|
"ARID": [ { "physical_name": "m_axi_arid" } ],
|
||||||
|
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||||
|
"ARLEN": [ { "physical_name": "m_axi_arlen" } ],
|
||||||
|
"ARSIZE": [ { "physical_name": "m_axi_arsize" } ],
|
||||||
|
"ARBURST": [ { "physical_name": "m_axi_arburst" } ],
|
||||||
|
"ARLOCK": [ { "physical_name": "m_axi_arlock" } ],
|
||||||
|
"ARCACHE": [ { "physical_name": "m_axi_arcache" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||||
|
"ARREGION": [ { "physical_name": "m_axi_arregion" } ],
|
||||||
|
"ARQOS": [ { "physical_name": "m_axi_arqos" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||||
|
"RID": [ { "physical_name": "m_axi_rid" } ],
|
||||||
|
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||||
|
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||||
|
"RLAST": [ { "physical_name": "m_axi_rlast" } ],
|
||||||
|
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||||
|
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,170 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_mdm_1_0",
|
||||||
|
"cell_name": "mdm_1",
|
||||||
|
"component_reference": "xilinx.com:ip:mdm:3.2",
|
||||||
|
"ip_revision": "23",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_mdm_1_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_XMTC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BRK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_JTAG_CHAIN": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BSCAN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BSCANID": [ { "value": "76547328", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DEBUG_INTERFACE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERCONNECT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADDR_SIZE": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_ID_WIDTH": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_UART": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRIG_IN_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_TRIG_OUT_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_EXT_TRIG_RESET_VALUE": [ { "value": "0xF1234", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_TRACE_OUTPUT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRACE_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_TRACE_CLK_FREQ_HZ": [ { "value": "200000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRACE_CLK_OUT_PHASE": [ { "value": "90", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRACE_PROTOCOL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRACE_ID": [ { "value": "110", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_mdm_1_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DEVICE": [ { "value": "xczu7ev", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_JTAG_CHAIN": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BSCAN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BSCANID": [ { "value": "76547328", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERCONNECT": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_UART": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EXT_TRIG_RESET_VALUE": [ { "value": "0xF1234", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_TRACE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRACE_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_TRACE_CLK_FREQ_HZ": [ { "value": "200000000", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_TRACE_CLK_OUT_PHASE": [ { "value": "90", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_TRACE_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_TRACE_ID": [ { "value": "110", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_M_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ADDR_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
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|
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|
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|
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|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
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|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
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|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_mdm_1_0" } ],
|
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|
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"SHAREDDIR": [ { "value": "../../ipshared" } ],
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"SWVERSION": [ { "value": "2022.2" } ],
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"Dbg_Disable_0": [ { "direction": "out" } ]
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||||||
|
},
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||||||
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"vlnv": "xilinx.com:signal:reset:1.0",
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|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
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|
"mode": "master",
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"parameters": {
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"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"RST": [ { "physical_name": "Debug_SYS_Rst" } ]
|
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|
}
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},
|
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|
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|
||||||
|
"vlnv": "xilinx.com:interface:mbdebug:3.0",
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|
"abstraction_type": "xilinx.com:interface:mbdebug_rtl:3.0",
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|
"mode": "master",
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|
"port_maps": {
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|
"CAPTURE": [ { "physical_name": "Dbg_Capture_0" } ],
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|
"CLK": [ { "physical_name": "Dbg_Clk_0" } ],
|
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|
"DISABLE": [ { "physical_name": "Dbg_Disable_0" } ],
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||||||
|
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|
"RST": [ { "physical_name": "Dbg_Rst_0" } ],
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||||||
|
"SHIFT": [ { "physical_name": "Dbg_Shift_0" } ],
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||||||
|
"TDI": [ { "physical_name": "Dbg_TDI_0" } ],
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|
"TDO": [ { "physical_name": "Dbg_TDO_0" } ],
|
||||||
|
"UPDATE": [ { "physical_name": "Dbg_Update_0" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
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|
"S_AXI": {
|
||||||
|
"description": "S_AXI memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Reg": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
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||||||
|
"display_name": "Reg",
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||||||
|
"description": "Register Block",
|
||||||
|
"usage": "register",
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,689 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_microblaze_0_0",
|
||||||
|
"cell_name": "microblaze_0",
|
||||||
|
"component_reference": "xilinx.com:ip:microblaze:11.0",
|
||||||
|
"ip_revision": "10",
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||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_microblaze_0_0",
|
||||||
|
"parameters": {
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||||||
|
"component_parameters": {
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"C_FREQ": [ { "value": "100000000", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_LMB_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_ADDR_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_DYNAMIC_BUS_SIZING": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_PC_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
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|
"C_INSTANCE": [ { "value": "microblaze", "resolve_type": "user", "usage": "all" } ],
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|
"C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_FAULT_TOLERANT": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_ECC_USE_CE_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_LOCKSTEP_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_TEMPORAL_DEPTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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|
"C_ENDIANNESS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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|
"C_INTERCONNECT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"C_BASE_VECTORS": [ { "value": "0x0000000000000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
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"C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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|
||||||
|
"C_NUM_SYNC_FF_CLK_IRQ": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_CLK_DEBUG": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_DBG_CLK": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_DBG_TRACE_CLK": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DP_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DP_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DP_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DP_EXCLUSIVE_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_D_AXI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DP_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DC_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||||
|
"C_D_LMB": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_D_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_D_LMB_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IP_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IP_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IP_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_I_AXI": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IP_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IC_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_I_LMB": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_I_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_I_LMB_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LOCKSTEP_SELECT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_DISCRETE_PORTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_USER_SIGNALS": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_USER_SIGNALS": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"G_TEMPLATE_LIST": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"G_USE_EXCEPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_MSR_INSTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_PCMP_INSTR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_REORDER_INSTR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BARREL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_DIV": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_HW_MUL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_FPU": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_UNALIGNED_EXCEPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ILL_OPCODE_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_I_BUS_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_M_AXI_D_BUS_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DIV_ZERO_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FPU_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_FSL_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_USE_STACK_PROTECTION": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IMPRECISE_EXCEPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PVR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PVR_USER1": [ { "value": "0x00", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_PVR_USER2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DEBUG_ENABLED": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUMBER_OF_PC_BRK": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUMBER_OF_RD_ADDR_BRK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUMBER_OF_WR_ADDR_BRK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DEBUG_EVENT_COUNTERS": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DEBUG_LATENCY_COUNTERS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DEBUG_COUNTER_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DEBUG_TRACE_SIZE": [ { "value": "8192", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DEBUG_EXTERNAL_TRACE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DEBUG_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DEBUG_PROFILE_SIZE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_INTERRUPT_IS_EDGE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EDGE_IS_POSITIVE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ASYNC_INTERRUPT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ASYNC_WAKEUP": [ { "value": "3", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_MSR_IE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_MSR_BIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_MSR_ICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_MSR_DCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_MSR_EE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_MSR_EIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OPCODE_0x0_ILLEGAL": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_FSL_LINKS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_EXTENDED_FSL_INSTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_M0_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S0_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M1_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S1_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M2_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S2_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M3_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S3_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M4_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S4_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M5_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S5_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M6_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S6_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M7_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S7_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M8_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S8_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M9_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S9_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M10_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S10_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M11_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S11_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M12_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S12_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M13_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S13_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M14_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S14_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M15_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_S15_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_M0_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S0_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M1_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S1_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M2_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M3_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S3_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M4_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S4_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M5_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S5_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M6_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S6_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M7_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S7_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M8_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S8_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M9_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S9_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M10_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S10_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M11_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S11_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M12_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S12_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M13_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S13_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M14_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S14_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M15_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S15_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ICACHE_BASEADDR": [ { "value": "0x0000000000000000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ICACHE_HIGHADDR": [ { "value": "0x000000003fffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_USE_ICACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ALLOW_ICACHE_WR": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ADDR_TAG_BITS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CACHE_BYTE_SIZE": [ { "value": "8192", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ICACHE_LINE_LEN": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ICACHE_ALWAYS_USED": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ICACHE_VICTIMS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ICACHE_STREAMS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ICACHE_FORCE_TAG_LUTRAM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_ICACHE_DATA_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_AWUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_ARUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_WUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_RUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_BUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_IC_USER_VALUE": [ { "value": "31", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DCACHE_BASEADDR": [ { "value": "0x0000000000000000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_HIGHADDR": [ { "value": "0x000000003fffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_USE_DCACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ALLOW_DCACHE_WR": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_ADDR_TAG": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DCACHE_BYTE_SIZE": [ { "value": "8192", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_LINE_LEN": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_ALWAYS_USED": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_USE_WRITEBACK": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_VICTIMS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_FORCE_TAG_LUTRAM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_DCACHE_DATA_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_AWUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_ARUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_WUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_RUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_BUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_EXCLUSIVE_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_DC_USER_VALUE": [ { "value": "31", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_MMU": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MMU_DTLB_SIZE": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MMU_ITLB_SIZE": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MMU_TLB_ACCESS": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MMU_ZONES": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_MMU_PRIVILEGED_INSTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_USE_INTERRUPT": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERRUPT_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_EXT_BRK": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_EXT_NM_BRK": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_NON_SECURE": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_BRANCH_TARGET_CACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BRANCH_TARGET_CACHE_SIZE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_microblaze_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_SCO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FREQ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_CLK": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_CLK_IRQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_CLK_DEBUG": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_DBG_CLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF_DBG_TRACE_CLK": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FAULT_TOLERANT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ECC_USE_CE_EXCEPTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LOCKSTEP_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LOCKSTEP_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_TEMPORAL_DEPTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENDIANNESS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_LMB_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INSTR_SIZE": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IADDR_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PIADDR_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DADDR_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INSTANCE": [ { "value": "design_1_microblaze_0_0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AREA_OPTIMIZED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERCONNECT": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BASE_VECTORS": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"Clk": [ { "direction": "in" } ],
|
||||||
|
"Reset": [ { "direction": "in" } ],
|
||||||
|
"Interrupt": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Interrupt_Address": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
|
||||||
|
"Interrupt_Ack": [ { "direction": "out", "size_left": "0", "size_right": "1" } ],
|
||||||
|
"Instr_Addr": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"Instr": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
|
||||||
|
"IFetch": [ { "direction": "out" } ],
|
||||||
|
"I_AS": [ { "direction": "out" } ],
|
||||||
|
"IReady": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"IWAIT": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"ICE": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"IUE": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Data_Addr": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"Data_Read": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
|
||||||
|
"Data_Write": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
|
||||||
|
"D_AS": [ { "direction": "out" } ],
|
||||||
|
"Read_Strobe": [ { "direction": "out" } ],
|
||||||
|
"Write_Strobe": [ { "direction": "out" } ],
|
||||||
|
"DReady": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"DWait": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"DCE": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"DUE": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Byte_Enable": [ { "direction": "out", "size_left": "0", "size_right": "3" } ],
|
||||||
|
"M_AXI_DP_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"M_AXI_DP_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"M_AXI_DP_AWVALID": [ { "direction": "out" } ],
|
||||||
|
"M_AXI_DP_AWREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"M_AXI_DP_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"M_AXI_DP_WVALID": [ { "direction": "out" } ],
|
||||||
|
"M_AXI_DP_WREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_BVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_BREADY": [ { "direction": "out" } ],
|
||||||
|
"M_AXI_DP_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"M_AXI_DP_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"M_AXI_DP_ARVALID": [ { "direction": "out" } ],
|
||||||
|
"M_AXI_DP_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"M_AXI_DP_RREADY": [ { "direction": "out" } ],
|
||||||
|
"Dbg_Clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Dbg_TDI": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Dbg_TDO": [ { "direction": "out" } ],
|
||||||
|
"Dbg_Reg_En": [ { "direction": "in", "size_left": "0", "size_right": "7", "driver_value": "0" } ],
|
||||||
|
"Dbg_Shift": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Dbg_Capture": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Dbg_Update": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Debug_Rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"Dbg_Disable": [ { "direction": "in", "driver_value": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"CLK.CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "Reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "Clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST.RESET": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "Reset" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"INTERRUPT": {
|
||||||
|
"vlnv": "xilinx.com:interface:mbinterrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:mbinterrupt_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"LOW_LATENCY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ACK": [ { "physical_name": "Interrupt_Ack" } ],
|
||||||
|
"ADDRESS": [ { "physical_name": "Interrupt_Address" } ],
|
||||||
|
"INTERRUPT": [ { "physical_name": "Interrupt" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"DLMB": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"address_space_ref": "Data",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "dependent", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "Data_Addr" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "D_AS" } ],
|
||||||
|
"BE": [ { "physical_name": "Byte_Enable" } ],
|
||||||
|
"CE": [ { "physical_name": "DCE" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "Data_Read" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "Read_Strobe" } ],
|
||||||
|
"READY": [ { "physical_name": "DReady" } ],
|
||||||
|
"UE": [ { "physical_name": "DUE" } ],
|
||||||
|
"WAIT": [ { "physical_name": "DWait" } ],
|
||||||
|
"WRITEDBUS": [ { "physical_name": "Data_Write" } ],
|
||||||
|
"WRITESTROBE": [ { "physical_name": "Write_Strobe" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"ILMB": {
|
||||||
|
"vlnv": "xilinx.com:interface:lmb:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"address_space_ref": "Instruction",
|
||||||
|
"parameters": {
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||||
|
"PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "dependent", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ABUS": [ { "physical_name": "Instr_Addr" } ],
|
||||||
|
"ADDRSTROBE": [ { "physical_name": "I_AS" } ],
|
||||||
|
"CE": [ { "physical_name": "ICE" } ],
|
||||||
|
"READDBUS": [ { "physical_name": "Instr" } ],
|
||||||
|
"READSTROBE": [ { "physical_name": "IFetch" } ],
|
||||||
|
"READY": [ { "physical_name": "IReady" } ],
|
||||||
|
"UE": [ { "physical_name": "IUE" } ],
|
||||||
|
"WAIT": [ { "physical_name": "IWAIT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_DP": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"address_space_ref": "Data",
|
||||||
|
"parameters": {
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ARADDR": [ { "physical_name": "M_AXI_DP_ARADDR" } ],
|
||||||
|
"ARPROT": [ { "physical_name": "M_AXI_DP_ARPROT" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "M_AXI_DP_ARREADY" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "M_AXI_DP_ARVALID" } ],
|
||||||
|
"AWADDR": [ { "physical_name": "M_AXI_DP_AWADDR" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "M_AXI_DP_AWPROT" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "M_AXI_DP_AWREADY" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "M_AXI_DP_AWVALID" } ],
|
||||||
|
"BREADY": [ { "physical_name": "M_AXI_DP_BREADY" } ],
|
||||||
|
"BRESP": [ { "physical_name": "M_AXI_DP_BRESP" } ],
|
||||||
|
"BVALID": [ { "physical_name": "M_AXI_DP_BVALID" } ],
|
||||||
|
"RDATA": [ { "physical_name": "M_AXI_DP_RDATA" } ],
|
||||||
|
"RREADY": [ { "physical_name": "M_AXI_DP_RREADY" } ],
|
||||||
|
"RRESP": [ { "physical_name": "M_AXI_DP_RRESP" } ],
|
||||||
|
"RVALID": [ { "physical_name": "M_AXI_DP_RVALID" } ],
|
||||||
|
"WDATA": [ { "physical_name": "M_AXI_DP_WDATA" } ],
|
||||||
|
"WREADY": [ { "physical_name": "M_AXI_DP_WREADY" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "M_AXI_DP_WSTRB" } ],
|
||||||
|
"WVALID": [ { "physical_name": "M_AXI_DP_WVALID" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"DEBUG": {
|
||||||
|
"vlnv": "xilinx.com:interface:mbdebug:3.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:mbdebug_rtl:3.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"port_maps": {
|
||||||
|
"CAPTURE": [ { "physical_name": "Dbg_Capture" } ],
|
||||||
|
"CLK": [ { "physical_name": "Dbg_Clk" } ],
|
||||||
|
"DISABLE": [ { "physical_name": "Dbg_Disable" } ],
|
||||||
|
"REG_EN": [ { "physical_name": "Dbg_Reg_En" } ],
|
||||||
|
"RST": [ { "physical_name": "Debug_Rst" } ],
|
||||||
|
"SHIFT": [ { "physical_name": "Dbg_Shift" } ],
|
||||||
|
"TDI": [ { "physical_name": "Dbg_TDI" } ],
|
||||||
|
"TDO": [ { "physical_name": "Dbg_TDO" } ],
|
||||||
|
"UPDATE": [ { "physical_name": "Dbg_Update" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"address_spaces": {
|
||||||
|
"Data": {
|
||||||
|
"range": "4294967296",
|
||||||
|
"width": "32"
|
||||||
|
},
|
||||||
|
"Instruction": {
|
||||||
|
"range": "4294967296",
|
||||||
|
"width": "32"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"S_AXI_DEBUG": {
|
||||||
|
"description": "AXI debug memory map",
|
||||||
|
"address_blocks": {
|
||||||
|
"Reg": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
|
||||||
|
"display_name": "Reg",
|
||||||
|
"description": "Debug Register Block",
|
||||||
|
"usage": "register",
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"contents": {
|
||||||
|
"cpus": {
|
||||||
|
"microblaze": {
|
||||||
|
"address_space_refs": "Data",
|
||||||
|
"parameters": {
|
||||||
|
"endian": [ { "value": "little" } ],
|
||||||
|
"elf_class": [ { "value": "32-bit" } ],
|
||||||
|
"instance_path": [ { "value": "" } ],
|
||||||
|
"bootloop_file": [ { "value": "data/mb_bootloop_le.elf" } ],
|
||||||
|
"processor_type": [ { "value": "MICROBLAZE_LE" } ],
|
||||||
|
"is_visible": [ { "value": "true" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,525 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_microblaze_0_axi_intc_0",
|
||||||
|
"cell_name": "microblaze_0_axi_intc",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_intc:4.1",
|
||||||
|
"ip_revision": "17",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_HAS_IPR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_SIE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_CIE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_IVR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_ILR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IRQ_ACTIVE": [ { "value": "0x1", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_KIND_OF_INTR": [ { "value": "0xFFFFFFF9", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_NUM_INTR_INPUTS": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SW_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_KIND_OF_LVL": [ { "value": "0xFFFFFFFF", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_ASYNC_INTR": [ { "value": "0xFFFFFFF8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IRQ_IS_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_KIND_OF_EDGE": [ { "value": "0xFFFFFFFF", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_HAS_FAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IVAR_RESET_VALUE": [ { "value": "0x0000000000000010", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_ENABLE_ASYNC": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_microblaze_0_axi_intc_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Sense_of_IRQ_Level_Type": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Sense_of_IRQ_Edge_Type": [ { "value": "Rising", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_EN_CASCADE_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CASCADE_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MB_CLK_NOT_CONNECTED": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DISABLE_SYNCHRONIZERS": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ACLK_FREQ_MHZ": [ { "value": "100.0", "value_src": "propagated", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PROCESSOR_CLK_FREQ_MHZ": [ { "value": "100.0", "value_src": "propagated", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"C_IRQ_CONNECTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INSTANCE": [ { "value": "design_1_microblaze_0_axi_intc_0", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ADDR_WIDTH": [ { "value": "9", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_INTR_INPUTS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_SW_INTR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_KIND_OF_INTR": [ { "value": "0xfffffff9", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_KIND_OF_EDGE": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_KIND_OF_LVL": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_ASYNC_INTR": [ { "value": "0xFFFFFFF8", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_NUM_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IVAR_RESET_VALUE": [ { "value": "0x0000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_ENABLE_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_IPR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_SIE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_CIE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_IVR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_ILR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IRQ_IS_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IRQ_ACTIVE": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_DISABLE_SYNCHRONIZERS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MB_CLK_NOT_CONNECTED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_FAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_EN_CASCADE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CASCADE_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "17" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"s_axi_aclk": [ { "direction": "in" } ],
|
||||||
|
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in" } ],
|
||||||
|
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0" } ],
|
||||||
|
"s_axi_arvalid": [ { "direction": "in" } ],
|
||||||
|
"s_axi_arready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_rready": [ { "direction": "in" } ],
|
||||||
|
"intr": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"processor_clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"processor_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"irq": [ { "direction": "out" } ],
|
||||||
|
"processor_ack": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"interrupt_address": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"s_axi": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"memory_map_ref": "S_AXI",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "9", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||||
|
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||||
|
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||||
|
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||||
|
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||||
|
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"s_axi_aclk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"s_resetn": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"proc_clock": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "interrupt", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "processor_rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "processor_clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"proc_reset": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "processor_rst" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"interrupt": {
|
||||||
|
"vlnv": "xilinx.com:interface:mbinterrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:mbinterrupt_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LOW_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"ACK": [ { "physical_name": "processor_ack" } ],
|
||||||
|
"ADDRESS": [ { "physical_name": "interrupt_address" } ],
|
||||||
|
"INTERRUPT": [ { "physical_name": "irq" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"interrupt_input": {
|
||||||
|
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"SENSITIVITY": [ { "value": "LEVEL_HIGH:LEVEL_HIGH:EDGE_RISING", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PortWidth": [ { "value": "3", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"INTERRUPT": [ { "physical_name": "intr" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"memory_maps": {
|
||||||
|
"S_AXI": {
|
||||||
|
"display_name": "S_AXI_MEM",
|
||||||
|
"description": "Memory Map for S_AXI",
|
||||||
|
"address_blocks": {
|
||||||
|
"Reg": {
|
||||||
|
"base_address": "0",
|
||||||
|
"range": "4096",
|
||||||
|
"display_name": "Reg",
|
||||||
|
"description": "Register Block",
|
||||||
|
"usage": "register",
|
||||||
|
"access": "read-write",
|
||||||
|
"registers": {
|
||||||
|
"ISR": {
|
||||||
|
"address_offset": "0x0",
|
||||||
|
"size": 3,
|
||||||
|
"display_name": "Interrupt Status Register",
|
||||||
|
"description": "Interrupt Status Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"INT": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 3,
|
||||||
|
"display_name": "Active Interrupt Signal",
|
||||||
|
"description": "Interrupt Status Register.\nFor each bit up to number of periperhal interrupts:\n R - Reads active interrupt signal.\n W - No effect after MER HIE bit has been set, otherwise writes active interrupt signal.\nFor remaining bits defined by number of software interrupts:\n R - Reads software interrupt value.\n W - Writes software interrupt value.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IPR": {
|
||||||
|
"address_offset": "0x4",
|
||||||
|
"size": 3,
|
||||||
|
"display_name": "Interrupt Pending Register",
|
||||||
|
"description": "Interrupt Pending Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"INT": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 3,
|
||||||
|
"display_name": "Pending Interrupt Signal",
|
||||||
|
"description": "Interrupt Pending Register.\nFor each bit:\n R - Reads logical AND of bits in ISR and IER.\n W - No effect.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IER": {
|
||||||
|
"address_offset": "0x8",
|
||||||
|
"size": 3,
|
||||||
|
"display_name": "Interrupt Enable Register",
|
||||||
|
"description": "Interrupt Enable Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"INT": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 3,
|
||||||
|
"display_name": "Interrupt Enable",
|
||||||
|
"description": "Interrupt Enable Register.\nFor each bit:\n R - Reads interrupt enable value.\n W - Writes interrupt enable value.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IAR": {
|
||||||
|
"address_offset": "0xC",
|
||||||
|
"size": 3,
|
||||||
|
"display_name": "Interrupt Acknowledge Register",
|
||||||
|
"description": "Interrupt Acknowledge Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"INT": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 3,
|
||||||
|
"display_name": "Interrupt Acknowledge",
|
||||||
|
"description": "Interrupt Acknowledge Register.\nFor each bit:\n W - Acknowledge interrupt.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "write-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"SIE": {
|
||||||
|
"address_offset": "0x10",
|
||||||
|
"size": 3,
|
||||||
|
"display_name": "Set Interrupt Enables",
|
||||||
|
"description": "Set Interrupt Enables",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"INT": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 3,
|
||||||
|
"display_name": "Set Interrupt Enable",
|
||||||
|
"description": "Set Interrupt Enables\nFor each bit:\n R - Reads active interrupt.\n W - Writing 1 enables the interrupt, writing 0 has no effect.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CIE": {
|
||||||
|
"address_offset": "0x14",
|
||||||
|
"size": 3,
|
||||||
|
"display_name": "Clear Interrupt Enables",
|
||||||
|
"description": "Clear Interrupt Enables",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"INT": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 3,
|
||||||
|
"display_name": "Clear Interrupt Enable",
|
||||||
|
"description": "Clear Interrupt Enables\nFor each bit:\n R - Reads active interrupt.\n W - Writing 1 disables the interrupt, writing 0 has no effect.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IVR": {
|
||||||
|
"address_offset": "0x18",
|
||||||
|
"size": 5,
|
||||||
|
"display_name": "Interrupt Vector Register",
|
||||||
|
"description": "Interrupt Vector Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"IVN": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 5,
|
||||||
|
"display_name": "Interrupt Vector Number",
|
||||||
|
"description": "Interrupt Vector Number.\n R - Reads ordinal of highest priority, enabled, active interrupt.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-only"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"MER": {
|
||||||
|
"address_offset": "0x1C",
|
||||||
|
"size": 2,
|
||||||
|
"display_name": "Master Enable Register",
|
||||||
|
"description": "Master Enable Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"ME": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Master IRQ Enable",
|
||||||
|
"description": "Master IRQ Enable.\n 0 - All interrupts disabled.\n 1 - All interrupts can be enabled.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
},
|
||||||
|
"HIE": {
|
||||||
|
"bit_offset": 1,
|
||||||
|
"bit_width": 1,
|
||||||
|
"display_name": "Hardware Interrupt Enable",
|
||||||
|
"description": "Hardware Interrupt Enable.\n 0 - HW interrupts disabled.\n 1 - HW interrupts enabled.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IMR": {
|
||||||
|
"address_offset": "0x20",
|
||||||
|
"size": 3,
|
||||||
|
"display_name": "Interrupt Mode Register",
|
||||||
|
"description": "Interrupt Mode Register",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x0",
|
||||||
|
"fields": {
|
||||||
|
"INT": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 3,
|
||||||
|
"display_name": "Interrupt Mode",
|
||||||
|
"description": "Interrupt Mode Register.\nFor each bit:\n R - Reads interrupt mode.\n W - Sets interrupt mode, where 0 is normal mode and 1 is fast mode.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IVAR[0]": {
|
||||||
|
"address_offset": "0x100",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Interrupt Vector Address Register 0",
|
||||||
|
"description": "Interrupt Vector Address Register 0",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x000000010",
|
||||||
|
"fields": {
|
||||||
|
"IVA": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 32,
|
||||||
|
"display_name": "Interrupt Vector Address",
|
||||||
|
"description": "Interrupt vector address of active interrupt 0 with highest priority.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IVAR[1]": {
|
||||||
|
"address_offset": "0x104",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Interrupt Vector Address Register 1",
|
||||||
|
"description": "Interrupt Vector Address Register 1",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x000000010",
|
||||||
|
"fields": {
|
||||||
|
"IVA": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 32,
|
||||||
|
"display_name": "Interrupt Vector Address",
|
||||||
|
"description": "Interrupt vector address of active interrupt 1 with highest priority.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IVAR[2]": {
|
||||||
|
"address_offset": "0x108",
|
||||||
|
"size": 32,
|
||||||
|
"display_name": "Interrupt Vector Address Register 2",
|
||||||
|
"description": "Interrupt Vector Address Register 2",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write",
|
||||||
|
"reset_value": "0x000000010",
|
||||||
|
"fields": {
|
||||||
|
"IVA": {
|
||||||
|
"bit_offset": 0,
|
||||||
|
"bit_width": 32,
|
||||||
|
"display_name": "Interrupt Vector Address",
|
||||||
|
"description": "Interrupt vector address of active interrupt 2 with highest priority.\n",
|
||||||
|
"is_volatile": true,
|
||||||
|
"access": "read-write"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,354 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_microblaze_0_axi_periph_0",
|
||||||
|
"cell_name": "microblaze_0_axi_periph",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
|
||||||
|
"ip_revision": "28",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_periph_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"NUM_MI": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SYNCHRONIZATION_STAGES": [ { "value": "3", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M16_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M17_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M18_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M19_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M20_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M21_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M22_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M23_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M24_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M25_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M26_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M27_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M28_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M29_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M30_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M31_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M32_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M33_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M34_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M35_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M36_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M37_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M38_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M39_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M40_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M41_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M42_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M43_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M44_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M45_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M46_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M47_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M48_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M49_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M50_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M51_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M52_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M53_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M54_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M55_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M56_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M57_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M58_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M59_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M60_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M61_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M62_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M63_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M16_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M17_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M18_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M19_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M20_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M21_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M22_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M23_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M24_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M25_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M26_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"M27_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
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"M24_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Component_Name": [ { "value": "design_1_microblaze_0_axi_periph_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
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"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
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||||||
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},
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||||||
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"runtime_parameters": {
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||||||
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"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
|
||||||
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"MANAGED": [ { "value": "TRUE" } ],
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|
||||||
|
}
|
||||||
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}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,310 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
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"ip_inst": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"ip_revision": "4",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_microblaze_0_xlconcat_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aux_reset": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"dbg_reset": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"mb_rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "mb_reset" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"bus_struct_reset": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"interconnect_low_rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"peripheral_high_rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"peripheral_low_rst": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,268 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_s00_data_fifo_0",
|
||||||
|
"cell_name": "axi_interconnect_1/s00_couplers/s00_data_fifo",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_data_fifo:2.1",
|
||||||
|
"ip_revision": "26",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s00_data_fifo_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WRITE_FIFO_DEPTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"READ_FIFO_DEPTH": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WRITE_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"READ_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_s00_data_fifo_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_DEPTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "26" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s00_data_fifo_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"aclk": [ { "direction": "in" } ],
|
||||||
|
"aresetn": [ { "direction": "in" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
|
||||||
|
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||||
|
"m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_wlast": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bready": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "s_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "m_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "m_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "m_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "m_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "m_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_bready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,268 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_s01_data_fifo_0",
|
||||||
|
"cell_name": "axi_interconnect_1/s01_couplers/s01_data_fifo",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_data_fifo:2.1",
|
||||||
|
"ip_revision": "26",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s01_data_fifo_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WRITE_FIFO_DEPTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"READ_FIFO_DEPTH": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"WRITE_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"READ_FIFO_DELAY": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_s01_data_fifo_0", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_WRITE_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_DEPTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_TYPE": [ { "value": "lut", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "26" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s01_data_fifo_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"aclk": [ { "direction": "in" } ],
|
||||||
|
"aresetn": [ { "direction": "in" } ],
|
||||||
|
"s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
|
||||||
|
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||||
|
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_awready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||||
|
"s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ],
|
||||||
|
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axi_wready": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||||
|
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_awlock": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axi_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_awregion": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||||
|
"m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_wlast": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"m_axi_bready": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "s_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "s_axi_bready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "m_axi_awlen" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "m_axi_awsize" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "m_axi_awburst" } ],
|
||||||
|
"AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||||
|
"AWREGION": [ { "physical_name": "m_axi_awregion" } ],
|
||||||
|
"AWQOS": [ { "physical_name": "m_axi_awqos" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||||
|
"WLAST": [ { "physical_name": "m_axi_wlast" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_bready" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"CLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"RST": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,119 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_util_ds_buf_0_0",
|
||||||
|
"cell_name": "util_ds_buf_0",
|
||||||
|
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
|
||||||
|
"ip_revision": "29",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BUF_TYPE": [ { "value": "IBUFDSGTE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "design_1_util_ds_buf_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||||
|
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_BUF_TYPE": [ { "value": "ibufdsgte4", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "29" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"IBUF_DS_ODIV2": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"CLK_IN_D": {
|
||||||
|
"vlnv": "xilinx.com:interface:diff_clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||||
|
"CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
|
||||||
|
"CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IBUF_OUT": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_util_ds_buf_0_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "IBUF_OUT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"IBUF_DS_ODIV2": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "design_1_util_ds_buf_0_0_IBUF_DS_ODIV2", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "IBUF_DS_ODIV2" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,51 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "design_1_xlconstant_0_0",
|
||||||
|
"cell_name": "xlconstant_0",
|
||||||
|
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||||
|
"ip_revision": "7",
|
||||||
|
"gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "design_1_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CONST_VAL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"CONST_VAL": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||||
|
"IPREVISION": [ { "value": "7" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xlconstant_0_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
193219
project_1.srcs/sources_1/bd/design_1/ipshared/25a8/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
Executable file
193219
project_1.srcs/sources_1/bd/design_1/ipshared/25a8/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
Executable file
File diff suppressed because it is too large
Load Diff
1956
project_1.srcs/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v
Executable file
1956
project_1.srcs/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v
Executable file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,88 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_bit_synchronizer # (
|
||||||
|
|
||||||
|
parameter INITIALIZE = 5'b00000,
|
||||||
|
parameter FREQUENCY = 512
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
input wire clk_in,
|
||||||
|
input wire i_in,
|
||||||
|
output wire o_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
|
||||||
|
// enable clustering. Their GSR default values are provided by the INITIALIZE parameter.
|
||||||
|
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0];
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1];
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2];
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3];
|
||||||
|
reg i_in_out = INITIALIZE[4];
|
||||||
|
|
||||||
|
always @(posedge clk_in) begin
|
||||||
|
i_in_meta <= i_in;
|
||||||
|
i_in_sync1 <= i_in_meta;
|
||||||
|
i_in_sync2 <= i_in_sync1;
|
||||||
|
i_in_sync3 <= i_in_sync2;
|
||||||
|
i_in_out <= i_in_sync3;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign o_out = i_in_out;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,608 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gte4_drp_arb
|
||||||
|
|
||||||
|
#(
|
||||||
|
parameter [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C,
|
||||||
|
parameter [9:0] ADDR_TX_PROGDIV_CFG = 10'h03E, //GTY /GTH addresses are different (003E in GTH; 0057 in GTY)
|
||||||
|
parameter [9:0] ADDR_RX_PROGDIV_CFG = 10'h0C6,
|
||||||
|
parameter [9:0] ADDR_X0E1 = 10'h0E1,
|
||||||
|
parameter [9:0] ADDR_X079 = 10'h079,
|
||||||
|
parameter [9:0] ADDR_X114 = 10'h114,
|
||||||
|
parameter C_NUM_CLIENTS = 2,
|
||||||
|
parameter C_ADDR_WIDTH = 9,
|
||||||
|
parameter C_DATA_WIDTH = 16
|
||||||
|
)
|
||||||
|
(
|
||||||
|
|
||||||
|
input wire DCLK_I,
|
||||||
|
|
||||||
|
input wire RESET_I,
|
||||||
|
|
||||||
|
input wire TX_CAL_DONE_I,
|
||||||
|
input wire RX_CAL_DONE_I,
|
||||||
|
|
||||||
|
input wire [C_NUM_CLIENTS-1:0] DEN_USR_I,
|
||||||
|
|
||||||
|
input wire [C_NUM_CLIENTS-1:0] DWE_USR_I,
|
||||||
|
|
||||||
|
input wire [(C_ADDR_WIDTH*C_NUM_CLIENTS)-1:0] DADDR_USR_I,
|
||||||
|
|
||||||
|
input wire [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0] DI_USR_I,
|
||||||
|
|
||||||
|
output reg [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0] DO_USR_O = 'h0,
|
||||||
|
|
||||||
|
output reg [C_NUM_CLIENTS-1:0] DRDY_USR_O = 'h0,
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
output reg DEN_O = 1'b0,
|
||||||
|
|
||||||
|
output reg DWE_O = 1'b0,
|
||||||
|
|
||||||
|
output reg [C_ADDR_WIDTH-1:0] DADDR_O = 1'b0,
|
||||||
|
|
||||||
|
output reg [C_DATA_WIDTH-1:0] DI_O = 'h0,
|
||||||
|
|
||||||
|
input wire [C_DATA_WIDTH-1:0] DO_I,
|
||||||
|
|
||||||
|
input wire DRDY_I
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
// log base 2
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
function integer clogb2;
|
||||||
|
|
||||||
|
input integer depth;
|
||||||
|
|
||||||
|
integer d;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
if (depth == 0)
|
||||||
|
|
||||||
|
clogb2 = 1;
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
d = depth;
|
||||||
|
|
||||||
|
for (clogb2=0; d > 0; clogb2 = clogb2+1)
|
||||||
|
|
||||||
|
d = d >> 1;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
reg [clogb2(C_NUM_CLIENTS)-1:0] idx = 'b0;
|
||||||
|
|
||||||
|
reg done = 1'b0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
reg rd = 1'b0;
|
||||||
|
|
||||||
|
reg wr = 1'b0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
reg [C_NUM_CLIENTS-1:0] en = 'h0;
|
||||||
|
|
||||||
|
reg [C_NUM_CLIENTS-1:0] we = 'h0;
|
||||||
|
|
||||||
|
reg [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0] data_i = 'h0;
|
||||||
|
|
||||||
|
reg [(C_ADDR_WIDTH*C_NUM_CLIENTS)-1:0] addr_i = 'h0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
reg [C_DATA_WIDTH-1:0] di = 'h0;
|
||||||
|
|
||||||
|
reg [C_ADDR_WIDTH-1:0] daddr = 'h0;
|
||||||
|
|
||||||
|
reg [C_DATA_WIDTH-1:0] do_r = 'h0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
// Arbitration state machine encodings
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
localparam [3:0] ARB_START = 4'd1;
|
||||||
|
|
||||||
|
localparam [3:0] ARB_WAIT = 4'd2;
|
||||||
|
|
||||||
|
localparam [3:0] ARB_REPORT = 4'd4;
|
||||||
|
|
||||||
|
localparam [3:0] ARB_INC = 4'd8;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
reg [3:0] arb_state = ARB_START;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
// DRP state machine encodings
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
localparam [6:0] DRP_WAIT = 7'd1;
|
||||||
|
|
||||||
|
localparam [6:0] DRP_READ = 7'd2;
|
||||||
|
|
||||||
|
localparam [6:0] DRP_READ_ACK = 7'd4;
|
||||||
|
|
||||||
|
localparam [6:0] DRP_MODIFY = 7'd8;
|
||||||
|
|
||||||
|
localparam [6:0] DRP_WRITE = 7'd16;
|
||||||
|
|
||||||
|
localparam [6:0] DRP_WRITE_ACK = 7'd32;
|
||||||
|
|
||||||
|
localparam [6:0] DRP_DONE = 7'd64;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
reg [6:0] drp_state = DRP_WAIT;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
reg [7:0] timeout_cntr = 0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
integer i;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
// Register incoming transactions: grab data, address, write enable when DEN is high
|
||||||
|
|
||||||
|
// Clear internal enable when transaction is (eventually) finished
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
always @(posedge DCLK_I)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
if (RESET_I)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
en <= 'b0;
|
||||||
|
|
||||||
|
we <= 'b0;
|
||||||
|
|
||||||
|
data_i <= 'b0;
|
||||||
|
|
||||||
|
addr_i <= 'b0;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
if (DEN_USR_I[0]) begin
|
||||||
|
|
||||||
|
en[0] <= 1'b1; // this means this client wants to do a transaction
|
||||||
|
|
||||||
|
we[0] <= DWE_USR_I[0];
|
||||||
|
|
||||||
|
//data_i[(i*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(i*C_DATA_WIDTH) +: C_DATA_WIDTH];
|
||||||
|
//addr_i[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
|
||||||
|
|
||||||
|
// if cpll cal not done (mask) from cpll cal, if user tries to write, always save progdiv to temp holding place.
|
||||||
|
if (!TX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_TX_PROGDIV_CFG && DWE_USR_I[0]) begin
|
||||||
|
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X079;
|
||||||
|
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
|
||||||
|
end
|
||||||
|
else if (!TX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_TX_PROGCLK_SEL && DWE_USR_I[0]) begin
|
||||||
|
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X0E1;
|
||||||
|
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
|
||||||
|
end
|
||||||
|
else if (!RX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_RX_PROGDIV_CFG && DWE_USR_I[0]) begin
|
||||||
|
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X114;
|
||||||
|
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
//behave normal
|
||||||
|
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
|
||||||
|
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH];
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
for (i = 1; i < C_NUM_CLIENTS; i= i+1)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
if (DEN_USR_I[i])
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
en[i] <= 1'b1; // this means this client wants to do a transaction
|
||||||
|
|
||||||
|
we[i] <= DWE_USR_I[i];
|
||||||
|
|
||||||
|
data_i[(i*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(i*C_DATA_WIDTH) +: C_DATA_WIDTH];
|
||||||
|
|
||||||
|
addr_i[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
if (done)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
en[idx] <= 1'b0;
|
||||||
|
|
||||||
|
we[idx] <= 1'b0;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
// Arbitration FSM - does a round-robin arbritration scheme
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
always @(posedge DCLK_I)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
if (RESET_I)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
idx <= 'b0;
|
||||||
|
|
||||||
|
di <= 'b0;
|
||||||
|
|
||||||
|
daddr <= 'b0;
|
||||||
|
|
||||||
|
rd <= 1'b0;
|
||||||
|
|
||||||
|
wr <= 1'b0;
|
||||||
|
|
||||||
|
arb_state <= ARB_START;
|
||||||
|
|
||||||
|
DRDY_USR_O <= 'b0;
|
||||||
|
|
||||||
|
DO_USR_O <= 'b0;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
case (arb_state)
|
||||||
|
|
||||||
|
ARB_START: begin
|
||||||
|
|
||||||
|
if (en[idx] == 1'b1)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
di <= data_i[idx*C_DATA_WIDTH +: C_DATA_WIDTH];
|
||||||
|
|
||||||
|
daddr <= addr_i[idx*C_ADDR_WIDTH +: C_ADDR_WIDTH];
|
||||||
|
|
||||||
|
rd <= !we[idx];
|
||||||
|
|
||||||
|
wr <= we[idx];
|
||||||
|
|
||||||
|
arb_state <= ARB_WAIT;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
rd <= 1'b0;
|
||||||
|
|
||||||
|
wr <= 1'b0;
|
||||||
|
|
||||||
|
arb_state <= ARB_INC;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
ARB_WAIT: begin
|
||||||
|
|
||||||
|
rd <= 1'b0;
|
||||||
|
|
||||||
|
wr <= 1'b0;
|
||||||
|
|
||||||
|
if (done == 1'b1)
|
||||||
|
|
||||||
|
arb_state <= ARB_REPORT;
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
arb_state <= ARB_WAIT;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
ARB_REPORT: begin
|
||||||
|
|
||||||
|
DRDY_USR_O[idx] <= 1'b1;
|
||||||
|
|
||||||
|
DO_USR_O[idx*C_DATA_WIDTH +: C_DATA_WIDTH] <= do_r;
|
||||||
|
|
||||||
|
arb_state <= ARB_INC;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
ARB_INC : begin
|
||||||
|
|
||||||
|
DRDY_USR_O[idx] <= 1'b0;
|
||||||
|
|
||||||
|
if (idx == C_NUM_CLIENTS-1)
|
||||||
|
|
||||||
|
idx <= 1'b0;
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
idx <= idx + 1;
|
||||||
|
|
||||||
|
arb_state <= ARB_START;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
default: arb_state <= ARB_START;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endcase
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
// DRP FSM - does the actual DRP read or write
|
||||||
|
|
||||||
|
//
|
||||||
|
|
||||||
|
always @(posedge DCLK_I)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
if (RESET_I)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
DEN_O <= 1'b0;
|
||||||
|
|
||||||
|
DWE_O <= 1'b0;
|
||||||
|
|
||||||
|
DI_O <= 16'h0000;
|
||||||
|
|
||||||
|
DADDR_O <= 'b0;
|
||||||
|
|
||||||
|
do_r <= 'b0;
|
||||||
|
|
||||||
|
drp_state <= DRP_WAIT;
|
||||||
|
|
||||||
|
done <= 1'b0;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
case (drp_state)
|
||||||
|
|
||||||
|
DRP_WAIT: begin
|
||||||
|
|
||||||
|
timeout_cntr <= 8'h0;
|
||||||
|
|
||||||
|
if (rd) drp_state <= DRP_READ;
|
||||||
|
|
||||||
|
else if (wr) drp_state <= DRP_WRITE;
|
||||||
|
|
||||||
|
else drp_state <= DRP_WAIT;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
DRP_READ: begin
|
||||||
|
|
||||||
|
DEN_O <= 1'b1;
|
||||||
|
|
||||||
|
DWE_O <= 1'b0;
|
||||||
|
|
||||||
|
DADDR_O <= daddr;
|
||||||
|
|
||||||
|
timeout_cntr <= 8'h0;
|
||||||
|
|
||||||
|
done <= 1'b0;
|
||||||
|
|
||||||
|
drp_state <= DRP_READ_ACK;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
DRP_READ_ACK: begin
|
||||||
|
|
||||||
|
DEN_O <= 1'b0;
|
||||||
|
|
||||||
|
DWE_O <= 1'b0;
|
||||||
|
|
||||||
|
timeout_cntr <= timeout_cntr + 1;
|
||||||
|
|
||||||
|
if (DRDY_I == 1'b1 || timeout_cntr == 8'hFF)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
do_r <= DO_I;
|
||||||
|
|
||||||
|
done <= 1'b1;
|
||||||
|
|
||||||
|
drp_state <= DRP_DONE;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
drp_state <= DRP_READ_ACK;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
DRP_WRITE: begin
|
||||||
|
|
||||||
|
DEN_O <= 1'b1;
|
||||||
|
|
||||||
|
DWE_O <= 1'b1;
|
||||||
|
|
||||||
|
DADDR_O <= daddr;
|
||||||
|
|
||||||
|
DI_O <= di;
|
||||||
|
|
||||||
|
timeout_cntr <= 8'h0;
|
||||||
|
|
||||||
|
done <= 1'b0;
|
||||||
|
|
||||||
|
drp_state <= DRP_WRITE_ACK;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
DRP_WRITE_ACK: begin
|
||||||
|
|
||||||
|
DEN_O <= 1'b0;
|
||||||
|
|
||||||
|
DWE_O <= 1'b0;
|
||||||
|
|
||||||
|
timeout_cntr <= timeout_cntr + 1;
|
||||||
|
|
||||||
|
if (DRDY_I == 1'b1 || timeout_cntr == 8'hFF)
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
do_r <= DO_I;
|
||||||
|
|
||||||
|
done <= 1'b1;
|
||||||
|
|
||||||
|
drp_state <= DRP_DONE;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
else
|
||||||
|
|
||||||
|
drp_state <= DRP_WRITE_ACK;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
DRP_DONE: begin
|
||||||
|
|
||||||
|
timeout_cntr <= 8'h0;
|
||||||
|
|
||||||
|
done <= 1'b0; // done was asserted in the previous state
|
||||||
|
|
||||||
|
drp_state <= DRP_WAIT;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
default: drp_state <= DRP_WAIT;
|
||||||
|
|
||||||
|
endcase
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
@@ -0,0 +1,224 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal_freq_counter # (
|
||||||
|
parameter REVISION = 1
|
||||||
|
)(
|
||||||
|
output reg [17:0] freq_cnt_o = 18'd0,
|
||||||
|
output reg done_o,
|
||||||
|
input wire rst_i,
|
||||||
|
input wire [15:0] test_term_cnt_i,
|
||||||
|
input wire ref_clk_i,
|
||||||
|
input wire test_clk_i
|
||||||
|
);
|
||||||
|
//****************************************************************************
|
||||||
|
// Local Parameters
|
||||||
|
//****************************************************************************
|
||||||
|
localparam RESET_STATE = 0;
|
||||||
|
localparam MEASURE_STATE = 1;
|
||||||
|
localparam HOLD_STATE = 2;
|
||||||
|
localparam UPDATE_STATE = 3;
|
||||||
|
localparam DONE_STATE = 4;
|
||||||
|
|
||||||
|
//****************************************************************************
|
||||||
|
// Local Signals
|
||||||
|
//****************************************************************************
|
||||||
|
reg [17:0] testclk_cnt = 18'h00000;
|
||||||
|
reg [15:0] refclk_cnt = 16'h0000;
|
||||||
|
reg [3:0] testclk_div4 = 4'h1;
|
||||||
|
wire testclk_rst;
|
||||||
|
wire testclk_en;
|
||||||
|
reg [5:0] hold_clk = 6'd0;
|
||||||
|
reg [4:0] state = 5'd1;
|
||||||
|
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
|
||||||
|
|
||||||
|
//
|
||||||
|
// need to get testclk_rst into TESTCLK_I domain
|
||||||
|
//
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
tstclk_rst_dly1 <= testclk_rst;
|
||||||
|
tstclk_rst_dly2 <= tstclk_rst_dly1;
|
||||||
|
end
|
||||||
|
|
||||||
|
//
|
||||||
|
// need to get testclk_en into TESTCLK_I domain
|
||||||
|
//
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
testclk_en_dly1 <= testclk_en;
|
||||||
|
testclk_en_dly2 <= testclk_en_dly1;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
if (tstclk_rst_dly2 == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_div4 <= 4'h1;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
wire testclk_rst_sync;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_testclk_rst_inst (
|
||||||
|
.clk_in (test_clk_i),
|
||||||
|
.rst_in (testclk_rst),
|
||||||
|
.rst_out (testclk_rst_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge test_clk_i or posedge testclk_rst_sync)
|
||||||
|
begin
|
||||||
|
if (testclk_rst_sync == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= testclk_cnt + 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
/* always @(posedge test_clk_i or posedge testclk_rst)
|
||||||
|
begin
|
||||||
|
if (testclk_rst == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= testclk_cnt + 1;
|
||||||
|
end
|
||||||
|
end */
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i or posedge rst_i)
|
||||||
|
begin
|
||||||
|
if (rst_i)
|
||||||
|
done_o <= 1'b0;
|
||||||
|
else
|
||||||
|
done_o <= state[DONE_STATE];
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i or posedge rst_i)
|
||||||
|
begin
|
||||||
|
if (rst_i) begin
|
||||||
|
state <= 0;
|
||||||
|
state[RESET_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
state <= 0;
|
||||||
|
case (1'b1) // synthesis parallel_case full_case
|
||||||
|
state[RESET_STATE]:
|
||||||
|
begin
|
||||||
|
if (hold_clk == 6'h3F)
|
||||||
|
state[MEASURE_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[RESET_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[MEASURE_STATE]:
|
||||||
|
begin
|
||||||
|
if (refclk_cnt == test_term_cnt_i)
|
||||||
|
state[HOLD_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[MEASURE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[HOLD_STATE]:
|
||||||
|
begin
|
||||||
|
if (hold_clk == 6'hF)
|
||||||
|
state[UPDATE_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[HOLD_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[UPDATE_STATE]:
|
||||||
|
begin
|
||||||
|
freq_cnt_o <= testclk_cnt;
|
||||||
|
state[DONE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[DONE_STATE]:
|
||||||
|
begin
|
||||||
|
state[DONE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign testclk_rst = state[RESET_STATE];
|
||||||
|
assign testclk_en = state[MEASURE_STATE];
|
||||||
|
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i)
|
||||||
|
begin
|
||||||
|
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
|
||||||
|
hold_clk <= hold_clk + 1;
|
||||||
|
else
|
||||||
|
hold_clk <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i)
|
||||||
|
begin
|
||||||
|
if (state[MEASURE_STATE] == 1'b1)
|
||||||
|
refclk_cnt <= refclk_cnt + 1;
|
||||||
|
else
|
||||||
|
refclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,748 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal # (
|
||||||
|
parameter REVISION = 2
|
||||||
|
)(
|
||||||
|
// control signals
|
||||||
|
input wire [17:0] TXOUTCLK_PERIOD_IN,
|
||||||
|
input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
|
||||||
|
input wire [17:0] CNT_TOL_IN,
|
||||||
|
input wire [15:0] FREQ_COUNT_WINDOW_IN,
|
||||||
|
// User Interface
|
||||||
|
input wire RESET_IN,
|
||||||
|
input wire CLK_IN,
|
||||||
|
input wire USER_TXPROGDIVRESET_IN,
|
||||||
|
output reg USER_TXPRGDIVRESETDONE_OUT,
|
||||||
|
input wire [2:0] USER_TXOUTCLKSEL_IN,
|
||||||
|
input wire USER_TXOUTCLK_BUFG_CE_IN,
|
||||||
|
input wire USER_TXOUTCLK_BUFG_CLR_IN,
|
||||||
|
output reg USER_CPLLLOCK_OUT,
|
||||||
|
input wire [8:0] USER_CHANNEL_DRPADDR_IN,
|
||||||
|
input wire [15:0] USER_CHANNEL_DRPDI_IN,
|
||||||
|
input wire USER_CHANNEL_DRPEN_IN,
|
||||||
|
input wire USER_CHANNEL_DRPWE_IN,
|
||||||
|
output reg USER_CHANNEL_DRPRDY_OUT,
|
||||||
|
output reg [15:0] USER_CHANNEL_DRPDO_OUT,
|
||||||
|
// Debug Interface
|
||||||
|
output wire CPLL_CAL_FAIL,
|
||||||
|
output wire CPLL_CAL_DONE,
|
||||||
|
output wire [15:0] DEBUG_OUT,
|
||||||
|
// GT Interface
|
||||||
|
input wire GTHE3_TXOUTCLK_IN,
|
||||||
|
input wire GTHE3_CPLLLOCK_IN,
|
||||||
|
output wire GTHE3_CPLLRESET_OUT,
|
||||||
|
output wire GTHE3_CPLLPD_OUT,
|
||||||
|
output reg GTHE3_TXPROGDIVRESET_OUT,
|
||||||
|
output reg [2:0] GTHE3_TXOUTCLKSEL_OUT,
|
||||||
|
input wire GTHE3_TXPRGDIVRESETDONE_IN,
|
||||||
|
output reg [8:0] GTHE3_CHANNEL_DRPADDR_OUT,
|
||||||
|
output reg [15:0] GTHE3_CHANNEL_DRPDI_OUT,
|
||||||
|
output reg GTHE3_CHANNEL_DRPEN_OUT,
|
||||||
|
output reg GTHE3_CHANNEL_DRPWE_OUT,
|
||||||
|
input wire GTHE3_CHANNEL_DRPRDY_IN,
|
||||||
|
input wire [15:0] GTHE3_CHANNEL_DRPDO_IN
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
//DRP FSM
|
||||||
|
localparam DRP_WAIT = 0;
|
||||||
|
localparam DRP_READ = 1;
|
||||||
|
localparam DRP_READ_ACK = 2;
|
||||||
|
localparam DRP_MODIFY = 3;
|
||||||
|
localparam DRP_WRITE = 4;
|
||||||
|
localparam DRP_WRITE_ACK = 5;
|
||||||
|
localparam DRP_DONE = 6;
|
||||||
|
|
||||||
|
//CPLL CAL FSM
|
||||||
|
localparam RESET = 0;
|
||||||
|
localparam READ_PROGCLK_SEL = 1;
|
||||||
|
localparam MODIFY_PROGCLK_SEL = 2;
|
||||||
|
localparam READ_PROGDIV = 3;
|
||||||
|
localparam MODIFY_PROGDIV = 4;
|
||||||
|
localparam MODIFY_TXOUTCLK_SEL = 5;
|
||||||
|
localparam ASSERT_CPLLRESET1 = 6;
|
||||||
|
localparam READ_FBOOST = 7;
|
||||||
|
localparam MODIFY_FBOOST = 8;
|
||||||
|
localparam ASSERT_CPLLRESET = 9;
|
||||||
|
localparam ASSERT_CPLLPD = 10;
|
||||||
|
localparam DEASSERT_CPLLPD = 11;
|
||||||
|
localparam DEASSERT_CPLLRESET = 12;
|
||||||
|
localparam RESTORE_FBOOST = 13;
|
||||||
|
localparam WAIT_GTCPLLLOCK = 14;
|
||||||
|
localparam ASSERT_PROGDIVRESET = 15;
|
||||||
|
localparam WAIT_PRGDIVRESETDONE = 16;
|
||||||
|
localparam CHECK_FREQ = 17;
|
||||||
|
localparam RESTORE_PROGDIV = 18;
|
||||||
|
localparam RESTORE_PROGCLK_SEL = 19;
|
||||||
|
localparam ASSERT_CPLLRESET2 = 20;
|
||||||
|
localparam WAIT_GTCPLLLOCK2 = 21;
|
||||||
|
localparam ASSERT_PROGDIVRESET2 = 22;
|
||||||
|
localparam WAIT_PRGDIVRESETDONE2= 23;
|
||||||
|
localparam CAL_FAIL = 24;
|
||||||
|
localparam CAL_DONE = 25;
|
||||||
|
|
||||||
|
reg [25:0] cpll_cal_state = 26'd0;
|
||||||
|
wire [4:0] cpll_cal_state_bin;
|
||||||
|
reg [6:0] drp_state = 7'd1;
|
||||||
|
wire drp_done;
|
||||||
|
reg [8:0] daddr = 9'd0;
|
||||||
|
//reg [8:0] daddr = 9'd0;
|
||||||
|
reg [15:0] di = 16'd0;
|
||||||
|
wire drdy;
|
||||||
|
wire [15:0] dout;
|
||||||
|
reg den = 1'b0;
|
||||||
|
reg dwe = 1'b0;
|
||||||
|
reg wr = 1'b0;
|
||||||
|
reg rd = 1'b0;
|
||||||
|
reg [15:0] di_msk;
|
||||||
|
reg [15:0] mask;
|
||||||
|
//reg [15:0] mask;
|
||||||
|
reg [15:0] wait_ctr;
|
||||||
|
reg [3:0] repeat_ctr;
|
||||||
|
reg [1:0] progclk_sel_store = 2'b00;
|
||||||
|
reg [15:0] progdiv_cfg_store = 16'd0;
|
||||||
|
reg fboost_store = 1'b0;
|
||||||
|
reg mask_user_in = 1'b0;
|
||||||
|
reg cpllreset_int = 1'b0;
|
||||||
|
reg cpllpd_int = 1'b0;
|
||||||
|
reg txprogdivreset_int = 1'b0;
|
||||||
|
reg [2:0] txoutclksel_int = 3'b000;
|
||||||
|
reg cal_fail_store = 1'b0;
|
||||||
|
|
||||||
|
localparam [4:0] WAIT_WIDTH_PROGDIVRESET = 5'd31;
|
||||||
|
localparam [4:0] WAIT_ASSERT_CPLLRESET = 5'd31;
|
||||||
|
localparam [4:0] WAIT_ASSERT_CPLLPD = 5'd31;
|
||||||
|
localparam [4:0] WAIT_DEASSERT_CPLLRESET = 5'd31;
|
||||||
|
localparam [15:0] WAIT_CPLLLOCK = 16'h4000;
|
||||||
|
localparam [3:0] REPEAT_RESET_LIMIT = 4'd15;
|
||||||
|
|
||||||
|
localparam [1:0] MOD_PROGCLK_SEL = 2'b10;
|
||||||
|
localparam [15:0] MOD_PROGDIV_CFG = 16'hA1A2; //divider 20
|
||||||
|
localparam [2:0] MOD_TXOUTCLK_SEL = 3'b101;
|
||||||
|
localparam MOD_FBOOST = 1'b1;
|
||||||
|
localparam [8:0] ADDR_TX_PROGCLK_SEL = 9'h00C;
|
||||||
|
localparam [8:0] ADDR_TX_PROGDIV_CFG = 9'h03E;
|
||||||
|
localparam [8:0] ADDR_FBOOST = 9'h0CB;
|
||||||
|
|
||||||
|
// Drive TXOUTCLK with BUFG_GT-buffered source clock, divider = 1
|
||||||
|
wire txoutclkmon;
|
||||||
|
BUFG_GT bufg_gt_txoutclkmon_inst (
|
||||||
|
.CE (USER_TXOUTCLK_BUFG_CE_IN),
|
||||||
|
.CEMASK (1'b1),
|
||||||
|
.CLR (USER_TXOUTCLK_BUFG_CLR_IN),
|
||||||
|
.CLRMASK (1'b1),
|
||||||
|
.DIV (3'b000),
|
||||||
|
.I (GTHE3_TXOUTCLK_IN),
|
||||||
|
.O (txoutclkmon)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire reset_in_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.rst_in (RESET_IN),
|
||||||
|
.rst_out (reset_in_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire gthe3_cplllock_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_cplllock_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (GTHE3_CPLLLOCK_IN),
|
||||||
|
.o_out (gthe3_cplllock_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire user_txprogdivreset_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (USER_TXPROGDIVRESET_IN),
|
||||||
|
.o_out (user_txprogdivreset_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire gthe3_txprgdivresetdone_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (GTHE3_TXPRGDIVRESETDONE_IN),
|
||||||
|
.o_out (gthe3_txprgdivresetdone_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [2:0] user_txoutclksel_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (USER_TXOUTCLKSEL_IN[0]),
|
||||||
|
.o_out (user_txoutclksel_sync[0])
|
||||||
|
);
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (USER_TXOUTCLKSEL_IN[1]),
|
||||||
|
.o_out (user_txoutclksel_sync[1])
|
||||||
|
);
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (USER_TXOUTCLKSEL_IN[2]),
|
||||||
|
.o_out (user_txoutclksel_sync[2])
|
||||||
|
);
|
||||||
|
|
||||||
|
assign GTHE3_CPLLRESET_OUT = cpllreset_int;
|
||||||
|
assign GTHE3_CPLLPD_OUT = cpllpd_int;
|
||||||
|
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | reset_in_sync)
|
||||||
|
USER_CPLLLOCK_OUT <= 1'b0;
|
||||||
|
else
|
||||||
|
USER_CPLLLOCK_OUT <= gthe3_cplllock_sync;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (mask_user_in)
|
||||||
|
GTHE3_TXPROGDIVRESET_OUT <= txprogdivreset_int;
|
||||||
|
else
|
||||||
|
GTHE3_TXPROGDIVRESET_OUT <= user_txprogdivreset_sync;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (mask_user_in)
|
||||||
|
GTHE3_TXOUTCLKSEL_OUT <= txoutclksel_int;
|
||||||
|
else
|
||||||
|
GTHE3_TXOUTCLKSEL_OUT <= user_txoutclksel_sync;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (mask_user_in)
|
||||||
|
USER_TXPRGDIVRESETDONE_OUT <= 1'b0;
|
||||||
|
else
|
||||||
|
USER_TXPRGDIVRESETDONE_OUT <= gthe3_txprgdivresetdone_sync;
|
||||||
|
end
|
||||||
|
|
||||||
|
// frequency counter for txoutclk
|
||||||
|
wire [17:0] txoutclk_freq_cnt;
|
||||||
|
reg freq_counter_rst = 1'b1;
|
||||||
|
wire freq_cnt_done;
|
||||||
|
gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
|
||||||
|
(
|
||||||
|
.freq_cnt_o(txoutclk_freq_cnt),
|
||||||
|
.done_o(freq_cnt_done),
|
||||||
|
.rst_i(freq_counter_rst),
|
||||||
|
.test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
|
||||||
|
.ref_clk_i(CLK_IN),
|
||||||
|
.test_clk_i(txoutclkmon)
|
||||||
|
);
|
||||||
|
|
||||||
|
//Debug signals
|
||||||
|
assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gthe3_cplllock_sync,fboost_store,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
|
||||||
|
assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
|
||||||
|
assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
|
||||||
|
|
||||||
|
//CPLL CAL FSM
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (reset_in_sync) begin
|
||||||
|
cpll_cal_state <= 0;
|
||||||
|
cpll_cal_state[RESET] <= 1'b1;
|
||||||
|
cpllreset_int <= 1'b0;
|
||||||
|
cpllpd_int <= 1'b0;
|
||||||
|
txprogdivreset_int <= 1'b0;
|
||||||
|
mask_user_in <= 1'b0;
|
||||||
|
wr <= 1'b0;
|
||||||
|
rd <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state <= 0;
|
||||||
|
case(1'b1) // synthesis parallel_case full_case
|
||||||
|
cpll_cal_state[RESET]:
|
||||||
|
begin
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
repeat_ctr <= 4'd0;
|
||||||
|
mask_user_in <= 1'b1;
|
||||||
|
di_msk <= 16'b0000_0000_0000_0000;
|
||||||
|
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[READ_PROGCLK_SEL]:
|
||||||
|
begin
|
||||||
|
rd <= 1'b1;
|
||||||
|
if (drp_done) begin
|
||||||
|
rd <= 1'b0;
|
||||||
|
progclk_sel_store <= dout[11:10];
|
||||||
|
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[MODIFY_PROGCLK_SEL]:
|
||||||
|
begin
|
||||||
|
if (!drp_done) begin
|
||||||
|
wr <= 1'b1;
|
||||||
|
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
wr <= 1'b0;
|
||||||
|
cpll_cal_state[READ_PROGDIV] <= 1'b1;
|
||||||
|
end
|
||||||
|
di_msk<= {4'd0,MOD_PROGCLK_SEL,10'd0};
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[READ_PROGDIV]:
|
||||||
|
begin
|
||||||
|
rd <= 1'b1;
|
||||||
|
if (drp_done) begin
|
||||||
|
rd <= 1'b0;
|
||||||
|
progdiv_cfg_store <= dout;
|
||||||
|
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state[READ_PROGDIV] <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[MODIFY_PROGDIV]:
|
||||||
|
begin
|
||||||
|
if (!drp_done) begin
|
||||||
|
wr <= 1'b1;
|
||||||
|
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
wr <= 1'b0;
|
||||||
|
cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
di_msk<= MOD_PROGDIV_CFG;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
|
||||||
|
begin
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET1] <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET1]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET1] <= 1'b1;
|
||||||
|
cpllreset_int <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpllreset_int <= 1'b0;
|
||||||
|
freq_counter_rst <= 1'b1;
|
||||||
|
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
repeat_ctr <= 4'd0;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[READ_FBOOST]:
|
||||||
|
begin
|
||||||
|
rd <= 1'b1;
|
||||||
|
if (drp_done) begin
|
||||||
|
rd <= 1'b0;
|
||||||
|
fboost_store <= dout[2];
|
||||||
|
cpll_cal_state[MODIFY_FBOOST] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state[READ_FBOOST] <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[MODIFY_FBOOST]:
|
||||||
|
begin
|
||||||
|
if (!drp_done) begin
|
||||||
|
wr <= 1'b1;
|
||||||
|
cpll_cal_state[MODIFY_FBOOST] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
wr <= 1'b0;
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
di_msk<= {13'd0,MOD_FBOOST,2'b00};
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpllreset_int <= 1'b1;
|
||||||
|
freq_counter_rst <= 1'b1;
|
||||||
|
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[ASSERT_CPLLPD]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpllpd_int <= 1'b1;
|
||||||
|
cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[DEASSERT_CPLLPD]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_DEASSERT_CPLLPD_IN) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpllpd_int <= 1'b0;
|
||||||
|
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[DEASSERT_CPLLRESET]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpllreset_int <= 1'b0;
|
||||||
|
cpll_cal_state[RESTORE_FBOOST] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[RESTORE_FBOOST]:
|
||||||
|
begin
|
||||||
|
if (!drp_done) begin
|
||||||
|
wr <= 1'b1;
|
||||||
|
cpll_cal_state[RESTORE_FBOOST] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
wr <= 1'b0;
|
||||||
|
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
|
||||||
|
end
|
||||||
|
di_msk<= {13'd0,fboost_store,2'b00};
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[WAIT_GTCPLLLOCK]:
|
||||||
|
begin
|
||||||
|
if(wait_ctr < WAIT_CPLLLOCK) begin
|
||||||
|
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[ASSERT_PROGDIVRESET]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
txprogdivreset_int <= 1'b1;
|
||||||
|
cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
txprogdivreset_int <= 1'b0;
|
||||||
|
cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[WAIT_PRGDIVRESETDONE]:
|
||||||
|
begin
|
||||||
|
if (gthe3_txprgdivresetdone_sync) begin
|
||||||
|
cpll_cal_state[CHECK_FREQ] <= 1'b1;
|
||||||
|
freq_counter_rst <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[CHECK_FREQ]:
|
||||||
|
begin
|
||||||
|
if(freq_cnt_done) begin
|
||||||
|
if ((txoutclk_freq_cnt >= (TXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (txoutclk_freq_cnt <= (TXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
|
||||||
|
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
|
||||||
|
cal_fail_store <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (repeat_ctr < REPEAT_RESET_LIMIT) begin
|
||||||
|
cpll_cal_state[READ_FBOOST] <= 1'b1;
|
||||||
|
repeat_ctr <= repeat_ctr + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
|
||||||
|
cal_fail_store <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else
|
||||||
|
cpll_cal_state[CHECK_FREQ] <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[RESTORE_PROGDIV]:
|
||||||
|
begin
|
||||||
|
if (!drp_done) begin
|
||||||
|
wr <= 1'b1;
|
||||||
|
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
wr <= 1'b0;
|
||||||
|
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
|
||||||
|
end
|
||||||
|
di_msk<= progdiv_cfg_store;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[RESTORE_PROGCLK_SEL]:
|
||||||
|
begin
|
||||||
|
if (!drp_done) begin
|
||||||
|
wr <= 1'b1;
|
||||||
|
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
wr <= 1'b0;
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET2] <= 1'b1;
|
||||||
|
end
|
||||||
|
di_msk<= {4'd0,progclk_sel_store,10'd0};
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET2]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
cpll_cal_state[ASSERT_CPLLRESET2] <= 1'b1;
|
||||||
|
cpllreset_int <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpllreset_int <= 1'b0;
|
||||||
|
cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[WAIT_GTCPLLLOCK2]:
|
||||||
|
begin
|
||||||
|
if(gthe3_cplllock_sync)
|
||||||
|
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
|
||||||
|
else
|
||||||
|
cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[ASSERT_PROGDIVRESET2]:
|
||||||
|
begin
|
||||||
|
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
|
||||||
|
wait_ctr <= wait_ctr + 1'b1;
|
||||||
|
txprogdivreset_int <= 1'b1;
|
||||||
|
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
txprogdivreset_int <= 1'b0;
|
||||||
|
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
|
||||||
|
wait_ctr <= 16'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
|
||||||
|
begin
|
||||||
|
if (gthe3_txprgdivresetdone_sync) begin
|
||||||
|
if (cal_fail_store)
|
||||||
|
cpll_cal_state[CAL_FAIL] <= 1'b1;
|
||||||
|
else
|
||||||
|
cpll_cal_state[CAL_DONE] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[CAL_FAIL]:
|
||||||
|
begin
|
||||||
|
cpll_cal_state[CAL_FAIL] <= 1'b1;
|
||||||
|
mask_user_in <= 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
cpll_cal_state[CAL_DONE]:
|
||||||
|
begin
|
||||||
|
cpll_cal_state[CAL_DONE] <= 1'b1;
|
||||||
|
mask_user_in <= 1'b0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end // always block
|
||||||
|
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (cpll_cal_state[RESET])
|
||||||
|
txoutclksel_int <= 3'b0;
|
||||||
|
else if (cpll_cal_state[MODIFY_TXOUTCLK_SEL])
|
||||||
|
txoutclksel_int <= MOD_TXOUTCLK_SEL;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (cpll_cal_state[RESET]) begin
|
||||||
|
daddr <= 9'h000;
|
||||||
|
mask <= 16'b1111_1111_1111_1111;
|
||||||
|
end
|
||||||
|
else if (cpll_cal_state[READ_PROGCLK_SEL] | cpll_cal_state[MODIFY_PROGCLK_SEL] | cpll_cal_state[RESTORE_PROGCLK_SEL]) begin
|
||||||
|
daddr <= ADDR_TX_PROGCLK_SEL;
|
||||||
|
mask <= 16'b1111_0011_1111_1111;
|
||||||
|
end
|
||||||
|
else if (cpll_cal_state[READ_PROGDIV] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
|
||||||
|
daddr <= ADDR_TX_PROGDIV_CFG;
|
||||||
|
mask <= 16'b0000_0000_0000_0000;
|
||||||
|
end
|
||||||
|
else if (cpll_cal_state[READ_FBOOST] | cpll_cal_state[MODIFY_FBOOST] | cpll_cal_state[RESTORE_FBOOST]) begin
|
||||||
|
daddr <= ADDR_FBOOST;
|
||||||
|
mask <= 16'b1111_1111_1111_1011;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
// DRP FSM
|
||||||
|
always @(posedge CLK_IN) begin
|
||||||
|
if (mask_user_in) begin
|
||||||
|
GTHE3_CHANNEL_DRPADDR_OUT <= daddr;
|
||||||
|
GTHE3_CHANNEL_DRPDI_OUT <= di;
|
||||||
|
GTHE3_CHANNEL_DRPEN_OUT <= den;
|
||||||
|
GTHE3_CHANNEL_DRPWE_OUT <= dwe;
|
||||||
|
USER_CHANNEL_DRPRDY_OUT <= 1'b0;
|
||||||
|
USER_CHANNEL_DRPDO_OUT <= 16'd0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
GTHE3_CHANNEL_DRPADDR_OUT <= USER_CHANNEL_DRPADDR_IN;
|
||||||
|
GTHE3_CHANNEL_DRPDI_OUT <= USER_CHANNEL_DRPDI_IN;
|
||||||
|
GTHE3_CHANNEL_DRPEN_OUT <= USER_CHANNEL_DRPEN_IN;
|
||||||
|
GTHE3_CHANNEL_DRPWE_OUT <= USER_CHANNEL_DRPWE_IN;
|
||||||
|
USER_CHANNEL_DRPRDY_OUT <= GTHE3_CHANNEL_DRPRDY_IN;
|
||||||
|
USER_CHANNEL_DRPDO_OUT <= GTHE3_CHANNEL_DRPDO_IN;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
assign drdy = GTHE3_CHANNEL_DRPRDY_IN;
|
||||||
|
assign dout = GTHE3_CHANNEL_DRPDO_IN;
|
||||||
|
|
||||||
|
always @(posedge CLK_IN or posedge reset_in_sync) begin
|
||||||
|
if (reset_in_sync) begin
|
||||||
|
den <= 1'b0;
|
||||||
|
dwe <= 1'b0;
|
||||||
|
di <= 16'h0000;
|
||||||
|
drp_state <= 0;
|
||||||
|
drp_state[DRP_WAIT] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
drp_state <= 0;
|
||||||
|
case (1'b1) // synthesis parallel_case full_case
|
||||||
|
drp_state[DRP_WAIT]:
|
||||||
|
begin
|
||||||
|
if (wr | rd) drp_state[DRP_READ] <= 1'b1;
|
||||||
|
else drp_state[DRP_WAIT] <= 1'b1;
|
||||||
|
end
|
||||||
|
drp_state[DRP_READ]:
|
||||||
|
begin
|
||||||
|
den <= 1'b1;
|
||||||
|
drp_state[DRP_READ_ACK] <= 1'b1;
|
||||||
|
end
|
||||||
|
drp_state[DRP_READ_ACK]:
|
||||||
|
begin
|
||||||
|
den <= 1'b0;
|
||||||
|
if (drdy == 1'b1) begin
|
||||||
|
if (rd) drp_state[DRP_DONE] <= 1'b1;
|
||||||
|
else drp_state[DRP_MODIFY] <= 1'b1;
|
||||||
|
end
|
||||||
|
else drp_state[DRP_READ_ACK] <= 1'b1;
|
||||||
|
end
|
||||||
|
drp_state[DRP_MODIFY]:
|
||||||
|
begin
|
||||||
|
di <= di_msk | (dout & mask);
|
||||||
|
drp_state[DRP_WRITE] <= 1'b1;
|
||||||
|
end
|
||||||
|
drp_state[DRP_WRITE]:
|
||||||
|
begin
|
||||||
|
den <= 1'b1;
|
||||||
|
dwe <= 1'b1;
|
||||||
|
drp_state[DRP_WRITE_ACK] <= 1'b1;
|
||||||
|
end
|
||||||
|
drp_state[DRP_WRITE_ACK]:
|
||||||
|
begin
|
||||||
|
den <= 1'b0;
|
||||||
|
dwe <= 1'b0;
|
||||||
|
if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
|
||||||
|
else drp_state[DRP_WRITE_ACK] <= 1'b1;
|
||||||
|
end
|
||||||
|
drp_state[DRP_DONE]:
|
||||||
|
begin
|
||||||
|
drp_state[DRP_WAIT] <= 1'b1;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign drp_done = drp_state[DRP_DONE];
|
||||||
|
|
||||||
|
|
||||||
|
//debug logic - convert one hot state to binary
|
||||||
|
genvar i,j;
|
||||||
|
generate
|
||||||
|
for (j=0; j<5; j=j+1)
|
||||||
|
begin : jl
|
||||||
|
wire [26-1:0] tmp_mask;
|
||||||
|
for (i=0; i<26; i=i+1)
|
||||||
|
begin : il
|
||||||
|
assign tmp_mask[i] = i[j];
|
||||||
|
end
|
||||||
|
assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule //CPLL_CAL
|
||||||
@@ -0,0 +1,224 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_freq_counter # (
|
||||||
|
parameter REVISION = 1
|
||||||
|
)(
|
||||||
|
output reg [17:0] freq_cnt_o = 18'd0,
|
||||||
|
output reg done_o,
|
||||||
|
input wire rst_i,
|
||||||
|
input wire [15:0] test_term_cnt_i,
|
||||||
|
input wire ref_clk_i,
|
||||||
|
input wire test_clk_i
|
||||||
|
);
|
||||||
|
//****************************************************************************
|
||||||
|
// Local Parameters
|
||||||
|
//****************************************************************************
|
||||||
|
localparam RESET_STATE = 0;
|
||||||
|
localparam MEASURE_STATE = 1;
|
||||||
|
localparam HOLD_STATE = 2;
|
||||||
|
localparam UPDATE_STATE = 3;
|
||||||
|
localparam DONE_STATE = 4;
|
||||||
|
|
||||||
|
//****************************************************************************
|
||||||
|
// Local Signals
|
||||||
|
//****************************************************************************
|
||||||
|
reg [17:0] testclk_cnt = 18'h00000;
|
||||||
|
reg [15:0] refclk_cnt = 16'h0000;
|
||||||
|
reg [3:0] testclk_div4 = 4'h1;
|
||||||
|
wire testclk_rst;
|
||||||
|
wire testclk_en;
|
||||||
|
reg [5:0] hold_clk = 6'd0;
|
||||||
|
reg [4:0] state = 5'd1;
|
||||||
|
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
|
||||||
|
|
||||||
|
//
|
||||||
|
// need to get testclk_rst into TESTCLK_I domain
|
||||||
|
//
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
tstclk_rst_dly1 <= testclk_rst;
|
||||||
|
tstclk_rst_dly2 <= tstclk_rst_dly1;
|
||||||
|
end
|
||||||
|
|
||||||
|
//
|
||||||
|
// need to get testclk_en into TESTCLK_I domain
|
||||||
|
//
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
testclk_en_dly1 <= testclk_en;
|
||||||
|
testclk_en_dly2 <= testclk_en_dly1;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
if (tstclk_rst_dly2 == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_div4 <= 4'h1;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
wire testclk_rst_sync;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_testclk_rst_inst (
|
||||||
|
.clk_in (test_clk_i),
|
||||||
|
.rst_in (testclk_rst),
|
||||||
|
.rst_out (testclk_rst_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge test_clk_i or posedge testclk_rst_sync)
|
||||||
|
begin
|
||||||
|
if (testclk_rst_sync == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= testclk_cnt + 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
/* always @(posedge test_clk_i or posedge testclk_rst)
|
||||||
|
begin
|
||||||
|
if (testclk_rst == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= testclk_cnt + 1;
|
||||||
|
end
|
||||||
|
end */
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i or posedge rst_i)
|
||||||
|
begin
|
||||||
|
if (rst_i)
|
||||||
|
done_o <= 1'b0;
|
||||||
|
else
|
||||||
|
done_o <= state[DONE_STATE];
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i or posedge rst_i)
|
||||||
|
begin
|
||||||
|
if (rst_i) begin
|
||||||
|
state <= 0;
|
||||||
|
state[RESET_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
state <= 0;
|
||||||
|
case (1'b1) // synthesis parallel_case full_case
|
||||||
|
state[RESET_STATE]:
|
||||||
|
begin
|
||||||
|
if (hold_clk == 6'h3F)
|
||||||
|
state[MEASURE_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[RESET_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[MEASURE_STATE]:
|
||||||
|
begin
|
||||||
|
if (refclk_cnt == test_term_cnt_i)
|
||||||
|
state[HOLD_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[MEASURE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[HOLD_STATE]:
|
||||||
|
begin
|
||||||
|
if (hold_clk == 6'hF)
|
||||||
|
state[UPDATE_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[HOLD_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[UPDATE_STATE]:
|
||||||
|
begin
|
||||||
|
freq_cnt_o <= testclk_cnt;
|
||||||
|
state[DONE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[DONE_STATE]:
|
||||||
|
begin
|
||||||
|
state[DONE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign testclk_rst = state[RESET_STATE];
|
||||||
|
assign testclk_en = state[MEASURE_STATE];
|
||||||
|
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i)
|
||||||
|
begin
|
||||||
|
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
|
||||||
|
hold_clk <= hold_clk + 1;
|
||||||
|
else
|
||||||
|
hold_clk <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i)
|
||||||
|
begin
|
||||||
|
if (state[MEASURE_STATE] == 1'b1)
|
||||||
|
refclk_cnt <= refclk_cnt + 1;
|
||||||
|
else
|
||||||
|
refclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,346 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal # (
|
||||||
|
parameter integer C_RX_PLL_TYPE = 0,
|
||||||
|
parameter integer C_TX_PLL_TYPE = 0,
|
||||||
|
parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
|
||||||
|
parameter SIM_RESET_SPEEDUP = "TRUE",
|
||||||
|
parameter C_FREERUN_FREQUENCY = 100,
|
||||||
|
parameter REVISION = 2,
|
||||||
|
parameter C_PCIE_ENABLE = "FALSE",
|
||||||
|
parameter C_PCIE_CORECLK_FREQ = 250
|
||||||
|
)(
|
||||||
|
// control signals
|
||||||
|
input wire [17:0] TXOUTCLK_PERIOD_IN,
|
||||||
|
input wire [17:0] CNT_TOL_IN,
|
||||||
|
input wire [15:0] FREQ_COUNT_WINDOW_IN,
|
||||||
|
// User Interface
|
||||||
|
input wire RESET_IN,
|
||||||
|
input wire CLK_IN,
|
||||||
|
input wire DRPRST_IN,
|
||||||
|
input wire [1:0] USER_TXPLLCLKSEL,
|
||||||
|
input wire [1:0] USER_RXPLLCLKSEL,
|
||||||
|
input wire USER_RXPROGDIVRESET_IN,
|
||||||
|
output wire USER_RXPRGDIVRESETDONE_OUT,
|
||||||
|
output wire USER_RXPMARESETDONE_OUT,
|
||||||
|
input wire [2:0] USER_RXOUTCLKSEL_IN,
|
||||||
|
input wire USER_RXOUTCLK_BUFG_CE_IN,
|
||||||
|
input wire USER_RXOUTCLK_BUFG_CLR_IN,
|
||||||
|
input wire USER_GTRXRESET_IN,
|
||||||
|
input wire USER_RXCDRHOLD_IN,
|
||||||
|
input wire USER_RXPMARESET_IN,
|
||||||
|
input wire USER_TXPROGDIVRESET_IN,
|
||||||
|
output wire USER_TXPRGDIVRESETDONE_OUT,
|
||||||
|
input wire [2:0] USER_TXOUTCLKSEL_IN,
|
||||||
|
input wire USER_TXOUTCLK_BUFG_CE_IN,
|
||||||
|
input wire USER_TXOUTCLK_BUFG_CLR_IN,
|
||||||
|
output wire USER_CPLLLOCK_OUT,
|
||||||
|
input wire [9:0] USER_CHANNEL_DRPADDR_IN,
|
||||||
|
input wire [15:0] USER_CHANNEL_DRPDI_IN,
|
||||||
|
input wire USER_CHANNEL_DRPEN_IN,
|
||||||
|
input wire USER_CHANNEL_DRPWE_IN,
|
||||||
|
output wire USER_CHANNEL_DRPRDY_OUT,
|
||||||
|
output wire [15:0] USER_CHANNEL_DRPDO_OUT,
|
||||||
|
// Debug Interface
|
||||||
|
output wire CPLL_CAL_FAIL,
|
||||||
|
output wire CPLL_CAL_DONE,
|
||||||
|
output wire [15:0] DEBUG_OUT,
|
||||||
|
output wire [17:0] CAL_FREQ_CNT,
|
||||||
|
input [3:0] REPEAT_RESET_LIMIT,
|
||||||
|
// GT Interface
|
||||||
|
input wire GTHE4_TXOUTCLK_IN,
|
||||||
|
input wire GTHE4_RXOUTCLK_IN,
|
||||||
|
input wire GTHE4_CPLLLOCK_IN,
|
||||||
|
output wire GTHE4_CPLLRESET_OUT,
|
||||||
|
output wire GTHE4_RXCDRHOLD_OUT,
|
||||||
|
output wire GTHE4_GTRXRESET_OUT,
|
||||||
|
output wire GTHE4_RXPMARESET_OUT,
|
||||||
|
output wire GTHE4_RXPROGDIVRESET_OUT,
|
||||||
|
output wire [2:0] GTHE4_RXOUTCLKSEL_OUT,
|
||||||
|
input wire GTHE4_RXPRGDIVRESETDONE_IN,
|
||||||
|
input wire GTHE4_RXPMARESETDONE_IN,
|
||||||
|
output wire GTHE4_CPLLPD_OUT,
|
||||||
|
output wire GTHE4_TXPROGDIVRESET_OUT,
|
||||||
|
output wire [2:0] GTHE4_TXOUTCLKSEL_OUT,
|
||||||
|
input wire GTHE4_TXPRGDIVRESETDONE_IN,
|
||||||
|
output wire [9:0] GTHE4_CHANNEL_DRPADDR_OUT,
|
||||||
|
output wire [15:0] GTHE4_CHANNEL_DRPDI_OUT,
|
||||||
|
output wire GTHE4_CHANNEL_DRPEN_OUT,
|
||||||
|
output wire GTHE4_CHANNEL_DRPWE_OUT,
|
||||||
|
input wire GTHE4_CHANNEL_DRPRDY_IN,
|
||||||
|
input wire [15:0] GTHE4_CHANNEL_DRPDO_IN
|
||||||
|
);
|
||||||
|
|
||||||
|
wire rx_done;
|
||||||
|
wire tx_done;
|
||||||
|
|
||||||
|
wire cal_on_rx_cal_fail;
|
||||||
|
wire cal_on_rx_cal_done;
|
||||||
|
wire [15:0] cal_on_rx_debug_out;
|
||||||
|
wire [17:0] cal_on_rx_cal_freq_cnt;
|
||||||
|
wire cal_on_rx_cpllreset_out;
|
||||||
|
wire cal_on_rx_cpllpd_out;
|
||||||
|
wire cal_on_rx_cplllock_out;
|
||||||
|
|
||||||
|
wire cal_on_rx_drpen_out;
|
||||||
|
wire cal_on_rx_drpwe_out;
|
||||||
|
wire [9:0] cal_on_rx_drpaddr_out;
|
||||||
|
wire [15:0] cal_on_rx_drpdi_out;
|
||||||
|
wire [15:0] cal_on_rx_dout;
|
||||||
|
wire cal_on_rx_drdy;
|
||||||
|
|
||||||
|
wire cal_on_tx_cal_fail;
|
||||||
|
wire cal_on_tx_cal_done;
|
||||||
|
wire [15:0] cal_on_tx_debug_out;
|
||||||
|
wire [17:0] cal_on_tx_cal_freq_cnt;
|
||||||
|
wire cal_on_tx_cpllreset_out;
|
||||||
|
wire cal_on_tx_cpllpd_out;
|
||||||
|
wire cal_on_tx_cplllock_out;
|
||||||
|
|
||||||
|
wire cal_on_tx_drpen_out;
|
||||||
|
wire cal_on_tx_drpwe_out;
|
||||||
|
wire [9:0] cal_on_tx_drpaddr_out;
|
||||||
|
wire [15:0] cal_on_tx_drpdi_out;
|
||||||
|
wire [15:0] cal_on_tx_dout;
|
||||||
|
wire cal_on_tx_drdy;
|
||||||
|
|
||||||
|
localparam [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C;
|
||||||
|
localparam [9:0] ADDR_TX_PROGDIV_CFG = 10'h03E; // GTH /GTY addresses are different (003E in GTH; 0057 in GTY)
|
||||||
|
localparam [9:0] ADDR_RX_PROGDIV_CFG = 10'h0C6;
|
||||||
|
localparam [9:0] ADDR_X0E1 = 10'h0E1;
|
||||||
|
localparam [9:0] ADDR_X079 = 10'h079;
|
||||||
|
localparam [9:0] ADDR_X114 = 10'h114;
|
||||||
|
localparam CPLL_CAL_ONLY_TX = (C_RX_PLL_TYPE == C_TX_PLL_TYPE); // If top level configuration of TX and RX PLL TYPE are same, don't use RX Cal block
|
||||||
|
|
||||||
|
wire cpll_cal_on_tx_or_rx; //1: RX cal block, 0: TX cal block;
|
||||||
|
assign cpll_cal_on_tx_or_rx = CPLL_CAL_ONLY_TX ? 1'b0 : ((USER_TXPLLCLKSEL != 2'b00 && USER_RXPLLCLKSEL == 2'b00) ? 1'b1 : 1'b0);
|
||||||
|
|
||||||
|
// TX reset version
|
||||||
|
wire cal_on_tx_reset_in;
|
||||||
|
assign cal_on_tx_reset_in = RESET_IN | cpll_cal_on_tx_or_rx;
|
||||||
|
|
||||||
|
wire cal_on_tx_reset_in_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_tx_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.rst_in (cal_on_tx_reset_in),
|
||||||
|
.rst_out (cal_on_tx_reset_in_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// RX reset version
|
||||||
|
wire cal_on_rx_reset_in;
|
||||||
|
assign cal_on_rx_reset_in = RESET_IN | !cpll_cal_on_tx_or_rx;
|
||||||
|
|
||||||
|
wire cal_on_rx_reset_in_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_rx_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.rst_in (cal_on_rx_reset_in),
|
||||||
|
.rst_out (cal_on_rx_reset_in_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire drprst_in_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_drprst_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (DRPRST_IN),
|
||||||
|
.o_out (drprst_in_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_tx #
|
||||||
|
(
|
||||||
|
.C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
|
||||||
|
.SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
|
||||||
|
.C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
|
||||||
|
.C_PCIE_ENABLE(C_PCIE_ENABLE),
|
||||||
|
.C_PCIE_CORECLK_FREQ(C_PCIE_CORECLK_FREQ)
|
||||||
|
) gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_tx_i
|
||||||
|
(
|
||||||
|
// control signals
|
||||||
|
.TXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
|
||||||
|
.CNT_TOL_IN(CNT_TOL_IN),
|
||||||
|
.FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
|
||||||
|
// User Interface
|
||||||
|
.RESET_IN(cal_on_tx_reset_in_sync),
|
||||||
|
.CLK_IN(CLK_IN),
|
||||||
|
.USER_TXPLLCLKSEL(USER_TXPLLCLKSEL),
|
||||||
|
.USER_TXPROGDIVRESET_IN(USER_TXPROGDIVRESET_IN),
|
||||||
|
.USER_TXPRGDIVRESETDONE_OUT(USER_TXPRGDIVRESETDONE_OUT),
|
||||||
|
.USER_TXOUTCLKSEL_IN(USER_TXOUTCLKSEL_IN),
|
||||||
|
.USER_TXOUTCLK_BUFG_CE_IN(USER_TXOUTCLK_BUFG_CE_IN),
|
||||||
|
.USER_TXOUTCLK_BUFG_CLR_IN(USER_TXOUTCLK_BUFG_CLR_IN),
|
||||||
|
.USER_CPLLLOCK_OUT(cal_on_tx_cplllock_out),
|
||||||
|
// Debug Interface
|
||||||
|
.CPLL_CAL_FAIL(cal_on_tx_cal_fail),
|
||||||
|
.CPLL_CAL_DONE(cal_on_tx_cal_done),
|
||||||
|
.DEBUG_OUT(cal_on_tx_debug_out),
|
||||||
|
.CAL_FREQ_CNT(cal_on_tx_cal_freq_cnt),
|
||||||
|
.REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
|
||||||
|
// GT Interface
|
||||||
|
.GTHE4_TXOUTCLK_IN(GTHE4_TXOUTCLK_IN),
|
||||||
|
.GTHE4_CPLLLOCK_IN(GTHE4_CPLLLOCK_IN),
|
||||||
|
.GTHE4_CPLLRESET_OUT(cal_on_tx_cpllreset_out),
|
||||||
|
.GTHE4_CPLLPD_OUT(cal_on_tx_cpllpd_out),
|
||||||
|
.GTHE4_TXPROGDIVRESET_OUT(GTHE4_TXPROGDIVRESET_OUT),
|
||||||
|
.GTHE4_TXOUTCLKSEL_OUT(GTHE4_TXOUTCLKSEL_OUT),
|
||||||
|
.GTHE4_TXPRGDIVRESETDONE_IN(GTHE4_TXPRGDIVRESETDONE_IN),
|
||||||
|
.GTHE4_CHANNEL_DRPADDR_OUT(cal_on_tx_drpaddr_out),
|
||||||
|
.GTHE4_CHANNEL_DRPDI_OUT(cal_on_tx_drpdi_out),
|
||||||
|
.GTHE4_CHANNEL_DRPEN_OUT(cal_on_tx_drpen_out),
|
||||||
|
.GTHE4_CHANNEL_DRPWE_OUT(cal_on_tx_drpwe_out),
|
||||||
|
.GTHE4_CHANNEL_DRPRDY_IN(cal_on_tx_drdy),
|
||||||
|
.GTHE4_CHANNEL_DRPDO_IN(cal_on_tx_dout),
|
||||||
|
.DONE(tx_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_rx #
|
||||||
|
(
|
||||||
|
.C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
|
||||||
|
.SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
|
||||||
|
.CPLL_CAL_ONLY_TX(CPLL_CAL_ONLY_TX),
|
||||||
|
.C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY)
|
||||||
|
) gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_rx_i
|
||||||
|
(
|
||||||
|
// control signals
|
||||||
|
.RXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
|
||||||
|
.CNT_TOL_IN(CNT_TOL_IN),
|
||||||
|
.FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
|
||||||
|
// User Interface
|
||||||
|
.RESET_IN(cal_on_rx_reset_in_sync),
|
||||||
|
.CLK_IN(CLK_IN),
|
||||||
|
.USER_RXPROGDIVRESET_IN(USER_RXPROGDIVRESET_IN),
|
||||||
|
.USER_RXPRGDIVRESETDONE_OUT(USER_RXPRGDIVRESETDONE_OUT),
|
||||||
|
.USER_RXPMARESETDONE_OUT(USER_RXPMARESETDONE_OUT),
|
||||||
|
.USER_RXOUTCLKSEL_IN(USER_RXOUTCLKSEL_IN),
|
||||||
|
.USER_RXOUTCLK_BUFG_CE_IN(USER_RXOUTCLK_BUFG_CE_IN),
|
||||||
|
.USER_RXOUTCLK_BUFG_CLR_IN(USER_RXOUTCLK_BUFG_CLR_IN),
|
||||||
|
.USER_CPLLLOCK_OUT(cal_on_rx_cplllock_out),
|
||||||
|
.USER_RXCDRHOLD_IN(USER_RXCDRHOLD_IN),
|
||||||
|
.USER_GTRXRESET_IN(USER_GTRXRESET_IN),
|
||||||
|
.USER_RXPMARESET_IN(USER_RXPMARESET_IN),
|
||||||
|
// Debug Interface
|
||||||
|
.CPLL_CAL_FAIL(cal_on_rx_cal_fail),
|
||||||
|
.CPLL_CAL_DONE(cal_on_rx_cal_done),
|
||||||
|
.DEBUG_OUT(cal_on_rx_debug_out),
|
||||||
|
.CAL_FREQ_CNT(cal_on_rx_cal_freq_cnt),
|
||||||
|
.REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
|
||||||
|
// GT Interface
|
||||||
|
.GTHE4_RXOUTCLK_IN(GTHE4_RXOUTCLK_IN),
|
||||||
|
.GTHE4_CPLLLOCK_IN(GTHE4_CPLLLOCK_IN),
|
||||||
|
.GTHE4_CPLLRESET_OUT(cal_on_rx_cpllreset_out),
|
||||||
|
.GTHE4_CPLLPD_OUT(cal_on_rx_cpllpd_out),
|
||||||
|
.GTHE4_RXPROGDIVRESET_OUT(GTHE4_RXPROGDIVRESET_OUT),
|
||||||
|
.GTHE4_RXOUTCLKSEL_OUT(GTHE4_RXOUTCLKSEL_OUT),
|
||||||
|
.GTHE4_RXPRGDIVRESETDONE_IN(GTHE4_RXPRGDIVRESETDONE_IN),
|
||||||
|
.GTHE4_CHANNEL_DRPADDR_OUT(cal_on_rx_drpaddr_out),
|
||||||
|
.GTHE4_CHANNEL_DRPDI_OUT(cal_on_rx_drpdi_out),
|
||||||
|
.GTHE4_CHANNEL_DRPEN_OUT(cal_on_rx_drpen_out),
|
||||||
|
.GTHE4_CHANNEL_DRPWE_OUT(cal_on_rx_drpwe_out),
|
||||||
|
.GTHE4_CHANNEL_DRPRDY_IN(cal_on_rx_drdy),
|
||||||
|
.GTHE4_CHANNEL_DRPDO_IN(cal_on_rx_dout),
|
||||||
|
.GTHE4_GTRXRESET_OUT(GTHE4_GTRXRESET_OUT),
|
||||||
|
.GTHE4_RXPMARESET_OUT(GTHE4_RXPMARESET_OUT),
|
||||||
|
.GTHE4_RXCDRHOLD_OUT(GTHE4_RXCDRHOLD_OUT),
|
||||||
|
.GTHE4_RXPMARESETDONE_IN(GTHE4_RXPMARESETDONE_IN),
|
||||||
|
.DONE(rx_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
//OR with TX versions
|
||||||
|
assign GTHE4_CPLLRESET_OUT = cal_on_rx_cpllreset_out | cal_on_tx_cpllreset_out;
|
||||||
|
assign GTHE4_CPLLPD_OUT = cal_on_rx_cpllpd_out | cal_on_tx_cpllpd_out;
|
||||||
|
assign USER_CPLLLOCK_OUT = cal_on_rx_cplllock_out | cal_on_tx_cplllock_out;
|
||||||
|
|
||||||
|
//Mux the debug signals out
|
||||||
|
assign CPLL_CAL_DONE = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_done : cal_on_tx_cal_done;
|
||||||
|
assign CPLL_CAL_FAIL = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_fail : cal_on_tx_cal_fail;
|
||||||
|
assign DEBUG_OUT = cpll_cal_on_tx_or_rx ? cal_on_rx_debug_out : cal_on_tx_debug_out;
|
||||||
|
assign CAL_FREQ_CNT = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_freq_cnt : cal_on_tx_cal_freq_cnt;
|
||||||
|
|
||||||
|
//----------------------------------------------------------------------------------------------
|
||||||
|
// DRP ARBITER
|
||||||
|
//----------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_gte4_drp_arb #
|
||||||
|
(
|
||||||
|
.ADDR_TX_PROGCLK_SEL(ADDR_TX_PROGCLK_SEL),
|
||||||
|
.ADDR_TX_PROGDIV_CFG(ADDR_TX_PROGDIV_CFG),
|
||||||
|
.ADDR_RX_PROGDIV_CFG(ADDR_RX_PROGDIV_CFG),
|
||||||
|
.ADDR_X0E1(ADDR_X0E1),
|
||||||
|
.ADDR_X079(ADDR_X079),
|
||||||
|
.ADDR_X114(ADDR_X114),
|
||||||
|
.C_NUM_CLIENTS(3),
|
||||||
|
.C_ADDR_WIDTH(10),
|
||||||
|
.C_DATA_WIDTH(16)
|
||||||
|
) gtwizard_ultrascale_v1_7_14_gte4_drp_arb_i
|
||||||
|
(
|
||||||
|
.DCLK_I (CLK_IN),
|
||||||
|
.RESET_I (drprst_in_sync),
|
||||||
|
.DEN_USR_I ({cal_on_tx_drpen_out, cal_on_rx_drpen_out, USER_CHANNEL_DRPEN_IN}),
|
||||||
|
.DWE_USR_I ({cal_on_tx_drpwe_out, cal_on_rx_drpwe_out, USER_CHANNEL_DRPWE_IN}),
|
||||||
|
.DADDR_USR_I ({cal_on_tx_drpaddr_out, cal_on_rx_drpaddr_out, USER_CHANNEL_DRPADDR_IN}),
|
||||||
|
.DI_USR_I ({cal_on_tx_drpdi_out, cal_on_rx_drpdi_out, USER_CHANNEL_DRPDI_IN}),
|
||||||
|
.DO_USR_O ({cal_on_tx_dout, cal_on_rx_dout, USER_CHANNEL_DRPDO_OUT}),
|
||||||
|
.DRDY_USR_O ({cal_on_tx_drdy, cal_on_rx_drdy, USER_CHANNEL_DRPRDY_OUT}),
|
||||||
|
// arbitrated port
|
||||||
|
.DEN_O (GTHE4_CHANNEL_DRPEN_OUT),
|
||||||
|
.DWE_O (GTHE4_CHANNEL_DRPWE_OUT),
|
||||||
|
.DADDR_O (GTHE4_CHANNEL_DRPADDR_OUT),
|
||||||
|
.DI_O (GTHE4_CHANNEL_DRPDI_OUT),
|
||||||
|
.DO_I (GTHE4_CHANNEL_DRPDO_IN),
|
||||||
|
.DRDY_I (GTHE4_CHANNEL_DRPRDY_IN),
|
||||||
|
.TX_CAL_DONE_I (tx_done),
|
||||||
|
.RX_CAL_DONE_I (rx_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule //CPLL_CAL
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,170 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gthe4_delay_powergood # (
|
||||||
|
parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
|
||||||
|
parameter C_PCIE_ENABLE = "FALSE"
|
||||||
|
)(
|
||||||
|
input wire GT_RXOUTCLKPCS,
|
||||||
|
|
||||||
|
input wire GT_GTPOWERGOOD,
|
||||||
|
input wire [2:0] USER_RXRATE,
|
||||||
|
input wire USER_RXRATEMODE,
|
||||||
|
input wire USER_GTRXRESET,
|
||||||
|
input wire USER_RXPMARESET,
|
||||||
|
input wire [1:0] USER_RXPD,
|
||||||
|
|
||||||
|
output wire USER_GTPOWERGOOD,
|
||||||
|
output wire [2:0] GT_RXRATE,
|
||||||
|
output wire GT_RXRATEMODE,
|
||||||
|
output wire GT_GTRXRESET,
|
||||||
|
output wire GT_RXPMARESET,
|
||||||
|
output wire [1:0] GT_RXPD
|
||||||
|
);
|
||||||
|
|
||||||
|
generate if (C_PCIE_ENABLE || (C_USER_GTPOWERGOOD_DELAY_EN == 0))
|
||||||
|
begin : gen_powergood_nodelay
|
||||||
|
assign GT_RXPD = USER_RXPD;
|
||||||
|
assign GT_GTRXRESET = USER_GTRXRESET;
|
||||||
|
assign GT_RXPMARESET = USER_RXPMARESET;
|
||||||
|
assign GT_RXRATE = USER_RXRATE;
|
||||||
|
assign GT_RXRATEMODE = USER_RXRATEMODE;
|
||||||
|
assign USER_GTPOWERGOOD = GT_GTPOWERGOOD;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin: gen_powergood_delay
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r = 5'd0;
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [8:0] wait_cnt;
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg int_pwr_on_fsm = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
|
||||||
|
wire intclk_rrst_n;
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
// POWER ON FSM Encoding
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
localparam PWR_ON_WAIT_CNT = 4'd0;
|
||||||
|
localparam PWR_ON_DONE = 4'd1;
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
// Reset Synchronizer
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
always @ (posedge GT_RXOUTCLKPCS or negedge GT_GTPOWERGOOD)
|
||||||
|
begin
|
||||||
|
if (!GT_GTPOWERGOOD)
|
||||||
|
intclk_rrst_n_r <= 5'd0;
|
||||||
|
else if(!int_pwr_on_fsm)
|
||||||
|
intclk_rrst_n_r <= {intclk_rrst_n_r[3:0], 1'd1};
|
||||||
|
end
|
||||||
|
|
||||||
|
assign intclk_rrst_n = intclk_rrst_n_r[4];
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
// Wait counter
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
always @ (posedge GT_RXOUTCLKPCS)
|
||||||
|
begin
|
||||||
|
if (!intclk_rrst_n)
|
||||||
|
wait_cnt <= 9'd0;
|
||||||
|
else begin
|
||||||
|
if (int_pwr_on_fsm == PWR_ON_WAIT_CNT)
|
||||||
|
wait_cnt <= {wait_cnt[7:0],1'b1};
|
||||||
|
else
|
||||||
|
wait_cnt <= wait_cnt;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
// Power On FSM
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
always @ (posedge GT_RXOUTCLKPCS or negedge GT_GTPOWERGOOD)
|
||||||
|
begin
|
||||||
|
if (!GT_GTPOWERGOOD)
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (int_pwr_on_fsm)
|
||||||
|
PWR_ON_WAIT_CNT :
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= (wait_cnt[7] == 1'b1) ? PWR_ON_DONE : PWR_ON_WAIT_CNT;
|
||||||
|
end
|
||||||
|
|
||||||
|
PWR_ON_DONE :
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= PWR_ON_DONE;
|
||||||
|
end
|
||||||
|
|
||||||
|
default :
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge GT_RXOUTCLKPCS)
|
||||||
|
pwr_on_fsm <= int_pwr_on_fsm;
|
||||||
|
|
||||||
|
assign GT_RXPD = pwr_on_fsm ? USER_RXPD : 2'b11;
|
||||||
|
assign GT_GTRXRESET = pwr_on_fsm ? USER_GTRXRESET : !GT_GTPOWERGOOD;
|
||||||
|
assign GT_RXPMARESET = pwr_on_fsm ? USER_RXPMARESET : 1'b0;
|
||||||
|
assign GT_RXRATE = pwr_on_fsm ? USER_RXRATE : 3'b001;
|
||||||
|
assign GT_RXRATEMODE = pwr_on_fsm ? USER_RXRATEMODE : 1'b1;
|
||||||
|
assign USER_GTPOWERGOOD = pwr_on_fsm;
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,245 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_rx #(
|
||||||
|
|
||||||
|
parameter integer P_BUFFER_BYPASS_MODE = 0,
|
||||||
|
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
|
||||||
|
parameter integer P_MASTER_CHANNEL_POINTER = 0
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
// User interface ports
|
||||||
|
input wire gtwiz_buffbypass_rx_clk_in,
|
||||||
|
input wire gtwiz_buffbypass_rx_reset_in,
|
||||||
|
input wire gtwiz_buffbypass_rx_start_user_in,
|
||||||
|
input wire gtwiz_buffbypass_rx_resetdone_in,
|
||||||
|
output reg gtwiz_buffbypass_rx_done_out = 1'b0,
|
||||||
|
output reg gtwiz_buffbypass_rx_error_out = 1'b0,
|
||||||
|
|
||||||
|
// Transceiver interface ports
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphaligndone_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlysresetdone_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncout_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncdone_in,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphdlyreset_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphalign_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphalignen_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphdlypd_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxphovrden_out,
|
||||||
|
output reg [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlysreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}},
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlybypass_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlyen_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxdlyovrden_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncmode_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncallin_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] rxsyncin_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Receiver buffer bypass conditional generation, based on parameter values in module instantiation
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_RX_IDLE = 2'd0;
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET = 2'd1;
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE = 2'd2;
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_RX_DONE = 2'd3;
|
||||||
|
|
||||||
|
generate if (1) begin: gen_gtwiz_buffbypass_rx_main
|
||||||
|
|
||||||
|
// Use auto mode buffer bypass
|
||||||
|
if (P_BUFFER_BYPASS_MODE == 0) begin : gen_auto_mode
|
||||||
|
|
||||||
|
// For single-lane auto mode buffer bypass, perform specified input port tie-offs
|
||||||
|
if (P_TOTAL_NUMBER_OF_CHANNELS == 1) begin : gen_assign_one_chan
|
||||||
|
assign rxphdlyreset_out = 1'b0;
|
||||||
|
assign rxphalign_out = 1'b0;
|
||||||
|
assign rxphalignen_out = 1'b0;
|
||||||
|
assign rxphdlypd_out = 1'b0;
|
||||||
|
assign rxphovrden_out = 1'b0;
|
||||||
|
assign rxdlybypass_out = 1'b0;
|
||||||
|
assign rxdlyen_out = 1'b0;
|
||||||
|
assign rxdlyovrden_out = 1'b0;
|
||||||
|
assign rxsyncmode_out = 1'b1;
|
||||||
|
assign rxsyncallin_out = rxphaligndone_in;
|
||||||
|
assign rxsyncin_out = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
// For multi-lane auto mode buffer bypass, perform specified master and slave lane input port tie-offs
|
||||||
|
else begin : gen_assign_multi_chan
|
||||||
|
assign rxphdlyreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign rxphalign_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign rxphalignen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign rxphdlypd_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign rxphovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign rxdlybypass_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign rxdlyen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign rxdlyovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
|
||||||
|
genvar gi;
|
||||||
|
for (gi = 0; gi < P_TOTAL_NUMBER_OF_CHANNELS; gi = gi + 1) begin : gen_assign_rxsyncmode
|
||||||
|
if (gi == P_MASTER_CHANNEL_POINTER)
|
||||||
|
assign rxsyncmode_out[gi] = 1'b1;
|
||||||
|
else
|
||||||
|
assign rxsyncmode_out[gi] = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign rxsyncallin_out = {P_TOTAL_NUMBER_OF_CHANNELS{&rxphaligndone_in}};
|
||||||
|
assign rxsyncin_out = {P_TOTAL_NUMBER_OF_CHANNELS{rxsyncout_in[P_MASTER_CHANNEL_POINTER]}};
|
||||||
|
end
|
||||||
|
|
||||||
|
// Detect the rising edge of the receiver reset done re-synchronized input. Assign an internal buffer bypass
|
||||||
|
// start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
|
||||||
|
wire gtwiz_buffbypass_rx_resetdone_sync_int;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
|
||||||
|
.clk_in (gtwiz_buffbypass_rx_clk_in),
|
||||||
|
.rst_in (gtwiz_buffbypass_rx_resetdone_in),
|
||||||
|
.rst_out (gtwiz_buffbypass_rx_resetdone_sync_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
reg gtwiz_buffbypass_rx_resetdone_reg = 1'b0;
|
||||||
|
wire gtwiz_buffbypass_rx_start_int;
|
||||||
|
|
||||||
|
always @(posedge gtwiz_buffbypass_rx_clk_in) begin
|
||||||
|
if (gtwiz_buffbypass_rx_reset_in)
|
||||||
|
gtwiz_buffbypass_rx_resetdone_reg <= 1'b0;
|
||||||
|
else
|
||||||
|
gtwiz_buffbypass_rx_resetdone_reg <= gtwiz_buffbypass_rx_resetdone_sync_int;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign gtwiz_buffbypass_rx_start_int = (gtwiz_buffbypass_rx_resetdone_sync_int &&
|
||||||
|
~gtwiz_buffbypass_rx_resetdone_reg) || gtwiz_buffbypass_rx_start_user_in;
|
||||||
|
|
||||||
|
// Synchronize the master channel's buffer bypass completion output (RXSYNCDONE) into the local clock domain
|
||||||
|
// and detect its rising edge for purposes of safe state machine transitions
|
||||||
|
reg gtwiz_buffbypass_rx_master_syncdone_sync_reg = 1'b0;
|
||||||
|
wire gtwiz_buffbypass_rx_master_syncdone_sync_int;
|
||||||
|
wire gtwiz_buffbypass_rx_master_syncdone_sync_re;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_mastersyncdone_inst (
|
||||||
|
.clk_in (gtwiz_buffbypass_rx_clk_in),
|
||||||
|
.i_in (rxsyncdone_in[P_MASTER_CHANNEL_POINTER]),
|
||||||
|
.o_out (gtwiz_buffbypass_rx_master_syncdone_sync_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge gtwiz_buffbypass_rx_clk_in)
|
||||||
|
gtwiz_buffbypass_rx_master_syncdone_sync_reg <= gtwiz_buffbypass_rx_master_syncdone_sync_int;
|
||||||
|
|
||||||
|
assign gtwiz_buffbypass_rx_master_syncdone_sync_re = gtwiz_buffbypass_rx_master_syncdone_sync_int &&
|
||||||
|
~gtwiz_buffbypass_rx_master_syncdone_sync_reg;
|
||||||
|
|
||||||
|
// Synchronize the master channel's phase alignment completion output (RXPHALIGNDONE) into the local clock domain
|
||||||
|
wire gtwiz_buffbypass_rx_master_phaligndone_sync_int;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_masterphaligndone_inst (
|
||||||
|
.clk_in (gtwiz_buffbypass_rx_clk_in),
|
||||||
|
.i_in (rxphaligndone_in[P_MASTER_CHANNEL_POINTER]),
|
||||||
|
.o_out (gtwiz_buffbypass_rx_master_phaligndone_sync_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Implement a simple state machine to perform the receiver auto mode buffer bypass procedure
|
||||||
|
reg [1:0] sm_buffbypass_rx = ST_BUFFBYPASS_RX_IDLE;
|
||||||
|
|
||||||
|
always @(posedge gtwiz_buffbypass_rx_clk_in) begin
|
||||||
|
if (gtwiz_buffbypass_rx_reset_in) begin
|
||||||
|
gtwiz_buffbypass_rx_done_out <= 1'b0;
|
||||||
|
gtwiz_buffbypass_rx_error_out <= 1'b0;
|
||||||
|
rxdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_IDLE;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (sm_buffbypass_rx)
|
||||||
|
|
||||||
|
// Upon assertion of the internal buffer bypass start signal, assert RXDLYSRESET output(s)
|
||||||
|
default: begin
|
||||||
|
if (gtwiz_buffbypass_rx_start_int) begin
|
||||||
|
gtwiz_buffbypass_rx_done_out <= 1'b0;
|
||||||
|
gtwiz_buffbypass_rx_error_out <= 1'b0;
|
||||||
|
rxdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b1}};
|
||||||
|
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// De-assert the RXDLYSRESET output(s)
|
||||||
|
ST_BUFFBYPASS_RX_DEASSERT_RXDLYSRESET: begin
|
||||||
|
rxdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Upon assertion of the synchronized RXSYNCDONE indicator, transition to the final state
|
||||||
|
ST_BUFFBYPASS_RX_WAIT_RXSYNCDONE: begin
|
||||||
|
if (gtwiz_buffbypass_rx_master_syncdone_sync_re)
|
||||||
|
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_DONE;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Assert the buffer bypass procedure done user indicator, and set the procedure error flag if the
|
||||||
|
// synchronized RXPHALIGNDONE indicator is not high
|
||||||
|
ST_BUFFBYPASS_RX_DONE: begin
|
||||||
|
gtwiz_buffbypass_rx_done_out <= 1'b1;
|
||||||
|
gtwiz_buffbypass_rx_error_out <= ~gtwiz_buffbypass_rx_master_phaligndone_sync_int;
|
||||||
|
sm_buffbypass_rx <= ST_BUFFBYPASS_RX_IDLE;
|
||||||
|
end
|
||||||
|
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,258 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_tx #(
|
||||||
|
|
||||||
|
parameter integer P_BUFFER_BYPASS_MODE = 0,
|
||||||
|
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
|
||||||
|
parameter integer P_MASTER_CHANNEL_POINTER = 0
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
// User interface ports
|
||||||
|
input wire gtwiz_buffbypass_tx_clk_in,
|
||||||
|
input wire gtwiz_buffbypass_tx_reset_in,
|
||||||
|
input wire gtwiz_buffbypass_tx_start_user_in,
|
||||||
|
input wire gtwiz_buffbypass_tx_resetdone_in,
|
||||||
|
output reg gtwiz_buffbypass_tx_done_out = 1'b0,
|
||||||
|
output reg gtwiz_buffbypass_tx_error_out = 1'b0,
|
||||||
|
|
||||||
|
// Transceiver interface ports
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphaligndone_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinitdone_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysresetdone_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncout_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncdone_in,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlyreset_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalign_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphalignen_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlypd_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphinit_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphovrden_out,
|
||||||
|
output reg [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlysreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}},
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlybypass_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyen_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyovrden_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txphdlytstclk_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyhold_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txdlyupdown_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncmode_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncallin_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS-1):0] txsyncin_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Transmitter buffer bypass conditional generation, based on parameter values in module instantiation
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_TX_IDLE = 2'd0;
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET = 2'd1;
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE = 2'd2;
|
||||||
|
localparam [1:0] ST_BUFFBYPASS_TX_DONE = 2'd3;
|
||||||
|
|
||||||
|
generate if (1) begin: gen_gtwiz_buffbypass_tx_main
|
||||||
|
|
||||||
|
// Use auto mode buffer bypass
|
||||||
|
if (P_BUFFER_BYPASS_MODE == 0) begin : gen_auto_mode
|
||||||
|
|
||||||
|
// For single-lane auto mode buffer bypass, perform specified input port tie-offs
|
||||||
|
if (P_TOTAL_NUMBER_OF_CHANNELS == 1) begin : gen_assign_one_chan
|
||||||
|
assign txphdlyreset_out = 1'b0;
|
||||||
|
assign txphalign_out = 1'b0;
|
||||||
|
assign txphalignen_out = 1'b0;
|
||||||
|
assign txphdlypd_out = 1'b0;
|
||||||
|
assign txphinit_out = 1'b0;
|
||||||
|
assign txphovrden_out = 1'b0;
|
||||||
|
assign txdlybypass_out = 1'b0;
|
||||||
|
assign txdlyen_out = 1'b0;
|
||||||
|
assign txdlyovrden_out = 1'b0;
|
||||||
|
assign txphdlytstclk_out = 1'b0;
|
||||||
|
assign txdlyhold_out = 1'b0;
|
||||||
|
assign txdlyupdown_out = 1'b0;
|
||||||
|
assign txsyncmode_out = 1'b1;
|
||||||
|
assign txsyncallin_out = txphaligndone_in;
|
||||||
|
assign txsyncin_out = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
// For multi-lane auto mode buffer bypass, perform specified master and slave lane input port tie-offs
|
||||||
|
else begin : gen_assign_multi_chan
|
||||||
|
assign txphdlyreset_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txphalign_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txphalignen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txphdlypd_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txphinit_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txphovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txdlybypass_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txdlyen_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txdlyovrden_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txphdlytstclk_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txdlyhold_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
assign txdlyupdown_out = {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
|
||||||
|
genvar gi;
|
||||||
|
for (gi = 0; gi < P_TOTAL_NUMBER_OF_CHANNELS; gi = gi + 1) begin : gen_assign_txsyncmode
|
||||||
|
if (gi == P_MASTER_CHANNEL_POINTER)
|
||||||
|
assign txsyncmode_out[gi] = 1'b1;
|
||||||
|
else
|
||||||
|
assign txsyncmode_out[gi] = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign txsyncallin_out = {P_TOTAL_NUMBER_OF_CHANNELS{&txphaligndone_in}};
|
||||||
|
assign txsyncin_out = {P_TOTAL_NUMBER_OF_CHANNELS{txsyncout_in[P_MASTER_CHANNEL_POINTER]}};
|
||||||
|
end
|
||||||
|
|
||||||
|
// Detect the rising edge of the transmitter reset done re-synchronized input. Assign an internal buffer bypass
|
||||||
|
// start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
|
||||||
|
wire gtwiz_buffbypass_tx_resetdone_sync_int;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
|
||||||
|
.clk_in (gtwiz_buffbypass_tx_clk_in),
|
||||||
|
.rst_in (gtwiz_buffbypass_tx_resetdone_in),
|
||||||
|
.rst_out (gtwiz_buffbypass_tx_resetdone_sync_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
reg gtwiz_buffbypass_tx_resetdone_reg = 1'b0;
|
||||||
|
wire gtwiz_buffbypass_tx_start_int;
|
||||||
|
|
||||||
|
always @(posedge gtwiz_buffbypass_tx_clk_in) begin
|
||||||
|
if (gtwiz_buffbypass_tx_reset_in)
|
||||||
|
gtwiz_buffbypass_tx_resetdone_reg <= 1'b0;
|
||||||
|
else
|
||||||
|
gtwiz_buffbypass_tx_resetdone_reg <= gtwiz_buffbypass_tx_resetdone_sync_int;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign gtwiz_buffbypass_tx_start_int = (gtwiz_buffbypass_tx_resetdone_sync_int &&
|
||||||
|
~gtwiz_buffbypass_tx_resetdone_reg) || gtwiz_buffbypass_tx_start_user_in;
|
||||||
|
|
||||||
|
// Synchronize the master channel's buffer bypass completion output (TXSYNCDONE) into the local clock domain
|
||||||
|
// and detect its rising edge for purposes of safe state machine transitions
|
||||||
|
reg gtwiz_buffbypass_tx_master_syncdone_sync_reg = 1'b0;
|
||||||
|
wire gtwiz_buffbypass_tx_master_syncdone_sync_int;
|
||||||
|
wire gtwiz_buffbypass_tx_master_syncdone_sync_re;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_master_syncdone_inst (
|
||||||
|
.clk_in (gtwiz_buffbypass_tx_clk_in),
|
||||||
|
.i_in (txsyncdone_in[P_MASTER_CHANNEL_POINTER]),
|
||||||
|
.o_out (gtwiz_buffbypass_tx_master_syncdone_sync_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge gtwiz_buffbypass_tx_clk_in)
|
||||||
|
gtwiz_buffbypass_tx_master_syncdone_sync_reg <= gtwiz_buffbypass_tx_master_syncdone_sync_int;
|
||||||
|
|
||||||
|
assign gtwiz_buffbypass_tx_master_syncdone_sync_re = gtwiz_buffbypass_tx_master_syncdone_sync_int &&
|
||||||
|
~gtwiz_buffbypass_tx_master_syncdone_sync_reg;
|
||||||
|
|
||||||
|
// Synchronize the master channel's phase alignment completion output (TXPHALIGNDONE) into the local clock domain
|
||||||
|
wire gtwiz_buffbypass_tx_master_phaligndone_sync_int;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_master_phaligndone_inst (
|
||||||
|
.clk_in (gtwiz_buffbypass_tx_clk_in),
|
||||||
|
.i_in (txphaligndone_in[P_MASTER_CHANNEL_POINTER]),
|
||||||
|
.o_out (gtwiz_buffbypass_tx_master_phaligndone_sync_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Implement a simple state machine to perform the transmitter auto mode buffer bypass procedure
|
||||||
|
reg [1:0] sm_buffbypass_tx = ST_BUFFBYPASS_TX_IDLE;
|
||||||
|
|
||||||
|
always @(posedge gtwiz_buffbypass_tx_clk_in) begin
|
||||||
|
if (gtwiz_buffbypass_tx_reset_in) begin
|
||||||
|
gtwiz_buffbypass_tx_done_out <= 1'b0;
|
||||||
|
gtwiz_buffbypass_tx_error_out <= 1'b0;
|
||||||
|
txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_IDLE;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (sm_buffbypass_tx)
|
||||||
|
|
||||||
|
// Upon assertion of the internal buffer bypass start signal, assert TXDLYSRESET output(s)
|
||||||
|
default: begin
|
||||||
|
if (gtwiz_buffbypass_tx_start_int) begin
|
||||||
|
gtwiz_buffbypass_tx_done_out <= 1'b0;
|
||||||
|
gtwiz_buffbypass_tx_error_out <= 1'b0;
|
||||||
|
txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b1}};
|
||||||
|
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// De-assert the TXDLYSRESET output(s)
|
||||||
|
ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET: begin
|
||||||
|
txdlysreset_out <= {P_TOTAL_NUMBER_OF_CHANNELS{1'b0}};
|
||||||
|
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Upon assertion of the synchronized TXSYNCDONE indicator, transition to the final state
|
||||||
|
ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE: begin
|
||||||
|
if (gtwiz_buffbypass_tx_master_syncdone_sync_re)
|
||||||
|
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_DONE;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Assert the buffer bypass procedure done user indicator, and set the procedure error flag if the
|
||||||
|
// synchronized TXPHALIGNDONE indicator is not high
|
||||||
|
ST_BUFFBYPASS_TX_DONE: begin
|
||||||
|
gtwiz_buffbypass_tx_done_out <= 1'b1;
|
||||||
|
gtwiz_buffbypass_tx_error_out <= ~gtwiz_buffbypass_tx_master_phaligndone_sync_int;
|
||||||
|
sm_buffbypass_tx <= ST_BUFFBYPASS_TX_IDLE;
|
||||||
|
end
|
||||||
|
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,766 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtwiz_reset # (
|
||||||
|
|
||||||
|
parameter real P_FREERUN_FREQUENCY = 200,
|
||||||
|
parameter integer P_USE_CPLL_CAL = 0,
|
||||||
|
parameter integer P_TX_PLL_TYPE = 0,
|
||||||
|
parameter integer P_RX_PLL_TYPE = 0,
|
||||||
|
parameter real P_RX_LINE_RATE = 10.3125,
|
||||||
|
parameter [25:0] P_CDR_TIMEOUT_FREERUN_CYC = (37000 * P_FREERUN_FREQUENCY) / P_RX_LINE_RATE
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
// User interface ports
|
||||||
|
input wire gtwiz_reset_clk_freerun_in,
|
||||||
|
input wire gtwiz_reset_all_in,
|
||||||
|
input wire gtwiz_reset_tx_pll_and_datapath_in,
|
||||||
|
input wire gtwiz_reset_tx_datapath_in,
|
||||||
|
input wire gtwiz_reset_rx_pll_and_datapath_in,
|
||||||
|
input wire gtwiz_reset_rx_datapath_in,
|
||||||
|
output wire gtwiz_reset_rx_cdr_stable_out,
|
||||||
|
output wire gtwiz_reset_tx_done_out,
|
||||||
|
output wire gtwiz_reset_rx_done_out,
|
||||||
|
input wire gtwiz_reset_userclk_tx_active_in,
|
||||||
|
input wire gtwiz_reset_userclk_rx_active_in,
|
||||||
|
|
||||||
|
// Transceiver interface ports
|
||||||
|
input wire gtpowergood_in,
|
||||||
|
input wire txusrclk2_in,
|
||||||
|
input wire plllock_tx_in,
|
||||||
|
input wire txresetdone_in,
|
||||||
|
input wire rxusrclk2_in,
|
||||||
|
input wire plllock_rx_in,
|
||||||
|
input wire rxcdrlock_in,
|
||||||
|
input wire rxresetdone_in,
|
||||||
|
output reg pllreset_tx_out = 1'b1,
|
||||||
|
output wire txprogdivreset_out,
|
||||||
|
output reg gttxreset_out = 1'b1,
|
||||||
|
output reg txuserrdy_out = 1'b0,
|
||||||
|
output reg pllreset_rx_out,
|
||||||
|
output reg rxprogdivreset_out = 1'b1,
|
||||||
|
output reg gtrxreset_out = 1'b1,
|
||||||
|
output reg rxuserrdy_out = 1'b0,
|
||||||
|
|
||||||
|
// Tie-offs based on core configuration
|
||||||
|
input wire tx_enabled_tie_in,
|
||||||
|
input wire rx_enabled_tie_in,
|
||||||
|
input wire shared_pll_tie_in
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// "Reset all" state machine
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// The "reset all" state machine responds to the synchronized gtwiz_reset_all_in input by resetting the enabled PLLs
|
||||||
|
// and data paths of those transceiver resources to which the reset helper block is connected. It does so by guiding
|
||||||
|
// the independent transmitter and receiver reset state machines, which are also user-accessible. The path through the
|
||||||
|
// "reset all" state machine is a function of module input tie-offs, which depend on the core configuration.
|
||||||
|
|
||||||
|
// Synchronize the "reset all" input signal into the free-running clock domain
|
||||||
|
wire gtwiz_reset_all_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_all_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (gtwiz_reset_all_in),
|
||||||
|
.rst_out (gtwiz_reset_all_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the transceiver power good indicator
|
||||||
|
wire gtpowergood_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtpowergood_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (gtpowergood_in),
|
||||||
|
.o_out (gtpowergood_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Declare the "reset all" state machine reset timer registers
|
||||||
|
reg sm_reset_all_timer_clr = 1'b1;
|
||||||
|
reg [2:0] sm_reset_all_timer_ctr = 3'd0;
|
||||||
|
reg sm_reset_all_timer_sat = 1'b0;
|
||||||
|
|
||||||
|
// Declare local parameters used to represent both static and variable state machine state values
|
||||||
|
localparam [2:0] ST_RESET_ALL_INIT = 3'd0;
|
||||||
|
localparam [2:0] ST_RESET_ALL_BRANCH = 3'd1;
|
||||||
|
localparam [2:0] ST_RESET_ALL_TX_PLL = 3'd2;
|
||||||
|
localparam [2:0] ST_RESET_ALL_TX_PLL_WAIT = 3'd3;
|
||||||
|
localparam [2:0] ST_RESET_ALL_RX_DP = 3'd4;
|
||||||
|
localparam [2:0] ST_RESET_ALL_RX_PLL = 3'd5;
|
||||||
|
localparam [2:0] ST_RESET_ALL_RX_WAIT = 3'd6;
|
||||||
|
localparam [2:0] ST_RESET_ALL_DONE = 3'd7;
|
||||||
|
reg [2:0] sm_reset_all = ST_RESET_ALL_INIT;
|
||||||
|
|
||||||
|
// Declare relevant internal control and status registers of this and other state machines
|
||||||
|
reg gtwiz_reset_tx_pll_and_datapath_int = 1'b0;
|
||||||
|
reg gtwiz_reset_tx_done_int = 1'b0;
|
||||||
|
reg gtwiz_reset_rx_pll_and_datapath_int = 1'b0;
|
||||||
|
reg gtwiz_reset_rx_datapath_int = 1'b0;
|
||||||
|
reg gtwiz_reset_rx_done_int = 1'b0;
|
||||||
|
|
||||||
|
// Implement the "reset all" state machine control and its outputs as a single sequential process. The state machine
|
||||||
|
// is reset by the synchronized gtwiz_reset_all_sync input.
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
if (gtwiz_reset_all_sync) begin
|
||||||
|
gtwiz_reset_tx_pll_and_datapath_int <= 1'b0;
|
||||||
|
gtwiz_reset_rx_pll_and_datapath_int <= 1'b0;
|
||||||
|
gtwiz_reset_rx_datapath_int <= 1'b0;
|
||||||
|
sm_reset_all_timer_clr <= 1'b1;
|
||||||
|
sm_reset_all <= ST_RESET_ALL_BRANCH;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (sm_reset_all)
|
||||||
|
|
||||||
|
// Upon initial configuration, check or wait for the transceiver power good indicator to be asserted before
|
||||||
|
// proceeding with the sequence automatically
|
||||||
|
ST_RESET_ALL_INIT: begin
|
||||||
|
if (gtpowergood_sync)
|
||||||
|
sm_reset_all <= ST_RESET_ALL_BRANCH;
|
||||||
|
end
|
||||||
|
|
||||||
|
// If the transmitter is enabled, begin by resetting the TX PLL. If the transmitter is disabled, begin by
|
||||||
|
// resetting the RX PLL.
|
||||||
|
ST_RESET_ALL_BRANCH: begin
|
||||||
|
if (tx_enabled_tie_in)
|
||||||
|
sm_reset_all <= ST_RESET_ALL_TX_PLL;
|
||||||
|
else
|
||||||
|
sm_reset_all <= ST_RESET_ALL_RX_PLL;
|
||||||
|
sm_reset_all_timer_clr <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Force the transmitter reset state machine to reset the TX PLL and data path
|
||||||
|
ST_RESET_ALL_TX_PLL: begin
|
||||||
|
gtwiz_reset_tx_pll_and_datapath_int <= 1'b1;
|
||||||
|
sm_reset_all <= ST_RESET_ALL_TX_PLL_WAIT;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Await completion of the TX PLL and data path reset sequence. Then, if the receiver is enabled, continue by
|
||||||
|
// either resetting just the RX data path (if the receiver and transmitter share a PLL) or the RX PLL (if the
|
||||||
|
// receiver and transmitter PLLs are indepdendent). If the receiver is disabled, complete the sequence.
|
||||||
|
ST_RESET_ALL_TX_PLL_WAIT: begin
|
||||||
|
gtwiz_reset_tx_pll_and_datapath_int <= 1'b0;
|
||||||
|
sm_reset_all_timer_clr <= 1'b0;
|
||||||
|
if (gtwiz_reset_tx_done_int && (~sm_reset_all_timer_clr) && sm_reset_all_timer_sat) begin
|
||||||
|
if (rx_enabled_tie_in) begin
|
||||||
|
if (shared_pll_tie_in)
|
||||||
|
sm_reset_all <= ST_RESET_ALL_RX_DP;
|
||||||
|
else
|
||||||
|
sm_reset_all <= ST_RESET_ALL_RX_PLL;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
sm_reset_all <= ST_RESET_ALL_DONE;
|
||||||
|
sm_reset_all_timer_clr <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Force the receiver reset state machine to reset the RX data path
|
||||||
|
ST_RESET_ALL_RX_DP: begin
|
||||||
|
gtwiz_reset_rx_datapath_int <= 1'b1;
|
||||||
|
sm_reset_all <= ST_RESET_ALL_RX_WAIT;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Force the receiver reset state machine to reset the RX PLL and data path
|
||||||
|
ST_RESET_ALL_RX_PLL: begin
|
||||||
|
gtwiz_reset_rx_pll_and_datapath_int <= 1'b1;
|
||||||
|
sm_reset_all <= ST_RESET_ALL_RX_WAIT;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Await completion of whichever RX reset sequence was performed
|
||||||
|
ST_RESET_ALL_RX_WAIT: begin
|
||||||
|
gtwiz_reset_rx_datapath_int <= 1'b0;
|
||||||
|
sm_reset_all_timer_clr <= 1'b0;
|
||||||
|
gtwiz_reset_rx_pll_and_datapath_int <= 1'b0;
|
||||||
|
if (gtwiz_reset_rx_done_int && (~sm_reset_all_timer_clr) && sm_reset_all_timer_sat) begin
|
||||||
|
sm_reset_all <= ST_RESET_ALL_DONE;
|
||||||
|
sm_reset_all_timer_clr <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Generate a small "reset all" state machine reset timer, used to stall certain states to guarantee that their
|
||||||
|
// synchronized input values are being used at the appropriate time
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
if (sm_reset_all_timer_clr) begin
|
||||||
|
sm_reset_all_timer_ctr <= 3'd0;
|
||||||
|
sm_reset_all_timer_sat <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (sm_reset_all_timer_ctr != 3'd7)
|
||||||
|
sm_reset_all_timer_ctr <= sm_reset_all_timer_ctr + 3'd1;
|
||||||
|
else
|
||||||
|
sm_reset_all_timer_sat <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Transmitter reset state machine
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// The transmitter reset state machine responds to various synchronized inputs by resetting enabled transmitter-
|
||||||
|
// related transceiver resources to which the reset helper block is connected. Various entry points to the sequential
|
||||||
|
// reset sequence are available.
|
||||||
|
|
||||||
|
// Synchronize the OR of all user input and internal TX reset signals for use in resetting the TX reset state machine
|
||||||
|
wire gtwiz_reset_tx_any;
|
||||||
|
wire gtwiz_reset_tx_any_sync;
|
||||||
|
assign gtwiz_reset_tx_any = gtwiz_reset_tx_pll_and_datapath_in ||
|
||||||
|
gtwiz_reset_tx_pll_and_datapath_int ||
|
||||||
|
gtwiz_reset_tx_datapath_in;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_any_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (gtwiz_reset_tx_any),
|
||||||
|
.rst_out (gtwiz_reset_tx_any_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the OR of the user input and internal TX PLL and data path reset signals
|
||||||
|
wire gtwiz_reset_tx_pll_and_datapath_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (gtwiz_reset_tx_pll_and_datapath_in || gtwiz_reset_tx_pll_and_datapath_int),
|
||||||
|
.rst_out (gtwiz_reset_tx_pll_and_datapath_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Use another synchronizer to delay the above signal for purposes of its detection following reset
|
||||||
|
wire gtwiz_reset_tx_pll_and_datapath_dly;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (gtwiz_reset_tx_pll_and_datapath_sync),
|
||||||
|
.o_out (gtwiz_reset_tx_pll_and_datapath_dly)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the TX data path reset user input
|
||||||
|
wire gtwiz_reset_tx_datapath_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_datapath_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (gtwiz_reset_tx_datapath_in),
|
||||||
|
.rst_out (gtwiz_reset_tx_datapath_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Use another synchronizer to delay the above signal for purposes of its detection following reset
|
||||||
|
wire gtwiz_reset_tx_datapath_dly;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (gtwiz_reset_tx_datapath_sync),
|
||||||
|
.o_out (gtwiz_reset_tx_datapath_dly)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the TX user clock active indicator
|
||||||
|
wire gtwiz_reset_userclk_tx_active_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_tx_active_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (gtwiz_reset_userclk_tx_active_in),
|
||||||
|
.o_out (gtwiz_reset_userclk_tx_active_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the TX PLL lock indicator
|
||||||
|
wire plllock_tx_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_plllock_tx_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (plllock_tx_in),
|
||||||
|
.o_out (plllock_tx_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Declare the TX state machine reset timer registers
|
||||||
|
reg sm_reset_tx_timer_clr = 1'b1;
|
||||||
|
reg [2:0] sm_reset_tx_timer_ctr = 3'd0;
|
||||||
|
reg sm_reset_tx_timer_sat = 1'b0;
|
||||||
|
|
||||||
|
// Declare the TX state machine PLL reset timer registers
|
||||||
|
localparam [9:0] P_TX_PLL_RESET_FREERUN_CYC = (P_TX_PLL_TYPE == 2) ?
|
||||||
|
(2 * P_FREERUN_FREQUENCY) + 2 : 7;
|
||||||
|
reg sm_reset_tx_pll_timer_clr = 1'b1;
|
||||||
|
reg [9:0] sm_reset_tx_pll_timer_ctr = 10'd0;
|
||||||
|
reg sm_reset_tx_pll_timer_sat = 1'b0;
|
||||||
|
wire [9:0] p_tx_pll_reset_freerun_cyc_int = P_TX_PLL_RESET_FREERUN_CYC;
|
||||||
|
|
||||||
|
// Declare local parameters for TX reset state machine state values
|
||||||
|
localparam [2:0] ST_RESET_TX_BRANCH = 3'd0;
|
||||||
|
localparam [2:0] ST_RESET_TX_PLL = 3'd1;
|
||||||
|
localparam [2:0] ST_RESET_TX_DATAPATH = 3'd2;
|
||||||
|
localparam [2:0] ST_RESET_TX_WAIT_LOCK = 3'd3;
|
||||||
|
localparam [2:0] ST_RESET_TX_WAIT_USERRDY = 3'd4;
|
||||||
|
localparam [2:0] ST_RESET_TX_WAIT_RESETDONE = 3'd5;
|
||||||
|
localparam [2:0] ST_RESET_TX_IDLE = 3'd6;
|
||||||
|
reg [2:0] sm_reset_tx = ST_RESET_TX_BRANCH;
|
||||||
|
|
||||||
|
// Implementation of transmitter reset state machine synchronous process
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
|
||||||
|
// The state machine is synchronously reset by the synchronized OR of all user input and internal TX reset signals
|
||||||
|
if (gtwiz_reset_tx_any_sync) begin
|
||||||
|
gtwiz_reset_tx_done_int <= 1'b0;
|
||||||
|
sm_reset_tx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx_pll_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx <= ST_RESET_TX_BRANCH;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (sm_reset_tx)
|
||||||
|
|
||||||
|
// Once released from reset, branch to the reset control state indicated by the highest-priority synchronized
|
||||||
|
// signal (which remains asserted due to its long synchronizer chain)
|
||||||
|
ST_RESET_TX_BRANCH: begin
|
||||||
|
if (gtwiz_reset_tx_pll_and_datapath_dly)
|
||||||
|
sm_reset_tx <= ST_RESET_TX_PLL;
|
||||||
|
else if (gtwiz_reset_tx_datapath_dly)
|
||||||
|
sm_reset_tx <= ST_RESET_TX_DATAPATH;
|
||||||
|
sm_reset_tx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx_pll_timer_clr <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Assert the TX PLL and TX data path reset outputs
|
||||||
|
ST_RESET_TX_PLL: begin
|
||||||
|
pllreset_tx_out <= 1'b1;
|
||||||
|
gttxreset_out <= 1'b1;
|
||||||
|
txuserrdy_out <= 1'b0;
|
||||||
|
sm_reset_tx_pll_timer_clr <= 1'b0;
|
||||||
|
if ((~sm_reset_tx_pll_timer_clr) && sm_reset_tx_pll_timer_sat) begin
|
||||||
|
sm_reset_tx_pll_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx <= ST_RESET_TX_WAIT_LOCK;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Assert the TX data path reset output
|
||||||
|
ST_RESET_TX_DATAPATH: begin
|
||||||
|
gttxreset_out <= 1'b1;
|
||||||
|
txuserrdy_out <= 1'b0;
|
||||||
|
sm_reset_tx_timer_clr <= 1'b0;
|
||||||
|
if ((~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
|
||||||
|
sm_reset_tx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx <= ST_RESET_TX_WAIT_LOCK;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// De-assert the TX PLL reset output, and await the TX PLL lock indicator before de-asserting the TX data path
|
||||||
|
// reset output
|
||||||
|
ST_RESET_TX_WAIT_LOCK: begin
|
||||||
|
pllreset_tx_out <= 1'b0;
|
||||||
|
sm_reset_tx_timer_clr <= 1'b0;
|
||||||
|
if (plllock_tx_sync && (~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
|
||||||
|
gttxreset_out <= 1'b0;
|
||||||
|
sm_reset_tx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx <= ST_RESET_TX_WAIT_USERRDY;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Await the TX user clock active indicator from the TX user clocking helper block before asserting the TX user
|
||||||
|
// ready output
|
||||||
|
ST_RESET_TX_WAIT_USERRDY: begin
|
||||||
|
sm_reset_tx_timer_clr <= 1'b0;
|
||||||
|
if (gtwiz_reset_userclk_tx_active_sync && (~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
|
||||||
|
txuserrdy_out <= 1'b1;
|
||||||
|
sm_reset_tx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx <= ST_RESET_TX_WAIT_RESETDONE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Await the TX reset done indicator before asserting the reset helper block TX reset done user output
|
||||||
|
ST_RESET_TX_WAIT_RESETDONE: begin
|
||||||
|
sm_reset_tx_timer_clr <= 1'b0;
|
||||||
|
if (txresetdone_in && (~sm_reset_tx_timer_clr) && sm_reset_tx_timer_sat) begin
|
||||||
|
gtwiz_reset_tx_done_int <= 1'b1;
|
||||||
|
sm_reset_tx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_tx <= ST_RESET_TX_IDLE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// While idle, de-assert the reset helper block TX reset done user output if PLL lock is lost, signaling the
|
||||||
|
// need for user intervention
|
||||||
|
ST_RESET_TX_IDLE: begin
|
||||||
|
if (!plllock_tx_sync)
|
||||||
|
gtwiz_reset_tx_done_int <= 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Encountering the default case indicates a state register error, so de-assert the reset helper block TX
|
||||||
|
// reset done user output, signaling the need for user intervention
|
||||||
|
default: begin
|
||||||
|
gtwiz_reset_tx_done_int <= 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Generate a small TX state machine reset timer, used to stall certain states to guarantee that their synchronized
|
||||||
|
// input values are being used at the appropriate time
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
if (sm_reset_tx_timer_clr) begin
|
||||||
|
sm_reset_tx_timer_ctr <= 3'd0;
|
||||||
|
sm_reset_tx_timer_sat <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (sm_reset_tx_timer_ctr != 3'd7)
|
||||||
|
sm_reset_tx_timer_ctr <= sm_reset_tx_timer_ctr + 3'd1;
|
||||||
|
else
|
||||||
|
sm_reset_tx_timer_sat <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Generate an TX PLL reset timer, used to indicate when the specified minimum TX PLL reset duration has expired. This
|
||||||
|
// is used by the TX state machine to proceed beyond the ST_RESET_TX_PLL wait state.
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
if (sm_reset_tx_pll_timer_clr) begin
|
||||||
|
sm_reset_tx_pll_timer_ctr <= 10'd0;
|
||||||
|
sm_reset_tx_pll_timer_sat <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (sm_reset_tx_pll_timer_ctr != p_tx_pll_reset_freerun_cyc_int)
|
||||||
|
sm_reset_tx_pll_timer_ctr <= sm_reset_tx_pll_timer_ctr + 10'd1;
|
||||||
|
else
|
||||||
|
sm_reset_tx_pll_timer_sat <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Hold the TX programmable divider in reset until the TX PLL has locked
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_txprogdivreset_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (~plllock_tx_in),
|
||||||
|
.rst_out (txprogdivreset_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the reset helper block TX reset done user output into the TXUSRCLK2 domain for user consumption
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_tx_done_inst (
|
||||||
|
.clk_in (txusrclk2_in),
|
||||||
|
.rst_in (gtwiz_reset_tx_done_int),
|
||||||
|
.rst_out (gtwiz_reset_tx_done_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Receiver reset state machine
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// The receiver reset state machine responds to various synchronized inputs by resetting enabled receiver-
|
||||||
|
// related transceiver resources to which the reset helper block is connected. Various entry points to the sequential
|
||||||
|
// reset sequence are available.
|
||||||
|
|
||||||
|
// Initialize (for both synthesis and simulation) the RX PLL reset output flip-flop to 0 if the TX and RX PLLs are
|
||||||
|
// shared upon device configuration, so as to not block TX PLL reset; or to 1 if the PLLs are independent, for
|
||||||
|
// consistency with TX PLL initialization
|
||||||
|
initial begin
|
||||||
|
if (P_TX_PLL_TYPE == P_RX_PLL_TYPE)
|
||||||
|
pllreset_rx_out = 1'b0;
|
||||||
|
else
|
||||||
|
pllreset_rx_out = 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Synchronize the OR of all user input and internal RX reset signals for use in resetting the RX reset state machine
|
||||||
|
wire gtwiz_reset_rx_any;
|
||||||
|
wire gtwiz_reset_rx_any_sync;
|
||||||
|
assign gtwiz_reset_rx_any = gtwiz_reset_rx_pll_and_datapath_in ||
|
||||||
|
gtwiz_reset_rx_pll_and_datapath_int ||
|
||||||
|
gtwiz_reset_rx_datapath_in ||
|
||||||
|
gtwiz_reset_rx_datapath_int;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_any_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (gtwiz_reset_rx_any),
|
||||||
|
.rst_out (gtwiz_reset_rx_any_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the OR of the user input and internal RX PLL and data path reset signals
|
||||||
|
wire gtwiz_reset_rx_pll_and_datapath_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (gtwiz_reset_rx_pll_and_datapath_in || gtwiz_reset_rx_pll_and_datapath_int),
|
||||||
|
.rst_out (gtwiz_reset_rx_pll_and_datapath_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Use another synchronizer to delay the above signal for purposes of its detection following reset
|
||||||
|
wire gtwiz_reset_rx_pll_and_datapath_dly;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (gtwiz_reset_rx_pll_and_datapath_sync),
|
||||||
|
.o_out (gtwiz_reset_rx_pll_and_datapath_dly)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the RX data path reset user input
|
||||||
|
wire gtwiz_reset_rx_datapath_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_datapath_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.rst_in (gtwiz_reset_rx_datapath_in || gtwiz_reset_rx_datapath_int),
|
||||||
|
.rst_out (gtwiz_reset_rx_datapath_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Use another synchronizer to delay the above signal for purposes of its detection following reset
|
||||||
|
wire gtwiz_reset_rx_datapath_dly;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (gtwiz_reset_rx_datapath_sync),
|
||||||
|
.o_out (gtwiz_reset_rx_datapath_dly)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the RX user clock active indicator
|
||||||
|
wire gtwiz_reset_userclk_rx_active_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (gtwiz_reset_userclk_rx_active_in),
|
||||||
|
.o_out (gtwiz_reset_userclk_rx_active_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the RX PLL lock indicator
|
||||||
|
wire plllock_rx_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_plllock_rx_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (plllock_rx_in),
|
||||||
|
.o_out (plllock_rx_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Synchronize the RX CDR lock indicator
|
||||||
|
wire rxcdrlock_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_rxcdrlock_inst (
|
||||||
|
.clk_in (gtwiz_reset_clk_freerun_in),
|
||||||
|
.i_in (rxcdrlock_in),
|
||||||
|
.o_out (rxcdrlock_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Declare the RX state machine reset timer registers
|
||||||
|
reg sm_reset_rx_timer_clr = 1'b1;
|
||||||
|
reg [2:0] sm_reset_rx_timer_ctr = 3'd0;
|
||||||
|
reg sm_reset_rx_timer_sat = 1'b0;
|
||||||
|
|
||||||
|
// Declare the RX state machine PLL reset timer registers
|
||||||
|
localparam [9:0] P_RX_PLL_RESET_FREERUN_CYC = (P_RX_PLL_TYPE == 2) ?
|
||||||
|
(2 * P_FREERUN_FREQUENCY) + 2 : 7;
|
||||||
|
reg sm_reset_rx_pll_timer_clr = 1'b1;
|
||||||
|
reg [9:0] sm_reset_rx_pll_timer_ctr = 10'd0;
|
||||||
|
reg sm_reset_rx_pll_timer_sat = 1'b0;
|
||||||
|
wire [9:0] p_rx_pll_reset_freerun_cyc_int = P_RX_PLL_RESET_FREERUN_CYC;
|
||||||
|
|
||||||
|
// Declare the RX state machine CDR lock timeout counter
|
||||||
|
reg sm_reset_rx_cdr_to_clr = 1'b1;
|
||||||
|
reg [25:0] sm_reset_rx_cdr_to_ctr = 26'd0;
|
||||||
|
reg sm_reset_rx_cdr_to_sat = 1'b0;
|
||||||
|
wire [25:0] p_cdr_timeout_freerun_cyc_int = P_CDR_TIMEOUT_FREERUN_CYC;
|
||||||
|
|
||||||
|
// Declare local parameters for RX reset state machine state values
|
||||||
|
localparam [2:0] ST_RESET_RX_BRANCH = 3'd0;
|
||||||
|
localparam [2:0] ST_RESET_RX_PLL = 3'd1;
|
||||||
|
localparam [2:0] ST_RESET_RX_DATAPATH = 3'd2;
|
||||||
|
localparam [2:0] ST_RESET_RX_WAIT_LOCK = 3'd3;
|
||||||
|
localparam [2:0] ST_RESET_RX_WAIT_CDR = 3'd4;
|
||||||
|
localparam [2:0] ST_RESET_RX_WAIT_USERRDY = 3'd5;
|
||||||
|
localparam [2:0] ST_RESET_RX_WAIT_RESETDONE = 3'd6;
|
||||||
|
localparam [2:0] ST_RESET_RX_IDLE = 3'd7;
|
||||||
|
reg [2:0] sm_reset_rx = ST_RESET_RX_BRANCH;
|
||||||
|
|
||||||
|
// Implementation of receiver reset state machine synchronous process
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
|
||||||
|
// The state machine is synchronously reset by the synchronized OR of all user input and internal RX reset signals
|
||||||
|
if (gtwiz_reset_rx_any_sync) begin
|
||||||
|
gtwiz_reset_rx_done_int <= 1'b0;
|
||||||
|
sm_reset_rx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx_pll_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx_cdr_to_clr <= 1'b1;
|
||||||
|
sm_reset_rx <= ST_RESET_RX_BRANCH;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (sm_reset_rx)
|
||||||
|
|
||||||
|
// Once released from reset, branch to the reset control state indicated by the highest-priority synchronized
|
||||||
|
// signal (which remains asserted due to its long synchronizer chain)
|
||||||
|
ST_RESET_RX_BRANCH: begin
|
||||||
|
if (gtwiz_reset_rx_pll_and_datapath_dly)
|
||||||
|
sm_reset_rx <= ST_RESET_RX_PLL;
|
||||||
|
else if (gtwiz_reset_rx_datapath_dly)
|
||||||
|
sm_reset_rx <= ST_RESET_RX_DATAPATH;
|
||||||
|
sm_reset_rx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx_pll_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx_cdr_to_clr <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Assert the RX PLL, RX programmable divider, and RX data path reset outputs
|
||||||
|
ST_RESET_RX_PLL: begin
|
||||||
|
pllreset_rx_out <= 1'b1;
|
||||||
|
rxprogdivreset_out <= 1'b1;
|
||||||
|
gtrxreset_out <= 1'b1;
|
||||||
|
rxuserrdy_out <= 1'b0;
|
||||||
|
sm_reset_rx_pll_timer_clr <= 1'b0;
|
||||||
|
if ((~sm_reset_rx_pll_timer_clr) && sm_reset_rx_pll_timer_sat) begin
|
||||||
|
sm_reset_rx_pll_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx <= ST_RESET_RX_WAIT_LOCK;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Assert the RX data path and RX programmable divider reset outputs
|
||||||
|
ST_RESET_RX_DATAPATH: begin
|
||||||
|
rxprogdivreset_out <= 1'b1;
|
||||||
|
gtrxreset_out <= 1'b1;
|
||||||
|
rxuserrdy_out <= 1'b0;
|
||||||
|
sm_reset_rx_timer_clr <= 1'b0;
|
||||||
|
if ((~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat) begin
|
||||||
|
sm_reset_rx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx <= ST_RESET_RX_WAIT_LOCK;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// De-assert the RX PLL reset output, and await the RX PLL lock indicator before de-asserting the RX data path
|
||||||
|
// reset output
|
||||||
|
ST_RESET_RX_WAIT_LOCK: begin
|
||||||
|
pllreset_rx_out <= 1'b0;
|
||||||
|
sm_reset_rx_timer_clr <= 1'b0;
|
||||||
|
if (plllock_rx_sync && (~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat) begin
|
||||||
|
gtrxreset_out <= 1'b0;
|
||||||
|
sm_reset_rx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx_cdr_to_clr <= 1'b0;
|
||||||
|
sm_reset_rx <= ST_RESET_RX_WAIT_CDR;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Await an indication of CDR stability (either the direct transceiver RXCDRLOCK output, or expiration of the
|
||||||
|
// specified maximum CDR locking time, whichever occurs first) before removing the RX programmable divider reset
|
||||||
|
// and proceeding
|
||||||
|
ST_RESET_RX_WAIT_CDR: begin
|
||||||
|
if (rxcdrlock_sync || sm_reset_rx_cdr_to_sat) begin
|
||||||
|
rxprogdivreset_out <= 1'b0;
|
||||||
|
sm_reset_rx_cdr_to_clr <= 1'b1;
|
||||||
|
sm_reset_rx <= ST_RESET_RX_WAIT_USERRDY;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Await the RX user clock active indicator from the RX user clocking helper block before asserting the RX user
|
||||||
|
// ready output
|
||||||
|
ST_RESET_RX_WAIT_USERRDY: begin
|
||||||
|
sm_reset_rx_timer_clr <= 1'b0;
|
||||||
|
if (gtwiz_reset_userclk_rx_active_sync && (~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat) begin
|
||||||
|
rxuserrdy_out <= 1'b1;
|
||||||
|
sm_reset_rx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx <= ST_RESET_RX_WAIT_RESETDONE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Await the RX reset done indicator before asserting the reset helper block RX reset done user output
|
||||||
|
ST_RESET_RX_WAIT_RESETDONE: begin
|
||||||
|
sm_reset_rx_timer_clr <= 1'b0;
|
||||||
|
if (rxresetdone_in && (~sm_reset_rx_timer_clr) && sm_reset_rx_timer_sat)
|
||||||
|
begin
|
||||||
|
gtwiz_reset_rx_done_int <= 1'b1;
|
||||||
|
sm_reset_rx_timer_clr <= 1'b1;
|
||||||
|
sm_reset_rx <= ST_RESET_RX_IDLE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// While idle, de-assert the reset helper block RX reset done user output if PLL lock is lost, signaling the
|
||||||
|
// need for user intervention
|
||||||
|
ST_RESET_RX_IDLE: begin
|
||||||
|
if (!plllock_rx_sync)
|
||||||
|
gtwiz_reset_rx_done_int <= 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Generate a small RX state machine reset timer, used to stall certain states to guarantee that their synchronized
|
||||||
|
// input values are being used at the appropriate time
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
if (sm_reset_rx_timer_clr) begin
|
||||||
|
sm_reset_rx_timer_ctr <= 3'd0;
|
||||||
|
sm_reset_rx_timer_sat <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (sm_reset_rx_timer_ctr != 3'd7)
|
||||||
|
sm_reset_rx_timer_ctr <= sm_reset_rx_timer_ctr + 3'd1;
|
||||||
|
else
|
||||||
|
sm_reset_rx_timer_sat <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Generate an RX PLL reset timer, used to indicate when the specified minimum RX PLL reset duration has expired. This
|
||||||
|
// is used by the RX state machine to proceed beyond the ST_RESET_RX_PLL wait state.
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
if (sm_reset_rx_pll_timer_clr) begin
|
||||||
|
sm_reset_rx_pll_timer_ctr <= 10'd0;
|
||||||
|
sm_reset_rx_pll_timer_sat <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (sm_reset_rx_pll_timer_ctr != p_rx_pll_reset_freerun_cyc_int)
|
||||||
|
sm_reset_rx_pll_timer_ctr <= sm_reset_rx_pll_timer_ctr + 10'd1;
|
||||||
|
else
|
||||||
|
sm_reset_rx_pll_timer_sat <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Generate a CDR lock timeout timer, used to indicate when the specified maximum CDR locking time has expired. This
|
||||||
|
// is used by the RX state machine to proceed beyond the ST_RESET_RX_WAIT_CDR wait state in the event that the
|
||||||
|
// transceiver RXCDRLOCK output does not assert within that time period.
|
||||||
|
always @(posedge gtwiz_reset_clk_freerun_in) begin
|
||||||
|
if (sm_reset_rx_cdr_to_clr) begin
|
||||||
|
sm_reset_rx_cdr_to_ctr <= 26'd0;
|
||||||
|
sm_reset_rx_cdr_to_sat <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (sm_reset_rx_cdr_to_ctr != p_cdr_timeout_freerun_cyc_int)
|
||||||
|
sm_reset_rx_cdr_to_ctr <= sm_reset_rx_cdr_to_ctr + 26'd1;
|
||||||
|
else
|
||||||
|
sm_reset_rx_cdr_to_sat <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Assign the RX CDR stable user indicator to the transceiver RXCDRLOCK output
|
||||||
|
assign gtwiz_reset_rx_cdr_stable_out = rxcdrlock_sync;
|
||||||
|
|
||||||
|
// Synchronize the reset helper block RX reset done user output into the RXUSRCLK2 domain for user consumption
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_rx_done_inst (
|
||||||
|
.clk_in (rxusrclk2_in),
|
||||||
|
.rst_in (gtwiz_reset_rx_done_int),
|
||||||
|
.rst_out (gtwiz_reset_rx_done_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,140 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtwiz_userclk_rx #(
|
||||||
|
|
||||||
|
parameter integer P_CONTENTS = 0,
|
||||||
|
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
|
||||||
|
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
input wire gtwiz_userclk_rx_srcclk_in,
|
||||||
|
input wire gtwiz_userclk_rx_reset_in,
|
||||||
|
output wire gtwiz_userclk_rx_usrclk_out,
|
||||||
|
output wire gtwiz_userclk_rx_usrclk2_out,
|
||||||
|
output wire gtwiz_userclk_rx_active_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Local parameters
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
|
||||||
|
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
|
||||||
|
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
|
||||||
|
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
|
||||||
|
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Receiver user clocking network conditional generation, based on parameter values in module instantiation
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
generate if (1) begin: gen_gtwiz_userclk_rx_main
|
||||||
|
|
||||||
|
// Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio
|
||||||
|
if (P_CONTENTS == 0) begin
|
||||||
|
|
||||||
|
// Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK
|
||||||
|
// frequency ratio
|
||||||
|
BUFG_GT bufg_gt_usrclk_inst (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (gtwiz_userclk_rx_reset_in),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (P_USRCLK_DIV),
|
||||||
|
.I (gtwiz_userclk_rx_srcclk_in),
|
||||||
|
.O (gtwiz_userclk_rx_usrclk_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
// If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
|
||||||
|
// RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency.
|
||||||
|
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
|
||||||
|
assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out;
|
||||||
|
else begin
|
||||||
|
BUFG_GT bufg_gt_usrclk2_inst (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (gtwiz_userclk_rx_reset_in),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (P_USRCLK2_DIV),
|
||||||
|
.I (gtwiz_userclk_rx_srcclk_in),
|
||||||
|
.O (gtwiz_userclk_rx_usrclk2_out)
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0;
|
||||||
|
always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin
|
||||||
|
if (gtwiz_userclk_rx_reset_in) begin
|
||||||
|
gtwiz_userclk_rx_active_meta <= 1'b0;
|
||||||
|
gtwiz_userclk_rx_active_sync <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
gtwiz_userclk_rx_active_meta <= 1'b1;
|
||||||
|
gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,140 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtwiz_userclk_tx #(
|
||||||
|
|
||||||
|
parameter integer P_CONTENTS = 0,
|
||||||
|
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
|
||||||
|
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
input wire gtwiz_userclk_tx_srcclk_in,
|
||||||
|
input wire gtwiz_userclk_tx_reset_in,
|
||||||
|
output wire gtwiz_userclk_tx_usrclk_out,
|
||||||
|
output wire gtwiz_userclk_tx_usrclk2_out,
|
||||||
|
output wire gtwiz_userclk_tx_active_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Local parameters
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
|
||||||
|
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
|
||||||
|
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
|
||||||
|
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
|
||||||
|
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Transmitter user clocking network conditional generation, based on parameter values in module instantiation
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
generate if (1) begin: gen_gtwiz_userclk_tx_main
|
||||||
|
|
||||||
|
// Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
|
||||||
|
if (P_CONTENTS == 0) begin
|
||||||
|
|
||||||
|
// Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
|
||||||
|
// frequency ratio
|
||||||
|
BUFG_GT bufg_gt_usrclk_inst (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (gtwiz_userclk_tx_reset_in),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (P_USRCLK_DIV),
|
||||||
|
.I (gtwiz_userclk_tx_srcclk_in),
|
||||||
|
.O (gtwiz_userclk_tx_usrclk_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
// If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
|
||||||
|
// TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
|
||||||
|
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
|
||||||
|
assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
|
||||||
|
else begin
|
||||||
|
BUFG_GT bufg_gt_usrclk2_inst (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (gtwiz_userclk_tx_reset_in),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (P_USRCLK2_DIV),
|
||||||
|
.I (gtwiz_userclk_tx_srcclk_in),
|
||||||
|
.O (gtwiz_userclk_tx_usrclk2_out)
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_meta = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_sync = 1'b0;
|
||||||
|
always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
|
||||||
|
if (gtwiz_userclk_tx_reset_in) begin
|
||||||
|
gtwiz_userclk_tx_active_meta <= 1'b0;
|
||||||
|
gtwiz_userclk_tx_active_sync <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
gtwiz_userclk_tx_active_meta <= 1'b1;
|
||||||
|
gtwiz_userclk_tx_active_sync <= gtwiz_userclk_tx_active_meta;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_sync;
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,219 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtwiz_userdata_rx #(
|
||||||
|
|
||||||
|
parameter integer P_RX_USER_DATA_WIDTH = 32,
|
||||||
|
parameter integer P_RX_DATA_DECODING = 0,
|
||||||
|
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS*128)-1:0] rxdata_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0] rxctrl0_in,
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0] rxctrl1_in,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS*P_RX_USER_DATA_WIDTH)-1:0] gtwiz_userdata_rx_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Receiver user data width sizing conditional generation, based on parameter values in module instantiation
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
generate if (1) begin : gen_gtwiz_userdata_rx_main
|
||||||
|
genvar ch_idx;
|
||||||
|
|
||||||
|
// If receiver data decoding is either not raw mode, or is raw mode but user data width is not modulus 10, then
|
||||||
|
// simply assign the user-facing data vector with the active data bits from the transceiver-facing RXDATA vector.
|
||||||
|
if ((P_RX_DATA_DECODING != 0) ||
|
||||||
|
((P_RX_DATA_DECODING == 0) && (P_RX_USER_DATA_WIDTH % 10 != 0))) begin : gen_rxdata
|
||||||
|
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_assign
|
||||||
|
assign gtwiz_userdata_rx_out[(P_RX_USER_DATA_WIDTH*ch_idx)+P_RX_USER_DATA_WIDTH-1:
|
||||||
|
(P_RX_USER_DATA_WIDTH*ch_idx)] =
|
||||||
|
rxdata_in[(128*ch_idx)+P_RX_USER_DATA_WIDTH-1:(128*ch_idx)];
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
// If receiver data decoding is raw mode and user data width is modulus 10, then assign the user-facing data vector
|
||||||
|
// with the specified combination of transceiver-facing RXDATA, RXCTRL0, and RXCTRL1 vectors. The interleaving of
|
||||||
|
// these vectors is always in a repeating 8-1-1 bit pattern, scaling with the user data width size.
|
||||||
|
else begin : gen_rxdata_rxctrl
|
||||||
|
|
||||||
|
case (P_RX_USER_DATA_WIDTH)
|
||||||
|
20:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width20
|
||||||
|
assign gtwiz_userdata_rx_out [(ch_idx*20)+19:(ch_idx*20)] =
|
||||||
|
{rxctrl1_in[(ch_idx* 16)+1],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+1],
|
||||||
|
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
|
||||||
|
rxctrl1_in[(ch_idx* 16)],
|
||||||
|
rxctrl0_in[(ch_idx* 16)],
|
||||||
|
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
|
||||||
|
end
|
||||||
|
|
||||||
|
40:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width40
|
||||||
|
assign gtwiz_userdata_rx_out [(ch_idx*40)+39:(ch_idx*40)] =
|
||||||
|
{rxctrl1_in[(ch_idx* 16)+3],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+3],
|
||||||
|
rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+2],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+2],
|
||||||
|
rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+1],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+1],
|
||||||
|
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
|
||||||
|
rxctrl1_in[(ch_idx* 16)],
|
||||||
|
rxctrl0_in[(ch_idx* 16)],
|
||||||
|
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
|
||||||
|
end
|
||||||
|
|
||||||
|
80:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width80
|
||||||
|
assign gtwiz_userdata_rx_out [(ch_idx*80)+79:(ch_idx*80)] =
|
||||||
|
{rxctrl1_in[(ch_idx* 16)+7],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+7],
|
||||||
|
rxdata_in [(ch_idx*128)+63:(ch_idx*128)+56],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+6],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+6],
|
||||||
|
rxdata_in [(ch_idx*128)+55:(ch_idx*128)+48],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+5],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+5],
|
||||||
|
rxdata_in [(ch_idx*128)+47:(ch_idx*128)+40],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+4],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+4],
|
||||||
|
rxdata_in [(ch_idx*128)+39:(ch_idx*128)+32],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+3],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+3],
|
||||||
|
rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+2],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+2],
|
||||||
|
rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+1],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+1],
|
||||||
|
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
|
||||||
|
rxctrl1_in[(ch_idx* 16)],
|
||||||
|
rxctrl0_in[(ch_idx* 16)],
|
||||||
|
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
|
||||||
|
end
|
||||||
|
|
||||||
|
160:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width160
|
||||||
|
assign gtwiz_userdata_rx_out [(ch_idx*160)+159:(ch_idx*160)] =
|
||||||
|
{rxctrl1_in[(ch_idx* 16)+15],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+15],
|
||||||
|
rxdata_in [(ch_idx*128)+127:(ch_idx*128)+120],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+14],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+14],
|
||||||
|
rxdata_in [(ch_idx*128)+119:(ch_idx*128)+112],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+13],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+13],
|
||||||
|
rxdata_in [(ch_idx*128)+111:(ch_idx*128)+104],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+12],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+12],
|
||||||
|
rxdata_in [(ch_idx*128)+103:(ch_idx*128)+96],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+11],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+11],
|
||||||
|
rxdata_in [(ch_idx*128)+95:(ch_idx*128)+88],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+10],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+10],
|
||||||
|
rxdata_in [(ch_idx*128)+87:(ch_idx*128)+80],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+9],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+9],
|
||||||
|
rxdata_in [(ch_idx*128)+79:(ch_idx*128)+72],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+8],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+8],
|
||||||
|
rxdata_in [(ch_idx*128)+71:(ch_idx*128)+64],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+7],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+7],
|
||||||
|
rxdata_in [(ch_idx*128)+63:(ch_idx*128)+56],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+6],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+6],
|
||||||
|
rxdata_in [(ch_idx*128)+55:(ch_idx*128)+48],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+5],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+5],
|
||||||
|
rxdata_in [(ch_idx*128)+47:(ch_idx*128)+40],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+4],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+4],
|
||||||
|
rxdata_in [(ch_idx*128)+39:(ch_idx*128)+32],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+3],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+3],
|
||||||
|
rxdata_in [(ch_idx*128)+31:(ch_idx*128)+24],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+2],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+2],
|
||||||
|
rxdata_in [(ch_idx*128)+23:(ch_idx*128)+16],
|
||||||
|
rxctrl1_in[(ch_idx* 16)+1],
|
||||||
|
rxctrl0_in[(ch_idx* 16)+1],
|
||||||
|
rxdata_in [(ch_idx*128)+15:(ch_idx*128)+8],
|
||||||
|
rxctrl1_in[(ch_idx* 16)],
|
||||||
|
rxctrl0_in[(ch_idx* 16)],
|
||||||
|
rxdata_in [(ch_idx*128)+7:ch_idx*128]};
|
||||||
|
end
|
||||||
|
|
||||||
|
default:
|
||||||
|
begin : gen_default
|
||||||
|
// The default case is a configuration error scenario should never be exercised
|
||||||
|
assign gtwiz_userdata_rx_out = {P_TOTAL_NUMBER_OF_CHANNELS*P_RX_USER_DATA_WIDTH{1'b1}};
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,249 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtwiz_userdata_tx #(
|
||||||
|
|
||||||
|
parameter integer P_TX_USER_DATA_WIDTH = 32,
|
||||||
|
parameter integer P_TX_DATA_ENCODING = 0,
|
||||||
|
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
input wire [(P_TOTAL_NUMBER_OF_CHANNELS*P_TX_USER_DATA_WIDTH)-1:0] gtwiz_userdata_tx_in,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS*128)-1:0] txdata_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0] txctrl0_out,
|
||||||
|
output wire [(P_TOTAL_NUMBER_OF_CHANNELS* 16)-1:0] txctrl1_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
// Transmitter user data width sizing conditional generation, based on parameter values in module instantiation
|
||||||
|
// -------------------------------------------------------------------------------------------------------------------
|
||||||
|
generate if (1) begin : gen_gtwiz_userdata_tx_main
|
||||||
|
genvar ch_idx;
|
||||||
|
|
||||||
|
// If transmitter data encoding is either not raw mode, or is raw mode but user data width is not modulus 10, then
|
||||||
|
// simply assign the transceiver-facing TXDATA vector with data bits from the user-facing data vector, plus padding.
|
||||||
|
if ((P_TX_DATA_ENCODING != 0) ||
|
||||||
|
((P_TX_DATA_ENCODING == 0) && (P_TX_USER_DATA_WIDTH % 10 != 0))) begin : gen_txdata
|
||||||
|
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_assign
|
||||||
|
if (P_TX_USER_DATA_WIDTH < 128) begin : gen_less_128
|
||||||
|
assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
|
||||||
|
{{128-P_TX_USER_DATA_WIDTH{1'b0}},
|
||||||
|
gtwiz_userdata_tx_in[(P_TX_USER_DATA_WIDTH*ch_idx)+P_TX_USER_DATA_WIDTH-1:
|
||||||
|
(P_TX_USER_DATA_WIDTH*ch_idx)]};
|
||||||
|
end
|
||||||
|
else begin : gen_128
|
||||||
|
assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
|
||||||
|
gtwiz_userdata_tx_in[(P_TX_USER_DATA_WIDTH*ch_idx)+P_TX_USER_DATA_WIDTH-1:
|
||||||
|
(P_TX_USER_DATA_WIDTH*ch_idx)];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Transceiver-facing TXCTRL0 and TXCTRL1 vectors are not driven by this helper block in this configuration
|
||||||
|
assign txctrl0_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b0}};
|
||||||
|
assign txctrl1_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b0}};
|
||||||
|
end
|
||||||
|
|
||||||
|
// If transmitter data encoding is raw mode and user data width is modulus 10, then assign the specified combination
|
||||||
|
// of transceiver-facing TXDATA, TXCTRL0, and TXCTRL1 vectors with the user-facing data vector. The interleaving of
|
||||||
|
// these vectors is always in a repeating 8-1-1 bit pattern, scaling with the user data width size.
|
||||||
|
else begin : gen_txdata_txctrl
|
||||||
|
|
||||||
|
case (P_TX_USER_DATA_WIDTH)
|
||||||
|
20:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width20
|
||||||
|
assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{14'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*20)+19],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*20)+9]};
|
||||||
|
assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{14'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*20)+18],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*20)+8]};
|
||||||
|
assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
|
||||||
|
{112'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*20)+17:(ch_idx*20)+10],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*20)+7:ch_idx*20]};
|
||||||
|
end
|
||||||
|
|
||||||
|
40:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width40
|
||||||
|
assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{12'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+39],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+29],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+19],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+9]};
|
||||||
|
assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{12'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+38],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+28],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+18],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+8]};
|
||||||
|
assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
|
||||||
|
{96'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+37:(ch_idx*40)+30],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+27:(ch_idx*40)+20],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+17:(ch_idx*40)+10],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*40)+7:ch_idx*40]};
|
||||||
|
end
|
||||||
|
|
||||||
|
80:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width80
|
||||||
|
assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{8'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+79],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+69],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+59],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+49],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+39],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+29],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+19],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+9]};
|
||||||
|
assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{8'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+78],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+68],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+58],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+48],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+38],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+28],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+18],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+8]};
|
||||||
|
assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
|
||||||
|
{64'b0,
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+77:(ch_idx*80)+70],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+67:(ch_idx*80)+60],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+57:(ch_idx*80)+50],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+47:(ch_idx*80)+40],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+37:(ch_idx*80)+30],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+27:(ch_idx*80)+20],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+17:(ch_idx*80)+10],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*80)+7:ch_idx*80]};
|
||||||
|
end
|
||||||
|
|
||||||
|
160:
|
||||||
|
for (ch_idx = 0; ch_idx < P_TOTAL_NUMBER_OF_CHANNELS; ch_idx = ch_idx + 1) begin : gen_width160
|
||||||
|
assign txctrl1_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{gtwiz_userdata_tx_in[(ch_idx*160)+159],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+149],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+139],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+129],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+119],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+109],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+99],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+89],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+79],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+69],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+59],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+49],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+39],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+29],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+19],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+9]};
|
||||||
|
assign txctrl0_out[(16*ch_idx)+15:(16*ch_idx)] =
|
||||||
|
{gtwiz_userdata_tx_in[(ch_idx*160)+158],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+148],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+138],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+128],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+118],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+108],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+98],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+88],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+78],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+68],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+58],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+48],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+38],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+28],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+18],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+8]};
|
||||||
|
assign txdata_out[(128*ch_idx)+127:(128*ch_idx)] =
|
||||||
|
{gtwiz_userdata_tx_in[(ch_idx*160)+157:(ch_idx*160)+150],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+147:(ch_idx*160)+140],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+137:(ch_idx*160)+130],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+127:(ch_idx*160)+120],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+117:(ch_idx*160)+110],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+107:(ch_idx*160)+100],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+97:(ch_idx*160)+90],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+87:(ch_idx*160)+80],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+77:(ch_idx*160)+70],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+67:(ch_idx*160)+60],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+57:(ch_idx*160)+50],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+47:(ch_idx*160)+40],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+37:(ch_idx*160)+30],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+27:(ch_idx*160)+20],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+17:(ch_idx*160)+10],
|
||||||
|
gtwiz_userdata_tx_in[(ch_idx*160)+7:ch_idx*160]};
|
||||||
|
end
|
||||||
|
|
||||||
|
default:
|
||||||
|
begin : gen_default
|
||||||
|
// The default case is a configuration error scenario should never be exercised
|
||||||
|
assign txdata_out = {P_TOTAL_NUMBER_OF_CHANNELS*128{1'b1}};
|
||||||
|
assign txctrl0_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b1}};
|
||||||
|
assign txctrl1_out = {P_TOTAL_NUMBER_OF_CHANNELS*16{1'b1}};
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,224 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal_freq_counter # (
|
||||||
|
parameter REVISION = 1
|
||||||
|
)(
|
||||||
|
output reg [17:0] freq_cnt_o = 18'd0,
|
||||||
|
output reg done_o,
|
||||||
|
input wire rst_i,
|
||||||
|
input wire [15:0] test_term_cnt_i,
|
||||||
|
input wire ref_clk_i,
|
||||||
|
input wire test_clk_i
|
||||||
|
);
|
||||||
|
//****************************************************************************
|
||||||
|
// Local Parameters
|
||||||
|
//****************************************************************************
|
||||||
|
localparam RESET_STATE = 0;
|
||||||
|
localparam MEASURE_STATE = 1;
|
||||||
|
localparam HOLD_STATE = 2;
|
||||||
|
localparam UPDATE_STATE = 3;
|
||||||
|
localparam DONE_STATE = 4;
|
||||||
|
|
||||||
|
//****************************************************************************
|
||||||
|
// Local Signals
|
||||||
|
//****************************************************************************
|
||||||
|
reg [17:0] testclk_cnt = 18'h00000;
|
||||||
|
reg [15:0] refclk_cnt = 16'h0000;
|
||||||
|
reg [3:0] testclk_div4 = 4'h1;
|
||||||
|
wire testclk_rst;
|
||||||
|
wire testclk_en;
|
||||||
|
reg [5:0] hold_clk = 6'd0;
|
||||||
|
reg [4:0] state = 5'd1;
|
||||||
|
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
|
||||||
|
|
||||||
|
//
|
||||||
|
// need to get testclk_rst into TESTCLK_I domain
|
||||||
|
//
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
tstclk_rst_dly1 <= testclk_rst;
|
||||||
|
tstclk_rst_dly2 <= tstclk_rst_dly1;
|
||||||
|
end
|
||||||
|
|
||||||
|
//
|
||||||
|
// need to get testclk_en into TESTCLK_I domain
|
||||||
|
//
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
testclk_en_dly1 <= testclk_en;
|
||||||
|
testclk_en_dly2 <= testclk_en_dly1;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge test_clk_i)
|
||||||
|
begin
|
||||||
|
if (tstclk_rst_dly2 == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_div4 <= 4'h1;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
wire testclk_rst_sync;
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_testclk_rst_inst (
|
||||||
|
.clk_in (test_clk_i),
|
||||||
|
.rst_in (testclk_rst),
|
||||||
|
.rst_out (testclk_rst_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge test_clk_i or posedge testclk_rst_sync)
|
||||||
|
begin
|
||||||
|
if (testclk_rst_sync == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= testclk_cnt + 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
/* always @(posedge test_clk_i or posedge testclk_rst)
|
||||||
|
begin
|
||||||
|
if (testclk_rst == 1'b1)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
|
||||||
|
begin
|
||||||
|
testclk_cnt <= testclk_cnt + 1;
|
||||||
|
end
|
||||||
|
end */
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i or posedge rst_i)
|
||||||
|
begin
|
||||||
|
if (rst_i)
|
||||||
|
done_o <= 1'b0;
|
||||||
|
else
|
||||||
|
done_o <= state[DONE_STATE];
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i or posedge rst_i)
|
||||||
|
begin
|
||||||
|
if (rst_i) begin
|
||||||
|
state <= 0;
|
||||||
|
state[RESET_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
state <= 0;
|
||||||
|
case (1'b1) // synthesis parallel_case full_case
|
||||||
|
state[RESET_STATE]:
|
||||||
|
begin
|
||||||
|
if (hold_clk == 6'h3F)
|
||||||
|
state[MEASURE_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[RESET_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[MEASURE_STATE]:
|
||||||
|
begin
|
||||||
|
if (refclk_cnt == test_term_cnt_i)
|
||||||
|
state[HOLD_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[MEASURE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[HOLD_STATE]:
|
||||||
|
begin
|
||||||
|
if (hold_clk == 6'hF)
|
||||||
|
state[UPDATE_STATE] <= 1'b1;
|
||||||
|
else
|
||||||
|
state[HOLD_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[UPDATE_STATE]:
|
||||||
|
begin
|
||||||
|
freq_cnt_o <= testclk_cnt;
|
||||||
|
state[DONE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
state[DONE_STATE]:
|
||||||
|
begin
|
||||||
|
state[DONE_STATE] <= 1'b1;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign testclk_rst = state[RESET_STATE];
|
||||||
|
assign testclk_en = state[MEASURE_STATE];
|
||||||
|
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i)
|
||||||
|
begin
|
||||||
|
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
|
||||||
|
hold_clk <= hold_clk + 1;
|
||||||
|
else
|
||||||
|
hold_clk <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge ref_clk_i)
|
||||||
|
begin
|
||||||
|
if (state[MEASURE_STATE] == 1'b1)
|
||||||
|
refclk_cnt <= refclk_cnt + 1;
|
||||||
|
else
|
||||||
|
refclk_cnt <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,346 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal # (
|
||||||
|
parameter integer C_RX_PLL_TYPE = 0,
|
||||||
|
parameter integer C_TX_PLL_TYPE = 0,
|
||||||
|
parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
|
||||||
|
parameter SIM_RESET_SPEEDUP = "TRUE",
|
||||||
|
parameter C_FREERUN_FREQUENCY = 100,
|
||||||
|
parameter REVISION = 2,
|
||||||
|
parameter C_PCIE_ENABLE = "FALSE",
|
||||||
|
parameter C_PCIE_CORECLK_FREQ = 250
|
||||||
|
)(
|
||||||
|
// control signals
|
||||||
|
input wire [17:0] TXOUTCLK_PERIOD_IN,
|
||||||
|
input wire [17:0] CNT_TOL_IN,
|
||||||
|
input wire [15:0] FREQ_COUNT_WINDOW_IN,
|
||||||
|
// User Interface
|
||||||
|
input wire RESET_IN,
|
||||||
|
input wire CLK_IN,
|
||||||
|
input wire DRPRST_IN,
|
||||||
|
input wire [1:0] USER_TXPLLCLKSEL,
|
||||||
|
input wire [1:0] USER_RXPLLCLKSEL,
|
||||||
|
input wire USER_RXPROGDIVRESET_IN,
|
||||||
|
output wire USER_RXPRGDIVRESETDONE_OUT,
|
||||||
|
output wire USER_RXPMARESETDONE_OUT,
|
||||||
|
input wire [2:0] USER_RXOUTCLKSEL_IN,
|
||||||
|
input wire USER_RXOUTCLK_BUFG_CE_IN,
|
||||||
|
input wire USER_RXOUTCLK_BUFG_CLR_IN,
|
||||||
|
input wire USER_GTRXRESET_IN,
|
||||||
|
input wire USER_RXCDRHOLD_IN,
|
||||||
|
input wire USER_RXPMARESET_IN,
|
||||||
|
input wire USER_TXPROGDIVRESET_IN,
|
||||||
|
output wire USER_TXPRGDIVRESETDONE_OUT,
|
||||||
|
input wire [2:0] USER_TXOUTCLKSEL_IN,
|
||||||
|
input wire USER_TXOUTCLK_BUFG_CE_IN,
|
||||||
|
input wire USER_TXOUTCLK_BUFG_CLR_IN,
|
||||||
|
output wire USER_CPLLLOCK_OUT,
|
||||||
|
input wire [9:0] USER_CHANNEL_DRPADDR_IN,
|
||||||
|
input wire [15:0] USER_CHANNEL_DRPDI_IN,
|
||||||
|
input wire USER_CHANNEL_DRPEN_IN,
|
||||||
|
input wire USER_CHANNEL_DRPWE_IN,
|
||||||
|
output wire USER_CHANNEL_DRPRDY_OUT,
|
||||||
|
output wire [15:0] USER_CHANNEL_DRPDO_OUT,
|
||||||
|
// Debug Interface
|
||||||
|
output wire CPLL_CAL_FAIL,
|
||||||
|
output wire CPLL_CAL_DONE,
|
||||||
|
output wire [15:0] DEBUG_OUT,
|
||||||
|
output wire [17:0] CAL_FREQ_CNT,
|
||||||
|
input [3:0] REPEAT_RESET_LIMIT,
|
||||||
|
// GT Interface
|
||||||
|
input wire GTYE4_TXOUTCLK_IN,
|
||||||
|
input wire GTYE4_RXOUTCLK_IN,
|
||||||
|
input wire GTYE4_CPLLLOCK_IN,
|
||||||
|
output wire GTYE4_CPLLRESET_OUT,
|
||||||
|
output wire GTYE4_RXCDRHOLD_OUT,
|
||||||
|
output wire GTYE4_GTRXRESET_OUT,
|
||||||
|
output wire GTYE4_RXPMARESET_OUT,
|
||||||
|
output wire GTYE4_RXPROGDIVRESET_OUT,
|
||||||
|
output wire [2:0] GTYE4_RXOUTCLKSEL_OUT,
|
||||||
|
input wire GTYE4_RXPRGDIVRESETDONE_IN,
|
||||||
|
input wire GTYE4_RXPMARESETDONE_IN,
|
||||||
|
output wire GTYE4_CPLLPD_OUT,
|
||||||
|
output wire GTYE4_TXPROGDIVRESET_OUT,
|
||||||
|
output wire [2:0] GTYE4_TXOUTCLKSEL_OUT,
|
||||||
|
input wire GTYE4_TXPRGDIVRESETDONE_IN,
|
||||||
|
output wire [9:0] GTYE4_CHANNEL_DRPADDR_OUT,
|
||||||
|
output wire [15:0] GTYE4_CHANNEL_DRPDI_OUT,
|
||||||
|
output wire GTYE4_CHANNEL_DRPEN_OUT,
|
||||||
|
output wire GTYE4_CHANNEL_DRPWE_OUT,
|
||||||
|
input wire GTYE4_CHANNEL_DRPRDY_IN,
|
||||||
|
input wire [15:0] GTYE4_CHANNEL_DRPDO_IN
|
||||||
|
);
|
||||||
|
|
||||||
|
wire rx_done;
|
||||||
|
wire tx_done;
|
||||||
|
|
||||||
|
wire cal_on_rx_cal_fail;
|
||||||
|
wire cal_on_rx_cal_done;
|
||||||
|
wire [15:0] cal_on_rx_debug_out;
|
||||||
|
wire [17:0] cal_on_rx_cal_freq_cnt;
|
||||||
|
wire cal_on_rx_cpllreset_out;
|
||||||
|
wire cal_on_rx_cpllpd_out;
|
||||||
|
wire cal_on_rx_cplllock_out;
|
||||||
|
|
||||||
|
wire cal_on_rx_drpen_out;
|
||||||
|
wire cal_on_rx_drpwe_out;
|
||||||
|
wire [9:0] cal_on_rx_drpaddr_out;
|
||||||
|
wire [15:0] cal_on_rx_drpdi_out;
|
||||||
|
wire [15:0] cal_on_rx_dout;
|
||||||
|
wire cal_on_rx_drdy;
|
||||||
|
|
||||||
|
wire cal_on_tx_cal_fail;
|
||||||
|
wire cal_on_tx_cal_done;
|
||||||
|
wire [15:0] cal_on_tx_debug_out;
|
||||||
|
wire [17:0] cal_on_tx_cal_freq_cnt;
|
||||||
|
wire cal_on_tx_cpllreset_out;
|
||||||
|
wire cal_on_tx_cpllpd_out;
|
||||||
|
wire cal_on_tx_cplllock_out;
|
||||||
|
|
||||||
|
wire cal_on_tx_drpen_out;
|
||||||
|
wire cal_on_tx_drpwe_out;
|
||||||
|
wire [9:0] cal_on_tx_drpaddr_out;
|
||||||
|
wire [15:0] cal_on_tx_drpdi_out;
|
||||||
|
wire [15:0] cal_on_tx_dout;
|
||||||
|
wire cal_on_tx_drdy;
|
||||||
|
|
||||||
|
localparam [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C;
|
||||||
|
localparam [9:0] ADDR_TX_PROGDIV_CFG = 10'h057; // GTH /GTY addresses are different (003E in GTH; 0057 in GTY)
|
||||||
|
localparam [9:0] ADDR_RX_PROGDIV_CFG = 10'h0C6;
|
||||||
|
localparam [9:0] ADDR_X0E1 = 10'h0E1;
|
||||||
|
localparam [9:0] ADDR_X079 = 10'h079;
|
||||||
|
localparam [9:0] ADDR_X114 = 10'h114;
|
||||||
|
localparam CPLL_CAL_ONLY_TX = (C_RX_PLL_TYPE == C_TX_PLL_TYPE); // If top level configuration of TX and RX PLL TYPE are same, don't use RX Cal block
|
||||||
|
|
||||||
|
wire cpll_cal_on_tx_or_rx; //1: RX cal block, 0: TX cal block;
|
||||||
|
assign cpll_cal_on_tx_or_rx = CPLL_CAL_ONLY_TX ? 1'b0 : ((USER_TXPLLCLKSEL != 2'b00 && USER_RXPLLCLKSEL == 2'b00) ? 1'b1 : 1'b0);
|
||||||
|
|
||||||
|
// TX reset version
|
||||||
|
wire cal_on_tx_reset_in;
|
||||||
|
assign cal_on_tx_reset_in = RESET_IN | cpll_cal_on_tx_or_rx;
|
||||||
|
|
||||||
|
wire cal_on_tx_reset_in_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_tx_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.rst_in (cal_on_tx_reset_in),
|
||||||
|
.rst_out (cal_on_tx_reset_in_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
// RX reset version
|
||||||
|
wire cal_on_rx_reset_in;
|
||||||
|
assign cal_on_rx_reset_in = RESET_IN | !cpll_cal_on_tx_or_rx;
|
||||||
|
|
||||||
|
wire cal_on_rx_reset_in_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_rx_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.rst_in (cal_on_rx_reset_in),
|
||||||
|
.rst_out (cal_on_rx_reset_in_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire drprst_in_sync;
|
||||||
|
gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_drprst_inst (
|
||||||
|
.clk_in (CLK_IN),
|
||||||
|
.i_in (DRPRST_IN),
|
||||||
|
.o_out (drprst_in_sync)
|
||||||
|
);
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal_tx #
|
||||||
|
(
|
||||||
|
.C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
|
||||||
|
.SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
|
||||||
|
.C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
|
||||||
|
.C_PCIE_ENABLE(C_PCIE_ENABLE),
|
||||||
|
.C_PCIE_CORECLK_FREQ(C_PCIE_CORECLK_FREQ)
|
||||||
|
) gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal_tx_i
|
||||||
|
(
|
||||||
|
// control signals
|
||||||
|
.TXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
|
||||||
|
.CNT_TOL_IN(CNT_TOL_IN),
|
||||||
|
.FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
|
||||||
|
// User Interface
|
||||||
|
.RESET_IN(cal_on_tx_reset_in_sync),
|
||||||
|
.CLK_IN(CLK_IN),
|
||||||
|
.USER_TXPLLCLKSEL(USER_TXPLLCLKSEL),
|
||||||
|
.USER_TXPROGDIVRESET_IN(USER_TXPROGDIVRESET_IN),
|
||||||
|
.USER_TXPRGDIVRESETDONE_OUT(USER_TXPRGDIVRESETDONE_OUT),
|
||||||
|
.USER_TXOUTCLKSEL_IN(USER_TXOUTCLKSEL_IN),
|
||||||
|
.USER_TXOUTCLK_BUFG_CE_IN(USER_TXOUTCLK_BUFG_CE_IN),
|
||||||
|
.USER_TXOUTCLK_BUFG_CLR_IN(USER_TXOUTCLK_BUFG_CLR_IN),
|
||||||
|
.USER_CPLLLOCK_OUT(cal_on_tx_cplllock_out),
|
||||||
|
// Debug Interface
|
||||||
|
.CPLL_CAL_FAIL(cal_on_tx_cal_fail),
|
||||||
|
.CPLL_CAL_DONE(cal_on_tx_cal_done),
|
||||||
|
.DEBUG_OUT(cal_on_tx_debug_out),
|
||||||
|
.CAL_FREQ_CNT(cal_on_tx_cal_freq_cnt),
|
||||||
|
.REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
|
||||||
|
// GT Interface
|
||||||
|
.GTYE4_TXOUTCLK_IN(GTYE4_TXOUTCLK_IN),
|
||||||
|
.GTYE4_CPLLLOCK_IN(GTYE4_CPLLLOCK_IN),
|
||||||
|
.GTYE4_CPLLRESET_OUT(cal_on_tx_cpllreset_out),
|
||||||
|
.GTYE4_CPLLPD_OUT(cal_on_tx_cpllpd_out),
|
||||||
|
.GTYE4_TXPROGDIVRESET_OUT(GTYE4_TXPROGDIVRESET_OUT),
|
||||||
|
.GTYE4_TXOUTCLKSEL_OUT(GTYE4_TXOUTCLKSEL_OUT),
|
||||||
|
.GTYE4_TXPRGDIVRESETDONE_IN(GTYE4_TXPRGDIVRESETDONE_IN),
|
||||||
|
.GTYE4_CHANNEL_DRPADDR_OUT(cal_on_tx_drpaddr_out),
|
||||||
|
.GTYE4_CHANNEL_DRPDI_OUT(cal_on_tx_drpdi_out),
|
||||||
|
.GTYE4_CHANNEL_DRPEN_OUT(cal_on_tx_drpen_out),
|
||||||
|
.GTYE4_CHANNEL_DRPWE_OUT(cal_on_tx_drpwe_out),
|
||||||
|
.GTYE4_CHANNEL_DRPRDY_IN(cal_on_tx_drdy),
|
||||||
|
.GTYE4_CHANNEL_DRPDO_IN(cal_on_tx_dout),
|
||||||
|
.DONE(tx_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal_rx #
|
||||||
|
(
|
||||||
|
.C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
|
||||||
|
.SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
|
||||||
|
.CPLL_CAL_ONLY_TX(CPLL_CAL_ONLY_TX),
|
||||||
|
.C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY)
|
||||||
|
) gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal_rx_i
|
||||||
|
(
|
||||||
|
// control signals
|
||||||
|
.RXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
|
||||||
|
.CNT_TOL_IN(CNT_TOL_IN),
|
||||||
|
.FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
|
||||||
|
// User Interface
|
||||||
|
.RESET_IN(cal_on_rx_reset_in_sync),
|
||||||
|
.CLK_IN(CLK_IN),
|
||||||
|
.USER_RXPROGDIVRESET_IN(USER_RXPROGDIVRESET_IN),
|
||||||
|
.USER_RXPRGDIVRESETDONE_OUT(USER_RXPRGDIVRESETDONE_OUT),
|
||||||
|
.USER_RXPMARESETDONE_OUT(USER_RXPMARESETDONE_OUT),
|
||||||
|
.USER_RXOUTCLKSEL_IN(USER_RXOUTCLKSEL_IN),
|
||||||
|
.USER_RXOUTCLK_BUFG_CE_IN(USER_RXOUTCLK_BUFG_CE_IN),
|
||||||
|
.USER_RXOUTCLK_BUFG_CLR_IN(USER_RXOUTCLK_BUFG_CLR_IN),
|
||||||
|
.USER_CPLLLOCK_OUT(cal_on_rx_cplllock_out),
|
||||||
|
.USER_RXCDRHOLD_IN(USER_RXCDRHOLD_IN),
|
||||||
|
.USER_GTRXRESET_IN(USER_GTRXRESET_IN),
|
||||||
|
.USER_RXPMARESET_IN(USER_RXPMARESET_IN),
|
||||||
|
// Debug Interface
|
||||||
|
.CPLL_CAL_FAIL(cal_on_rx_cal_fail),
|
||||||
|
.CPLL_CAL_DONE(cal_on_rx_cal_done),
|
||||||
|
.DEBUG_OUT(cal_on_rx_debug_out),
|
||||||
|
.CAL_FREQ_CNT(cal_on_rx_cal_freq_cnt),
|
||||||
|
.REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT),
|
||||||
|
// GT Interface
|
||||||
|
.GTYE4_RXOUTCLK_IN(GTYE4_RXOUTCLK_IN),
|
||||||
|
.GTYE4_CPLLLOCK_IN(GTYE4_CPLLLOCK_IN),
|
||||||
|
.GTYE4_CPLLRESET_OUT(cal_on_rx_cpllreset_out),
|
||||||
|
.GTYE4_CPLLPD_OUT(cal_on_rx_cpllpd_out),
|
||||||
|
.GTYE4_RXPROGDIVRESET_OUT(GTYE4_RXPROGDIVRESET_OUT),
|
||||||
|
.GTYE4_RXOUTCLKSEL_OUT(GTYE4_RXOUTCLKSEL_OUT),
|
||||||
|
.GTYE4_RXPRGDIVRESETDONE_IN(GTYE4_RXPRGDIVRESETDONE_IN),
|
||||||
|
.GTYE4_CHANNEL_DRPADDR_OUT(cal_on_rx_drpaddr_out),
|
||||||
|
.GTYE4_CHANNEL_DRPDI_OUT(cal_on_rx_drpdi_out),
|
||||||
|
.GTYE4_CHANNEL_DRPEN_OUT(cal_on_rx_drpen_out),
|
||||||
|
.GTYE4_CHANNEL_DRPWE_OUT(cal_on_rx_drpwe_out),
|
||||||
|
.GTYE4_CHANNEL_DRPRDY_IN(cal_on_rx_drdy),
|
||||||
|
.GTYE4_CHANNEL_DRPDO_IN(cal_on_rx_dout),
|
||||||
|
.GTYE4_GTRXRESET_OUT(GTYE4_GTRXRESET_OUT),
|
||||||
|
.GTYE4_RXPMARESET_OUT(GTYE4_RXPMARESET_OUT),
|
||||||
|
.GTYE4_RXCDRHOLD_OUT(GTYE4_RXCDRHOLD_OUT),
|
||||||
|
.GTYE4_RXPMARESETDONE_IN(GTYE4_RXPMARESETDONE_IN),
|
||||||
|
.DONE(rx_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
//OR with TX versions
|
||||||
|
assign GTYE4_CPLLRESET_OUT = cal_on_rx_cpllreset_out | cal_on_tx_cpllreset_out;
|
||||||
|
assign GTYE4_CPLLPD_OUT = cal_on_rx_cpllpd_out | cal_on_tx_cpllpd_out;
|
||||||
|
assign USER_CPLLLOCK_OUT = cal_on_rx_cplllock_out | cal_on_tx_cplllock_out;
|
||||||
|
|
||||||
|
//Mux the debug signals out
|
||||||
|
assign CPLL_CAL_DONE = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_done : cal_on_tx_cal_done;
|
||||||
|
assign CPLL_CAL_FAIL = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_fail : cal_on_tx_cal_fail;
|
||||||
|
assign DEBUG_OUT = cpll_cal_on_tx_or_rx ? cal_on_rx_debug_out : cal_on_tx_debug_out;
|
||||||
|
assign CAL_FREQ_CNT = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_freq_cnt : cal_on_tx_cal_freq_cnt;
|
||||||
|
|
||||||
|
//----------------------------------------------------------------------------------------------
|
||||||
|
// DRP ARBITER
|
||||||
|
//----------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
gtwizard_ultrascale_v1_7_14_gte4_drp_arb #
|
||||||
|
(
|
||||||
|
.ADDR_TX_PROGCLK_SEL(ADDR_TX_PROGCLK_SEL),
|
||||||
|
.ADDR_TX_PROGDIV_CFG(ADDR_TX_PROGDIV_CFG),
|
||||||
|
.ADDR_RX_PROGDIV_CFG(ADDR_RX_PROGDIV_CFG),
|
||||||
|
.ADDR_X0E1(ADDR_X0E1),
|
||||||
|
.ADDR_X079(ADDR_X079),
|
||||||
|
.ADDR_X114(ADDR_X114),
|
||||||
|
.C_NUM_CLIENTS(3),
|
||||||
|
.C_ADDR_WIDTH(10),
|
||||||
|
.C_DATA_WIDTH(16)
|
||||||
|
) gtwizard_ultrascale_v1_7_14_gte4_drp_arb_i
|
||||||
|
(
|
||||||
|
.DCLK_I (CLK_IN),
|
||||||
|
.RESET_I (drprst_in_sync),
|
||||||
|
.DEN_USR_I ({cal_on_tx_drpen_out, cal_on_rx_drpen_out, USER_CHANNEL_DRPEN_IN}),
|
||||||
|
.DWE_USR_I ({cal_on_tx_drpwe_out, cal_on_rx_drpwe_out, USER_CHANNEL_DRPWE_IN}),
|
||||||
|
.DADDR_USR_I ({cal_on_tx_drpaddr_out, cal_on_rx_drpaddr_out, USER_CHANNEL_DRPADDR_IN}),
|
||||||
|
.DI_USR_I ({cal_on_tx_drpdi_out, cal_on_rx_drpdi_out, USER_CHANNEL_DRPDI_IN}),
|
||||||
|
.DO_USR_O ({cal_on_tx_dout, cal_on_rx_dout, USER_CHANNEL_DRPDO_OUT}),
|
||||||
|
.DRDY_USR_O ({cal_on_tx_drdy, cal_on_rx_drdy, USER_CHANNEL_DRPRDY_OUT}),
|
||||||
|
// arbitrated port
|
||||||
|
.DEN_O (GTYE4_CHANNEL_DRPEN_OUT),
|
||||||
|
.DWE_O (GTYE4_CHANNEL_DRPWE_OUT),
|
||||||
|
.DADDR_O (GTYE4_CHANNEL_DRPADDR_OUT),
|
||||||
|
.DI_O (GTYE4_CHANNEL_DRPDI_OUT),
|
||||||
|
.DO_I (GTYE4_CHANNEL_DRPDO_IN),
|
||||||
|
.DRDY_I (GTYE4_CHANNEL_DRPRDY_IN),
|
||||||
|
.TX_CAL_DONE_I (tx_done),
|
||||||
|
.RX_CAL_DONE_I (rx_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule //CPLL_CAL
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,170 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_gtye4_delay_powergood # (
|
||||||
|
parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
|
||||||
|
parameter C_PCIE_ENABLE = "FALSE"
|
||||||
|
)(
|
||||||
|
input wire GT_TXOUTCLKPCS,
|
||||||
|
|
||||||
|
input wire GT_GTPOWERGOOD,
|
||||||
|
input wire [2:0] USER_TXRATE,
|
||||||
|
input wire USER_TXRATEMODE,
|
||||||
|
input wire USER_GTTXRESET,
|
||||||
|
input wire USER_TXPMARESET,
|
||||||
|
input wire USER_TXPISOPD,
|
||||||
|
|
||||||
|
output wire USER_GTPOWERGOOD,
|
||||||
|
output wire [2:0] GT_TXRATE,
|
||||||
|
output wire GT_TXRATEMODE,
|
||||||
|
output wire GT_GTTXRESET,
|
||||||
|
output wire GT_TXPMARESET,
|
||||||
|
output wire GT_TXPISOPD
|
||||||
|
);
|
||||||
|
|
||||||
|
generate if (C_PCIE_ENABLE || (C_USER_GTPOWERGOOD_DELAY_EN == 0))
|
||||||
|
begin : gen_powergood_nodelay
|
||||||
|
assign GT_TXPISOPD = USER_TXPISOPD;
|
||||||
|
assign GT_GTTXRESET = USER_GTTXRESET;
|
||||||
|
assign GT_TXPMARESET = USER_TXPMARESET;
|
||||||
|
assign GT_TXRATE = USER_TXRATE;
|
||||||
|
assign GT_TXRATEMODE = USER_TXRATEMODE;
|
||||||
|
assign USER_GTPOWERGOOD = GT_GTPOWERGOOD;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin: gen_powergood_delay
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r = 5'd0;
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [8:0] wait_cnt;
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg int_pwr_on_fsm = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
|
||||||
|
wire intclk_rrst_n;
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
// POWER ON FSM Encoding
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
localparam PWR_ON_WAIT_CNT = 4'd0;
|
||||||
|
localparam PWR_ON_DONE = 4'd1;
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
// Reset Synchronizer
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
always @ (posedge GT_TXOUTCLKPCS or negedge GT_GTPOWERGOOD)
|
||||||
|
begin
|
||||||
|
if (!GT_GTPOWERGOOD)
|
||||||
|
intclk_rrst_n_r <= 5'd0;
|
||||||
|
else if(!int_pwr_on_fsm)
|
||||||
|
intclk_rrst_n_r <= {intclk_rrst_n_r[3:0], 1'd1};
|
||||||
|
end
|
||||||
|
|
||||||
|
assign intclk_rrst_n = intclk_rrst_n_r[4];
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
// Wait counter
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
always @ (posedge GT_TXOUTCLKPCS)
|
||||||
|
begin
|
||||||
|
if (!intclk_rrst_n)
|
||||||
|
wait_cnt <= 9'd0;
|
||||||
|
else begin
|
||||||
|
if (int_pwr_on_fsm == PWR_ON_WAIT_CNT)
|
||||||
|
wait_cnt <= {wait_cnt[7:0],1'b1};
|
||||||
|
else
|
||||||
|
wait_cnt <= wait_cnt;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
// Power On FSM
|
||||||
|
//--------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
always @ (posedge GT_TXOUTCLKPCS or negedge GT_GTPOWERGOOD)
|
||||||
|
begin
|
||||||
|
if (!GT_GTPOWERGOOD)
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (int_pwr_on_fsm)
|
||||||
|
PWR_ON_WAIT_CNT :
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= (wait_cnt[7] == 1'b1) ? PWR_ON_DONE : PWR_ON_WAIT_CNT;
|
||||||
|
end
|
||||||
|
|
||||||
|
PWR_ON_DONE :
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= PWR_ON_DONE;
|
||||||
|
end
|
||||||
|
|
||||||
|
default :
|
||||||
|
begin
|
||||||
|
int_pwr_on_fsm <= PWR_ON_WAIT_CNT;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge GT_TXOUTCLKPCS)
|
||||||
|
pwr_on_fsm <= int_pwr_on_fsm;
|
||||||
|
|
||||||
|
assign GT_TXPISOPD = pwr_on_fsm ? USER_TXPISOPD : 1'b1;
|
||||||
|
assign GT_GTTXRESET = pwr_on_fsm ? USER_GTTXRESET : !GT_GTPOWERGOOD;
|
||||||
|
assign GT_TXPMARESET = pwr_on_fsm ? USER_TXPMARESET : 1'b0;
|
||||||
|
assign GT_TXRATE = pwr_on_fsm ? USER_TXRATE : 3'b001;
|
||||||
|
assign GT_TXRATEMODE = pwr_on_fsm ? USER_TXRATEMODE : 1'b1;
|
||||||
|
assign USER_GTPOWERGOOD = pwr_on_fsm;
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,98 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer # (
|
||||||
|
|
||||||
|
parameter FREQUENCY = 512
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
input wire clk_in,
|
||||||
|
input wire rst_in,
|
||||||
|
output wire rst_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
|
||||||
|
// enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
|
||||||
|
// asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
|
||||||
|
// downstream logic is also removed from reset synchronously. This module is designed for active-low reset use.
|
||||||
|
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
|
||||||
|
reg rst_in_out = 1'b0;
|
||||||
|
|
||||||
|
always @(posedge clk_in, negedge rst_in) begin
|
||||||
|
if (!rst_in) begin
|
||||||
|
rst_in_meta <= 1'b0;
|
||||||
|
rst_in_sync1 <= 1'b0;
|
||||||
|
rst_in_sync2 <= 1'b0;
|
||||||
|
rst_in_sync3 <= 1'b0;
|
||||||
|
rst_in_out <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rst_in_meta <= 1'b1;
|
||||||
|
rst_in_sync1 <= rst_in_meta;
|
||||||
|
rst_in_sync2 <= rst_in_sync1;
|
||||||
|
rst_in_sync3 <= rst_in_sync2;
|
||||||
|
rst_in_out <= rst_in_sync3;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign rst_out = rst_in_out;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,98 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// ***************************
|
||||||
|
// * DO NOT MODIFY THIS FILE *
|
||||||
|
// ***************************
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module gtwizard_ultrascale_v1_7_14_reset_synchronizer # (
|
||||||
|
|
||||||
|
parameter FREQUENCY = 512
|
||||||
|
|
||||||
|
)(
|
||||||
|
|
||||||
|
input wire clk_in,
|
||||||
|
input wire rst_in,
|
||||||
|
output wire rst_out
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
|
||||||
|
// enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
|
||||||
|
// asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
|
||||||
|
// downstream logic is also removed from reset synchronously. This module is designed for active-high reset use.
|
||||||
|
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
|
||||||
|
(* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
|
||||||
|
reg rst_in_out = 1'b0;
|
||||||
|
|
||||||
|
always @(posedge clk_in, posedge rst_in) begin
|
||||||
|
if (rst_in) begin
|
||||||
|
rst_in_meta <= 1'b1;
|
||||||
|
rst_in_sync1 <= 1'b1;
|
||||||
|
rst_in_sync2 <= 1'b1;
|
||||||
|
rst_in_sync3 <= 1'b1;
|
||||||
|
rst_in_out <= 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
rst_in_meta <= 1'b0;
|
||||||
|
rst_in_sync1 <= rst_in_meta;
|
||||||
|
rst_in_sync2 <= rst_in_sync1;
|
||||||
|
rst_in_sync3 <= rst_in_sync2;
|
||||||
|
rst_in_out <= rst_in_sync3;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign rst_out = rst_in_out;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,138 @@
|
|||||||
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//-----------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Generic Functions used by AXI Infrastructure Modules
|
||||||
|
//
|
||||||
|
// Verilog-standard: Verilog 2001
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
// Global Parameters:
|
||||||
|
//
|
||||||
|
// Functions:
|
||||||
|
//
|
||||||
|
// Tasks:
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// BEGIN Global Parameters
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
localparam G_AXI_AWADDR_INDEX = 0;
|
||||||
|
localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||||
|
localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
|
||||||
|
localparam G_AXI_AWPROT_WIDTH = 3;
|
||||||
|
localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
|
||||||
|
localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||||
|
localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
|
||||||
|
localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||||
|
localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
|
||||||
|
localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||||
|
localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
|
||||||
|
localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||||
|
localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
|
||||||
|
localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||||
|
localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
|
||||||
|
localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||||
|
localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
|
||||||
|
localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||||
|
localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
|
||||||
|
localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||||
|
localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
|
||||||
|
localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
|
||||||
|
localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
|
||||||
|
localparam G_AXI_ARADDR_INDEX = 0;
|
||||||
|
localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||||
|
localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
|
||||||
|
localparam G_AXI_ARPROT_WIDTH = 3;
|
||||||
|
localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
|
||||||
|
localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||||
|
localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
|
||||||
|
localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||||
|
localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
|
||||||
|
localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||||
|
localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
|
||||||
|
localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||||
|
localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
|
||||||
|
localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||||
|
localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
|
||||||
|
localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||||
|
localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
|
||||||
|
localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||||
|
localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
|
||||||
|
localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||||
|
localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
|
||||||
|
localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
|
||||||
|
localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
|
||||||
|
// Write channel widths
|
||||||
|
localparam G_AXI_WDATA_INDEX = 0;
|
||||||
|
localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||||
|
localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
|
||||||
|
localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8;
|
||||||
|
localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
|
||||||
|
localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||||
|
localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
|
||||||
|
localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
|
||||||
|
localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
|
||||||
|
localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
|
||||||
|
localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
|
||||||
|
// Write Response channel Widths
|
||||||
|
localparam G_AXI_BRESP_INDEX = 0;
|
||||||
|
localparam G_AXI_BRESP_WIDTH = 2;
|
||||||
|
localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
|
||||||
|
localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||||
|
localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
|
||||||
|
localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
|
||||||
|
localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
|
||||||
|
// Read channel widths
|
||||||
|
localparam G_AXI_RDATA_INDEX = 0;
|
||||||
|
localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||||
|
localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
|
||||||
|
localparam G_AXI_RRESP_WIDTH = 2;
|
||||||
|
localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
|
||||||
|
localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||||
|
localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
|
||||||
|
localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||||
|
localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
|
||||||
|
localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
|
||||||
|
localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;
|
||||||
@@ -0,0 +1,670 @@
|
|||||||
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//-----------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// axis to vector
|
||||||
|
// A generic module to merge all axi signals into one signal called payload.
|
||||||
|
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||||
|
//
|
||||||
|
// Verilog-standard: Verilog 2001
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||||
|
module axi_infrastructure_v1_1_0_axi2vector #
|
||||||
|
(
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Parameter Definitions
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
parameter integer C_AXI_PROTOCOL = 0,
|
||||||
|
parameter integer C_AXI_ID_WIDTH = 4,
|
||||||
|
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||||
|
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||||
|
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||||
|
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||||
|
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||||
|
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||||
|
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||||
|
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||||
|
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||||
|
)
|
||||||
|
(
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Port Declarations
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Slave Interface Write Address Ports
|
||||||
|
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
|
||||||
|
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||||
|
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||||
|
input wire [3-1:0] s_axi_awsize,
|
||||||
|
input wire [2-1:0] s_axi_awburst,
|
||||||
|
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||||
|
input wire [4-1:0] s_axi_awcache,
|
||||||
|
input wire [3-1:0] s_axi_awprot,
|
||||||
|
input wire [4-1:0] s_axi_awregion,
|
||||||
|
input wire [4-1:0] s_axi_awqos,
|
||||||
|
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||||
|
|
||||||
|
// Slave Interface Write Data Ports
|
||||||
|
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
|
||||||
|
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
|
||||||
|
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||||
|
input wire s_axi_wlast,
|
||||||
|
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||||
|
|
||||||
|
// Slave Interface Write Response Ports
|
||||||
|
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
|
||||||
|
output wire [2-1:0] s_axi_bresp,
|
||||||
|
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||||
|
|
||||||
|
// Slave Interface Read Address Ports
|
||||||
|
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
|
||||||
|
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||||
|
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||||
|
input wire [3-1:0] s_axi_arsize,
|
||||||
|
input wire [2-1:0] s_axi_arburst,
|
||||||
|
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||||
|
input wire [4-1:0] s_axi_arcache,
|
||||||
|
input wire [3-1:0] s_axi_arprot,
|
||||||
|
input wire [4-1:0] s_axi_arregion,
|
||||||
|
input wire [4-1:0] s_axi_arqos,
|
||||||
|
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||||
|
|
||||||
|
// Slave Interface Read Data Ports
|
||||||
|
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
|
||||||
|
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
|
||||||
|
output wire [2-1:0] s_axi_rresp,
|
||||||
|
output wire s_axi_rlast,
|
||||||
|
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||||
|
|
||||||
|
// payloads
|
||||||
|
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
|
||||||
|
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
|
||||||
|
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
|
||||||
|
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
|
||||||
|
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
|
||||||
|
);
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Functions
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
`include "axi_infrastructure_v1_1_0.vh"
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Local parameters
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Wires/Reg declarations
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// BEGIN RTL
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
// AXI4, AXI4LITE, AXI3 packing
|
||||||
|
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
|
||||||
|
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
|
||||||
|
|
||||||
|
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
|
||||||
|
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
|
||||||
|
|
||||||
|
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
|
||||||
|
|
||||||
|
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
|
||||||
|
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
|
||||||
|
|
||||||
|
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
|
||||||
|
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
|
||||||
|
|
||||||
|
generate
|
||||||
|
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||||
|
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
|
||||||
|
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
|
||||||
|
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
|
||||||
|
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
|
||||||
|
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
|
||||||
|
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
|
||||||
|
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
|
||||||
|
|
||||||
|
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
|
||||||
|
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||||
|
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
|
||||||
|
end
|
||||||
|
else begin : gen_no_axi3_wid_packing
|
||||||
|
end
|
||||||
|
|
||||||
|
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
|
||||||
|
|
||||||
|
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
|
||||||
|
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
|
||||||
|
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
|
||||||
|
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
|
||||||
|
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
|
||||||
|
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
|
||||||
|
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
|
||||||
|
|
||||||
|
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
|
||||||
|
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
|
||||||
|
|
||||||
|
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||||
|
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
|
||||||
|
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
|
||||||
|
end
|
||||||
|
else begin : gen_no_region_signals
|
||||||
|
end
|
||||||
|
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||||
|
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
|
||||||
|
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
|
||||||
|
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
|
||||||
|
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
|
||||||
|
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
|
||||||
|
end
|
||||||
|
else begin : gen_no_user_signals
|
||||||
|
assign s_axi_buser = 'b0;
|
||||||
|
assign s_axi_ruser = 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin : gen_axi4lite_packing
|
||||||
|
assign s_axi_bid = 'b0;
|
||||||
|
assign s_axi_buser = 'b0;
|
||||||
|
|
||||||
|
assign s_axi_rlast = 1'b1;
|
||||||
|
assign s_axi_rid = 'b0;
|
||||||
|
assign s_axi_ruser = 'b0;
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|
||||||
|
|
||||||
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//-----------------------------------------------------------------------------
|
||||||
|
// Description: SRL based FIFO for AXIS/AXI Channels.
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||||
|
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Parameter Definitions
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
parameter C_FAMILY = "virtex7",
|
||||||
|
parameter integer C_PAYLOAD_WIDTH = 1,
|
||||||
|
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
|
||||||
|
)
|
||||||
|
(
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Port Declarations
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
input wire aclk, // Clock
|
||||||
|
input wire aresetn, // Reset
|
||||||
|
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
|
||||||
|
input wire s_valid, // Input data valid
|
||||||
|
output reg s_ready, // Input data ready
|
||||||
|
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
|
||||||
|
output reg m_valid, // Output data valid
|
||||||
|
input wire m_ready // Output data ready
|
||||||
|
);
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Functions
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// ceiling logb2
|
||||||
|
function integer f_clogb2 (input integer size);
|
||||||
|
integer s;
|
||||||
|
begin
|
||||||
|
s = size;
|
||||||
|
s = s - 1;
|
||||||
|
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||||
|
s = s >> 1;
|
||||||
|
end
|
||||||
|
endfunction // clogb2
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Local parameters
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Wires/Reg declarations
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
|
||||||
|
wire [4-1:0] fifo_addr;
|
||||||
|
wire push;
|
||||||
|
wire pop ;
|
||||||
|
reg areset_r1;
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// BEGIN RTL
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
always @(posedge aclk) begin
|
||||||
|
areset_r1 <= ~aresetn;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge aclk) begin
|
||||||
|
if (~aresetn) begin
|
||||||
|
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
|
||||||
|
~push & pop ? fifo_index - 1'b1 :
|
||||||
|
fifo_index;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign push = s_valid & s_ready;
|
||||||
|
|
||||||
|
always @(posedge aclk) begin
|
||||||
|
if (~aresetn) begin
|
||||||
|
s_ready <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
s_ready <= areset_r1 ? 1'b1 :
|
||||||
|
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
|
||||||
|
~push & pop ? 1'b1 :
|
||||||
|
s_ready;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign pop = m_valid & m_ready;
|
||||||
|
|
||||||
|
always @(posedge aclk) begin
|
||||||
|
if (~aresetn) begin
|
||||||
|
m_valid <= 1'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
|
||||||
|
push & ~pop ? 1'b1 :
|
||||||
|
m_valid;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
generate
|
||||||
|
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
|
||||||
|
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||||
|
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
|
||||||
|
end
|
||||||
|
else begin : gen_fifo_addr
|
||||||
|
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
generate
|
||||||
|
genvar i;
|
||||||
|
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
|
||||||
|
SRL16E
|
||||||
|
u_srl_fifo(
|
||||||
|
.Q ( m_payload[i] ) ,
|
||||||
|
.A0 ( fifo_addr[0] ) ,
|
||||||
|
.A1 ( fifo_addr[1] ) ,
|
||||||
|
.A2 ( fifo_addr[2] ) ,
|
||||||
|
.A3 ( fifo_addr[3] ) ,
|
||||||
|
.CE ( push ) ,
|
||||||
|
.CLK ( aclk ) ,
|
||||||
|
.D ( s_payload[i] )
|
||||||
|
);
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|
||||||
|
|
||||||
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//-----------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// axi to vector
|
||||||
|
// A generic module to merge all axi signals into one signal called payload.
|
||||||
|
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||||
|
//
|
||||||
|
// Verilog-standard: Verilog 2001
|
||||||
|
//--------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||||
|
module axi_infrastructure_v1_1_0_vector2axi #
|
||||||
|
(
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Parameter Definitions
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
parameter integer C_AXI_PROTOCOL = 0,
|
||||||
|
parameter integer C_AXI_ID_WIDTH = 4,
|
||||||
|
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||||
|
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||||
|
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||||
|
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||||
|
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||||
|
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||||
|
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||||
|
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||||
|
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||||
|
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||||
|
)
|
||||||
|
(
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Port Declarations
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Slave Interface Write Address Ports
|
||||||
|
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||||
|
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||||
|
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||||
|
output wire [3-1:0] m_axi_awsize,
|
||||||
|
output wire [2-1:0] m_axi_awburst,
|
||||||
|
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||||
|
output wire [4-1:0] m_axi_awcache,
|
||||||
|
output wire [3-1:0] m_axi_awprot,
|
||||||
|
output wire [4-1:0] m_axi_awregion,
|
||||||
|
output wire [4-1:0] m_axi_awqos,
|
||||||
|
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||||
|
|
||||||
|
// Slave Interface Write Data Ports
|
||||||
|
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
|
||||||
|
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||||
|
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||||
|
output wire m_axi_wlast,
|
||||||
|
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||||
|
|
||||||
|
// Slave Interface Write Response Ports
|
||||||
|
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||||
|
input wire [2-1:0] m_axi_bresp,
|
||||||
|
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||||
|
|
||||||
|
// Slave Interface Read Address Ports
|
||||||
|
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||||
|
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||||
|
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||||
|
output wire [3-1:0] m_axi_arsize,
|
||||||
|
output wire [2-1:0] m_axi_arburst,
|
||||||
|
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||||
|
output wire [4-1:0] m_axi_arcache,
|
||||||
|
output wire [3-1:0] m_axi_arprot,
|
||||||
|
output wire [4-1:0] m_axi_arregion,
|
||||||
|
output wire [4-1:0] m_axi_arqos,
|
||||||
|
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||||
|
|
||||||
|
// Slave Interface Read Data Ports
|
||||||
|
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||||
|
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||||
|
input wire [2-1:0] m_axi_rresp,
|
||||||
|
input wire m_axi_rlast,
|
||||||
|
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||||
|
|
||||||
|
// payloads
|
||||||
|
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
|
||||||
|
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
|
||||||
|
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
|
||||||
|
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
|
||||||
|
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
|
||||||
|
);
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Functions
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
`include "axi_infrastructure_v1_1_0.vh"
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Local parameters
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Wires/Reg declarations
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// BEGIN RTL
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
// AXI4, AXI4LITE, AXI3 packing
|
||||||
|
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
|
||||||
|
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
|
||||||
|
|
||||||
|
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
|
||||||
|
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
|
||||||
|
|
||||||
|
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
|
||||||
|
|
||||||
|
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
|
||||||
|
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
|
||||||
|
|
||||||
|
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
|
||||||
|
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
|
||||||
|
|
||||||
|
generate
|
||||||
|
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||||
|
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
|
||||||
|
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
|
||||||
|
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
|
||||||
|
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
|
||||||
|
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
|
||||||
|
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
|
||||||
|
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
|
||||||
|
|
||||||
|
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
|
||||||
|
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||||
|
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
|
||||||
|
end
|
||||||
|
else begin : gen_no_axi3_wid_packing
|
||||||
|
assign m_axi_wid = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
|
||||||
|
|
||||||
|
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
|
||||||
|
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
|
||||||
|
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
|
||||||
|
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
|
||||||
|
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
|
||||||
|
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
|
||||||
|
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
|
||||||
|
|
||||||
|
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
|
||||||
|
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
|
||||||
|
|
||||||
|
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||||
|
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
|
||||||
|
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
|
||||||
|
end
|
||||||
|
else begin : gen_no_region_signals
|
||||||
|
assign m_axi_awregion = 'b0;
|
||||||
|
assign m_axi_arregion = 'b0;
|
||||||
|
end
|
||||||
|
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||||
|
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
|
||||||
|
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
|
||||||
|
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
|
||||||
|
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
|
||||||
|
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
|
||||||
|
end
|
||||||
|
else begin : gen_no_user_signals
|
||||||
|
assign m_axi_awuser = 'b0;
|
||||||
|
assign m_axi_wuser = 'b0;
|
||||||
|
assign m_axi_aruser = 'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin : gen_axi4lite_packing
|
||||||
|
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||||
|
assign m_axi_awburst = 'b0;
|
||||||
|
assign m_axi_awcache = 'b0;
|
||||||
|
assign m_axi_awlen = 'b0;
|
||||||
|
assign m_axi_awlock = 'b0;
|
||||||
|
assign m_axi_awid = 'b0;
|
||||||
|
assign m_axi_awqos = 'b0;
|
||||||
|
|
||||||
|
assign m_axi_wlast = 1'b1;
|
||||||
|
assign m_axi_wid = 'b0;
|
||||||
|
|
||||||
|
|
||||||
|
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||||
|
assign m_axi_arburst = 'b0;
|
||||||
|
assign m_axi_arcache = 'b0;
|
||||||
|
assign m_axi_arlen = 'b0;
|
||||||
|
assign m_axi_arlock = 'b0;
|
||||||
|
assign m_axi_arid = 'b0;
|
||||||
|
assign m_axi_arqos = 'b0;
|
||||||
|
|
||||||
|
assign m_axi_awregion = 'b0;
|
||||||
|
assign m_axi_arregion = 'b0;
|
||||||
|
|
||||||
|
assign m_axi_awuser = 'b0;
|
||||||
|
assign m_axi_wuser = 'b0;
|
||||||
|
assign m_axi_aruser = 'b0;
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
95
project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
Normal file
95
project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
Normal file
@@ -0,0 +1,95 @@
|
|||||||
|
{
|
||||||
|
"ActiveEmotionalView":"Default View",
|
||||||
|
"Default View_ScaleFactor":"1.10748",
|
||||||
|
"Default View_TopLeft":"939,944",
|
||||||
|
"ExpandedHierarchyInLayout":"",
|
||||||
|
"guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
|
||||||
|
# -string -flagsOSRD
|
||||||
|
preplace port UART_0 -pg 1 -lvl 7 -x 2500 -y 470 -defaultsOSRD
|
||||||
|
preplace port axil_descriptors -pg 1 -lvl 7 -x 2500 -y 1550 -defaultsOSRD
|
||||||
|
preplace port axil_dma_ctrl0 -pg 1 -lvl 7 -x 2500 -y 1580 -defaultsOSRD
|
||||||
|
preplace port axil_dma_ctrl1 -pg 1 -lvl 7 -x 2500 -y 1610 -defaultsOSRD
|
||||||
|
preplace port axil_util -pg 1 -lvl 7 -x 2500 -y 1640 -defaultsOSRD
|
||||||
|
preplace port pcie_mgt_0 -pg 1 -lvl 7 -x 2500 -y 1100 -defaultsOSRD
|
||||||
|
preplace port pcie_refclk -pg 1 -lvl 0 -x -30 -y 1350 -defaultsOSRD
|
||||||
|
preplace port sys_clk -pg 1 -lvl 0 -x -30 -y 800 -defaultsOSRD
|
||||||
|
preplace port axil_timing -pg 1 -lvl 7 -x 2500 -y 1670 -defaultsOSRD
|
||||||
|
preplace port axil_data_gen -pg 1 -lvl 7 -x 2500 -y 1700 -defaultsOSRD
|
||||||
|
preplace port pcie_m_axi0 -pg 1 -lvl 0 -x -30 -y 1030 -defaultsOSRD
|
||||||
|
preplace port pcie_m_axi1 -pg 1 -lvl 0 -x -30 -y 1060 -defaultsOSRD
|
||||||
|
preplace port port-id_axi_pcie_aresetn -pg 1 -lvl 7 -x 2500 -y 1190 -defaultsOSRD
|
||||||
|
preplace port port-id_axi_pcie_clk -pg 1 -lvl 7 -x 2500 -y 1880 -defaultsOSRD
|
||||||
|
preplace port port-id_axil_clk -pg 1 -lvl 7 -x 2500 -y 790 -defaultsOSRD
|
||||||
|
preplace port port-id_pcie_rstn -pg 1 -lvl 0 -x -30 -y 1400 -defaultsOSRD
|
||||||
|
preplace port port-id_pcie_user_lnk_up -pg 1 -lvl 7 -x 2500 -y 1160 -defaultsOSRD
|
||||||
|
preplace portBus axil_resetn -pg 1 -lvl 7 -x 2500 -y 820 -defaultsOSRD
|
||||||
|
preplace portBus pcie_cfg_ltssm_state -pg 1 -lvl 7 -x 2500 -y 1130 -defaultsOSRD
|
||||||
|
preplace portBus usr_irq_req -pg 1 -lvl 0 -x -30 -y 1430 -defaultsOSRD
|
||||||
|
preplace inst axi_interconnect_0 -pg 1 -lvl 5 -x 1560 -y 320 -defaultsOSRD
|
||||||
|
preplace inst axi_timer_0 -pg 1 -lvl 6 -x 2140 -y 290 -defaultsOSRD
|
||||||
|
preplace inst axi_uartlite_0 -pg 1 -lvl 6 -x 2140 -y 480 -defaultsOSRD
|
||||||
|
preplace inst clk_wiz_1 -pg 1 -lvl 5 -x 1560 -y 800 -defaultsOSRD
|
||||||
|
preplace inst mdm_1 -pg 1 -lvl 3 -x 710 -y 870 -defaultsOSRD
|
||||||
|
preplace inst microblaze_0 -pg 1 -lvl 4 -x 1100 -y 660 -defaultsOSRD
|
||||||
|
preplace inst microblaze_0_axi_intc -pg 1 -lvl 3 -x 710 -y 640 -defaultsOSRD
|
||||||
|
preplace inst microblaze_0_axi_periph -pg 1 -lvl 6 -x 2140 -y 1610 -defaultsOSRD
|
||||||
|
preplace inst microblaze_0_local_memory -pg 1 -lvl 5 -x 1560 -y 670 -defaultsOSRD
|
||||||
|
preplace inst microblaze_0_xlconcat -pg 1 -lvl 2 -x 370 -y 720 -defaultsOSRD
|
||||||
|
preplace inst rst_clk_wiz_1_100M -pg 1 -lvl 2 -x 370 -y 920 -defaultsOSRD
|
||||||
|
preplace inst system_management_wiz_0 -pg 1 -lvl 6 -x 2140 -y 680 -defaultsOSRD
|
||||||
|
preplace inst util_ds_buf_0 -pg 1 -lvl 4 -x 1100 -y 1350 -defaultsOSRD
|
||||||
|
preplace inst xdma_0 -pg 1 -lvl 5 -x 1560 -y 1440 -defaultsOSRD
|
||||||
|
preplace inst xlconstant_0 -pg 1 -lvl 1 -x 70 -y 900 -defaultsOSRD
|
||||||
|
preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 6 -x 2140 -y 100 -defaultsOSRD
|
||||||
|
preplace inst axi_interconnect_1 -pg 1 -lvl 4 -x 1100 -y 1130 -defaultsOSRD
|
||||||
|
preplace netloc S01_ARESETN_1 1 3 4 860 1280 1370J 1270 1720 1300 2480J
|
||||||
|
preplace netloc axi_timer_0_interrupt 1 1 6 160 500 NJ 500 NJ 500 1360J 520 1790J 560 2480
|
||||||
|
preplace netloc axi_uartlite_0_interrupt 1 1 6 150 100 NJ 100 NJ 100 NJ 100 1810J 400 2450
|
||||||
|
preplace netloc clk_wiz_1_locked 1 1 5 170 810 580J 780 NJ 780 1360J 870 1740
|
||||||
|
preplace netloc mdm_1_debug_sys_rst 1 1 3 190 820 590J 790 830
|
||||||
|
preplace netloc microblaze_0_Clk 1 1 6 180 640 580 530 850 560 1390 110 1800 790 NJ
|
||||||
|
preplace netloc microblaze_0_intr 1 2 1 550 650n
|
||||||
|
preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 2 3 550 940 840J 570 1360J
|
||||||
|
preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 2 570 520 860J
|
||||||
|
preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 2 5 560 460 NJ 460 1360 120 1780 820 NJ
|
||||||
|
preplace netloc sys_rst_n_0_1 1 0 5 NJ 1400 NJ 1400 NJ 1400 830J 1470 NJ
|
||||||
|
preplace netloc system_management_wiz_0_ip2intc_irpt 1 1 6 170 510 NJ 510 870J 530 NJ 530 1720J 570 2450
|
||||||
|
preplace netloc usr_irq_req_0_1 1 0 5 NJ 1430 NJ 1430 NJ 1430 NJ 1430 1330J
|
||||||
|
preplace netloc util_ds_buf_0_IBUF_DS_ODIV2 1 4 1 1340 1360n
|
||||||
|
preplace netloc util_ds_buf_0_IBUF_OUT 1 4 1 1350 1340n
|
||||||
|
preplace netloc xdma_0_axi_aclk 1 3 4 840 1420 1380J 1280 1740 1880 NJ
|
||||||
|
preplace netloc xdma_0_axi_ctl_aresetn 1 5 1 1820 1460n
|
||||||
|
preplace netloc xdma_0_cfg_ltssm_state 1 5 2 1790J 1280 2460J
|
||||||
|
preplace netloc xdma_0_user_lnk_up 1 5 2 1730J 1290 2470J
|
||||||
|
preplace netloc xlconstant_0_dout 1 1 1 150 900n
|
||||||
|
preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 5 2 1820 10 2480
|
||||||
|
preplace netloc CLK_IN1_D_0_1 1 0 5 NJ 800 NJ 800 NJ 800 NJ 800 NJ
|
||||||
|
preplace netloc CLK_IN_D_0_1 1 0 4 NJ 1350 NJ 1350 NJ 1350 NJ
|
||||||
|
preplace netloc S00_AXI_0_1 1 0 4 NJ 1030 NJ 1030 NJ 1030 850J
|
||||||
|
preplace netloc S00_AXI_1 1 4 1 1340 180n
|
||||||
|
preplace netloc S01_AXI_0_1 1 0 4 NJ 1060 NJ 1060 NJ 1060 NJ
|
||||||
|
preplace netloc axi_interconnect_0_M00_AXI 1 2 4 590 90 NJ 90 NJ 90 1740
|
||||||
|
preplace netloc axi_interconnect_0_M01_AXI 1 5 1 1770 240n
|
||||||
|
preplace netloc axi_interconnect_0_M02_AXI 1 5 1 1790 320n
|
||||||
|
preplace netloc axi_interconnect_0_M03_AXI 1 5 1 1740 340n
|
||||||
|
preplace netloc axi_interconnect_0_M04_AXI 1 5 1 1770 360n
|
||||||
|
preplace netloc axi_interconnect_1_M00_AXI 1 4 1 1360 1130n
|
||||||
|
preplace netloc axi_uartlite_0_UART 1 6 1 NJ 470
|
||||||
|
preplace netloc microblaze_0_axi_periph_M00_AXI 1 4 3 1390 1260 NJ 1260 2440
|
||||||
|
preplace netloc microblaze_0_axi_periph_M01_AXI 1 6 1 2470J 1550n
|
||||||
|
preplace netloc microblaze_0_axi_periph_M02_AXI 1 6 1 2460J 1580n
|
||||||
|
preplace netloc microblaze_0_axi_periph_M03_AXI 1 6 1 NJ 1610
|
||||||
|
preplace netloc microblaze_0_axi_periph_M04_AXI 1 6 1 2460J 1630n
|
||||||
|
preplace netloc microblaze_0_axi_periph_M05_AXI 1 6 1 2470J 1650n
|
||||||
|
preplace netloc microblaze_0_axi_periph_M06_AXI 1 6 1 2450J 1670n
|
||||||
|
preplace netloc microblaze_0_debug 1 3 1 870 650n
|
||||||
|
preplace netloc microblaze_0_dlmb_1 1 4 1 N 640
|
||||||
|
preplace netloc microblaze_0_ilmb_1 1 4 1 N 660
|
||||||
|
preplace netloc microblaze_0_interrupt 1 3 1 830 630n
|
||||||
|
preplace netloc xdma_0_M_AXI_B 1 5 1 1750 1340n
|
||||||
|
preplace netloc xdma_0_pcie_mgt 1 5 2 1760J 1270 2450J
|
||||||
|
levelinfo -pg 1 -30 70 370 710 1100 1560 2140 2500
|
||||||
|
pagesize -pg 1 -db -bbox -sgen -190 0 2720 1970
|
||||||
|
"
|
||||||
|
}
|
||||||
|
0
|
||||||
142
project_1.srcs/sources_1/hdl/axi_descriptor.sv
Executable file
142
project_1.srcs/sources_1/hdl/axi_descriptor.sv
Executable file
@@ -0,0 +1,142 @@
|
|||||||
|
module axi_descriptor #
|
||||||
|
(
|
||||||
|
parameter integer DESCRIPTOR_WIDTH = 128,
|
||||||
|
parameter integer DESCRIPTOR_LENGTH = 1
|
||||||
|
)
|
||||||
|
(
|
||||||
|
axi4l_intf.slave axi,
|
||||||
|
input [DESCRIPTOR_WIDTH-1:0] descriptor_list[DESCRIPTOR_LENGTH]
|
||||||
|
);
|
||||||
|
|
||||||
|
// incoming pipeline of write address
|
||||||
|
reg awaddr_valid;
|
||||||
|
reg [axi.AXI_ADDR_WIDTH-1:0] awaddr;
|
||||||
|
|
||||||
|
// incoming pipeline of write data
|
||||||
|
reg wdata_valid;
|
||||||
|
reg [((axi.AXI_DATA_WIDTH/8)-1):0] wstrb;
|
||||||
|
reg [axi.AXI_DATA_WIDTH-1:0] wdata;
|
||||||
|
|
||||||
|
// incoming pipeline of read address
|
||||||
|
reg araddr_valid;
|
||||||
|
reg [axi.AXI_ADDR_WIDTH:0] araddr;
|
||||||
|
|
||||||
|
// outgoing pipeline of read data
|
||||||
|
reg rvalid;
|
||||||
|
reg [axi.AXI_DATA_WIDTH-1:0] rdata;
|
||||||
|
|
||||||
|
integer descriptor_index1, descriptor_index2;
|
||||||
|
|
||||||
|
// ready while data hasn't been latched and still waiting
|
||||||
|
// for acknowledgement to our response
|
||||||
|
assign axi.awready = !awaddr_valid && !axi.bvalid;
|
||||||
|
assign axi.wready = !wdata_valid && !axi.bvalid;
|
||||||
|
|
||||||
|
always @( posedge axi.clk )
|
||||||
|
begin
|
||||||
|
if ( axi.resetn == 1'b0 ) begin
|
||||||
|
awaddr_valid <= 1'b0;
|
||||||
|
awaddr <= 'b0;
|
||||||
|
wdata_valid <= 1'b0;
|
||||||
|
wstrb <= 'b0;
|
||||||
|
wdata <= 'b0;
|
||||||
|
axi.bvalid <= 1'b0;
|
||||||
|
axi.bresp <= 2'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// latch awaddr and valid signal
|
||||||
|
if (axi.awready && axi.awvalid) begin
|
||||||
|
awaddr_valid <= 1'b1;
|
||||||
|
awaddr <= axi.awaddr;
|
||||||
|
end
|
||||||
|
|
||||||
|
// latch wirte data and valid signal
|
||||||
|
if (axi.wready && axi.wvalid) begin
|
||||||
|
wdata_valid <= 1'b1;
|
||||||
|
wstrb <= axi.wstrb;
|
||||||
|
wdata <= axi.wdata;
|
||||||
|
end
|
||||||
|
|
||||||
|
// clear valids when both high;
|
||||||
|
// data needs to be consumed on this same condition
|
||||||
|
if (awaddr_valid && wdata_valid && !axi.bvalid) begin
|
||||||
|
awaddr_valid <= 1'b0;
|
||||||
|
wdata_valid <= 1'b0;
|
||||||
|
|
||||||
|
axi.bvalid <= 1'b1;
|
||||||
|
axi.bresp <= 2'b0; // 'OKAY' response
|
||||||
|
end
|
||||||
|
|
||||||
|
// clear bvalid when it has been acknowledged
|
||||||
|
if (axi.bvalid && axi.bready) begin
|
||||||
|
axi.bvalid <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// ready while data hasn't been latched and still waiting
|
||||||
|
// for acknowledgement to our response
|
||||||
|
assign axi.arready = !araddr_valid && !axi.rvalid;
|
||||||
|
|
||||||
|
always @( posedge axi.clk )
|
||||||
|
begin
|
||||||
|
if ( axi.resetn == 1'b0 ) begin
|
||||||
|
araddr_valid <= 1'b0;
|
||||||
|
araddr <= 'b0;
|
||||||
|
axi.rvalid <= 1'b0;
|
||||||
|
axi.rresp <= 2'b0;
|
||||||
|
axi.rdata <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// latch araddr and valid signal
|
||||||
|
if (axi.arready && axi.arvalid) begin
|
||||||
|
araddr_valid <= 1'b1;
|
||||||
|
araddr <= axi.araddr;
|
||||||
|
end
|
||||||
|
|
||||||
|
// if address is valid and rdata has been latched;
|
||||||
|
// set axi bus rdata and valid signal
|
||||||
|
if (araddr_valid && rvalid && !axi.rvalid) begin
|
||||||
|
araddr_valid <= 1'b0;
|
||||||
|
|
||||||
|
axi.rvalid <= 1'b1;
|
||||||
|
axi.rresp <= 2'b0; // 'OKAY' response
|
||||||
|
axi.rdata <= rdata;
|
||||||
|
end
|
||||||
|
|
||||||
|
// clear rvalid when it has been acknowledged
|
||||||
|
if (axi.rvalid && axi.rready) begin
|
||||||
|
axi.rvalid <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( posedge axi.clk )
|
||||||
|
begin
|
||||||
|
if ( axi.resetn == 1'b0 ) begin
|
||||||
|
rvalid <= 1'b0;
|
||||||
|
rdata <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
|
||||||
|
// by default rvalid is low; unless read address is valid;
|
||||||
|
// latch appropriate data and set valid signal
|
||||||
|
rvalid <= 1'b0;
|
||||||
|
rdata <= 'b0;
|
||||||
|
if (araddr_valid) begin
|
||||||
|
for ( descriptor_index2 = 0; descriptor_index2 < DESCRIPTOR_LENGTH; descriptor_index2 = descriptor_index2+1 ) begin
|
||||||
|
for ( descriptor_index1 = 0; descriptor_index1 < (DESCRIPTOR_WIDTH/32); descriptor_index1 = descriptor_index1+1 ) begin
|
||||||
|
if ( araddr[7:0] == (((descriptor_index2 * (DESCRIPTOR_WIDTH/32)) + descriptor_index1) * 4) ) begin
|
||||||
|
rdata <= descriptor_list[descriptor_index2][descriptor_index1*32 +: 32];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
rvalid <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
281
project_1.srcs/sources_1/hdl/axi_intf.sv
Executable file
281
project_1.srcs/sources_1/hdl/axi_intf.sv
Executable file
@@ -0,0 +1,281 @@
|
|||||||
|
interface axi4_intf#(
|
||||||
|
// Width of S_AXI address araddr
|
||||||
|
parameter integer AXI_ADDR_WIDTH = 32,
|
||||||
|
// Width of S_AXI data bus
|
||||||
|
parameter integer AXI_DATA_WIDTH = 32
|
||||||
|
|
||||||
|
) (
|
||||||
|
input wire clk,
|
||||||
|
input wire resetn
|
||||||
|
);
|
||||||
|
|
||||||
|
logic [(AXI_ADDR_WIDTH-1):0] araddr;
|
||||||
|
logic [ 1:0] arburst;
|
||||||
|
logic [ 3:0] arcache;
|
||||||
|
logic [ 7:0] arlen;
|
||||||
|
logic arlock;
|
||||||
|
logic [ 2:0] arprot;
|
||||||
|
logic [ 3:0] arqos;
|
||||||
|
logic arready;
|
||||||
|
logic [ 2:0] arsize;
|
||||||
|
logic arvalid;
|
||||||
|
|
||||||
|
logic [(AXI_ADDR_WIDTH-1):0] awaddr;
|
||||||
|
logic [ 1:0] awburst;
|
||||||
|
logic [ 3:0] awcache;
|
||||||
|
logic [ 7:0] awlen;
|
||||||
|
logic awlock;
|
||||||
|
logic [ 2:0] awprot;
|
||||||
|
logic [ 3:0] awqos;
|
||||||
|
logic awready;
|
||||||
|
logic [ 2:0] awsize;
|
||||||
|
logic awvalid;
|
||||||
|
|
||||||
|
logic bready;
|
||||||
|
logic [1:0] bresp;
|
||||||
|
logic bvalid;
|
||||||
|
|
||||||
|
logic [(AXI_DATA_WIDTH-1):0] rdata;
|
||||||
|
logic rlast;
|
||||||
|
logic rready;
|
||||||
|
logic [1:0] rresp;
|
||||||
|
logic rvalid;
|
||||||
|
|
||||||
|
logic [(AXI_DATA_WIDTH-1):0] wdata;
|
||||||
|
logic wlast;
|
||||||
|
logic wready;
|
||||||
|
logic [((AXI_DATA_WIDTH/8)-1):0] wstrb;
|
||||||
|
logic wvalid;
|
||||||
|
|
||||||
|
modport master (
|
||||||
|
input clk,
|
||||||
|
input resetn,
|
||||||
|
|
||||||
|
output araddr,
|
||||||
|
output arburst,
|
||||||
|
output arcache,
|
||||||
|
output arlen,
|
||||||
|
output arlock,
|
||||||
|
output arprot,
|
||||||
|
output arqos,
|
||||||
|
input arready,
|
||||||
|
output arsize,
|
||||||
|
output arvalid,
|
||||||
|
|
||||||
|
output awaddr,
|
||||||
|
output awburst,
|
||||||
|
output awcache,
|
||||||
|
output awlen,
|
||||||
|
output awlock,
|
||||||
|
output awprot,
|
||||||
|
output awqos,
|
||||||
|
input awready,
|
||||||
|
output awsize,
|
||||||
|
output awvalid,
|
||||||
|
|
||||||
|
output bready,
|
||||||
|
input bresp,
|
||||||
|
input bvalid,
|
||||||
|
|
||||||
|
input rdata,
|
||||||
|
input rlast,
|
||||||
|
output rready,
|
||||||
|
input rresp,
|
||||||
|
input rvalid,
|
||||||
|
|
||||||
|
output wdata,
|
||||||
|
output wlast,
|
||||||
|
input wready,
|
||||||
|
output wstrb,
|
||||||
|
output wvalid);
|
||||||
|
|
||||||
|
modport slave (
|
||||||
|
input clk,
|
||||||
|
input resetn,
|
||||||
|
|
||||||
|
input araddr,
|
||||||
|
input arburst,
|
||||||
|
input arcache,
|
||||||
|
input arlen,
|
||||||
|
input arlock,
|
||||||
|
input arprot,
|
||||||
|
input arqos,
|
||||||
|
output arready,
|
||||||
|
input arsize,
|
||||||
|
input arvalid,
|
||||||
|
|
||||||
|
input awaddr,
|
||||||
|
input awburst,
|
||||||
|
input awcache,
|
||||||
|
input awlen,
|
||||||
|
input awlock,
|
||||||
|
input awprot,
|
||||||
|
input awqos,
|
||||||
|
output awready,
|
||||||
|
input awsize,
|
||||||
|
input awvalid,
|
||||||
|
|
||||||
|
input bready,
|
||||||
|
output bresp,
|
||||||
|
output bvalid,
|
||||||
|
|
||||||
|
output rdata,
|
||||||
|
output rlast,
|
||||||
|
input rready,
|
||||||
|
output rresp,
|
||||||
|
output rvalid,
|
||||||
|
|
||||||
|
input wdata,
|
||||||
|
input wlast,
|
||||||
|
output wready,
|
||||||
|
input wstrb,
|
||||||
|
input wvalid);
|
||||||
|
|
||||||
|
endinterface
|
||||||
|
|
||||||
|
|
||||||
|
interface axi4l_intf#(
|
||||||
|
// Width of S_AXI address araddr
|
||||||
|
parameter integer AXI_ADDR_WIDTH = 32,
|
||||||
|
// Width of S_AXI data bus
|
||||||
|
parameter integer AXI_DATA_WIDTH = 32
|
||||||
|
|
||||||
|
) (
|
||||||
|
input wire clk,
|
||||||
|
input wire resetn
|
||||||
|
);
|
||||||
|
|
||||||
|
logic [(AXI_ADDR_WIDTH-1):0] araddr;
|
||||||
|
logic [2:0] arprot;
|
||||||
|
logic arready;
|
||||||
|
logic arvalid;
|
||||||
|
|
||||||
|
logic [(AXI_ADDR_WIDTH-1):0] awaddr;
|
||||||
|
logic [2:0] awprot;
|
||||||
|
logic awready;
|
||||||
|
logic awvalid;
|
||||||
|
|
||||||
|
logic bready;
|
||||||
|
logic [1:0] bresp;
|
||||||
|
logic bvalid;
|
||||||
|
|
||||||
|
logic [(AXI_DATA_WIDTH-1):0] rdata;
|
||||||
|
logic rready;
|
||||||
|
logic [1:0] rresp;
|
||||||
|
logic rvalid;
|
||||||
|
|
||||||
|
logic [(AXI_DATA_WIDTH-1):0] wdata;
|
||||||
|
logic wready;
|
||||||
|
logic [((AXI_DATA_WIDTH/8)-1):0] wstrb;
|
||||||
|
logic wvalid;
|
||||||
|
|
||||||
|
modport master (
|
||||||
|
input clk,
|
||||||
|
input resetn,
|
||||||
|
|
||||||
|
output araddr,
|
||||||
|
output arprot,
|
||||||
|
input arready,
|
||||||
|
output arvalid,
|
||||||
|
|
||||||
|
output awaddr,
|
||||||
|
output awprot,
|
||||||
|
input awready,
|
||||||
|
output awvalid,
|
||||||
|
|
||||||
|
output bready,
|
||||||
|
input bresp,
|
||||||
|
input bvalid,
|
||||||
|
|
||||||
|
input rdata,
|
||||||
|
output rready,
|
||||||
|
input rresp,
|
||||||
|
input rvalid,
|
||||||
|
|
||||||
|
output wdata,
|
||||||
|
input wready,
|
||||||
|
output wstrb,
|
||||||
|
output wvalid);
|
||||||
|
|
||||||
|
modport slave (
|
||||||
|
input clk,
|
||||||
|
input resetn,
|
||||||
|
|
||||||
|
input araddr,
|
||||||
|
input arprot,
|
||||||
|
output arready,
|
||||||
|
input arvalid,
|
||||||
|
|
||||||
|
input awaddr,
|
||||||
|
input awprot,
|
||||||
|
output awready,
|
||||||
|
input awvalid,
|
||||||
|
|
||||||
|
input bready,
|
||||||
|
output bresp,
|
||||||
|
output bvalid,
|
||||||
|
|
||||||
|
output rdata,
|
||||||
|
input rready,
|
||||||
|
output rresp,
|
||||||
|
output rvalid,
|
||||||
|
|
||||||
|
input wdata,
|
||||||
|
output wready,
|
||||||
|
input wstrb,
|
||||||
|
input wvalid);
|
||||||
|
|
||||||
|
endinterface
|
||||||
|
|
||||||
|
interface axi4s_intf#(
|
||||||
|
// Width of S_AXI data bus
|
||||||
|
parameter integer AXI_DATA_WIDTH = 32,
|
||||||
|
parameter integer AXI_ID_WIDTH = 4,
|
||||||
|
parameter integer AXI_DEST_WIDTH = 4,
|
||||||
|
parameter integer AXI_USER_WIDTH = 4
|
||||||
|
|
||||||
|
) (
|
||||||
|
input wire clk,
|
||||||
|
input wire resetn
|
||||||
|
);
|
||||||
|
|
||||||
|
logic [(AXI_DATA_WIDTH-1):0] tdata;
|
||||||
|
logic tready;
|
||||||
|
logic [((AXI_DATA_WIDTH/8)-1):0] tstrb;
|
||||||
|
logic [((AXI_DATA_WIDTH/8)-1):0] tkeep;
|
||||||
|
logic tvalid;
|
||||||
|
logic tlast;
|
||||||
|
logic [(AXI_ID_WIDTH-1):0] tid;
|
||||||
|
logic [(AXI_DEST_WIDTH-1):0] tdest;
|
||||||
|
logic [(AXI_USER_WIDTH-1):0] tuser;
|
||||||
|
|
||||||
|
modport master (
|
||||||
|
input clk,
|
||||||
|
input resetn,
|
||||||
|
|
||||||
|
output tdata,
|
||||||
|
input tready,
|
||||||
|
output tstrb,
|
||||||
|
output tkeep,
|
||||||
|
output tvalid,
|
||||||
|
output tlast,
|
||||||
|
output tid,
|
||||||
|
output tdest,
|
||||||
|
output tuser);
|
||||||
|
|
||||||
|
modport slave (
|
||||||
|
input clk,
|
||||||
|
input resetn,
|
||||||
|
|
||||||
|
input tdata,
|
||||||
|
output tready,
|
||||||
|
input tstrb,
|
||||||
|
input tkeep,
|
||||||
|
input tvalid,
|
||||||
|
input tlast,
|
||||||
|
input tid,
|
||||||
|
input tdest,
|
||||||
|
input tuser);
|
||||||
|
|
||||||
|
|
||||||
|
endinterface
|
||||||
294
project_1.srcs/sources_1/hdl/axil_slave.v
Executable file
294
project_1.srcs/sources_1/hdl/axil_slave.v
Executable file
@@ -0,0 +1,294 @@
|
|||||||
|
|
||||||
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
module axil_slave #
|
||||||
|
(
|
||||||
|
parameter integer DATA_WIDTH = 32,
|
||||||
|
parameter integer ADDR_WIDTH = 9
|
||||||
|
)
|
||||||
|
(
|
||||||
|
// AXIL Slave
|
||||||
|
input wire S_AXI_ACLK,
|
||||||
|
input wire S_AXI_ARESETN,
|
||||||
|
input wire [ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
|
||||||
|
input wire [2 : 0] S_AXI_AWPROT,
|
||||||
|
input wire S_AXI_AWVALID,
|
||||||
|
output wire S_AXI_AWREADY,
|
||||||
|
input wire [DATA_WIDTH-1 : 0] S_AXI_WDATA,
|
||||||
|
input wire [(DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
|
||||||
|
input wire S_AXI_WVALID,
|
||||||
|
output wire S_AXI_WREADY,
|
||||||
|
output wire [1 : 0] S_AXI_BRESP,
|
||||||
|
output wire S_AXI_BVALID,
|
||||||
|
input wire S_AXI_BREADY,
|
||||||
|
input wire [ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
|
||||||
|
input wire [2 : 0] S_AXI_ARPROT,
|
||||||
|
input wire S_AXI_ARVALID,
|
||||||
|
output wire S_AXI_ARREADY,
|
||||||
|
output wire [DATA_WIDTH-1 : 0] S_AXI_RDATA,
|
||||||
|
output wire [1 : 0] S_AXI_RRESP,
|
||||||
|
output wire S_AXI_RVALID,
|
||||||
|
input wire S_AXI_RREADY,
|
||||||
|
|
||||||
|
output wire [ADDR_WIDTH-1 : 0] raddr,
|
||||||
|
output wire [ADDR_WIDTH-1 : 0] waddr,
|
||||||
|
output wire wren,
|
||||||
|
output wire rden,
|
||||||
|
output wire [DATA_WIDTH-1 : 0] wdata,
|
||||||
|
input wire [DATA_WIDTH-1 : 0] rdata
|
||||||
|
);
|
||||||
|
|
||||||
|
// AXI4LITE signals
|
||||||
|
reg [ADDR_WIDTH-1 : 0] axi_awaddr;
|
||||||
|
reg axi_awready;
|
||||||
|
reg axi_wready;
|
||||||
|
reg [1 : 0] axi_bresp;
|
||||||
|
reg axi_bvalid;
|
||||||
|
reg [ADDR_WIDTH-1 : 0] axi_araddr;
|
||||||
|
reg axi_arready;
|
||||||
|
wire [DATA_WIDTH-1 : 0] axi_rdata;
|
||||||
|
reg [1 : 0] axi_rresp;
|
||||||
|
reg axi_rvalid;
|
||||||
|
|
||||||
|
// Example-specific design signals
|
||||||
|
// local parameter for addressing 32 bit / 64 bit DATA_WIDTH
|
||||||
|
// ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||||
|
// ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||||
|
// ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||||
|
localparam integer ADDR_LSB = (DATA_WIDTH/32) + 1;
|
||||||
|
localparam integer OPT_MEM_ADDR_BITS = 6;
|
||||||
|
|
||||||
|
wire slv_reg_rden;
|
||||||
|
wire slv_reg_wren;
|
||||||
|
wire [DATA_WIDTH-1:0] reg_data_out;
|
||||||
|
integer byte_index;
|
||||||
|
reg aw_en;
|
||||||
|
|
||||||
|
|
||||||
|
//----------------------------------------------
|
||||||
|
//-- AXIL Protocl Implementation
|
||||||
|
//------------------------------------------------
|
||||||
|
assign S_AXI_AWREADY = axi_awready;
|
||||||
|
assign S_AXI_WREADY = axi_wready;
|
||||||
|
assign S_AXI_BRESP = axi_bresp;
|
||||||
|
assign S_AXI_BVALID = axi_bvalid;
|
||||||
|
assign S_AXI_ARREADY = axi_arready;
|
||||||
|
assign S_AXI_RDATA = axi_rdata;
|
||||||
|
assign S_AXI_RRESP = axi_rresp;
|
||||||
|
assign S_AXI_RVALID = axi_rvalid;
|
||||||
|
|
||||||
|
// Implement axi_awready generation
|
||||||
|
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||||
|
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||||
|
// de-asserted when reset is low.
|
||||||
|
always @( posedge S_AXI_ACLK )
|
||||||
|
begin
|
||||||
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
|
begin
|
||||||
|
axi_awready <= 1'b0;
|
||||||
|
aw_en <= 1'b1;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
||||||
|
begin
|
||||||
|
// slave is ready to accept write address when
|
||||||
|
// there is a valid write address and write data
|
||||||
|
// on the write address and data bus. This design
|
||||||
|
// expects no outstanding transactions.
|
||||||
|
axi_awready <= 1'b1;
|
||||||
|
aw_en <= 1'b0;
|
||||||
|
end
|
||||||
|
else if (S_AXI_BREADY && axi_bvalid)
|
||||||
|
begin
|
||||||
|
aw_en <= 1'b1;
|
||||||
|
axi_awready <= 1'b0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
axi_awready <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Implement axi_awaddr latching
|
||||||
|
// This process is used to latch the address when both
|
||||||
|
// S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||||
|
always @( posedge S_AXI_ACLK )
|
||||||
|
begin
|
||||||
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
|
begin
|
||||||
|
axi_awaddr <= 0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
||||||
|
begin
|
||||||
|
// Write Address latching
|
||||||
|
axi_awaddr <= S_AXI_AWADDR;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Implement axi_wready generation
|
||||||
|
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||||
|
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||||
|
// de-asserted when reset is low.
|
||||||
|
always @( posedge S_AXI_ACLK )
|
||||||
|
begin
|
||||||
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
|
begin
|
||||||
|
axi_wready <= 1'b0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
|
||||||
|
begin
|
||||||
|
// slave is ready to accept write data when
|
||||||
|
// there is a valid write address and write data
|
||||||
|
// on the write address and data bus. This design
|
||||||
|
// expects no outstanding transactions.
|
||||||
|
axi_wready <= 1'b1;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
axi_wready <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Implement write response logic generation
|
||||||
|
// The write response and response valid signals are asserted by the slave
|
||||||
|
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||||
|
// This marks the acceptance of address and indicates the status of
|
||||||
|
// write transaction.
|
||||||
|
always @( posedge S_AXI_ACLK )
|
||||||
|
begin
|
||||||
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
|
begin
|
||||||
|
axi_bvalid <= 0;
|
||||||
|
axi_bresp <= 2'b0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
|
||||||
|
begin
|
||||||
|
// indicates a valid write response is available
|
||||||
|
axi_bvalid <= 1'b1;
|
||||||
|
axi_bresp <= 2'b0; // 'OKAY' response
|
||||||
|
end // work error responses in future
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (S_AXI_BREADY && axi_bvalid)
|
||||||
|
//check if bready is asserted while bvalid is high)
|
||||||
|
//(there is a possibility that bready is always asserted high)
|
||||||
|
begin
|
||||||
|
axi_bvalid <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Implement axi_arready generation
|
||||||
|
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||||
|
// S_AXI_ARVALID is asserted. axi_awready is
|
||||||
|
// de-asserted when reset (active low) is asserted.
|
||||||
|
// The read address is also latched when S_AXI_ARVALID is
|
||||||
|
// asserted. axi_araddr is reset to zero on reset assertion.
|
||||||
|
always @( posedge S_AXI_ACLK )
|
||||||
|
begin
|
||||||
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
|
begin
|
||||||
|
axi_arready <= 1'b0;
|
||||||
|
axi_araddr <= 32'b0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (~axi_arready && S_AXI_ARVALID)
|
||||||
|
begin
|
||||||
|
// indicates that the slave has acceped the valid read address
|
||||||
|
axi_arready <= 1'b1;
|
||||||
|
// Read address latching
|
||||||
|
axi_araddr <= S_AXI_ARADDR;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
axi_arready <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Implement axi_arvalid generation
|
||||||
|
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||||
|
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||||
|
// data are available on the axi_rdata bus at this instance. The
|
||||||
|
// assertion of axi_rvalid marks the validity of read data on the
|
||||||
|
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||||
|
// is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||||
|
// cleared to zero on reset (active low).
|
||||||
|
always @( posedge S_AXI_ACLK )
|
||||||
|
begin
|
||||||
|
if ( S_AXI_ARESETN == 1'b0 )
|
||||||
|
begin
|
||||||
|
axi_rvalid <= 0;
|
||||||
|
axi_rresp <= 0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
|
||||||
|
begin
|
||||||
|
// Valid read data is available at the read data bus
|
||||||
|
axi_rvalid <= 1'b1;
|
||||||
|
axi_rresp <= 2'b0; // 'OKAY' response
|
||||||
|
end
|
||||||
|
else if (axi_rvalid && S_AXI_RREADY)
|
||||||
|
begin
|
||||||
|
// Read data is accepted by the master
|
||||||
|
axi_rvalid <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// Implement memory mapped register select and write logic generation
|
||||||
|
// The write data is accepted and written to memory mapped registers when
|
||||||
|
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||||
|
// select byte enables of slave registers while writing.
|
||||||
|
// These registers are cleared when reset (active low) is applied.
|
||||||
|
// Slave register write enable is asserted when valid address and data are available
|
||||||
|
// and the slave is ready to accept the write address and write data.
|
||||||
|
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
|
||||||
|
|
||||||
|
// Implement memory mapped register select and read logic generation
|
||||||
|
// Slave register read enable is asserted when valid address is available
|
||||||
|
// and the slave is ready to accept the read address.
|
||||||
|
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
|
||||||
|
|
||||||
|
// // Output register or memory read data
|
||||||
|
// always @( posedge S_AXI_ACLK )
|
||||||
|
// begin
|
||||||
|
// if ( S_AXI_ARESETN == 1'b0 )
|
||||||
|
// begin
|
||||||
|
// axi_rdata <= 0;
|
||||||
|
// end
|
||||||
|
// else
|
||||||
|
// begin
|
||||||
|
// // When there is a valid read address (S_AXI_ARVALID) with
|
||||||
|
// // acceptance of read address by the slave (axi_arready),
|
||||||
|
// // output the read dada
|
||||||
|
// if (slv_reg_rden)
|
||||||
|
// begin
|
||||||
|
// axi_rdata <= reg_data_out; // register read data
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
assign axi_rdata = rdata;
|
||||||
|
|
||||||
|
assign wren = slv_reg_wren;
|
||||||
|
assign rden = slv_reg_rden;
|
||||||
|
assign wdata = S_AXI_WDATA;
|
||||||
|
assign waddr = axi_awaddr;
|
||||||
|
assign raddr = axi_araddr;
|
||||||
|
// assign reg_data_out = rdata;
|
||||||
|
|
||||||
|
endmodule
|
||||||
138
project_1.srcs/sources_1/hdl/data_gen.sv
Executable file
138
project_1.srcs/sources_1/hdl/data_gen.sv
Executable file
@@ -0,0 +1,138 @@
|
|||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
module data_gen #
|
||||||
|
(
|
||||||
|
parameter NUM_CH = 2
|
||||||
|
)
|
||||||
|
(
|
||||||
|
// AXI4L Config Interface
|
||||||
|
axi4l_intf.slave ctrl_if,
|
||||||
|
input wire trigger,
|
||||||
|
|
||||||
|
// Output Data
|
||||||
|
axi4s_intf.master data_out[NUM_CH]
|
||||||
|
);
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// AXIL Decode
|
||||||
|
// ------------------------------
|
||||||
|
wire [ctrl_if.AXI_ADDR_WIDTH-1 : 0] raddr;
|
||||||
|
wire [ctrl_if.AXI_ADDR_WIDTH-1 : 0] waddr;
|
||||||
|
wire rden;
|
||||||
|
wire wren;
|
||||||
|
wire [ctrl_if.AXI_DATA_WIDTH-1 : 0] wdata;
|
||||||
|
reg [ctrl_if.AXI_DATA_WIDTH-1 : 0] rdata;
|
||||||
|
|
||||||
|
|
||||||
|
axil_slave
|
||||||
|
# (
|
||||||
|
.DATA_WIDTH(ctrl_if.AXI_DATA_WIDTH),
|
||||||
|
.ADDR_WIDTH(ctrl_if.AXI_ADDR_WIDTH)
|
||||||
|
) axil_slave_i
|
||||||
|
(
|
||||||
|
// AXIL Slave
|
||||||
|
.S_AXI_ACLK(ctrl_if.clk),
|
||||||
|
.S_AXI_ARESETN(ctrl_if.resetn),
|
||||||
|
.S_AXI_AWADDR(ctrl_if.awaddr),
|
||||||
|
.S_AXI_AWPROT(ctrl_if.awprot),
|
||||||
|
.S_AXI_AWVALID(ctrl_if.awvalid),
|
||||||
|
.S_AXI_AWREADY(ctrl_if.awready),
|
||||||
|
.S_AXI_WDATA(ctrl_if.wdata),
|
||||||
|
.S_AXI_WSTRB(ctrl_if.wstrb),
|
||||||
|
.S_AXI_WVALID(ctrl_if.wvalid),
|
||||||
|
.S_AXI_WREADY(ctrl_if.wready),
|
||||||
|
.S_AXI_BRESP(ctrl_if.bresp),
|
||||||
|
.S_AXI_BVALID(ctrl_if.bvalid),
|
||||||
|
.S_AXI_BREADY(ctrl_if.bready),
|
||||||
|
.S_AXI_ARADDR(ctrl_if.araddr),
|
||||||
|
.S_AXI_ARPROT(ctrl_if.arprot),
|
||||||
|
.S_AXI_ARVALID(ctrl_if.arvalid),
|
||||||
|
.S_AXI_ARREADY(ctrl_if.arready),
|
||||||
|
.S_AXI_RDATA(ctrl_if.rdata),
|
||||||
|
.S_AXI_RRESP(ctrl_if.rresp),
|
||||||
|
.S_AXI_RVALID(ctrl_if.rvalid),
|
||||||
|
.S_AXI_RREADY(ctrl_if.rready),
|
||||||
|
|
||||||
|
.raddr(raddr),
|
||||||
|
.waddr(waddr),
|
||||||
|
.wren(wren),
|
||||||
|
.rden(rden),
|
||||||
|
.wdata(wdata),
|
||||||
|
.rdata(rdata)
|
||||||
|
);
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Config Registers
|
||||||
|
// ------------------------------
|
||||||
|
wire reset;
|
||||||
|
assign reset = ~ctrl_if.resetn;
|
||||||
|
reg [31:0] num_samples;
|
||||||
|
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (~ctrl_if.resetn) begin
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
if (wren) begin
|
||||||
|
if ( waddr[15:0] == 'h000 )
|
||||||
|
num_samples <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (rden) begin
|
||||||
|
if (raddr[11:0] == 'h000)
|
||||||
|
rdata <= num_samples;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Data Generation
|
||||||
|
// ------------------------------
|
||||||
|
wire valid;
|
||||||
|
wire tlast;
|
||||||
|
pulse_generator pulse_generator_i(
|
||||||
|
.clk(ctrl_if.clk),
|
||||||
|
.rst(reset),
|
||||||
|
.pulse_length(num_samples),
|
||||||
|
.start_of_pulse(trigger),
|
||||||
|
.pulse_out(valid),
|
||||||
|
.pulse_tlast(tlast)
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [63:0] cnt_data;
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
cnt_data <= cnt_data + 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
genvar ch_ind;
|
||||||
|
generate
|
||||||
|
for (ch_ind=0; ch_ind < NUM_CH; ch_ind++) begin
|
||||||
|
wire [7:0] ch_num = ch_ind;
|
||||||
|
wire [127:0] ch_data = {ch_num, 24'h000000, 32'h00000000, cnt_data};
|
||||||
|
|
||||||
|
ch_data_buffer ch_data_buffer_i (
|
||||||
|
.s_axis_aresetn(ctrl_if.resetn),
|
||||||
|
.s_axis_aclk(ctrl_if.clk),
|
||||||
|
.s_axis_tvalid(valid),
|
||||||
|
.s_axis_tready(),
|
||||||
|
.s_axis_tdata(ch_data),
|
||||||
|
.s_axis_tlast(tlast),
|
||||||
|
.m_axis_tvalid(data_out[ch_ind].tvalid),
|
||||||
|
.m_axis_tready(data_out[ch_ind].tready),
|
||||||
|
.m_axis_tdata(data_out[ch_ind].tdata),
|
||||||
|
.m_axis_tlast(data_out[ch_ind].tlast)
|
||||||
|
);
|
||||||
|
|
||||||
|
assign data_out[ch_ind].tkeep = 16'hFFFF;
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
`resetall
|
||||||
386
project_1.srcs/sources_1/hdl/dma_engine_256.sv
Executable file
386
project_1.srcs/sources_1/hdl/dma_engine_256.sv
Executable file
@@ -0,0 +1,386 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module dma_engine_256 (
|
||||||
|
axi4l_intf.slave ctrl_if,
|
||||||
|
axi4s_intf.slave axis,
|
||||||
|
axi4_intf.master axim
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [ctrl_if.AXI_DATA_WIDTH-1:0] ctrl_reg[3:0];
|
||||||
|
wire [ctrl_if.AXI_DATA_WIDTH-1:0] status_reg[4:0];
|
||||||
|
|
||||||
|
reg ctrl_fifo_wren;
|
||||||
|
reg [127:0] ctrl_fifo_din;
|
||||||
|
|
||||||
|
wire dma_rst;
|
||||||
|
wire dma_enable;
|
||||||
|
|
||||||
|
wire ctrl_fifo_rst;
|
||||||
|
reg ctrl_fifo_rden;
|
||||||
|
wire [71:0] ctrl_fifo_dout;
|
||||||
|
|
||||||
|
wire ctrl_fifo_full;
|
||||||
|
wire ctrl_fifo_empty;
|
||||||
|
wire [9:0] ctrl_fifo_count;
|
||||||
|
|
||||||
|
wire stat_fifo_rst;
|
||||||
|
|
||||||
|
reg stat_fifo_wren;
|
||||||
|
reg [71:0] stat_fifo_din;
|
||||||
|
reg stat_fifo_rden;
|
||||||
|
wire [71:0] stat_fifo_dout;
|
||||||
|
|
||||||
|
wire stat_fifo_full;
|
||||||
|
wire stat_fifo_empty;
|
||||||
|
wire [9:0] stat_fifo_count;
|
||||||
|
|
||||||
|
reg [1:0] state;
|
||||||
|
|
||||||
|
reg [71:0] active_buf;
|
||||||
|
reg [22:0] remaining_len;
|
||||||
|
reg [22:0] bytes_written;
|
||||||
|
|
||||||
|
wire s_axis_s2mm_cmd_tvalid;
|
||||||
|
wire s_axis_s2mm_cmd_tready;
|
||||||
|
reg [79:0] s_axis_s2mm_cmd_tdata;
|
||||||
|
|
||||||
|
wire m_axis_s2mm_sts_tvalid;
|
||||||
|
wire m_axis_s2mm_sts_tready;
|
||||||
|
wire [7:0] m_axis_s2mm_sts_tdata;
|
||||||
|
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// AXIL Decode
|
||||||
|
// ------------------------------
|
||||||
|
wire [ctrl_if.AXI_ADDR_WIDTH-1 : 0] raddr;
|
||||||
|
wire [ctrl_if.AXI_ADDR_WIDTH-1 : 0] waddr;
|
||||||
|
wire rden;
|
||||||
|
wire wren;
|
||||||
|
wire [ctrl_if.AXI_DATA_WIDTH-1 : 0] wdata;
|
||||||
|
reg [ctrl_if.AXI_DATA_WIDTH-1 : 0] rdata;
|
||||||
|
|
||||||
|
|
||||||
|
axil_slave
|
||||||
|
# (
|
||||||
|
.DATA_WIDTH(ctrl_if.AXI_DATA_WIDTH),
|
||||||
|
.ADDR_WIDTH(ctrl_if.AXI_ADDR_WIDTH)
|
||||||
|
) axil_slave_i
|
||||||
|
(
|
||||||
|
// AXIL Slave
|
||||||
|
.S_AXI_ACLK(ctrl_if.clk),
|
||||||
|
.S_AXI_ARESETN(ctrl_if.resetn),
|
||||||
|
.S_AXI_AWADDR(ctrl_if.awaddr),
|
||||||
|
.S_AXI_AWPROT(ctrl_if.awprot),
|
||||||
|
.S_AXI_AWVALID(ctrl_if.awvalid),
|
||||||
|
.S_AXI_AWREADY(ctrl_if.awready),
|
||||||
|
.S_AXI_WDATA(ctrl_if.wdata),
|
||||||
|
.S_AXI_WSTRB(ctrl_if.wstrb),
|
||||||
|
.S_AXI_WVALID(ctrl_if.wvalid),
|
||||||
|
.S_AXI_WREADY(ctrl_if.wready),
|
||||||
|
.S_AXI_BRESP(ctrl_if.bresp),
|
||||||
|
.S_AXI_BVALID(ctrl_if.bvalid),
|
||||||
|
.S_AXI_BREADY(ctrl_if.bready),
|
||||||
|
.S_AXI_ARADDR(ctrl_if.araddr),
|
||||||
|
.S_AXI_ARPROT(ctrl_if.arprot),
|
||||||
|
.S_AXI_ARVALID(ctrl_if.arvalid),
|
||||||
|
.S_AXI_ARREADY(ctrl_if.arready),
|
||||||
|
.S_AXI_RDATA(ctrl_if.rdata),
|
||||||
|
.S_AXI_RRESP(ctrl_if.rresp),
|
||||||
|
.S_AXI_RVALID(ctrl_if.rvalid),
|
||||||
|
.S_AXI_RREADY(ctrl_if.rready),
|
||||||
|
|
||||||
|
.raddr(raddr),
|
||||||
|
.waddr(waddr),
|
||||||
|
.wren(wren),
|
||||||
|
.rden(rden),
|
||||||
|
.wdata(wdata),
|
||||||
|
.rdata(rdata)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (~ctrl_if.resetn) begin
|
||||||
|
ctrl_reg[0] <= 'b111;
|
||||||
|
ctrl_reg[1] <= 'b0;
|
||||||
|
ctrl_reg[2] <= 'b0;
|
||||||
|
ctrl_reg[3] <= 'b0;
|
||||||
|
|
||||||
|
ctrl_fifo_wren <= 'b0;
|
||||||
|
ctrl_fifo_din <= 'b0;
|
||||||
|
|
||||||
|
stat_fifo_rden <= 1'b0;
|
||||||
|
|
||||||
|
rdata <= 'b0;
|
||||||
|
end else begin
|
||||||
|
ctrl_fifo_wren <= 'b0;
|
||||||
|
|
||||||
|
if (wren) begin
|
||||||
|
if ( waddr[7:0] == 'h00 )
|
||||||
|
ctrl_reg[0] <= wdata;
|
||||||
|
if ( waddr[7:0] == 'h04 )
|
||||||
|
ctrl_reg[1] <= wdata;
|
||||||
|
if ( waddr[7:0] == 'h08 )
|
||||||
|
ctrl_reg[2] <= wdata;
|
||||||
|
if ( waddr[7:0] == 'h0C )
|
||||||
|
ctrl_reg[3] <= wdata;
|
||||||
|
if ( waddr[7:0] == 'h20 )
|
||||||
|
ctrl_fifo_din[31:0] <= wdata;
|
||||||
|
if ( waddr[7:0] == 'h24 )
|
||||||
|
ctrl_fifo_din[63:32] <= wdata;
|
||||||
|
if ( waddr[7:0] == 'h28 ) begin
|
||||||
|
ctrl_fifo_din[95:64] <= wdata;
|
||||||
|
ctrl_fifo_wren <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
stat_fifo_rden <= 1'b0;
|
||||||
|
if (rden) begin
|
||||||
|
if (raddr[7:0] == 'h00)
|
||||||
|
rdata <= ctrl_reg[0];
|
||||||
|
if (raddr[7:0] == 'h04)
|
||||||
|
rdata <= ctrl_reg[1];
|
||||||
|
if (raddr[7:0] == 'h08)
|
||||||
|
rdata <= ctrl_reg[2];
|
||||||
|
if (raddr[7:0] == 'h0C)
|
||||||
|
rdata <= ctrl_reg[3];
|
||||||
|
if (raddr[7:0] == 'h10)
|
||||||
|
rdata <= status_reg[0];
|
||||||
|
if (raddr[7] == 'h14)
|
||||||
|
rdata <= status_reg[1];
|
||||||
|
if (raddr[7:0] == 'h18)
|
||||||
|
rdata <= status_reg[2];
|
||||||
|
if (raddr[7:0] == 'h1C)
|
||||||
|
rdata <= status_reg[3];
|
||||||
|
|
||||||
|
if (raddr[7:0] == 'h20)
|
||||||
|
rdata <= stat_fifo_dout[31:0];
|
||||||
|
if (raddr[7:0] == 'h24)
|
||||||
|
rdata <= stat_fifo_dout[63:32];
|
||||||
|
if (raddr[7:0] == 'h28) begin
|
||||||
|
rdata <= {24'b0, stat_fifo_dout[71:64]};
|
||||||
|
stat_fifo_rden <= 1'b1;
|
||||||
|
end
|
||||||
|
if (raddr[7:0] == 'h2C)
|
||||||
|
rdata <= status_reg[4];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
assign ctrl_fifo_rst = ctrl_reg[0][0];
|
||||||
|
assign stat_fifo_rst = ctrl_reg[0][1];
|
||||||
|
assign dma_rst = ctrl_reg[0][2];
|
||||||
|
|
||||||
|
assign dma_enable = ctrl_reg[0][8];
|
||||||
|
|
||||||
|
assign status_reg[0] = {30'h00, state};
|
||||||
|
assign status_reg[1] = {16'h00, 8'd23, 8'd9};
|
||||||
|
assign status_reg[2] = {6'b0, ctrl_fifo_count, 15'b0, ctrl_fifo_full};
|
||||||
|
assign status_reg[3] = {6'b0, stat_fifo_count, 15'b0, stat_fifo_empty};
|
||||||
|
assign status_reg[4] = 32'hBEEF_BEEF;
|
||||||
|
|
||||||
|
|
||||||
|
// State Machines
|
||||||
|
parameter DMA_IDLE = 0;
|
||||||
|
parameter DMA_START = 1;
|
||||||
|
parameter DMA_ACTIVE = 2;
|
||||||
|
parameter DMA_COMP = 3;
|
||||||
|
|
||||||
|
axi4s_intf # (
|
||||||
|
.AXI_DATA_WIDTH(axis.AXI_DATA_WIDTH)
|
||||||
|
)
|
||||||
|
axis_gated(
|
||||||
|
.clk(axis.clk)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @( posedge ctrl_if.clk )
|
||||||
|
begin
|
||||||
|
ctrl_fifo_rden <= 1'b0;
|
||||||
|
stat_fifo_wren <= 1'b0;
|
||||||
|
|
||||||
|
if ( dma_rst == 1'b1 ) begin
|
||||||
|
state <= DMA_IDLE;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (state)
|
||||||
|
DMA_IDLE: begin
|
||||||
|
s_axis_s2mm_cmd_tdata <= 'b0;
|
||||||
|
s_axis_s2mm_cmd_tdata[71:32] <= ctrl_fifo_dout[71:32];
|
||||||
|
s_axis_s2mm_cmd_tdata[30] <= 1'b1;
|
||||||
|
s_axis_s2mm_cmd_tdata[23] <= 1'b1;
|
||||||
|
s_axis_s2mm_cmd_tdata[22:0] <= ctrl_fifo_dout[31:9];
|
||||||
|
|
||||||
|
active_buf <= ctrl_fifo_dout;
|
||||||
|
remaining_len <= ctrl_fifo_dout[31:9];
|
||||||
|
bytes_written <= 'b0;
|
||||||
|
|
||||||
|
if ((ctrl_fifo_empty == 1'b0) && ( dma_enable == 1'b1 )) begin
|
||||||
|
ctrl_fifo_rden <= 1'b1;
|
||||||
|
state <= DMA_START;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
DMA_START : begin
|
||||||
|
if (s_axis_s2mm_cmd_tready == 1'b1) begin
|
||||||
|
state <= DMA_ACTIVE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
DMA_ACTIVE : begin
|
||||||
|
if ((axis_gated.tready == 1'b1) && (axis_gated.tvalid == 1'b1)) begin
|
||||||
|
if ( dma_enable == 1'b1 ) begin
|
||||||
|
remaining_len <= remaining_len - (axis.AXI_DATA_WIDTH/8);
|
||||||
|
bytes_written <= bytes_written + (axis.AXI_DATA_WIDTH/8);
|
||||||
|
|
||||||
|
// if (remaining_len == (axis.AXI_DATA_WIDTH/8)) begin
|
||||||
|
if (axis_gated.tlast) begin
|
||||||
|
state <= DMA_COMP;
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
state <= DMA_COMP;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
DMA_COMP: begin
|
||||||
|
if (m_axis_s2mm_sts_tvalid == 1'b1) begin //TODO: this is a bug
|
||||||
|
stat_fifo_wren <= 1'b1;
|
||||||
|
|
||||||
|
stat_fifo_din <= active_buf;
|
||||||
|
stat_fifo_din[31:9] <= bytes_written;
|
||||||
|
|
||||||
|
state <= DMA_IDLE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
default : begin
|
||||||
|
state <= DMA_IDLE;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign s_axis_s2mm_cmd_tvalid = (state == DMA_START) ? 1'b1 : 1'b0;
|
||||||
|
|
||||||
|
assign axis_gated.tdata = axis.tdata;
|
||||||
|
assign axis_gated.tkeep = axis.tkeep;
|
||||||
|
// assign axis_gated.tlast = ((remaining_len == (axis.AXI_DATA_WIDTH/8)) || ( dma_enable == 1'b0 )) ? 1'b1 : 1'b0;
|
||||||
|
assign axis_gated.tlast = ((remaining_len == (axis.AXI_DATA_WIDTH/8)) || axis.tlast) ? 1'b1 : 1'b0;
|
||||||
|
assign axis_gated.tvalid = (state == DMA_ACTIVE) ? (( dma_enable == 1'b0 ) ? 1'b1 : axis.tvalid) : 1'b0;
|
||||||
|
assign axis.tready = (state == DMA_ACTIVE) ? axis_gated.tready : (( dma_enable == 1'b0 ) ? 1'b1 : 1'b0);
|
||||||
|
// This can be removed and changed back to just 1'b0;
|
||||||
|
assign m_axis_s2mm_sts_tready = (state == DMA_COMP) ? 1'b1 : 1'b0;
|
||||||
|
|
||||||
|
// basic idea behind datamover control;
|
||||||
|
// control fifo allows dma driver to allocate PS DDR buffer and load the physical address
|
||||||
|
// into the fifo; once the transfer is complete the result fifo will be loaded with completion result
|
||||||
|
// that will also contain the physical DDR buffer address
|
||||||
|
|
||||||
|
dma_ctrl_status_fifo_0 ctrl_fifo_i (
|
||||||
|
.clk( ctrl_if.clk ), // : IN STD_LOGIC;
|
||||||
|
.srst( ctrl_fifo_rst ), // : IN STD_LOGIC;
|
||||||
|
.din( ctrl_fifo_din[71:0] ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.wr_en( ctrl_fifo_wren ), // : IN STD_LOGIC;
|
||||||
|
.rd_en( ctrl_fifo_rden ), // : IN STD_LOGIC;
|
||||||
|
.dout( ctrl_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.full( ctrl_fifo_full ), // : OUT STD_LOGIC;
|
||||||
|
.empty( ctrl_fifo_empty ), // : OUT STD_LOGIC;
|
||||||
|
.data_count( ctrl_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||||
|
.wr_rst_busy( ),
|
||||||
|
.rd_rst_busy( )
|
||||||
|
);
|
||||||
|
|
||||||
|
dma_ctrl_status_fifo_0 stat_fifo_i (
|
||||||
|
.clk( ctrl_if.clk ), // : IN STD_LOGIC;
|
||||||
|
.srst( stat_fifo_rst ), // : IN STD_LOGIC;
|
||||||
|
.din( stat_fifo_din ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.wr_en( stat_fifo_wren ), // : IN STD_LOGIC;
|
||||||
|
.rd_en( stat_fifo_rden ), // : IN STD_LOGIC;
|
||||||
|
.dout( stat_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.full( stat_fifo_full ), // : OUT STD_LOGIC;
|
||||||
|
.empty( stat_fifo_empty ), // : OUT STD_LOGIC;
|
||||||
|
.data_count( stat_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||||
|
.wr_rst_busy( ),
|
||||||
|
.rd_rst_busy( )
|
||||||
|
);
|
||||||
|
|
||||||
|
// Do a soft shutdown of the datamover on a reset request. This should ensure the AXI bus does not get hung mid burst
|
||||||
|
// and allow the datamover to be instantiated without using store-forward. This will save blockrams, and is OK because we already
|
||||||
|
// have buffering in the receive path
|
||||||
|
logic s2mm_err;
|
||||||
|
logic s2mm_halt;
|
||||||
|
logic s2mm_halt_cmplt;
|
||||||
|
logic datamover_rst;
|
||||||
|
logic dma_rst_q;
|
||||||
|
logic dma_rst_q2;
|
||||||
|
logic dma_rst_red;
|
||||||
|
|
||||||
|
always @ (posedge axim.clk) begin
|
||||||
|
|
||||||
|
dma_rst_q <= dma_rst;
|
||||||
|
dma_rst_q2 <= dma_rst_q;
|
||||||
|
dma_rst_red <= dma_rst_q & ~dma_rst_q;
|
||||||
|
|
||||||
|
|
||||||
|
s2mm_halt <= dma_rst;
|
||||||
|
|
||||||
|
// Clear the datamover reset when the dma reset clears
|
||||||
|
if (dma_rst == 1'b0) begin
|
||||||
|
datamover_rst <= 1'b0;
|
||||||
|
end
|
||||||
|
else if (s2mm_halt_cmplt == 1'b1) begin
|
||||||
|
// Wait for halt complete to trigger datamover reset
|
||||||
|
datamover_rst <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
axi_datamover_256_0 axi_datamover_0_i (
|
||||||
|
.m_axi_s2mm_aclk( axim.clk ), //
|
||||||
|
.m_axi_s2mm_aresetn( ~datamover_rst ), // : IN STD_LOGIC;
|
||||||
|
|
||||||
|
.s2mm_halt(s2mm_halt), // input wire s2mm_halt
|
||||||
|
.s2mm_halt_cmplt(s2mm_halt_cmplt), // output wire s2mm_halt_cmplt
|
||||||
|
|
||||||
|
.s2mm_allow_addr_req(1'b1), // input wire s2mm_allow_addr_req
|
||||||
|
.s2mm_addr_req_posted(), // output wire s2mm_addr_req_posted
|
||||||
|
.s2mm_wr_xfer_cmplt(), // output wire s2mm_wr_xfer_cmplt
|
||||||
|
.s2mm_ld_nxt_len(), // output wire s2mm_ld_nxt_len
|
||||||
|
.s2mm_wr_len(), // output wire [7 : 0] s2mm_wr_len
|
||||||
|
|
||||||
|
.s2mm_err(s2mm_err), // : OUT STD_LOGIC;
|
||||||
|
|
||||||
|
.m_axis_s2mm_cmdsts_awclk( ctrl_if.clk ), // : IN STD_LOGIC;
|
||||||
|
.m_axis_s2mm_cmdsts_aresetn( ~dma_rst ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_cmd_tvalid( s_axis_s2mm_cmd_tvalid ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_cmd_tready( s_axis_s2mm_cmd_tready ), // : OUT STD_LOGIC;
|
||||||
|
.s_axis_s2mm_cmd_tdata( s_axis_s2mm_cmd_tdata), // : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
|
||||||
|
.m_axis_s2mm_sts_tvalid( m_axis_s2mm_sts_tvalid ), // : OUT STD_LOGIC;
|
||||||
|
.m_axis_s2mm_sts_tready( m_axis_s2mm_sts_tready), // : IN STD_LOGIC;
|
||||||
|
.m_axis_s2mm_sts_tdata( m_axis_s2mm_sts_tdata ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
.m_axis_s2mm_sts_tkeep( ), // : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
.m_axis_s2mm_sts_tlast( ), // : OUT STD_LOGIC;
|
||||||
|
|
||||||
|
.m_axi_s2mm_awaddr( axim.awaddr ), // : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awlen( axim.awlen ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awsize( axim.awsize ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awburst( axim.awburst ), // : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awprot( axim.awprot ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awcache( axim.awcache ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awuser( ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awvalid( axim.awvalid ), // : OUT STD_LOGIC;
|
||||||
|
.m_axi_s2mm_awready( axim.awready ), // : IN STD_LOGIC;
|
||||||
|
.m_axi_s2mm_wdata( axim.wdata ), // : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_wstrb( axim.wstrb ), // : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_wlast( axim.wlast ), // : OUT STD_LOGIC;
|
||||||
|
.m_axi_s2mm_wvalid( axim.wvalid ), // : OUT STD_LOGIC;
|
||||||
|
.m_axi_s2mm_wready( axim.wready ), // : IN STD_LOGIC;
|
||||||
|
.m_axi_s2mm_bresp( axim.bresp ), // : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_bvalid( axim.bvalid ), // : IN STD_LOGIC;
|
||||||
|
.m_axi_s2mm_bready( axim.bready ), // : OUT STD_LOGIC;
|
||||||
|
|
||||||
|
.s_axis_s2mm_tdata( axis_gated.tdata ), // : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||||
|
.s_axis_s2mm_tkeep( axis_gated.tkeep ), // : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
.s_axis_s2mm_tlast( axis_gated.tlast ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_tvalid( axis_gated.tvalid ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_tready( axis_gated.tready ) // : OUT STD_LOGIC
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
489
project_1.srcs/sources_1/hdl/dma_engine_256_og.sv
Executable file
489
project_1.srcs/sources_1/hdl/dma_engine_256_og.sv
Executable file
@@ -0,0 +1,489 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// Author : Torry Akins
|
||||||
|
// Creation Date : 06/04/2024
|
||||||
|
// File Name : dma_engine_256.sv
|
||||||
|
// Tool Version : 2021.2
|
||||||
|
// Description : DMA Engine (256 bits wide)
|
||||||
|
//
|
||||||
|
// Copyright (c) 2024 Wide Swath Research, LLC.
|
||||||
|
// This design is confidential and is the proprietary property
|
||||||
|
// of Wide Swath Research, LLC.
|
||||||
|
//
|
||||||
|
// Design licensed for use by Aloft Sensing, Inc.
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
module dma_engine_256 (
|
||||||
|
axi4l_intf.slave axi,
|
||||||
|
axi4s_intf.slave axis,
|
||||||
|
axi4_intf.master axim
|
||||||
|
);
|
||||||
|
|
||||||
|
// incoming pipeline of write address
|
||||||
|
reg awaddr_valid;
|
||||||
|
reg [axi.AXI_ADDR_WIDTH-1:0] awaddr;
|
||||||
|
|
||||||
|
// incoming pipeline of write data
|
||||||
|
reg wdata_valid;
|
||||||
|
reg [((axi.AXI_DATA_WIDTH/8)-1):0] wstrb;
|
||||||
|
reg [axi.AXI_DATA_WIDTH-1:0] wdata;
|
||||||
|
|
||||||
|
// incoming pipeline of read address
|
||||||
|
reg araddr_valid;
|
||||||
|
reg [axi.AXI_ADDR_WIDTH:0] araddr;
|
||||||
|
|
||||||
|
// outgoing pipeline of read data
|
||||||
|
reg rvalid;
|
||||||
|
reg [axi.AXI_DATA_WIDTH-1:0] rdata;
|
||||||
|
|
||||||
|
integer byte_index;
|
||||||
|
|
||||||
|
reg [axi.AXI_DATA_WIDTH-1:0] ctrl_reg[3:0];
|
||||||
|
wire [axi.AXI_DATA_WIDTH-1:0] status_reg[4:0];
|
||||||
|
|
||||||
|
reg ctrl_fifo_wren;
|
||||||
|
reg [127:0] ctrl_fifo_din;
|
||||||
|
|
||||||
|
wire dma_rst;
|
||||||
|
wire dma_enable;
|
||||||
|
|
||||||
|
wire ctrl_fifo_rst;
|
||||||
|
reg ctrl_fifo_rden;
|
||||||
|
wire [71:0] ctrl_fifo_dout;
|
||||||
|
|
||||||
|
wire ctrl_fifo_full;
|
||||||
|
wire ctrl_fifo_empty;
|
||||||
|
wire [9:0] ctrl_fifo_count;
|
||||||
|
|
||||||
|
wire stat_fifo_rst;
|
||||||
|
|
||||||
|
reg stat_fifo_wren;
|
||||||
|
reg [71:0] stat_fifo_din;
|
||||||
|
reg stat_fifo_rden;
|
||||||
|
wire [71:0] stat_fifo_dout;
|
||||||
|
|
||||||
|
wire stat_fifo_full;
|
||||||
|
wire stat_fifo_empty;
|
||||||
|
wire [9:0] stat_fifo_count;
|
||||||
|
|
||||||
|
reg [1:0] state;
|
||||||
|
|
||||||
|
reg [71:0] active_buf;
|
||||||
|
reg [22:0] remaining_len;
|
||||||
|
reg [22:0] bytes_written;
|
||||||
|
|
||||||
|
wire s_axis_s2mm_cmd_tvalid;
|
||||||
|
wire s_axis_s2mm_cmd_tready;
|
||||||
|
reg [79:0] s_axis_s2mm_cmd_tdata;
|
||||||
|
|
||||||
|
wire m_axis_s2mm_sts_tvalid;
|
||||||
|
wire m_axis_s2mm_sts_tready;
|
||||||
|
wire [7:0] m_axis_s2mm_sts_tdata;
|
||||||
|
|
||||||
|
|
||||||
|
// ready while data hasn't been latched and still waiting
|
||||||
|
// for acknowledgement to our response
|
||||||
|
assign axi.awready = !awaddr_valid && !axi.bvalid && axi.resetn;
|
||||||
|
assign axi.wready = !wdata_valid && !axi.bvalid && axi.resetn;
|
||||||
|
|
||||||
|
always @( posedge axi.clk )
|
||||||
|
begin
|
||||||
|
if ( axi.resetn == 1'b0 ) begin
|
||||||
|
awaddr_valid <= 1'b0;
|
||||||
|
awaddr <= 'b0;
|
||||||
|
wdata_valid <= 1'b0;
|
||||||
|
wstrb <= 'b0;
|
||||||
|
wdata <= 'b0;
|
||||||
|
axi.bvalid <= 1'b0;
|
||||||
|
axi.bresp <= 2'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// latch awaddr and valid signal
|
||||||
|
if (axi.awready && axi.awvalid) begin
|
||||||
|
awaddr_valid <= 1'b1;
|
||||||
|
awaddr <= axi.awaddr;
|
||||||
|
end
|
||||||
|
|
||||||
|
// latch wirte data and valid signal
|
||||||
|
if (axi.wready && axi.wvalid) begin
|
||||||
|
wdata_valid <= 1'b1;
|
||||||
|
wstrb <= axi.wstrb;
|
||||||
|
wdata <= axi.wdata;
|
||||||
|
end
|
||||||
|
|
||||||
|
// clear valids when both high;
|
||||||
|
// data needs to be consumed on this same condition
|
||||||
|
if (awaddr_valid && wdata_valid && !axi.bvalid) begin
|
||||||
|
awaddr_valid <= 1'b0;
|
||||||
|
wdata_valid <= 1'b0;
|
||||||
|
|
||||||
|
axi.bvalid <= 1'b1;
|
||||||
|
axi.bresp <= 2'b0; // 'OKAY' response
|
||||||
|
end
|
||||||
|
|
||||||
|
// clear bvalid when it has been acknowledged
|
||||||
|
if (axi.bvalid && axi.bready) begin
|
||||||
|
axi.bvalid <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// ready while data hasn't been latched and still waiting
|
||||||
|
// for acknowledgement to our response
|
||||||
|
assign axi.arready = !araddr_valid && !axi.rvalid && axi.resetn;
|
||||||
|
|
||||||
|
always @( posedge axi.clk )
|
||||||
|
begin
|
||||||
|
if ( axi.resetn == 1'b0 ) begin
|
||||||
|
araddr_valid <= 1'b0;
|
||||||
|
araddr <= 'b0;
|
||||||
|
axi.rvalid <= 1'b0;
|
||||||
|
axi.rresp <= 2'b0;
|
||||||
|
axi.rdata <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// latch araddr and valid signal
|
||||||
|
if (axi.arready && axi.arvalid) begin
|
||||||
|
araddr_valid <= 1'b1;
|
||||||
|
araddr <= axi.araddr;
|
||||||
|
end
|
||||||
|
|
||||||
|
// if address is valid and rdata has been latched;
|
||||||
|
// set axi bus rdata and valid signal
|
||||||
|
if (araddr_valid && rvalid && !axi.rvalid) begin
|
||||||
|
araddr_valid <= 1'b0;
|
||||||
|
|
||||||
|
axi.rvalid <= 1'b1;
|
||||||
|
axi.rresp <= 2'b0; // 'OKAY' response
|
||||||
|
axi.rdata <= rdata;
|
||||||
|
end
|
||||||
|
|
||||||
|
// clear rvalid when it has been acknowledged
|
||||||
|
if (axi.rvalid && axi.rready) begin
|
||||||
|
axi.rvalid <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( posedge axi.clk )
|
||||||
|
begin
|
||||||
|
if ( axi.resetn == 1'b0 ) begin
|
||||||
|
ctrl_reg[0] <= 'b111;
|
||||||
|
ctrl_reg[1] <= 'b0;
|
||||||
|
ctrl_reg[2] <= 'b0;
|
||||||
|
ctrl_reg[3] <= 'b0;
|
||||||
|
|
||||||
|
ctrl_fifo_wren <= 'b0;
|
||||||
|
ctrl_fifo_din <= 'b0;
|
||||||
|
|
||||||
|
stat_fifo_rden <= 1'b0;
|
||||||
|
|
||||||
|
rvalid <= 1'b0;
|
||||||
|
rdata <= 'b0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
|
||||||
|
ctrl_fifo_wren <= 'b0;
|
||||||
|
// everything is valid; latch data to the correct location
|
||||||
|
if (awaddr_valid && wdata_valid) begin
|
||||||
|
for ( byte_index = 0; byte_index <= (axi.AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) begin
|
||||||
|
if ( wstrb[byte_index] == 1 ) begin
|
||||||
|
if ( awaddr[7:0] == 'h00 )
|
||||||
|
ctrl_reg[0][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
|
||||||
|
|
||||||
|
if ( awaddr[7:0] == 'h04 )
|
||||||
|
ctrl_reg[1][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
|
||||||
|
|
||||||
|
if ( awaddr[7:0] == 'h08 )
|
||||||
|
ctrl_reg[2][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
|
||||||
|
|
||||||
|
if ( awaddr[7:0] == 'h0C )
|
||||||
|
ctrl_reg[3][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
|
||||||
|
|
||||||
|
if ( awaddr[7:0] == 'h20 )
|
||||||
|
ctrl_fifo_din[(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
|
||||||
|
|
||||||
|
if ( awaddr[7:0] == 'h24 )
|
||||||
|
ctrl_fifo_din[(byte_index*8)+32 +: 8] <= wdata[(byte_index*8) +: 8];
|
||||||
|
|
||||||
|
if ( awaddr[7:0] == 'h28 ) begin
|
||||||
|
ctrl_fifo_din[(byte_index*8)+64 +: 8] <= wdata[(byte_index*8) +: 8];
|
||||||
|
if (byte_index == 0) ctrl_fifo_wren <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
stat_fifo_rden <= 1'b0;
|
||||||
|
|
||||||
|
// by default rvalid is low; unless read address is valid;
|
||||||
|
// latch appropriate data and set valid signal
|
||||||
|
rvalid <= 1'b0;
|
||||||
|
if (araddr_valid && !rvalid) begin
|
||||||
|
if ( araddr[7:0] == 'h0 )
|
||||||
|
rdata <= ctrl_reg[0];
|
||||||
|
if ( araddr[7:0] == 'h4 )
|
||||||
|
rdata <= ctrl_reg[1];
|
||||||
|
if ( araddr[7:0] == 'h8 )
|
||||||
|
rdata <= ctrl_reg[2];
|
||||||
|
if ( araddr[7:0] == 'hC )
|
||||||
|
rdata <= ctrl_reg[3];
|
||||||
|
if ( araddr[7:0] == 'h10 )
|
||||||
|
rdata <= status_reg[0];
|
||||||
|
if ( araddr[7:0] == 'h14 )
|
||||||
|
rdata <= status_reg[1];
|
||||||
|
if ( araddr[7:0] == 'h18 )
|
||||||
|
rdata <= status_reg[2];
|
||||||
|
if ( araddr[7:0] == 'h1C )
|
||||||
|
rdata <= status_reg[3];
|
||||||
|
|
||||||
|
if ( araddr[7:0] == 'h20 )
|
||||||
|
rdata <= stat_fifo_dout[31:0];
|
||||||
|
|
||||||
|
if ( araddr[7:0] == 'h24 ) begin
|
||||||
|
rdata <= stat_fifo_dout[63:32];
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( araddr[7:0] == 'h28 ) begin
|
||||||
|
rdata <= {24'b0, stat_fifo_dout[71:64]};
|
||||||
|
stat_fifo_rden <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( araddr[7:0] == 'h2C) begin
|
||||||
|
rdata <= status_reg[4];
|
||||||
|
end
|
||||||
|
|
||||||
|
rvalid <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
assign ctrl_fifo_rst = ctrl_reg[0][0];
|
||||||
|
assign stat_fifo_rst = ctrl_reg[0][1];
|
||||||
|
assign dma_rst = ctrl_reg[0][2];
|
||||||
|
|
||||||
|
assign dma_enable = ctrl_reg[0][8];
|
||||||
|
|
||||||
|
assign status_reg[0] = {30'h00, state};
|
||||||
|
assign status_reg[1] = {16'h00, 8'd23, 8'd9};
|
||||||
|
assign status_reg[2] = {6'b0, ctrl_fifo_count, 15'b0, ctrl_fifo_full};
|
||||||
|
assign status_reg[3] = {6'b0, stat_fifo_count, 15'b0, stat_fifo_empty};
|
||||||
|
assign status_reg[4] = 32'hBEEF_BEEF;
|
||||||
|
|
||||||
|
|
||||||
|
// State Machines
|
||||||
|
parameter DMA_IDLE = 0;
|
||||||
|
parameter DMA_START = 1;
|
||||||
|
parameter DMA_ACTIVE = 2;
|
||||||
|
parameter DMA_COMP = 3;
|
||||||
|
|
||||||
|
axi4s_intf # (
|
||||||
|
.AXI_DATA_WIDTH(axis.AXI_DATA_WIDTH)
|
||||||
|
)
|
||||||
|
axis_gated(
|
||||||
|
.clk(axis.clk)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @( posedge axi.clk )
|
||||||
|
begin
|
||||||
|
ctrl_fifo_rden <= 1'b0;
|
||||||
|
stat_fifo_wren <= 1'b0;
|
||||||
|
|
||||||
|
if ( dma_rst == 1'b1 ) begin
|
||||||
|
state <= DMA_IDLE;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case (state)
|
||||||
|
DMA_IDLE: begin
|
||||||
|
s_axis_s2mm_cmd_tdata <= 'b0;
|
||||||
|
s_axis_s2mm_cmd_tdata[71:32] <= ctrl_fifo_dout[71:32];
|
||||||
|
s_axis_s2mm_cmd_tdata[30] <= 1'b1;
|
||||||
|
s_axis_s2mm_cmd_tdata[23] <= 1'b1;
|
||||||
|
s_axis_s2mm_cmd_tdata[22:0] <= ctrl_fifo_dout[31:9];
|
||||||
|
|
||||||
|
active_buf <= ctrl_fifo_dout;
|
||||||
|
remaining_len <= ctrl_fifo_dout[31:9];
|
||||||
|
bytes_written <= 'b0;
|
||||||
|
|
||||||
|
if ((ctrl_fifo_empty == 1'b0) && ( dma_enable == 1'b1 )) begin
|
||||||
|
ctrl_fifo_rden <= 1'b1;
|
||||||
|
state <= DMA_START;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
DMA_START : begin
|
||||||
|
if (s_axis_s2mm_cmd_tready == 1'b1) begin
|
||||||
|
state <= DMA_ACTIVE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
DMA_ACTIVE : begin
|
||||||
|
if ((axis_gated.tready == 1'b1) && (axis_gated.tvalid == 1'b1)) begin
|
||||||
|
if ( dma_enable == 1'b1 ) begin
|
||||||
|
remaining_len <= remaining_len - (axis.AXI_DATA_WIDTH/8);
|
||||||
|
bytes_written <= bytes_written + (axis.AXI_DATA_WIDTH/8);
|
||||||
|
|
||||||
|
if (remaining_len == (axis.AXI_DATA_WIDTH/8)) begin
|
||||||
|
state <= DMA_COMP;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
state <= DMA_COMP;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
DMA_COMP: begin
|
||||||
|
if (m_axis_s2mm_sts_tvalid == 1'b1) begin //TODO: this is a bug
|
||||||
|
stat_fifo_wren <= 1'b1;
|
||||||
|
|
||||||
|
stat_fifo_din <= active_buf;
|
||||||
|
stat_fifo_din[31:9] <= bytes_written;
|
||||||
|
|
||||||
|
state <= DMA_IDLE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
default : begin
|
||||||
|
state <= DMA_IDLE;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign s_axis_s2mm_cmd_tvalid = (state == DMA_START) ? 1'b1 : 1'b0;
|
||||||
|
|
||||||
|
assign axis_gated.tdata = axis.tdata;
|
||||||
|
assign axis_gated.tkeep = axis.tkeep;
|
||||||
|
assign axis_gated.tlast = ((remaining_len == (axis.AXI_DATA_WIDTH/8)) || ( dma_enable == 1'b0 )) ? 1'b1 : 1'b0;
|
||||||
|
assign axis_gated.tvalid = (state == DMA_ACTIVE) ? (( dma_enable == 1'b0 ) ? 1'b1 : axis.tvalid) : 1'b0;
|
||||||
|
assign axis.tready = (state == DMA_ACTIVE) ? axis_gated.tready : (( dma_enable == 1'b0 ) ? 1'b1 : 1'b0);
|
||||||
|
// This can be removed and changed back to just 1'b0;
|
||||||
|
assign m_axis_s2mm_sts_tready = (state == DMA_COMP) ? 1'b1 : 1'b0;
|
||||||
|
|
||||||
|
// basic idea behind datamover control;
|
||||||
|
// control fifo allows dma driver to allocate PS DDR buffer and load the physical address
|
||||||
|
// into the fifo; once the transfer is complete the result fifo will be loaded with completion result
|
||||||
|
// that will also contain the physical DDR buffer address
|
||||||
|
|
||||||
|
dma_ctrl_status_fifo_0 ctrl_fifo_i (
|
||||||
|
.clk( axi.clk ), // : IN STD_LOGIC;
|
||||||
|
.srst( ctrl_fifo_rst ), // : IN STD_LOGIC;
|
||||||
|
.din( ctrl_fifo_din[71:0] ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.wr_en( ctrl_fifo_wren ), // : IN STD_LOGIC;
|
||||||
|
.rd_en( ctrl_fifo_rden ), // : IN STD_LOGIC;
|
||||||
|
.dout( ctrl_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.full( ctrl_fifo_full ), // : OUT STD_LOGIC;
|
||||||
|
.empty( ctrl_fifo_empty ), // : OUT STD_LOGIC;
|
||||||
|
.data_count( ctrl_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||||
|
.wr_rst_busy( ),
|
||||||
|
.rd_rst_busy( )
|
||||||
|
);
|
||||||
|
|
||||||
|
dma_ctrl_status_fifo_0 stat_fifo_i (
|
||||||
|
.clk( axi.clk ), // : IN STD_LOGIC;
|
||||||
|
.srst( stat_fifo_rst ), // : IN STD_LOGIC;
|
||||||
|
.din( stat_fifo_din ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.wr_en( stat_fifo_wren ), // : IN STD_LOGIC;
|
||||||
|
.rd_en( stat_fifo_rden ), // : IN STD_LOGIC;
|
||||||
|
.dout( stat_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
|
||||||
|
.full( stat_fifo_full ), // : OUT STD_LOGIC;
|
||||||
|
.empty( stat_fifo_empty ), // : OUT STD_LOGIC;
|
||||||
|
.data_count( stat_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||||
|
.wr_rst_busy( ),
|
||||||
|
.rd_rst_busy( )
|
||||||
|
);
|
||||||
|
|
||||||
|
// Do a soft shutdown of the datamover on a reset request. This should ensure the AXI bus does not get hung mid burst
|
||||||
|
// and allow the datamover to be instantiated without using store-forward. This will save blockrams, and is OK because we already
|
||||||
|
// have buffering in the receive path
|
||||||
|
logic s2mm_err;
|
||||||
|
logic s2mm_halt;
|
||||||
|
logic s2mm_halt_cmplt;
|
||||||
|
logic datamover_rst;
|
||||||
|
logic dma_rst_q;
|
||||||
|
logic dma_rst_q2;
|
||||||
|
logic dma_rst_red;
|
||||||
|
|
||||||
|
always @ (posedge axim.clk) begin
|
||||||
|
|
||||||
|
dma_rst_q <= dma_rst;
|
||||||
|
dma_rst_q2 <= dma_rst_q;
|
||||||
|
dma_rst_red <= dma_rst_q & ~dma_rst_q;
|
||||||
|
|
||||||
|
|
||||||
|
s2mm_halt <= dma_rst;
|
||||||
|
|
||||||
|
// Clear the datamover reset when the dma reset clears
|
||||||
|
if (dma_rst == 1'b0) begin
|
||||||
|
datamover_rst <= 1'b0;
|
||||||
|
// s2mm_halt <= 1'b0;
|
||||||
|
end
|
||||||
|
// else if (dma_rst_red == 1'b1) begin
|
||||||
|
// // Trigger soft shutdown when the dma reset signal goes high
|
||||||
|
// s2mm_halt <= 1;
|
||||||
|
// end
|
||||||
|
else if (s2mm_halt_cmplt == 1'b1) begin
|
||||||
|
// Wait for halt complete to trigger datamover reset
|
||||||
|
datamover_rst <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
axi_datamover_256_0 axi_datamover_0_i (
|
||||||
|
.m_axi_s2mm_aclk( axim.clk ), //
|
||||||
|
// .m_axi_s2mm_aresetn( ~dma_rst ), // : IN STD_LOGIC;
|
||||||
|
.m_axi_s2mm_aresetn( ~datamover_rst ), // : IN STD_LOGIC;
|
||||||
|
|
||||||
|
.s2mm_halt(s2mm_halt), // input wire s2mm_halt
|
||||||
|
.s2mm_halt_cmplt(s2mm_halt_cmplt), // output wire s2mm_halt_cmplt
|
||||||
|
|
||||||
|
.s2mm_allow_addr_req(1'b1), // input wire s2mm_allow_addr_req
|
||||||
|
.s2mm_addr_req_posted(), // output wire s2mm_addr_req_posted
|
||||||
|
.s2mm_wr_xfer_cmplt(), // output wire s2mm_wr_xfer_cmplt
|
||||||
|
.s2mm_ld_nxt_len(), // output wire s2mm_ld_nxt_len
|
||||||
|
.s2mm_wr_len(), // output wire [7 : 0] s2mm_wr_len
|
||||||
|
|
||||||
|
.s2mm_err(s2mm_err), // : OUT STD_LOGIC;
|
||||||
|
|
||||||
|
.m_axis_s2mm_cmdsts_awclk( axi.clk ), // : IN STD_LOGIC;
|
||||||
|
.m_axis_s2mm_cmdsts_aresetn( ~dma_rst ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_cmd_tvalid( s_axis_s2mm_cmd_tvalid ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_cmd_tready( s_axis_s2mm_cmd_tready ), // : OUT STD_LOGIC;
|
||||||
|
.s_axis_s2mm_cmd_tdata( s_axis_s2mm_cmd_tdata), // : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
|
||||||
|
.m_axis_s2mm_sts_tvalid( m_axis_s2mm_sts_tvalid ), // : OUT STD_LOGIC;
|
||||||
|
.m_axis_s2mm_sts_tready( m_axis_s2mm_sts_tready), // : IN STD_LOGIC;
|
||||||
|
.m_axis_s2mm_sts_tdata( m_axis_s2mm_sts_tdata ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
.m_axis_s2mm_sts_tkeep( ), // : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
.m_axis_s2mm_sts_tlast( ), // : OUT STD_LOGIC;
|
||||||
|
|
||||||
|
.m_axi_s2mm_awaddr( axim.awaddr ), // : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awlen( axim.awlen ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awsize( axim.awsize ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awburst( axim.awburst ), // : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awprot( axim.awprot ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awcache( axim.awcache ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awuser( ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_awvalid( axim.awvalid ), // : OUT STD_LOGIC;
|
||||||
|
.m_axi_s2mm_awready( axim.awready ), // : IN STD_LOGIC;
|
||||||
|
.m_axi_s2mm_wdata( axim.wdata ), // : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_wstrb( axim.wstrb ), // : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_wlast( axim.wlast ), // : OUT STD_LOGIC;
|
||||||
|
.m_axi_s2mm_wvalid( axim.wvalid ), // : OUT STD_LOGIC;
|
||||||
|
.m_axi_s2mm_wready( axim.wready ), // : IN STD_LOGIC;
|
||||||
|
.m_axi_s2mm_bresp( axim.bresp ), // : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
.m_axi_s2mm_bvalid( axim.bvalid ), // : IN STD_LOGIC;
|
||||||
|
.m_axi_s2mm_bready( axim.bready ), // : OUT STD_LOGIC;
|
||||||
|
|
||||||
|
.s_axis_s2mm_tdata( axis_gated.tdata ), // : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||||
|
.s_axis_s2mm_tkeep( axis_gated.tkeep ), // : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||||
|
.s_axis_s2mm_tlast( axis_gated.tlast ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_tvalid( axis_gated.tvalid ), // : IN STD_LOGIC;
|
||||||
|
.s_axis_s2mm_tready( axis_gated.tready ) // : OUT STD_LOGIC
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
49
project_1.srcs/sources_1/hdl/pulse_generator.v
Executable file
49
project_1.srcs/sources_1/hdl/pulse_generator.v
Executable file
@@ -0,0 +1,49 @@
|
|||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
module pulse_generator #
|
||||||
|
(
|
||||||
|
parameter integer COUNTER_BITS = 28
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire clk,
|
||||||
|
input wire rst,
|
||||||
|
input wire [COUNTER_BITS-1:0] pulse_length,
|
||||||
|
input wire start_of_pulse,
|
||||||
|
output wire pulse_out,
|
||||||
|
output wire pulse_tlast
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [COUNTER_BITS-1:0] pulse_cnt;
|
||||||
|
reg pulse_active;
|
||||||
|
|
||||||
|
assign pulse_out = pulse_active;
|
||||||
|
|
||||||
|
assign pulse_tlast = (pulse_cnt == 0) ? pulse_active : 0;
|
||||||
|
|
||||||
|
always @ (posedge clk) begin
|
||||||
|
if (rst == 1'b1) begin
|
||||||
|
pulse_cnt <= 0;
|
||||||
|
pulse_active <= 0;
|
||||||
|
end else begin
|
||||||
|
if (start_of_pulse) begin
|
||||||
|
pulse_active <= 1;
|
||||||
|
pulse_cnt <= pulse_length;
|
||||||
|
end
|
||||||
|
|
||||||
|
if (pulse_active) begin
|
||||||
|
pulse_cnt <= pulse_cnt - 1;
|
||||||
|
if (pulse_cnt == 0) begin
|
||||||
|
pulse_active <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
`resetall
|
||||||
430
project_1.srcs/sources_1/hdl/timing_engine.sv
Executable file
430
project_1.srcs/sources_1/hdl/timing_engine.sv
Executable file
@@ -0,0 +1,430 @@
|
|||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
module timing_engine #
|
||||||
|
(
|
||||||
|
parameter integer AXI_ADDR_WIDTH = 32,
|
||||||
|
parameter integer AXI_DATA_WIDTH = 32,
|
||||||
|
parameter NUM_RX = 2,
|
||||||
|
parameter NUM_TIMING_PULSES = 8
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire clk,
|
||||||
|
input wire pps,
|
||||||
|
|
||||||
|
// AXI4L Config Interface
|
||||||
|
axi4l_intf.slave ctrl_if,
|
||||||
|
|
||||||
|
output wire start_of_cpi,
|
||||||
|
output wire start_of_pulse,
|
||||||
|
|
||||||
|
output wire [NUM_TIMING_PULSES-1:0] timing_pulses
|
||||||
|
|
||||||
|
// axi4s_intf.master hdr_out[NUM_RX]
|
||||||
|
);
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// AXIL Decode
|
||||||
|
// ------------------------------
|
||||||
|
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
|
||||||
|
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
|
||||||
|
wire rden;
|
||||||
|
wire wren;
|
||||||
|
wire [AXI_DATA_WIDTH-1 : 0] wdata;
|
||||||
|
reg [AXI_DATA_WIDTH-1 : 0] rdata;
|
||||||
|
|
||||||
|
|
||||||
|
axil_slave
|
||||||
|
# (
|
||||||
|
.DATA_WIDTH(AXI_DATA_WIDTH),
|
||||||
|
.ADDR_WIDTH(AXI_ADDR_WIDTH)
|
||||||
|
) axil_slave_i
|
||||||
|
(
|
||||||
|
// AXIL Slave
|
||||||
|
.S_AXI_ACLK(ctrl_if.clk),
|
||||||
|
.S_AXI_ARESETN(ctrl_if.resetn),
|
||||||
|
.S_AXI_AWADDR(ctrl_if.awaddr),
|
||||||
|
.S_AXI_AWPROT(ctrl_if.awprot),
|
||||||
|
.S_AXI_AWVALID(ctrl_if.awvalid),
|
||||||
|
.S_AXI_AWREADY(ctrl_if.awready),
|
||||||
|
.S_AXI_WDATA(ctrl_if.wdata),
|
||||||
|
.S_AXI_WSTRB(ctrl_if.wstrb),
|
||||||
|
.S_AXI_WVALID(ctrl_if.wvalid),
|
||||||
|
.S_AXI_WREADY(ctrl_if.wready),
|
||||||
|
.S_AXI_BRESP(ctrl_if.bresp),
|
||||||
|
.S_AXI_BVALID(ctrl_if.bvalid),
|
||||||
|
.S_AXI_BREADY(ctrl_if.bready),
|
||||||
|
.S_AXI_ARADDR(ctrl_if.araddr),
|
||||||
|
.S_AXI_ARPROT(ctrl_if.arprot),
|
||||||
|
.S_AXI_ARVALID(ctrl_if.arvalid),
|
||||||
|
.S_AXI_ARREADY(ctrl_if.arready),
|
||||||
|
.S_AXI_RDATA(ctrl_if.rdata),
|
||||||
|
.S_AXI_RRESP(ctrl_if.rresp),
|
||||||
|
.S_AXI_RVALID(ctrl_if.rvalid),
|
||||||
|
.S_AXI_RREADY(ctrl_if.rready),
|
||||||
|
|
||||||
|
.raddr(raddr),
|
||||||
|
.waddr(waddr),
|
||||||
|
.wren(wren),
|
||||||
|
.rden(rden),
|
||||||
|
.wdata(wdata),
|
||||||
|
.rdata(rdata)
|
||||||
|
);
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Config Registers
|
||||||
|
// ------------------------------
|
||||||
|
wire reset;
|
||||||
|
assign reset = ~ctrl_if.resetn;
|
||||||
|
reg [31:0] reg_ctrl;
|
||||||
|
reg [27:0] reg_pri;
|
||||||
|
reg [27:0] reg_num_pulses;
|
||||||
|
reg [27:0] reg_inter_cpi;
|
||||||
|
reg [31:0] reg_pps_sec_set;
|
||||||
|
reg [27:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
|
||||||
|
reg [28:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
|
||||||
|
|
||||||
|
reg [63:0] system_time;
|
||||||
|
reg [63:0] pps_frac_sec;
|
||||||
|
reg [31:0] pps_sec;
|
||||||
|
reg reg_pps_set;
|
||||||
|
reg hdr_bram_we;
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
reg_ctrl <= 0;
|
||||||
|
end else if (wren && waddr[11:0] == 'h000) begin
|
||||||
|
reg_ctrl <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
reg_pri <= 0;
|
||||||
|
end else if (wren && waddr[11:0] == 'h004) begin
|
||||||
|
reg_pri <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
reg_num_pulses <= 0;
|
||||||
|
end else if (wren && waddr[11:0] == 'h008) begin
|
||||||
|
reg_num_pulses <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
reg_inter_cpi <= 0;
|
||||||
|
end else if (wren && waddr[11:0] == 'h010) begin
|
||||||
|
reg_inter_cpi <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
reg_pps_sec_set <= 0;
|
||||||
|
reg_pps_set <= 0;
|
||||||
|
end else if (wren && waddr[11:0] == 'h014) begin
|
||||||
|
reg_pps_sec_set <= wdata;
|
||||||
|
reg_pps_set <= 1;
|
||||||
|
end else begin
|
||||||
|
reg_pps_set <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
genvar gen_reg;
|
||||||
|
generate
|
||||||
|
for (gen_reg = 0; gen_reg < NUM_TIMING_PULSES; gen_reg = gen_reg + 1) begin
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
reg_pulse_start[gen_reg] <= 28'hFFFFFF;
|
||||||
|
end else if (wren && waddr[11:0] == ('h080 + gen_reg*8)) begin
|
||||||
|
reg_pulse_start[gen_reg] <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (reset) begin
|
||||||
|
reg_pulse_width[gen_reg] <= 0;
|
||||||
|
end else if (wren && waddr[11:0] == ('h080 + gen_reg*8 + 4)) begin
|
||||||
|
reg_pulse_width[gen_reg] <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (wren && waddr[11:10] == 2'b11) begin
|
||||||
|
hdr_bram_we <= 1;
|
||||||
|
end else begin
|
||||||
|
hdr_bram_we <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (rden) begin
|
||||||
|
if (raddr[11:0] == 'h000)
|
||||||
|
rdata <= reg_ctrl;
|
||||||
|
if (raddr[11:0] == 'h004)
|
||||||
|
rdata <= reg_pri;
|
||||||
|
if (raddr[11:0] == 'h008)
|
||||||
|
rdata <= reg_num_pulses;
|
||||||
|
if (raddr[11:0] == 'h00C)
|
||||||
|
rdata <= reg_inter_cpi;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Timestamping
|
||||||
|
// ------------------------------
|
||||||
|
reg [63:0] system_time_start_of_cpi;
|
||||||
|
reg [63:0] pps_sec_start_of_cpi;
|
||||||
|
reg [63:0] pps_frac_sec_start_of_cpi;
|
||||||
|
|
||||||
|
|
||||||
|
reg [15:0] pps_pipe;
|
||||||
|
reg pps_debounce;
|
||||||
|
reg pps_q;
|
||||||
|
reg pps_q2;
|
||||||
|
reg pps_red;
|
||||||
|
|
||||||
|
always @ (posedge clk) begin
|
||||||
|
pps_pipe <= {pps_pipe[14:0], pps};
|
||||||
|
pps_debounce = |pps_pipe;
|
||||||
|
pps_q <= pps_debounce;
|
||||||
|
pps_q2 <= pps_q;
|
||||||
|
pps_red <= !pps_q2 & pps_q;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @ (posedge clk) begin
|
||||||
|
system_time <= system_time + 1;
|
||||||
|
|
||||||
|
if (start_of_cpi) begin
|
||||||
|
system_time_start_of_cpi <= system_time;
|
||||||
|
pps_frac_sec_start_of_cpi <= pps_frac_sec;
|
||||||
|
pps_sec_start_of_cpi <= pps_sec;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Fractional seconds rolls over every time PPS strobes
|
||||||
|
if (pps_red) begin
|
||||||
|
pps_frac_sec <= 0;
|
||||||
|
end else begin
|
||||||
|
pps_frac_sec <= pps_frac_sec + 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
if (reg_pps_set) begin
|
||||||
|
pps_sec <= reg_pps_sec_set;
|
||||||
|
end else if (pps_red) begin
|
||||||
|
pps_sec <= pps_sec + 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Header Generation
|
||||||
|
// ------------------------------
|
||||||
|
// wire start_of_cpi_hdr_clk;
|
||||||
|
|
||||||
|
// xpm_cdc_pulse #(
|
||||||
|
// .RST_USED(0)
|
||||||
|
// )
|
||||||
|
// xpm_cdc_pulse_inst (
|
||||||
|
// .src_clk(clk),
|
||||||
|
// .src_pulse(start_of_cpi_stretch),
|
||||||
|
// .dest_clk(hdr_out[0].clk),
|
||||||
|
// .dest_pulse(start_of_cpi_hdr_clk)
|
||||||
|
// );
|
||||||
|
|
||||||
|
// reg [7:0] hdr_count;
|
||||||
|
// reg hdr_active;
|
||||||
|
// reg hdr_active_q;
|
||||||
|
// reg hdr_active_q2;
|
||||||
|
// reg hdr_active_q3;
|
||||||
|
// reg [63:0] hdr_bram_out;
|
||||||
|
// reg [63:0] hdr_data;
|
||||||
|
// wire hdr_tlast;
|
||||||
|
// reg hdr_tlast_q;
|
||||||
|
// reg hdr_tlast_q2;
|
||||||
|
// reg hdr_tlast_q3;
|
||||||
|
|
||||||
|
// always @ (posedge hdr_out[0].clk) begin
|
||||||
|
// if (rst == 1'b1) begin
|
||||||
|
// hdr_count <= 0;
|
||||||
|
// hdr_active <= 0;
|
||||||
|
// end else begin
|
||||||
|
// if (start_of_cpi_hdr_clk) begin
|
||||||
|
// hdr_active <= 1;
|
||||||
|
// hdr_count <= 0;
|
||||||
|
// end
|
||||||
|
|
||||||
|
// if (hdr_active) begin
|
||||||
|
// hdr_count <= hdr_count + 1;
|
||||||
|
// if (hdr_count == 127) begin
|
||||||
|
// hdr_active <= 0;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
// hdr_active_q <= hdr_active;
|
||||||
|
// hdr_active_q2 <= hdr_active_q;
|
||||||
|
// hdr_active_q3 <= hdr_active_q2;
|
||||||
|
|
||||||
|
// hdr_tlast_q <= hdr_tlast;
|
||||||
|
// hdr_tlast_q2 <= hdr_tlast_q;
|
||||||
|
// hdr_tlast_q3 <= hdr_tlast_q2;
|
||||||
|
|
||||||
|
|
||||||
|
// if (hdr_count == 6) begin // index 3 of header after accounting for latency (64 bit words)
|
||||||
|
// hdr_data <= {32'h00000000, pps_sec_start_of_cpi};
|
||||||
|
// end else if (hdr_count == 7) begin
|
||||||
|
// hdr_data <= pps_frac_sec_start_of_cpi;
|
||||||
|
// end else if (hdr_count == 8) begin
|
||||||
|
// hdr_data <= system_time_start_of_cpi;
|
||||||
|
// end else begin
|
||||||
|
// hdr_data <= hdr_bram_out;
|
||||||
|
// end
|
||||||
|
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
// assign hdr_tlast = (hdr_count == 127) ? 1 : 0;
|
||||||
|
|
||||||
|
// hdr_mem hdr_mem_i (
|
||||||
|
// .clka(ctrl_if.clk),
|
||||||
|
// .ena(1'b1),
|
||||||
|
// .wea(hdr_bram_we),
|
||||||
|
// .addra(waddr[9:2]),
|
||||||
|
// .dina(wdata),
|
||||||
|
|
||||||
|
// .clkb(hdr_out[0].clk),
|
||||||
|
// .enb(1'b1),
|
||||||
|
// .addrb(hdr_count),
|
||||||
|
// .doutb(hdr_bram_out)
|
||||||
|
// );
|
||||||
|
|
||||||
|
|
||||||
|
// genvar i;
|
||||||
|
// generate
|
||||||
|
// for (i = 0; i < NUM_RX; i = i + 1) begin
|
||||||
|
// hdr_fifo hdr_fifo_i (
|
||||||
|
// .s_axis_aresetn(rstn),
|
||||||
|
// .s_axis_aclk(hdr_out[i].clk),
|
||||||
|
|
||||||
|
// .s_axis_tvalid(hdr_active_q3),
|
||||||
|
// .s_axis_tready(),
|
||||||
|
// .s_axis_tdata(hdr_data),
|
||||||
|
// .s_axis_tlast(hdr_tlast_q3),
|
||||||
|
|
||||||
|
// .m_axis_tvalid(hdr_out[i].tvalid),
|
||||||
|
// .m_axis_tready(hdr_out[i].tready),
|
||||||
|
// .m_axis_tdata(hdr_out[i].tdata),
|
||||||
|
// .m_axis_tlast(hdr_out[i].tlast)
|
||||||
|
// );
|
||||||
|
|
||||||
|
// assign hdr_out[i].tkeep = '1;
|
||||||
|
// assign hdr_out[i].tuser = 64;
|
||||||
|
// assign hdr_out[i].tdest = 0;
|
||||||
|
// end
|
||||||
|
// endgenerate
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Timing
|
||||||
|
// ------------------------------
|
||||||
|
wire rst;
|
||||||
|
wire rstn;
|
||||||
|
|
||||||
|
reg [27:0] pri_cnt;
|
||||||
|
reg [27:0] pulse_cnt;
|
||||||
|
wire inter_cpi_active;
|
||||||
|
reg start_of_pulse_reg;
|
||||||
|
reg start_of_cpi_reg;
|
||||||
|
reg [3:0] start_of_cpi_pipe;
|
||||||
|
wire start_of_cpi_stretch;
|
||||||
|
|
||||||
|
assign rst = reg_ctrl[0];
|
||||||
|
assign rstn = ~rst;
|
||||||
|
assign start_of_cpi = start_of_cpi_reg;
|
||||||
|
assign start_of_pulse = start_of_pulse_reg;
|
||||||
|
|
||||||
|
assign inter_cpi_active = (pulse_cnt < reg_num_pulses) ? 0 : 1;
|
||||||
|
assign start_of_cpi_stretch = |start_of_cpi_pipe;
|
||||||
|
|
||||||
|
always @ (posedge clk) begin
|
||||||
|
if (rst == 1'b1) begin
|
||||||
|
pri_cnt <= 0;
|
||||||
|
pulse_cnt <= 0;
|
||||||
|
start_of_pulse_reg = 1'b0;
|
||||||
|
end else begin
|
||||||
|
|
||||||
|
start_of_cpi_pipe <= {start_of_cpi_pipe[2:0], start_of_cpi};
|
||||||
|
|
||||||
|
start_of_pulse_reg = 1'b0;
|
||||||
|
start_of_cpi_reg = 1'b0;
|
||||||
|
pri_cnt <= pri_cnt + 1;
|
||||||
|
|
||||||
|
if (inter_cpi_active == 0) begin
|
||||||
|
|
||||||
|
if (pri_cnt == 1) begin
|
||||||
|
start_of_pulse_reg = 1'b1;
|
||||||
|
if (pulse_cnt == 0) begin
|
||||||
|
start_of_cpi_reg = 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
if (pri_cnt == reg_pri) begin
|
||||||
|
pri_cnt <= 0;
|
||||||
|
pulse_cnt <= pulse_cnt + 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
|
||||||
|
if (pri_cnt == reg_inter_cpi) begin
|
||||||
|
pri_cnt <= 0;
|
||||||
|
pulse_cnt <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Pulse Generators
|
||||||
|
// ------------------------------
|
||||||
|
reg [NUM_TIMING_PULSES-1:0] pulse_start;
|
||||||
|
reg [NUM_TIMING_PULSES-1:0] timing_pulses_i;
|
||||||
|
|
||||||
|
genvar j;
|
||||||
|
generate
|
||||||
|
for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
|
||||||
|
|
||||||
|
assign timing_pulses[j] = timing_pulses_i[j] | reg_pulse_start[j][28];
|
||||||
|
|
||||||
|
always @ (posedge clk) begin
|
||||||
|
if (pri_cnt == reg_pulse_start[j][27:0]) begin
|
||||||
|
pulse_start[j] <= 1;
|
||||||
|
end else begin
|
||||||
|
pulse_start[j] <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
pulse_generator pulse_generator_i(
|
||||||
|
.clk(clk),
|
||||||
|
.rst(rst),
|
||||||
|
.pulse_length(reg_pulse_width[j]),
|
||||||
|
.start_of_pulse(pulse_start[j]),
|
||||||
|
.pulse_out(timing_pulses_i[j]),
|
||||||
|
.pulse_tlast()
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
`resetall
|
||||||
395
project_1.srcs/sources_1/hdl/top.sv
Normal file
395
project_1.srcs/sources_1/hdl/top.sv
Normal file
@@ -0,0 +1,395 @@
|
|||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
module top #
|
||||||
|
(
|
||||||
|
parameter NUM_RX = 2
|
||||||
|
)
|
||||||
|
(
|
||||||
|
input wire sys_clk_p,
|
||||||
|
input wire sys_clk_n,
|
||||||
|
output wire [2:0] leds,
|
||||||
|
input wire uart_rxd,
|
||||||
|
output wire uart_txd,
|
||||||
|
output wire fan_pwm,
|
||||||
|
|
||||||
|
output wire [7:0] pcie_mgt_txp,
|
||||||
|
output wire [7:0] pcie_mgt_txn,
|
||||||
|
input wire [7:0] pcie_mgt_rxp,
|
||||||
|
input wire [7:0] pcie_mgt_rxn,
|
||||||
|
input wire pcie_rst_n,
|
||||||
|
input wire pcie_ref_clk_p,
|
||||||
|
input wire pcie_ref_clk_n
|
||||||
|
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
parameter DATE_CODE = 32'h0000_0000;
|
||||||
|
parameter TIME_CODE = 32'h0000_0000;
|
||||||
|
|
||||||
|
wire axi_pcie_resetn;
|
||||||
|
wire axi_pcie_clk;
|
||||||
|
wire axil_resetn;
|
||||||
|
wire axil_clk;
|
||||||
|
wire usr_irq_req;
|
||||||
|
wire [5:0] pcie_cfg_ltssm_state;
|
||||||
|
wire pcie_user_lnk_up;
|
||||||
|
wire [31:0] gpo;
|
||||||
|
wire [31:0] gpi;
|
||||||
|
assign usr_irq_req = 1'b0;
|
||||||
|
|
||||||
|
|
||||||
|
axi4l_intf # (
|
||||||
|
.AXI_ADDR_WIDTH(32),
|
||||||
|
.AXI_DATA_WIDTH(32)
|
||||||
|
)
|
||||||
|
util_reg_if (
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.resetn(axi_pcie_resetn)
|
||||||
|
);
|
||||||
|
|
||||||
|
axi4l_intf # (
|
||||||
|
.AXI_ADDR_WIDTH(32),
|
||||||
|
.AXI_DATA_WIDTH(32)
|
||||||
|
)
|
||||||
|
descriptors_if (
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.resetn(axi_pcie_resetn)
|
||||||
|
);
|
||||||
|
|
||||||
|
axi4l_intf # (
|
||||||
|
.AXI_ADDR_WIDTH(32),
|
||||||
|
.AXI_DATA_WIDTH(32)
|
||||||
|
)
|
||||||
|
timing_if (
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.resetn(axi_pcie_resetn)
|
||||||
|
);
|
||||||
|
|
||||||
|
axi4l_intf # (
|
||||||
|
.AXI_ADDR_WIDTH(32),
|
||||||
|
.AXI_DATA_WIDTH(32)
|
||||||
|
)
|
||||||
|
data_gen_if (
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.resetn(axi_pcie_resetn)
|
||||||
|
);
|
||||||
|
|
||||||
|
parameter NUM_DMA = 2;
|
||||||
|
|
||||||
|
axi4l_intf # (
|
||||||
|
.AXI_ADDR_WIDTH(32),
|
||||||
|
.AXI_DATA_WIDTH(32)
|
||||||
|
)
|
||||||
|
pcie_dma_ctrl_axi[NUM_DMA](
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.resetn(axi_pcie_resetn)
|
||||||
|
);
|
||||||
|
|
||||||
|
axi4_intf # (
|
||||||
|
.AXI_ADDR_WIDTH(40),
|
||||||
|
.AXI_DATA_WIDTH(256)
|
||||||
|
)
|
||||||
|
pcie_dma_maxi[NUM_DMA](
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.resetn(axi_pcie_resetn)
|
||||||
|
);
|
||||||
|
|
||||||
|
axi4s_intf # (
|
||||||
|
.AXI_DATA_WIDTH(128)
|
||||||
|
)
|
||||||
|
pcie_dma_axis[NUM_DMA](
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.resetn(axi_pcie_resetn)
|
||||||
|
);
|
||||||
|
|
||||||
|
design_1 design_1_i
|
||||||
|
(
|
||||||
|
.sys_clk_clk_n(sys_clk_n),
|
||||||
|
.sys_clk_clk_p(sys_clk_p),
|
||||||
|
.UART_0_rxd(uart_rxd),
|
||||||
|
.UART_0_txd(uart_txd),
|
||||||
|
.pcie_mgt_0_rxn(pcie_mgt_rxn),
|
||||||
|
.pcie_mgt_0_rxp(pcie_mgt_rxp),
|
||||||
|
.pcie_mgt_0_txn(pcie_mgt_txn),
|
||||||
|
.pcie_mgt_0_txp(pcie_mgt_txp),
|
||||||
|
.pcie_refclk_clk_n(pcie_ref_clk_n),
|
||||||
|
.pcie_refclk_clk_p(pcie_ref_clk_p),
|
||||||
|
.pcie_rstn(pcie_rst_n),
|
||||||
|
.pcie_cfg_ltssm_state(pcie_cfg_ltssm_state),
|
||||||
|
.pcie_user_lnk_up(pcie_user_lnk_up),
|
||||||
|
.usr_irq_req(usr_irq_req),
|
||||||
|
|
||||||
|
.axi_pcie_aresetn(axi_pcie_resetn),
|
||||||
|
.axi_pcie_clk(axi_pcie_clk),
|
||||||
|
.axil_resetn(axil_resetn),
|
||||||
|
.axil_clk(axil_clk),
|
||||||
|
|
||||||
|
.axil_util_araddr(util_reg_if.araddr),
|
||||||
|
.axil_util_arprot(util_reg_if.arprot),
|
||||||
|
.axil_util_arready(util_reg_if.arready),
|
||||||
|
.axil_util_arvalid(util_reg_if.arvalid),
|
||||||
|
.axil_util_awaddr(util_reg_if.awaddr),
|
||||||
|
.axil_util_awprot(util_reg_if.awprot),
|
||||||
|
.axil_util_awready(util_reg_if.awready),
|
||||||
|
.axil_util_awvalid(util_reg_if.awvalid),
|
||||||
|
.axil_util_bready(util_reg_if.bready),
|
||||||
|
.axil_util_bresp(util_reg_if.bresp),
|
||||||
|
.axil_util_bvalid(util_reg_if.bvalid),
|
||||||
|
.axil_util_rdata(util_reg_if.rdata),
|
||||||
|
.axil_util_rready(util_reg_if.rready),
|
||||||
|
.axil_util_rresp(util_reg_if.rresp),
|
||||||
|
.axil_util_rvalid(util_reg_if.rvalid),
|
||||||
|
.axil_util_wdata(util_reg_if.wdata),
|
||||||
|
.axil_util_wready(util_reg_if.wready),
|
||||||
|
.axil_util_wstrb(util_reg_if.wstrb),
|
||||||
|
.axil_util_wvalid(util_reg_if.wvalid),
|
||||||
|
|
||||||
|
.axil_timing_araddr(timing_if.araddr),
|
||||||
|
.axil_timing_arprot(timing_if.arprot),
|
||||||
|
.axil_timing_arready(timing_if.arready),
|
||||||
|
.axil_timing_arvalid(timing_if.arvalid),
|
||||||
|
.axil_timing_awaddr(timing_if.awaddr),
|
||||||
|
.axil_timing_awprot(timing_if.awprot),
|
||||||
|
.axil_timing_awready(timing_if.awready),
|
||||||
|
.axil_timing_awvalid(timing_if.awvalid),
|
||||||
|
.axil_timing_bready(timing_if.bready),
|
||||||
|
.axil_timing_bresp(timing_if.bresp),
|
||||||
|
.axil_timing_bvalid(timing_if.bvalid),
|
||||||
|
.axil_timing_rdata(timing_if.rdata),
|
||||||
|
.axil_timing_rready(timing_if.rready),
|
||||||
|
.axil_timing_rresp(timing_if.rresp),
|
||||||
|
.axil_timing_rvalid(timing_if.rvalid),
|
||||||
|
.axil_timing_wdata(timing_if.wdata),
|
||||||
|
.axil_timing_wready(timing_if.wready),
|
||||||
|
.axil_timing_wstrb(timing_if.wstrb),
|
||||||
|
.axil_timing_wvalid(timing_if.wvalid),
|
||||||
|
|
||||||
|
.axil_data_gen_araddr(data_gen_if.araddr),
|
||||||
|
.axil_data_gen_arprot(data_gen_if.arprot),
|
||||||
|
.axil_data_gen_arready(data_gen_if.arready),
|
||||||
|
.axil_data_gen_arvalid(data_gen_if.arvalid),
|
||||||
|
.axil_data_gen_awaddr(data_gen_if.awaddr),
|
||||||
|
.axil_data_gen_awprot(data_gen_if.awprot),
|
||||||
|
.axil_data_gen_awready(data_gen_if.awready),
|
||||||
|
.axil_data_gen_awvalid(data_gen_if.awvalid),
|
||||||
|
.axil_data_gen_bready(data_gen_if.bready),
|
||||||
|
.axil_data_gen_bresp(data_gen_if.bresp),
|
||||||
|
.axil_data_gen_bvalid(data_gen_if.bvalid),
|
||||||
|
.axil_data_gen_rdata(data_gen_if.rdata),
|
||||||
|
.axil_data_gen_rready(data_gen_if.rready),
|
||||||
|
.axil_data_gen_rresp(data_gen_if.rresp),
|
||||||
|
.axil_data_gen_rvalid(data_gen_if.rvalid),
|
||||||
|
.axil_data_gen_wdata(data_gen_if.wdata),
|
||||||
|
.axil_data_gen_wready(data_gen_if.wready),
|
||||||
|
.axil_data_gen_wstrb(data_gen_if.wstrb),
|
||||||
|
.axil_data_gen_wvalid(data_gen_if.wvalid),
|
||||||
|
|
||||||
|
.axil_descriptors_araddr(descriptors_if.araddr),
|
||||||
|
.axil_descriptors_arprot(descriptors_if.arprot),
|
||||||
|
.axil_descriptors_arready(descriptors_if.arready),
|
||||||
|
.axil_descriptors_arvalid(descriptors_if.arvalid),
|
||||||
|
.axil_descriptors_awaddr(descriptors_if.awaddr),
|
||||||
|
.axil_descriptors_awprot(descriptors_if.awprot),
|
||||||
|
.axil_descriptors_awready(descriptors_if.awready),
|
||||||
|
.axil_descriptors_awvalid(descriptors_if.awvalid),
|
||||||
|
.axil_descriptors_bready(descriptors_if.bready),
|
||||||
|
.axil_descriptors_bresp(descriptors_if.bresp),
|
||||||
|
.axil_descriptors_bvalid(descriptors_if.bvalid),
|
||||||
|
.axil_descriptors_rdata(descriptors_if.rdata),
|
||||||
|
.axil_descriptors_rready(descriptors_if.rready),
|
||||||
|
.axil_descriptors_rresp(descriptors_if.rresp),
|
||||||
|
.axil_descriptors_rvalid(descriptors_if.rvalid),
|
||||||
|
.axil_descriptors_wdata(descriptors_if.wdata),
|
||||||
|
.axil_descriptors_wready(descriptors_if.wready),
|
||||||
|
.axil_descriptors_wstrb(descriptors_if.wstrb),
|
||||||
|
.axil_descriptors_wvalid(descriptors_if.wvalid),
|
||||||
|
|
||||||
|
.axil_dma_ctrl0_araddr(pcie_dma_ctrl_axi[0].araddr),
|
||||||
|
.axil_dma_ctrl0_arprot(pcie_dma_ctrl_axi[0].arprot),
|
||||||
|
.axil_dma_ctrl0_arready(pcie_dma_ctrl_axi[0].arready),
|
||||||
|
.axil_dma_ctrl0_arvalid(pcie_dma_ctrl_axi[0].arvalid),
|
||||||
|
.axil_dma_ctrl0_awaddr(pcie_dma_ctrl_axi[0].awaddr),
|
||||||
|
.axil_dma_ctrl0_awprot(pcie_dma_ctrl_axi[0].awprot),
|
||||||
|
.axil_dma_ctrl0_awready(pcie_dma_ctrl_axi[0].awready),
|
||||||
|
.axil_dma_ctrl0_awvalid(pcie_dma_ctrl_axi[0].awvalid),
|
||||||
|
.axil_dma_ctrl0_bready(pcie_dma_ctrl_axi[0].bready),
|
||||||
|
.axil_dma_ctrl0_bresp(pcie_dma_ctrl_axi[0].bresp),
|
||||||
|
.axil_dma_ctrl0_bvalid(pcie_dma_ctrl_axi[0].bvalid),
|
||||||
|
.axil_dma_ctrl0_rdata(pcie_dma_ctrl_axi[0].rdata),
|
||||||
|
.axil_dma_ctrl0_rready(pcie_dma_ctrl_axi[0].rready),
|
||||||
|
.axil_dma_ctrl0_rresp(pcie_dma_ctrl_axi[0].rresp),
|
||||||
|
.axil_dma_ctrl0_rvalid(pcie_dma_ctrl_axi[0].rvalid),
|
||||||
|
.axil_dma_ctrl0_wdata(pcie_dma_ctrl_axi[0].wdata),
|
||||||
|
.axil_dma_ctrl0_wready(pcie_dma_ctrl_axi[0].wready),
|
||||||
|
.axil_dma_ctrl0_wstrb(pcie_dma_ctrl_axi[0].wstrb),
|
||||||
|
.axil_dma_ctrl0_wvalid(pcie_dma_ctrl_axi[0].wvalid),
|
||||||
|
|
||||||
|
.axil_dma_ctrl1_araddr(pcie_dma_ctrl_axi[1].araddr),
|
||||||
|
.axil_dma_ctrl1_arprot(pcie_dma_ctrl_axi[1].arprot),
|
||||||
|
.axil_dma_ctrl1_arready(pcie_dma_ctrl_axi[1].arready),
|
||||||
|
.axil_dma_ctrl1_arvalid(pcie_dma_ctrl_axi[1].arvalid),
|
||||||
|
.axil_dma_ctrl1_awaddr(pcie_dma_ctrl_axi[1].awaddr),
|
||||||
|
.axil_dma_ctrl1_awprot(pcie_dma_ctrl_axi[1].awprot),
|
||||||
|
.axil_dma_ctrl1_awready(pcie_dma_ctrl_axi[1].awready),
|
||||||
|
.axil_dma_ctrl1_awvalid(pcie_dma_ctrl_axi[1].awvalid),
|
||||||
|
.axil_dma_ctrl1_bready(pcie_dma_ctrl_axi[1].bready),
|
||||||
|
.axil_dma_ctrl1_bresp(pcie_dma_ctrl_axi[1].bresp),
|
||||||
|
.axil_dma_ctrl1_bvalid(pcie_dma_ctrl_axi[1].bvalid),
|
||||||
|
.axil_dma_ctrl1_rdata(pcie_dma_ctrl_axi[1].rdata),
|
||||||
|
.axil_dma_ctrl1_rready(pcie_dma_ctrl_axi[1].rready),
|
||||||
|
.axil_dma_ctrl1_rresp(pcie_dma_ctrl_axi[1].rresp),
|
||||||
|
.axil_dma_ctrl1_rvalid(pcie_dma_ctrl_axi[1].rvalid),
|
||||||
|
.axil_dma_ctrl1_wdata(pcie_dma_ctrl_axi[1].wdata),
|
||||||
|
.axil_dma_ctrl1_wready(pcie_dma_ctrl_axi[1].wready),
|
||||||
|
.axil_dma_ctrl1_wstrb(pcie_dma_ctrl_axi[1].wstrb),
|
||||||
|
.axil_dma_ctrl1_wvalid(pcie_dma_ctrl_axi[1].wvalid),
|
||||||
|
|
||||||
|
// .pcie_m_axi0_araddr (pcie_dma_maxi[0].araddr),
|
||||||
|
// .pcie_m_axi0_arburst(pcie_dma_maxi[0].arburst),
|
||||||
|
// .pcie_m_axi0_arcache(pcie_dma_maxi[0].arcache),
|
||||||
|
// .pcie_m_axi0_arid (0),
|
||||||
|
// .pcie_m_axi0_arlen (pcie_dma_maxi[0].arlen),
|
||||||
|
// .pcie_m_axi0_arlock (pcie_dma_maxi[0].arlock),
|
||||||
|
// .pcie_m_axi0_arprot (pcie_dma_maxi[0].arprot),
|
||||||
|
// .pcie_m_axi0_arqos (pcie_dma_maxi[0].arqos),
|
||||||
|
// .pcie_m_axi0_arready(pcie_dma_maxi[0].arready),
|
||||||
|
// .pcie_m_axi0_arsize (pcie_dma_maxi[0].arsize),
|
||||||
|
// .pcie_m_axi0_arvalid(pcie_dma_maxi[0].arvalid),
|
||||||
|
.pcie_m_axi0_awaddr (pcie_dma_maxi[0].awaddr),
|
||||||
|
.pcie_m_axi0_awburst(pcie_dma_maxi[0].awburst),
|
||||||
|
.pcie_m_axi0_awcache(pcie_dma_maxi[0].awcache),
|
||||||
|
.pcie_m_axi0_awlen (pcie_dma_maxi[0].awlen),
|
||||||
|
.pcie_m_axi0_awlock (pcie_dma_maxi[0].awlock),
|
||||||
|
.pcie_m_axi0_awprot (pcie_dma_maxi[0].awprot),
|
||||||
|
.pcie_m_axi0_awqos (pcie_dma_maxi[0].awqos),
|
||||||
|
.pcie_m_axi0_awready(pcie_dma_maxi[0].awready),
|
||||||
|
.pcie_m_axi0_awregion(4'b0000),
|
||||||
|
.pcie_m_axi0_awsize (pcie_dma_maxi[0].awsize),
|
||||||
|
.pcie_m_axi0_awvalid(pcie_dma_maxi[0].awvalid),
|
||||||
|
.pcie_m_axi0_bready (pcie_dma_maxi[0].bready),
|
||||||
|
.pcie_m_axi0_bresp (pcie_dma_maxi[0].bresp),
|
||||||
|
.pcie_m_axi0_bvalid (pcie_dma_maxi[0].bvalid),
|
||||||
|
// .pcie_m_axi0_rdata (pcie_dma_maxi[0].rdata),
|
||||||
|
// .pcie_m_axi0_rid (),
|
||||||
|
// .pcie_m_axi0_rlast (pcie_dma_maxi[0].rlast),
|
||||||
|
// .pcie_m_axi0_rready (pcie_dma_maxi[0].rready),
|
||||||
|
// .pcie_m_axi0_rresp (pcie_dma_maxi[0].rresp),
|
||||||
|
// .pcie_m_axi0_rvalid (pcie_dma_maxi[0].rvalid),
|
||||||
|
.pcie_m_axi0_wdata (pcie_dma_maxi[0].wdata),
|
||||||
|
.pcie_m_axi0_wlast (pcie_dma_maxi[0].wlast),
|
||||||
|
.pcie_m_axi0_wready (pcie_dma_maxi[0].wready),
|
||||||
|
.pcie_m_axi0_wstrb (pcie_dma_maxi[0].wstrb),
|
||||||
|
.pcie_m_axi0_wvalid (pcie_dma_maxi[0].wvalid),
|
||||||
|
|
||||||
|
// .pcie_m_axi1_araddr (pcie_dma_maxi[1].araddr),
|
||||||
|
// .pcie_m_axi1_arburst(pcie_dma_maxi[1].arburst),
|
||||||
|
// .pcie_m_axi1_arcache(pcie_dma_maxi[1].arcache),
|
||||||
|
// .pcie_m_axi1_arid (0),
|
||||||
|
// .pcie_m_axi1_arlen (pcie_dma_maxi[1].arlen),
|
||||||
|
// .pcie_m_axi1_arlock (pcie_dma_maxi[1].arlock),
|
||||||
|
// .pcie_m_axi1_arprot (pcie_dma_maxi[1].arprot),
|
||||||
|
// .pcie_m_axi1_arqos (pcie_dma_maxi[1].arqos),
|
||||||
|
// .pcie_m_axi1_arready(pcie_dma_maxi[1].arready),
|
||||||
|
// .pcie_m_axi1_arsize (pcie_dma_maxi[1].arsize),
|
||||||
|
// .pcie_m_axi1_arvalid(pcie_dma_maxi[1].arvalid),
|
||||||
|
.pcie_m_axi1_awaddr (pcie_dma_maxi[1].awaddr),
|
||||||
|
.pcie_m_axi1_awburst(pcie_dma_maxi[1].awburst),
|
||||||
|
.pcie_m_axi1_awcache(pcie_dma_maxi[1].awcache),
|
||||||
|
.pcie_m_axi1_awlen (pcie_dma_maxi[1].awlen),
|
||||||
|
.pcie_m_axi1_awlock (pcie_dma_maxi[1].awlock),
|
||||||
|
.pcie_m_axi1_awprot (pcie_dma_maxi[1].awprot),
|
||||||
|
.pcie_m_axi1_awqos (pcie_dma_maxi[1].awqos),
|
||||||
|
.pcie_m_axi1_awready(pcie_dma_maxi[1].awready),
|
||||||
|
.pcie_m_axi1_awregion(4'b0000),
|
||||||
|
.pcie_m_axi1_awsize (pcie_dma_maxi[1].awsize),
|
||||||
|
.pcie_m_axi1_awvalid(pcie_dma_maxi[1].awvalid),
|
||||||
|
.pcie_m_axi1_bready (pcie_dma_maxi[1].bready),
|
||||||
|
.pcie_m_axi1_bresp (pcie_dma_maxi[1].bresp),
|
||||||
|
.pcie_m_axi1_bvalid (pcie_dma_maxi[1].bvalid),
|
||||||
|
// .pcie_m_axi1_rdata (pcie_dma_maxi[1].rdata),
|
||||||
|
// .pcie_m_axi1_rid (),
|
||||||
|
// .pcie_m_axi1_rlast (pcie_dma_maxi[1].rlast),
|
||||||
|
// .pcie_m_axi1_rready (pcie_dma_maxi[1].rready),
|
||||||
|
// .pcie_m_axi1_rresp (pcie_dma_maxi[1].rresp),
|
||||||
|
// .pcie_m_axi1_rvalid (pcie_dma_maxi[1].rvalid),
|
||||||
|
.pcie_m_axi1_wdata (pcie_dma_maxi[1].wdata),
|
||||||
|
.pcie_m_axi1_wlast (pcie_dma_maxi[1].wlast),
|
||||||
|
.pcie_m_axi1_wready (pcie_dma_maxi[1].wready),
|
||||||
|
.pcie_m_axi1_wstrb (pcie_dma_maxi[1].wstrb),
|
||||||
|
.pcie_m_axi1_wvalid (pcie_dma_maxi[1].wvalid)
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
assign gpi = 0;
|
||||||
|
|
||||||
|
util_reg util_reg_i
|
||||||
|
(
|
||||||
|
.ctrl_if(util_reg_if),
|
||||||
|
|
||||||
|
.gpo(gpo),
|
||||||
|
.gpi(gpi),
|
||||||
|
.fan_pwm(fan_pwm),
|
||||||
|
.datecode(DATE_CODE),
|
||||||
|
.timecode(TIME_CODE)
|
||||||
|
);
|
||||||
|
|
||||||
|
assign leds[0] = gpo[0];
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
wire [7:0] timing_pulses;
|
||||||
|
wire pps;
|
||||||
|
wire start_of_cpi;
|
||||||
|
wire start_of_pulse;
|
||||||
|
|
||||||
|
timing_engine timing_engine_i
|
||||||
|
(
|
||||||
|
.clk(axi_pcie_clk),
|
||||||
|
.pps(pps),
|
||||||
|
|
||||||
|
.ctrl_if(timing_if),
|
||||||
|
|
||||||
|
.start_of_cpi(start_of_cpi),
|
||||||
|
.start_of_pulse(start_of_pulse),
|
||||||
|
.timing_pulses(timing_pulses)
|
||||||
|
);
|
||||||
|
|
||||||
|
data_gen
|
||||||
|
# (
|
||||||
|
.NUM_CH(2)
|
||||||
|
) data_gen_i (
|
||||||
|
.ctrl_if(data_gen_if),
|
||||||
|
.trigger(start_of_pulse),
|
||||||
|
.data_out(pcie_dma_axis)
|
||||||
|
);
|
||||||
|
|
||||||
|
axi_descriptor
|
||||||
|
# (
|
||||||
|
.DESCRIPTOR_WIDTH(128),
|
||||||
|
.DESCRIPTOR_LENGTH(NUM_DMA+1)
|
||||||
|
) axi_descriptor_i
|
||||||
|
(
|
||||||
|
.axi(descriptors_if),
|
||||||
|
.descriptor_list('{{64'b0, 32'h00000000, 32'h10000},
|
||||||
|
{64'b0, 32'h01000000, 32'h20000},
|
||||||
|
{64'b0, 32'h01010000, 32'h20000}})
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
genvar dma_index;
|
||||||
|
generate
|
||||||
|
for (dma_index=0; dma_index < NUM_DMA; dma_index++) begin
|
||||||
|
dma_engine_256 dma_engine_256_i (
|
||||||
|
.ctrl_if(pcie_dma_ctrl_axi[dma_index]),
|
||||||
|
.axis(pcie_dma_axis[dma_index]), // Stream Data In
|
||||||
|
.axim(pcie_dma_maxi[dma_index]) // MM Data Out - Goes to Host Proc via PCIe
|
||||||
|
);
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
152
project_1.srcs/sources_1/hdl/util_reg.sv
Executable file
152
project_1.srcs/sources_1/hdl/util_reg.sv
Executable file
@@ -0,0 +1,152 @@
|
|||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
module util_reg #
|
||||||
|
(
|
||||||
|
parameter integer AXI_ADDR_WIDTH = 32,
|
||||||
|
parameter integer AXI_DATA_WIDTH = 32
|
||||||
|
)
|
||||||
|
(
|
||||||
|
// AXI4L Config Interface
|
||||||
|
axi4l_intf.slave ctrl_if,
|
||||||
|
|
||||||
|
output wire [31:0] gpo,
|
||||||
|
input wire [31:0] gpi,
|
||||||
|
output wire fan_pwm,
|
||||||
|
input wire [31:0] datecode,
|
||||||
|
input wire [31:0] timecode
|
||||||
|
);
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// AXIL Decode
|
||||||
|
// ------------------------------
|
||||||
|
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
|
||||||
|
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
|
||||||
|
wire rden;
|
||||||
|
wire wren;
|
||||||
|
wire [AXI_DATA_WIDTH-1 : 0] wdata;
|
||||||
|
reg [AXI_DATA_WIDTH-1 : 0] rdata;
|
||||||
|
|
||||||
|
|
||||||
|
axil_slave
|
||||||
|
# (
|
||||||
|
.DATA_WIDTH(AXI_DATA_WIDTH),
|
||||||
|
.ADDR_WIDTH(AXI_ADDR_WIDTH)
|
||||||
|
) axil_slave_i
|
||||||
|
(
|
||||||
|
// AXIL Slave
|
||||||
|
.S_AXI_ACLK(ctrl_if.clk),
|
||||||
|
.S_AXI_ARESETN(ctrl_if.resetn),
|
||||||
|
.S_AXI_AWADDR(ctrl_if.awaddr),
|
||||||
|
.S_AXI_AWPROT(ctrl_if.awprot),
|
||||||
|
.S_AXI_AWVALID(ctrl_if.awvalid),
|
||||||
|
.S_AXI_AWREADY(ctrl_if.awready),
|
||||||
|
.S_AXI_WDATA(ctrl_if.wdata),
|
||||||
|
.S_AXI_WSTRB(ctrl_if.wstrb),
|
||||||
|
.S_AXI_WVALID(ctrl_if.wvalid),
|
||||||
|
.S_AXI_WREADY(ctrl_if.wready),
|
||||||
|
.S_AXI_BRESP(ctrl_if.bresp),
|
||||||
|
.S_AXI_BVALID(ctrl_if.bvalid),
|
||||||
|
.S_AXI_BREADY(ctrl_if.bready),
|
||||||
|
.S_AXI_ARADDR(ctrl_if.araddr),
|
||||||
|
.S_AXI_ARPROT(ctrl_if.arprot),
|
||||||
|
.S_AXI_ARVALID(ctrl_if.arvalid),
|
||||||
|
.S_AXI_ARREADY(ctrl_if.arready),
|
||||||
|
.S_AXI_RDATA(ctrl_if.rdata),
|
||||||
|
.S_AXI_RRESP(ctrl_if.rresp),
|
||||||
|
.S_AXI_RVALID(ctrl_if.rvalid),
|
||||||
|
.S_AXI_RREADY(ctrl_if.rready),
|
||||||
|
|
||||||
|
.raddr(raddr),
|
||||||
|
.waddr(waddr),
|
||||||
|
.wren(wren),
|
||||||
|
.rden(rden),
|
||||||
|
.wdata(wdata),
|
||||||
|
.rdata(rdata)
|
||||||
|
);
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Config Registers
|
||||||
|
// ------------------------------
|
||||||
|
wire reset;
|
||||||
|
assign reset = ~ctrl_if.resetn;
|
||||||
|
reg [31:0] scratch;
|
||||||
|
reg [31:0] reg_gpo;
|
||||||
|
reg [24:0] pwm_period;
|
||||||
|
reg [24:0] pwm_pulsewidth;
|
||||||
|
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (~ctrl_if.resetn) begin
|
||||||
|
scratch <= 0;
|
||||||
|
reg_gpo <= 0;
|
||||||
|
pwm_period <= 1500000;
|
||||||
|
pwm_pulsewidth <= 500000;
|
||||||
|
end else begin
|
||||||
|
if (wren) begin
|
||||||
|
if ( waddr[15:0] == 'h004 )
|
||||||
|
scratch <= wdata;
|
||||||
|
if ( waddr[15:0] == 'h008 )
|
||||||
|
reg_gpo <= wdata;
|
||||||
|
if ( waddr[15:0] == 'h010 )
|
||||||
|
pwm_period <= wdata;
|
||||||
|
if ( waddr[15:0] == 'h014 )
|
||||||
|
pwm_pulsewidth <= wdata;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (rden) begin
|
||||||
|
if (raddr[11:0] == 'h000)
|
||||||
|
rdata <= 'h12345678;
|
||||||
|
if (raddr[11:0] == 'h004)
|
||||||
|
rdata <= scratch;
|
||||||
|
if (raddr[11:0] == 'h008)
|
||||||
|
rdata <= reg_gpo;
|
||||||
|
if (raddr[11:0] == 'h00C)
|
||||||
|
rdata <= gpi;
|
||||||
|
if (raddr[11:0] == 'h010)
|
||||||
|
rdata <= pwm_period;
|
||||||
|
if (raddr[11:0] == 'h014)
|
||||||
|
rdata <= pwm_pulsewidth;
|
||||||
|
if (raddr[11:0] == 'h100)
|
||||||
|
rdata <= datecode;
|
||||||
|
if (raddr[11:0] == 'h104)
|
||||||
|
rdata <= timecode;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
assign gpo = reg_gpo;
|
||||||
|
|
||||||
|
// ------------------------------
|
||||||
|
// Fan PWM
|
||||||
|
// ------------------------------
|
||||||
|
reg [24:0] pwm_cnt;
|
||||||
|
reg pwm_out;
|
||||||
|
|
||||||
|
assign fan_pwm = ~pwm_out;
|
||||||
|
|
||||||
|
always @ (posedge ctrl_if.clk) begin
|
||||||
|
if (pwm_cnt < pwm_period) begin
|
||||||
|
pwm_cnt <= pwm_cnt + 1;
|
||||||
|
end else begin
|
||||||
|
pwm_cnt <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
if (pwm_cnt < pwm_pulsewidth) begin
|
||||||
|
pwm_out <= 1'b1;
|
||||||
|
end else begin
|
||||||
|
pwm_out <= 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
`resetall
|
||||||
@@ -0,0 +1,409 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "axi_datamover_0_test",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_datamover:5.1",
|
||||||
|
"ip_revision": "29",
|
||||||
|
"gen_directory": "../../../../project_1.gen/sources_1/ip/axi_datamover_0_test",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "axi_datamover_0_test", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_include_mm2s": [ { "value": "Omit", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_stscmd_is_async": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_include_mm2s_dre": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_include_mm2s_stsfifo": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_btt_used": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_addr_pipe_depth": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_include_s2mm": [ { "value": "Full", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_s2mm_stscmd_is_async": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_data_width": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s_axis_s2mm_tdata_width": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_include_s2mm_dre": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_s2mm_burst_size": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_include_s2mm_stsfifo": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"c_s2mm_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s2mm_btt_used": [ { "value": "23", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s2mm_addr_pipe_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s2mm_support_indet_btt": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_mm2s_include_sf": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_s2mm_include_sf": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_arid": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_awid": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_enable_cache_user": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_enable_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_enable_s2mm": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_enable_mm2s_adv_sig": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_enable_s2mm_adv_sig": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_dummy": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
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|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
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|
||||||
|
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|
||||||
|
"C_M_AXI_MM2S_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_MM2S_STSFIFO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_STSCMD_FIFO_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_STSCMD_IS_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_BTT_USED": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_ADDR_PIPE_DEPTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_AWID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_S2MM_STSFIFO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_STSCMD_FIFO_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_STSCMD_IS_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_BTT_USED": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_SUPPORT_INDET_BTT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_ADDR_PIPE_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MM2S_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_CACHE_USER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_MM2S_TKEEP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_S2MM_TKEEP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_SKID_BUF": [ { "value": "11111", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_ENABLE_S2MM_ADV_SIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_MM2S_ADV_SIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CMD_WIDTH": [ { "value": "72", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "29" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../project_1.gen/sources_1/ip/axi_datamover_0_test" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||||
|
"s2mm_err": [ { "direction": "out" } ],
|
||||||
|
"m_axis_s2mm_cmdsts_awclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axis_s2mm_cmdsts_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||||
|
"s_axis_s2mm_cmd_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_cmd_tready": [ { "direction": "out" } ],
|
||||||
|
"s_axis_s2mm_cmd_tdata": [ { "direction": "in", "size_left": "71", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axis_s2mm_sts_tready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tkeep": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tlast": [ { "direction": "out" } ],
|
||||||
|
"m_axi_s2mm_awid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awuser": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||||
|
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||||
|
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0xFFFF" } ],
|
||||||
|
"s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_tready": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"M_AXI_S2MM": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"address_space_ref": "Data_S2MM",
|
||||||
|
"parameters": {
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "constant", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "128", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||||
|
"AWID": [ { "physical_name": "m_axi_s2mm_awid" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||||
|
"AWUSER": [ { "physical_name": "m_axi_s2mm_awuser" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||||
|
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_S2MM": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||||
|
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||||
|
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||||
|
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_S2MM_CMD": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_s2mm_cmd_tdata" } ],
|
||||||
|
"TREADY": [ { "physical_name": "s_axis_s2mm_cmd_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_s2mm_cmd_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_S2MM_STS": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_s2mm_sts_tdata" } ],
|
||||||
|
"TKEEP": [ { "physical_name": "m_axis_s2mm_sts_tkeep" } ],
|
||||||
|
"TLAST": [ { "physical_name": "m_axis_s2mm_sts_tlast" } ],
|
||||||
|
"TREADY": [ { "physical_name": "m_axis_s2mm_sts_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_s2mm_sts_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_MM2S_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXI", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axi_mm2s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_MM2S_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_S2MM_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axi_s2mm_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_S2MM_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "m_axi_s2mm_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_MM2S_CMDSTS_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_MM2S_CMD:M_AXIS_MM2S_STS", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axis_mm2s_cmdsts_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_MM2S_CMDSTS_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_S2MM_CMDSTS_AWCLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_S2MM_CMD:M_AXIS_S2MM_STS", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axis_s2mm_cmdsts_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "m_axis_s2mm_cmdsts_awclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_S2MM_CMDSTS_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "m_axis_s2mm_cmdsts_aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"address_spaces": {
|
||||||
|
"Data_S2MM": {
|
||||||
|
"range": "4294967296",
|
||||||
|
"width": "32"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,416 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "axi_datamover_256_0",
|
||||||
|
"component_reference": "xilinx.com:ip:axi_datamover:5.1",
|
||||||
|
"ip_revision": "29",
|
||||||
|
"gen_directory": "../../../../project_1.gen/sources_1/ip/axi_datamover_256_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "axi_datamover_256_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_include_mm2s": [ { "value": "Omit", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_stscmd_is_async": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_data_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axis_mm2s_tdata_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_include_mm2s_dre": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_include_mm2s_stsfifo": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_btt_used": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_mm2s_addr_pipe_depth": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_include_s2mm": [ { "value": "Full", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_s2mm_stscmd_is_async": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_data_width": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s_axis_s2mm_tdata_width": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_include_s2mm_dre": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_s2mm_burst_size": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_include_s2mm_stsfifo": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"c_s2mm_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s2mm_btt_used": [ { "value": "23", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s2mm_addr_pipe_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_s2mm_support_indet_btt": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_mm2s_include_sf": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_s2mm_include_sf": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_mm2s_arid": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_id_width": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_m_axi_s2mm_awid": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_enable_cache_user": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"c_enable_mm2s": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_enable_s2mm": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_enable_mm2s_adv_sig": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"c_enable_s2mm_adv_sig": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_dummy": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"c_single_interface": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_INCLUDE_MM2S": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_MM2S_ARID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_MM2S_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_MM2S_STSFIFO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_STSCMD_FIFO_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_STSCMD_IS_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_BTT_USED": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MM2S_ADDR_PIPE_DEPTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_AWID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_S2MM_STSFIFO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_STSCMD_FIFO_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_STSCMD_IS_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_BURST_SIZE": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_BTT_USED": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_SUPPORT_INDET_BTT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_ADDR_PIPE_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MM2S_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S2MM_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_CACHE_USER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_MM2S_TKEEP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_S2MM_TKEEP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_SKID_BUF": [ { "value": "11111", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_ENABLE_S2MM_ADV_SIG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_MM2S_ADV_SIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CMD_WIDTH": [ { "value": "80", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "29" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../project_1.gen/sources_1/ip/axi_datamover_256_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||||
|
"s2mm_halt": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s2mm_halt_cmplt": [ { "direction": "out" } ],
|
||||||
|
"s2mm_err": [ { "direction": "out" } ],
|
||||||
|
"m_axis_s2mm_cmdsts_awclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axis_s2mm_cmdsts_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||||
|
"s_axis_s2mm_cmd_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_cmd_tready": [ { "direction": "out" } ],
|
||||||
|
"s_axis_s2mm_cmd_tdata": [ { "direction": "in", "size_left": "79", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axis_s2mm_sts_tready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tkeep": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axis_s2mm_sts_tlast": [ { "direction": "out" } ],
|
||||||
|
"s2mm_allow_addr_req": [ { "direction": "in", "driver_value": "1" } ],
|
||||||
|
"s2mm_addr_req_posted": [ { "direction": "out" } ],
|
||||||
|
"s2mm_wr_xfer_cmplt": [ { "direction": "out" } ],
|
||||||
|
"s2mm_ld_nxt_len": [ { "direction": "out" } ],
|
||||||
|
"s2mm_wr_len": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awuser": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||||
|
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||||
|
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||||
|
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0xFFFF" } ],
|
||||||
|
"s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"s_axis_s2mm_tready": [ { "direction": "out" } ],
|
||||||
|
"s2mm_dbg_sel": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"s2mm_dbg_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"M_AXI_S2MM": {
|
||||||
|
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"address_space_ref": "Data_S2MM",
|
||||||
|
"parameters": {
|
||||||
|
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "constant", "format": "long", "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "256", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"AWUSER_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_CACHE": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_QOS": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"SUPPORTS_NARROW_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_OUTSTANDING": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"MAX_BURST_LENGTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||||
|
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||||
|
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||||
|
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||||
|
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||||
|
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||||
|
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||||
|
"AWUSER": [ { "physical_name": "m_axi_s2mm_awuser" } ],
|
||||||
|
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||||
|
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||||
|
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||||
|
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||||
|
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||||
|
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||||
|
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||||
|
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||||
|
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_S2MM": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||||
|
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||||
|
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||||
|
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_AXIS_S2MM_CMD": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "10", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_s2mm_cmd_tdata" } ],
|
||||||
|
"TREADY": [ { "physical_name": "s_axis_s2mm_cmd_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_s2mm_cmd_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_S2MM_STS": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_s2mm_sts_tdata" } ],
|
||||||
|
"TKEEP": [ { "physical_name": "m_axis_s2mm_sts_tkeep" } ],
|
||||||
|
"TLAST": [ { "physical_name": "m_axis_s2mm_sts_tlast" } ],
|
||||||
|
"TREADY": [ { "physical_name": "m_axis_s2mm_sts_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_s2mm_sts_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_MM2S_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXI", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axi_mm2s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_MM2S_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_S2MM_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axi_s2mm_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXI_S2MM_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "m_axi_s2mm_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_MM2S_CMDSTS_ACLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_MM2S_CMD:M_AXIS_MM2S_STS", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axis_mm2s_cmdsts_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_MM2S_CMDSTS_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_S2MM_CMDSTS_AWCLK": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_S2MM_CMD:M_AXIS_S2MM_STS", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "m_axis_s2mm_cmdsts_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "m_axis_s2mm_cmdsts_awclk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS_S2MM_CMDSTS_ARESETN": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "m_axis_s2mm_cmdsts_aresetn" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"address_spaces": {
|
||||||
|
"Data_S2MM": {
|
||||||
|
"range": "1099511627776",
|
||||||
|
"width": "40"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
179
project_1.srcs/sources_1/ip/ch_data_buffer/ch_data_buffer.xci
Normal file
179
project_1.srcs/sources_1/ip/ch_data_buffer/ch_data_buffer.xci
Normal file
@@ -0,0 +1,179 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "ch_data_buffer",
|
||||||
|
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||||
|
"ip_revision": "9",
|
||||||
|
"gen_directory": "../../../../project_1.gen/sources_1/ip/ch_data_buffer",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FIFO_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_TLAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Component_Name": [ { "value": "ch_data_buffer", "resolve_type": "user", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000010011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
|
"C_FIFO_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "9" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../project_1.gen/sources_1/ip/ch_data_buffer" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||||
|
"s_axis_tready": [ { "direction": "out" } ],
|
||||||
|
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||||
|
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||||
|
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||||
|
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
|
||||||
|
"m_axis_tlast": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"S_AXIS": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||||
|
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
|
||||||
|
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"M_AXIS": {
|
||||||
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||||
|
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||||
|
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||||
|
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_RSTIF": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"S_CLKIF": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,465 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "dma_ctrl_status_fifo_0",
|
||||||
|
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||||
|
"ip_revision": "7",
|
||||||
|
"gen_directory": "../../../../project_1.gen/sources_1/ip/dma_ctrl_status_fifo_0",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "dma_ctrl_status_fifo_0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Performance_Options": [ { "value": "First_Word_Fall_Through", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Input_Data_Width": [ { "value": "72", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Input_Depth": [ { "value": "512", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Output_Data_Width": [ { "value": "72", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Output_Depth": [ { "value": "512", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Use_Embedded_Registers": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Use_Extra_Logic": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Data_Count": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value": [ { "value": "511", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Negate_Value": [ { "value": "510", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Assert_Value": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Negate_Value": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||||
|
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||||
|
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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||||||
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|
||||||
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|
||||||
|
"C_USE_ECC_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_ECC_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_ECC_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ERROR_INJECTION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ERROR_INJECTION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ERROR_INJECTION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ERROR_INJECTION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ERROR_INJECTION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ERROR_INJECTION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DIN_WIDTH_WACH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DIN_WIDTH_WDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DIN_WIDTH_WRCH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DIN_WIDTH_RACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DIN_WIDTH_RDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_DIN_WIDTH_AXIS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_DEPTH_WACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_DEPTH_WDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_DEPTH_WRCH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_DEPTH_RACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_DEPTH_RDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_DEPTH_AXIS": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xczu7ev" } ],
|
||||||
|
"PACKAGE": [ { "value": "ffvc1156" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||||
|
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||||
|
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "7" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../project_1.gen/sources_1/ip/dma_ctrl_status_fifo_0" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2022.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"srst": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"din": [ { "direction": "in", "size_left": "71", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"dout": [ { "direction": "out", "size_left": "71", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||||
|
"empty": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||||
|
"data_count": [ { "direction": "out", "size_left": "9", "size_right": "0", "driver_value": "0" } ],
|
||||||
|
"wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
|
||||||
|
"rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"core_clk": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK": [ { "physical_name": "clk" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"FIFO_WRITE": {
|
||||||
|
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"port_maps": {
|
||||||
|
"FULL": [ { "physical_name": "full" } ],
|
||||||
|
"WR_DATA": [ { "physical_name": "din" } ],
|
||||||
|
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"FIFO_READ": {
|
||||||
|
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"port_maps": {
|
||||||
|
"EMPTY": [ { "physical_name": "empty" } ],
|
||||||
|
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||||
|
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
1364
project_1.xpr
Normal file
1364
project_1.xpr
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user