From b23f7fe4a630e293c1a20835542ebd15e4cdd9bd Mon Sep 17 00:00:00 2001 From: "bkiedinger@gmail.com" Date: Thu, 11 Jun 2026 23:19:03 -0500 Subject: [PATCH] 4 rx channels and 16 lane PCIe working on drex card --- cpp/data_recorder.h | 10 +- cpp/test_data_recorder.cpp | 4 +- project_1.srcs/constrs_1/constraints.xdc | 195 +- .../sources_1/bd/design_1/design_1.bd | 6275 +++-- .../sources_1/bd/design_1/design_1.bda | 554 +- .../design_1_auto_cc_0/design_1_auto_cc_0.xci | 8 +- .../design_1_auto_ds_0/design_1_auto_ds_0.xci | 24 +- .../design_1_auto_pc_0/design_1_auto_pc_0.xci | 12 +- .../design_1_auto_us_0/design_1_auto_us_0.xci | 265 + .../design_1_auto_us_1/design_1_auto_us_1.xci | 265 + .../design_1_auto_us_2/design_1_auto_us_2.xci | 265 + .../design_1_auto_us_3/design_1_auto_us_3.xci | 265 + .../design_1_axi_interconnect_0_0.xci | 6 +- .../design_1_axi_interconnect_1_0.xci | 12 +- .../design_1_axi_timer_0_0.xci | 8 +- .../design_1_axi_uartlite_0_0.xci | 364 - .../design_1_clk_wiz_1_0.xci | 36 +- .../design_1_dlmb_bram_if_cntlr_0.xci | 8 +- .../design_1_dlmb_v10_0.xci | 6 +- .../design_1_ilmb_bram_if_cntlr_0.xci | 8 +- .../design_1_ilmb_v10_0.xci | 6 +- .../design_1_lmb_bram_0.xci | 10 +- .../ip/design_1_mdm_1_0/design_1_mdm_1_0.xci | 285 +- .../design_1_microblaze_0_0.xci | 8 +- .../design_1_microblaze_0_axi_intc_0.xci | 14 +- .../design_1_microblaze_0_axi_periph_0.xci | 8 +- .../design_1_microblaze_0_xlconcat_0.xci | 8 +- .../design_1_rst_clk_wiz_1_100M_0.xci | 8 +- .../design_1_s00_data_fifo_0.xci | 64 +- .../design_1_s01_data_fifo_0.xci | 64 +- .../design_1_s02_data_fifo_0.xci | 268 + .../design_1_s03_data_fifo_0.xci | 268 + .../design_1_system_management_wiz_0_0.xci | 96 +- .../design_1_util_ds_buf_0_0.xci | 6 +- .../design_1_xbar_3.xci} | 44 +- .../design_1_xbar_4.xci} | 400 +- .../design_1_xbar_5.xci} | 236 +- .../design_1_xdma_0_0/design_1_xdma_0_0.xci | 130 +- .../design_1_xlconstant_0_0.xci | 6 +- .../design_1_zynq_ultra_ps_e_0_0.xci | 2012 -- .../83df/hdl/fifo_generator_v13_2_rfs.v | 7800 +++++++ .../83df/hdl/fifo_generator_v13_2_rfs.vhd | 18860 ++++++++++++++++ .../83df/simulation/fifo_generator_vlog_beh.v | 10519 +++++++++ .../c40e/hdl/axi_crossbar_v2_1_vl_rfs.v | 5804 +++++ .../sources_1/bd/design_1/ui/bd_1f5defd0.ui | 289 +- project_1.srcs/sources_1/hdl/top.sv | 146 +- .../axi_datamover_0_test.xci | 18 +- .../axi_datamover_256_0.xci | 18 +- .../ip/ch_data_buffer/ch_data_buffer.xci | 8 +- .../dma_ctrl_status_fifo_0.xci | 22 +- project_1.xpr | 118 +- 51 files changed, 49090 insertions(+), 7043 deletions(-) create mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/design_1_auto_us_0.xci create mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_1/design_1_auto_us_1.xci create mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_2/design_1_auto_us_2.xci create mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_3/design_1_auto_us_3.xci delete mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci create mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0/design_1_s02_data_fifo_0.xci create mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_s03_data_fifo_0/design_1_s03_data_fifo_0.xci rename project_1.srcs/sources_1/bd/design_1/ip/{design_1_xbar_0/design_1_xbar_0.xci => design_1_xbar_3/design_1_xbar_3.xci} (99%) rename project_1.srcs/sources_1/bd/design_1/ip/{design_1_xbar_2/design_1_xbar_2.xci => design_1_xbar_4/design_1_xbar_4.xci} (86%) rename project_1.srcs/sources_1/bd/design_1/ip/{design_1_xbar_1/design_1_xbar_1.xci => design_1_xbar_5/design_1_xbar_5.xci} (92%) delete mode 100644 project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xci create mode 100755 project_1.srcs/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.v create mode 100755 project_1.srcs/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.vhd create mode 100755 project_1.srcs/sources_1/bd/design_1/ipshared/83df/simulation/fifo_generator_vlog_beh.v create mode 100755 project_1.srcs/sources_1/bd/design_1/ipshared/c40e/hdl/axi_crossbar_v2_1_vl_rfs.v diff --git a/cpp/data_recorder.h b/cpp/data_recorder.h index 90b6f7c..b4f0d90 100755 --- a/cpp/data_recorder.h +++ b/cpp/data_recorder.h @@ -8,9 +8,13 @@ #include #include -#define UTIL_REG_BASE 0x100000 -#define TIMING_REG_BASE 0x110000 -#define DATA_GEN_REG_BASE 0x120000 +// #define UTIL_REG_BASE 0x100000 +// #define TIMING_REG_BASE 0x110000 +// #define DATA_GEN_REG_BASE 0x120000 + +#define UTIL_REG_BASE 0x10000 +#define TIMING_REG_BASE 0x20000 +#define DATA_GEN_REG_BASE 0x30000 #define WSRDMA_DMA_INIT 0 #define WSRDMA_DMA_CLEAR 1 diff --git a/cpp/test_data_recorder.cpp b/cpp/test_data_recorder.cpp index ffb37e1..e71659a 100755 --- a/cpp/test_data_recorder.cpp +++ b/cpp/test_data_recorder.cpp @@ -20,8 +20,8 @@ int main() { // Setup Timing Engine and data generator to test uint32_t n_pulses = 128; float inter_cpi = 100e-6; - float pri = 84e-6; - uint32_t n_samples = 8192; + float pri = 70e-6; + uint32_t n_samples = 16384; // float pri = 40e-6; // uint32_t n_samples = 4096; diff --git a/project_1.srcs/constrs_1/constraints.xdc b/project_1.srcs/constrs_1/constraints.xdc index b41b14a..4229783 100644 --- a/project_1.srcs/constrs_1/constraints.xdc +++ b/project_1.srcs/constrs_1/constraints.xdc @@ -1,50 +1,181 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property PACKAGE_PIN M9 [get_ports {leds[0]}] -set_property PACKAGE_PIN K8 [get_ports {leds[1]}] -set_property PACKAGE_PIN L8 [get_ports {leds[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}] +#set_property PACKAGE_PIN M9 [get_ports {leds[0]}] +#set_property PACKAGE_PIN K8 [get_ports {leds[1]}] +#set_property PACKAGE_PIN L8 [get_ports {leds[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}] -set_property PACKAGE_PIN N8 [get_ports uart_rxd] -set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd] +#set_property PACKAGE_PIN N8 [get_ports uart_rxd] +#set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd] -set_property PACKAGE_PIN N9 [get_ports uart_txd] -set_property IOSTANDARD LVCMOS33 [get_ports uart_txd] +#set_property PACKAGE_PIN N9 [get_ports uart_txd] +#set_property IOSTANDARD LVCMOS33 [get_ports uart_txd] -set_property PACKAGE_PIN AJ9 [get_ports sys_clk_p] -set_property PACKAGE_PIN AK9 [get_ports sys_clk_n] +set_property PACKAGE_PIN AP19 [get_ports sys_clk_p] +set_property PACKAGE_PIN AR19 [get_ports sys_clk_n] set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] -create_clock -period 5.000 -name sys_clk_clk_p [get_ports sys_clk_p] +create_clock -period 10.000 -name sys_clk_clk_p [get_ports sys_clk_p] -set_property PACKAGE_PIN M8 [get_ports fan_pwm] -set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm] +#set_property PACKAGE_PIN M8 [get_ports fan_pwm] +#set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm] #------------------------------------------- # PCIE #------------------------------------------- -set_property PACKAGE_PIN AD8 [get_ports pcie_ref_clk_p] +set_property PACKAGE_PIN AB27 [get_ports pcie_ref_clk_p] create_clock -period 10.000 -name pcie_ref_clk_p -waveform {0.000 5.000} [get_ports pcie_ref_clk_p] -set_property PACKAGE_PIN AP4 [get_ports {pcie_mgt_rxp[0]}] -set_property PACKAGE_PIN AN2 [get_ports {pcie_mgt_rxp[1]}] -set_property PACKAGE_PIN AL2 [get_ports {pcie_mgt_rxp[2]}] -set_property PACKAGE_PIN AK4 [get_ports {pcie_mgt_rxp[3]}] -set_property PACKAGE_PIN AJ2 [get_ports {pcie_mgt_rxp[4]}] -set_property PACKAGE_PIN AG2 [get_ports {pcie_mgt_rxp[5]}] -set_property PACKAGE_PIN AF4 [get_ports {pcie_mgt_rxp[6]}] -set_property PACKAGE_PIN AE2 [get_ports {pcie_mgt_rxp[7]}] +set_property PACKAGE_PIN AA38 [get_ports {pcie_mgt_rxp[8]}] +set_property PACKAGE_PIN AB36 [get_ports {pcie_mgt_rxp[9]}] +set_property PACKAGE_PIN AC38 [get_ports {pcie_mgt_rxp[10]}] +set_property PACKAGE_PIN AD36 [get_ports {pcie_mgt_rxp[11]}] +set_property PACKAGE_PIN AE38 [get_ports {pcie_mgt_rxp[12]}] +set_property PACKAGE_PIN AF36 [get_ports {pcie_mgt_rxp[13]}] +set_property PACKAGE_PIN AG38 [get_ports {pcie_mgt_rxp[14]}] +set_property PACKAGE_PIN AH36 [get_ports {pcie_mgt_rxp[15]}] -set_property PACKAGE_PIN AN6 [get_ports {pcie_mgt_txp[0]}] -set_property PACKAGE_PIN AM4 [get_ports {pcie_mgt_txp[1]}] -set_property PACKAGE_PIN AL6 [get_ports {pcie_mgt_txp[2]}] -set_property PACKAGE_PIN AJ6 [get_ports {pcie_mgt_txp[3]}] -set_property PACKAGE_PIN AH4 [get_ports {pcie_mgt_txp[4]}] -set_property PACKAGE_PIN AG6 [get_ports {pcie_mgt_txp[5]}] -set_property PACKAGE_PIN AE6 [get_ports {pcie_mgt_txp[6]}] -set_property PACKAGE_PIN AD4 [get_ports {pcie_mgt_txp[7]}] +set_property PACKAGE_PIN N38 [get_ports {pcie_mgt_rxp[0]}] +set_property PACKAGE_PIN L33 [get_ports {pcie_mgt_txp[0]}] +set_property PACKAGE_PIN P36 [get_ports {pcie_mgt_rxp[1]}] +set_property PACKAGE_PIN M31 [get_ports {pcie_mgt_txp[1]}] +set_property PACKAGE_PIN R38 [get_ports {pcie_mgt_rxp[2]}] +set_property PACKAGE_PIN N33 [get_ports {pcie_mgt_txp[2]}] +set_property PACKAGE_PIN T36 [get_ports {pcie_mgt_rxp[3]}] +set_property PACKAGE_PIN P31 [get_ports {pcie_mgt_txp[3]}] +set_property PACKAGE_PIN U38 [get_ports {pcie_mgt_rxp[4]}] +set_property PACKAGE_PIN R33 [get_ports {pcie_mgt_txp[4]}] +set_property PACKAGE_PIN V36 [get_ports {pcie_mgt_rxp[5]}] +set_property PACKAGE_PIN T31 [get_ports {pcie_mgt_txp[5]}] +set_property PACKAGE_PIN W38 [get_ports {pcie_mgt_rxp[6]}] +set_property PACKAGE_PIN U33 [get_ports {pcie_mgt_txp[6]}] +set_property PACKAGE_PIN Y36 [get_ports {pcie_mgt_rxp[7]}] +set_property PACKAGE_PIN V31 [get_ports {pcie_mgt_txp[7]}] +set_property PACKAGE_PIN W33 [get_ports {pcie_mgt_txp[8]}] +set_property PACKAGE_PIN AB36 [get_ports {pcie_mgt_txp[9]}] +set_property PACKAGE_PIN AA33 [get_ports {pcie_mgt_txp[10]}] +set_property PACKAGE_PIN AB31 [get_ports {pcie_mgt_txp[11]}] +set_property PACKAGE_PIN AC33 [get_ports {pcie_mgt_txp[12]}] +set_property PACKAGE_PIN AD31 [get_ports {pcie_mgt_txp[13]}] +set_property PACKAGE_PIN AE33 [get_ports {pcie_mgt_txp[14]}] +set_property PACKAGE_PIN AF31 [get_ports {pcie_mgt_txp[15]}] -set_property PACKAGE_PIN AA20 [get_ports pcie_rst_n] -set_property IOSTANDARD LVCMOS18 [get_ports pcie_rst_n] +set_property PACKAGE_PIN D13 [get_ports pcie_rst_n] +set_property IOSTANDARD LVCMOS33 [get_ports pcie_rst_n] + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list design_1_i/xdma_0/inst/pcie4_ip_i/inst/design_1_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/CLK_USERCLK]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 1 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/pcie_m_axi1_bvalid[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/pcie_m_axi1_wvalid[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {design_1_i/pcie_m_axi1_awvalid[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 1 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {design_1_i/pcie_m_axi1_wready[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {design_1_i/pcie_m_axi1_bready[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {design_1_i/pcie_m_axi1_awready[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 1 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {design_1_i/pcie_m_axi0_wvalid[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {design_1_i/pcie_m_axi0_bvalid[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {design_1_i/pcie_m_axi0_wready[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {design_1_i/pcie_m_axi0_bready[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {design_1_i/pcie_m_axi0_awvalid[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {design_1_i/pcie_m_axi1_wlast[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list {design_1_i/pcie_m_axi0_awready[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {design_1_i/pcie_m_axi0_wlast[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WVALID]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WREADY]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WLAST]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_BVALID]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_BREADY]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_AWVALID]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_AWREADY]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list start_of_pulse]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {pcie_dma_axis\\.tvalid}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {pcie_dma_axis\\.tready}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {pcie_dma_axis\\.tlast}]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets clk] diff --git a/project_1.srcs/sources_1/bd/design_1/design_1.bd b/project_1.srcs/sources_1/bd/design_1/design_1.bd index 0f7107e..81ab618 100644 --- a/project_1.srcs/sources_1/bd/design_1/design_1.bd +++ b/project_1.srcs/sources_1/bd/design_1/design_1.bd @@ -1,8 +1,8 @@ { "design": { "design_info": { - "boundary_crc": "0x170138D2157C3", - "device": "xczu7ev-ffvc1156-2-i", + "boundary_crc": "0x7C180B25792A5F3F", + "device": "xcku15p-ffve1517-2-i", "gen_directory": "../../../../project_1.gen/sources_1/bd/design_1", "name": "design_1", "rev_ctrl_bd_flag": "RevCtrlBdOff", @@ -11,6 +11,13 @@ "validated": "true" }, "design_tree": { + "microblaze_0_local_memory": { + "dlmb_bram_if_cntlr": "", + "dlmb_v10": "", + "ilmb_bram_if_cntlr": "", + "ilmb_v10": "", + "lmb_bram": "" + }, "axi_interconnect_0": { "xbar": "", "s00_couplers": {}, @@ -20,8 +27,27 @@ "m03_couplers": {}, "m04_couplers": {} }, + "axi_interconnect_1": { + "xbar": "", + "s00_couplers": { + "s00_data_fifo": "", + "auto_us": "" + }, + "s01_couplers": { + "s01_data_fifo": "", + "auto_us": "" + }, + "s02_couplers": { + "s02_data_fifo": "", + "auto_us": "" + }, + "s03_couplers": { + "s03_data_fifo": "", + "auto_us": "" + }, + "m00_couplers": {} + }, "axi_timer_0": "", - "axi_uartlite_0": "", "clk_wiz_1": "", "mdm_1": "", "microblaze_0": "", @@ -41,49 +67,18 @@ "m03_couplers": {}, "m04_couplers": {}, "m05_couplers": {}, - "m06_couplers": {} - }, - "microblaze_0_local_memory": { - "dlmb_bram_if_cntlr": "", - "dlmb_v10": "", - "ilmb_bram_if_cntlr": "", - "ilmb_v10": "", - "lmb_bram": "" + "m06_couplers": {}, + "m07_couplers": {}, + "m08_couplers": {} }, "microblaze_0_xlconcat": "", "rst_clk_wiz_1_100M": "", "system_management_wiz_0": "", "util_ds_buf_0": "", "xdma_0": "", - "xlconstant_0": "", - "zynq_ultra_ps_e_0": "", - "axi_interconnect_1": { - "xbar": "", - "s00_couplers": { - "s00_data_fifo": "" - }, - "s01_couplers": { - "s01_data_fifo": "" - }, - "m00_couplers": {} - } + "xlconstant_0": "" }, "interface_ports": { - "UART_0": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:uart:1.0", - "vlnv": "xilinx.com:interface:uart_rtl:1.0", - "port_maps": { - "RxD": { - "physical_name": "UART_0_rxd", - "direction": "I" - }, - "TxD": { - "physical_name": "UART_0_txd", - "direction": "O" - } - } - }, "axil_descriptors": { "mode": "Master", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", @@ -1052,25 +1047,25 @@ "rxn": { "physical_name": "pcie_mgt_0_rxn", "direction": "I", - "left": "7", + "left": "15", "right": "0" }, "rxp": { "physical_name": "pcie_mgt_0_rxp", "direction": "I", - "left": "7", + "left": "15", "right": "0" }, "txn": { "physical_name": "pcie_mgt_0_txn", "direction": "O", - "left": "7", + "left": "15", "right": "0" }, "txp": { "physical_name": "pcie_mgt_0_txp", "direction": "O", - "left": "7", + "left": "15", "right": "0" } } @@ -1114,7 +1109,7 @@ "value_src": "default" }, "FREQ_HZ": { - "value": "200000000" + "value": "100000000" } }, "port_maps": { @@ -2059,6 +2054,910 @@ "right": "0" } } + }, + "pcie_m_axi2": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "40" + }, + "ARUSER_WIDTH": { + "value": "0" + }, + "AWUSER_WIDTH": { + "value": "0" + }, + "BUSER_WIDTH": { + "value": "0" + }, + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "default_prop" + }, + "DATA_WIDTH": { + "value": "256" + }, + "FREQ_HZ": { + "value": "250000000", + "value_src": "user_prop" + }, + "HAS_BRESP": { + "value": "1" + }, + "HAS_BURST": { + "value": "1" + }, + "HAS_CACHE": { + "value": "0" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "0" + }, + "HAS_QOS": { + "value": "0" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1" + }, + "HAS_WSTRB": { + "value": "1" + }, + "ID_WIDTH": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "256" + }, + "NUM_READ_OUTSTANDING": { + "value": "2" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "16" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4" + }, + "READ_WRITE_MODE": { + "value": "WRITE_ONLY" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "RUSER_WIDTH": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "1" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + }, + "WUSER_WIDTH": { + "value": "0" + } + }, + "address_space_ref": "pcie_m_axi2", + "base_address": { + "minimum": "0x00000000", + "maximum": "0x00FFFFFFFFFF", + "width": "40" + }, + "port_maps": { + "AWADDR": { + "physical_name": "pcie_m_axi2_awaddr", + "direction": "I", + "left": "39", + "right": "0" + }, + "AWLEN": { + "physical_name": "pcie_m_axi2_awlen", + "direction": "I", + "left": "7", + "right": "0" + }, + "AWSIZE": { + "physical_name": "pcie_m_axi2_awsize", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWBURST": { + "physical_name": "pcie_m_axi2_awburst", + "direction": "I", + "left": "1", + "right": "0" + }, + "AWLOCK": { + "physical_name": "pcie_m_axi2_awlock", + "direction": "I", + "left": "0", + "right": "0" + }, + "AWCACHE": { + "physical_name": "pcie_m_axi2_awcache", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWPROT": { + "physical_name": "pcie_m_axi2_awprot", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWQOS": { + "physical_name": "pcie_m_axi2_awqos", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWVALID": { + "physical_name": "pcie_m_axi2_awvalid", + "direction": "I" + }, + "AWREADY": { + "physical_name": "pcie_m_axi2_awready", + "direction": "O" + }, + "WDATA": { + "physical_name": "pcie_m_axi2_wdata", + "direction": "I", + "left": "255", + "right": "0" + }, + "WSTRB": { + "physical_name": "pcie_m_axi2_wstrb", + "direction": "I", + "left": "31", + "right": "0" + }, + "WLAST": { + "physical_name": "pcie_m_axi2_wlast", + "direction": "I" + }, + "WVALID": { + "physical_name": "pcie_m_axi2_wvalid", + "direction": "I" + }, + "WREADY": { + "physical_name": "pcie_m_axi2_wready", + "direction": "O" + }, + "BRESP": { + "physical_name": "pcie_m_axi2_bresp", + "direction": "O", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "pcie_m_axi2_bvalid", + "direction": "O" + }, + "BREADY": { + "physical_name": "pcie_m_axi2_bready", + "direction": "I" + }, + "AWREGION": { + "physical_name": "pcie_m_axi2_awregion", + "direction": "I", + "left": "3", + "right": "0" + } + } + }, + "pcie_m_axi3": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "40" + }, + "ARUSER_WIDTH": { + "value": "0" + }, + "AWUSER_WIDTH": { + "value": "0" + }, + "BUSER_WIDTH": { + "value": "0" + }, + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "default_prop" + }, + "DATA_WIDTH": { + "value": "256" + }, + "FREQ_HZ": { + "value": "250000000", + "value_src": "user_prop" + }, + "HAS_BRESP": { + "value": "1" + }, + "HAS_BURST": { + "value": "1" + }, + "HAS_CACHE": { + "value": "0" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "0" + }, + "HAS_QOS": { + "value": "0" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1" + }, + "HAS_WSTRB": { + "value": "1" + }, + "ID_WIDTH": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "256" + }, + "NUM_READ_OUTSTANDING": { + "value": "2" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "16" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4" + }, + "READ_WRITE_MODE": { + "value": "WRITE_ONLY" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "RUSER_WIDTH": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "1" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + }, + "WUSER_WIDTH": { + "value": "0" + } + }, + "address_space_ref": "pcie_m_axi3", + "base_address": { + "minimum": "0x00000000", + "maximum": "0x00FFFFFFFFFF", + "width": "40" + }, + "port_maps": { + "AWADDR": { + "physical_name": "pcie_m_axi3_awaddr", + "direction": "I", + "left": "39", + "right": "0" + }, + "AWLEN": { + "physical_name": "pcie_m_axi3_awlen", + "direction": "I", + "left": "7", + "right": "0" + }, + "AWSIZE": { + "physical_name": "pcie_m_axi3_awsize", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWBURST": { + "physical_name": "pcie_m_axi3_awburst", + "direction": "I", + "left": "1", + "right": "0" + }, + "AWLOCK": { + "physical_name": "pcie_m_axi3_awlock", + "direction": "I", + "left": "0", + "right": "0" + }, + "AWCACHE": { + "physical_name": "pcie_m_axi3_awcache", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWPROT": { + "physical_name": "pcie_m_axi3_awprot", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWQOS": { + "physical_name": "pcie_m_axi3_awqos", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWVALID": { + "physical_name": "pcie_m_axi3_awvalid", + "direction": "I" + }, + "AWREADY": { + "physical_name": "pcie_m_axi3_awready", + "direction": "O" + }, + "WDATA": { + "physical_name": "pcie_m_axi3_wdata", + "direction": "I", + "left": "255", + "right": "0" + }, + "WSTRB": { + "physical_name": "pcie_m_axi3_wstrb", + "direction": "I", + "left": "31", + "right": "0" + }, + "WLAST": { + "physical_name": "pcie_m_axi3_wlast", + "direction": "I" + }, + "WVALID": { + "physical_name": "pcie_m_axi3_wvalid", + "direction": "I" + }, + "WREADY": { + "physical_name": "pcie_m_axi3_wready", + "direction": "O" + }, + "BRESP": { + "physical_name": "pcie_m_axi3_bresp", + "direction": "O", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "pcie_m_axi3_bvalid", + "direction": "O" + }, + "BREADY": { + "physical_name": "pcie_m_axi3_bready", + "direction": "I" + }, + "AWREGION": { + "physical_name": "pcie_m_axi3_awregion", + "direction": "I", + "left": "3", + "right": "0" + } + } + }, + "axil_dma_ctrl2": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "40" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "default_prop" + }, + "DATA_WIDTH": { + "value": "32" + }, + "FREQ_HZ": { + "value": "250000000", + "value_src": "user_prop" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_BURST": { + "value": "0" + }, + "HAS_CACHE": { + "value": "0" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_QOS": { + "value": "0" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "const_prop" + }, + "ID_WIDTH": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "1", + "value_src": "ip_prop" + }, + "NUM_READ_OUTSTANDING": { + "value": "1", + "value_src": "default" + }, + "NUM_READ_THREADS": { + "value": "1", + "value_src": "default" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1", + "value_src": "default" + }, + "NUM_WRITE_THREADS": { + "value": "1", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4LITE" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "default" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "default" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0", + "value_src": "ip_prop" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "default" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "default" + } + }, + "memory_map_ref": "axil_dma_ctrl2", + "port_maps": { + "AWADDR": { + "physical_name": "axil_dma_ctrl2_awaddr", + "direction": "O", + "left": "39", + "right": "0" + }, + "AWPROT": { + "physical_name": "axil_dma_ctrl2_awprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWVALID": { + "physical_name": "axil_dma_ctrl2_awvalid", + "direction": "O", + "left": "0", + "right": "0" + }, + "AWREADY": { + "physical_name": "axil_dma_ctrl2_awready", + "direction": "I", + "left": "0", + "right": "0" + }, + "WDATA": { + "physical_name": "axil_dma_ctrl2_wdata", + "direction": "O", + "left": "31", + "right": "0" + }, + "WSTRB": { + "physical_name": "axil_dma_ctrl2_wstrb", + "direction": "O", + "left": "3", + "right": "0" + }, + "WVALID": { + "physical_name": "axil_dma_ctrl2_wvalid", + "direction": "O", + "left": "0", + "right": "0" + }, + "WREADY": { + "physical_name": "axil_dma_ctrl2_wready", + "direction": "I", + "left": "0", + "right": "0" + }, + "BRESP": { + "physical_name": "axil_dma_ctrl2_bresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "axil_dma_ctrl2_bvalid", + "direction": "I", + "left": "0", + "right": "0" + }, + "BREADY": { + "physical_name": "axil_dma_ctrl2_bready", + "direction": "O", + "left": "0", + "right": "0" + }, + "ARADDR": { + "physical_name": "axil_dma_ctrl2_araddr", + "direction": "O", + "left": "39", + "right": "0" + }, + "ARPROT": { + "physical_name": "axil_dma_ctrl2_arprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARVALID": { + "physical_name": "axil_dma_ctrl2_arvalid", + "direction": "O", + "left": "0", + "right": "0" + }, + "ARREADY": { + "physical_name": "axil_dma_ctrl2_arready", + "direction": "I", + "left": "0", + "right": "0" + }, + "RDATA": { + "physical_name": "axil_dma_ctrl2_rdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "RRESP": { + "physical_name": "axil_dma_ctrl2_rresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "RVALID": { + "physical_name": "axil_dma_ctrl2_rvalid", + "direction": "I", + "left": "0", + "right": "0" + }, + "RREADY": { + "physical_name": "axil_dma_ctrl2_rready", + "direction": "O", + "left": "0", + "right": "0" + } + } + }, + "axil_dma_ctrl3": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "40" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "default_prop" + }, + "DATA_WIDTH": { + "value": "32" + }, + "FREQ_HZ": { + "value": "250000000", + "value_src": "user_prop" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_BURST": { + "value": "0" + }, + "HAS_CACHE": { + "value": "0" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_QOS": { + "value": "0" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "const_prop" + }, + "ID_WIDTH": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "1", + "value_src": "ip_prop" + }, + "NUM_READ_OUTSTANDING": { + "value": "1", + "value_src": "default" + }, + "NUM_READ_THREADS": { + "value": "1", + "value_src": "default" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1", + "value_src": "default" + }, + "NUM_WRITE_THREADS": { + "value": "1", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4LITE" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "default" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "default" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "default" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0", + "value_src": "ip_prop" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "default" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "default" + } + }, + "memory_map_ref": "axil_dma_ctrl3", + "port_maps": { + "AWADDR": { + "physical_name": "axil_dma_ctrl3_awaddr", + "direction": "O", + "left": "39", + "right": "0" + }, + "AWPROT": { + "physical_name": "axil_dma_ctrl3_awprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWVALID": { + "physical_name": "axil_dma_ctrl3_awvalid", + "direction": "O", + "left": "0", + "right": "0" + }, + "AWREADY": { + "physical_name": "axil_dma_ctrl3_awready", + "direction": "I", + "left": "0", + "right": "0" + }, + "WDATA": { + "physical_name": "axil_dma_ctrl3_wdata", + "direction": "O", + "left": "31", + "right": "0" + }, + "WSTRB": { + "physical_name": "axil_dma_ctrl3_wstrb", + "direction": "O", + "left": "3", + "right": "0" + }, + "WVALID": { + "physical_name": "axil_dma_ctrl3_wvalid", + "direction": "O", + "left": "0", + "right": "0" + }, + "WREADY": { + "physical_name": "axil_dma_ctrl3_wready", + "direction": "I", + "left": "0", + "right": "0" + }, + "BRESP": { + "physical_name": "axil_dma_ctrl3_bresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "axil_dma_ctrl3_bvalid", + "direction": "I", + "left": "0", + "right": "0" + }, + "BREADY": { + "physical_name": "axil_dma_ctrl3_bready", + "direction": "O", + "left": "0", + "right": "0" + }, + "ARADDR": { + "physical_name": "axil_dma_ctrl3_araddr", + "direction": "O", + "left": "39", + "right": "0" + }, + "ARPROT": { + "physical_name": "axil_dma_ctrl3_arprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARVALID": { + "physical_name": "axil_dma_ctrl3_arvalid", + "direction": "O", + "left": "0", + "right": "0" + }, + "ARREADY": { + "physical_name": "axil_dma_ctrl3_arready", + "direction": "I", + "left": "0", + "right": "0" + }, + "RDATA": { + "physical_name": "axil_dma_ctrl3_rdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "RRESP": { + "physical_name": "axil_dma_ctrl3_rresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "RVALID": { + "physical_name": "axil_dma_ctrl3_rvalid", + "direction": "I", + "left": "0", + "right": "0" + }, + "RREADY": { + "physical_name": "axil_dma_ctrl3_rready", + "direction": "O", + "left": "0", + "right": "0" + } + } } }, "ports": { @@ -2081,7 +2980,7 @@ "direction": "O", "parameters": { "ASSOCIATED_BUSIF": { - "value": "axil_dma_ctrl1:axil_dma_ctrl0:axil_descriptors:axil_timing:axil_data_gen:axil_util:pcie_m_axi0:pcie_m_axi1" + "value": "axil_dma_ctrl1:axil_dma_ctrl0:axil_descriptors:axil_timing:axil_data_gen:axil_util:pcie_m_axi0:pcie_m_axi1:pcie_m_axi2:pcie_m_axi3:axil_dma_ctrl2:axil_dma_ctrl3" }, "CLK_DOMAIN": { "value": "design_1_xdma_0_0_axi_aclk", @@ -2175,6 +3074,181 @@ } }, "components": { + "microblaze_0_local_memory": { + "interface_ports": { + "DLMB": { + "mode": "MirroredMaster", + "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", + "vlnv": "xilinx.com:interface:lmb_rtl:1.0" + }, + "ILMB": { + "mode": "MirroredMaster", + "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", + "vlnv": "xilinx.com:interface:lmb_rtl:1.0" + } + }, + "ports": { + "LMB_Clk": { + "type": "clk", + "direction": "I" + }, + "SYS_Rst": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "dlmb_bram_if_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "design_1_dlmb_bram_if_cntlr_0", + "xci_path": "ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci", + "inst_hier_path": "microblaze_0_local_memory/dlmb_bram_if_cntlr", + "parameters": { + "C_ECC": { + "value": "0" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_SPACE": { + "value": "byte 0x00000000 32 > design_1 microblaze_0_local_memory/lmb_bram", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "dlmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "design_1_dlmb_v10_0", + "xci_path": "ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci", + "inst_hier_path": "microblaze_0_local_memory/dlmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, + "ilmb_bram_if_cntlr": { + "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", + "xci_name": "design_1_ilmb_bram_if_cntlr_0", + "xci_path": "ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci", + "inst_hier_path": "microblaze_0_local_memory/ilmb_bram_if_cntlr", + "parameters": { + "C_ECC": { + "value": "0" + } + } + }, + "ilmb_v10": { + "vlnv": "xilinx.com:ip:lmb_v10:3.0", + "xci_name": "design_1_ilmb_v10_0", + "xci_path": "ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci", + "inst_hier_path": "microblaze_0_local_memory/ilmb_v10", + "interface_ports": { + "LMB_M": { + "vlnv": "xilinx.com:interface:lmb_rtl:1.0", + "mode": "MirroredMaster", + "bridges": [ + "LMB_Sl_0" + ] + } + } + }, + "lmb_bram": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "design_1_lmb_bram_0", + "xci_path": "ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci", + "inst_hier_path": "microblaze_0_local_memory/lmb_bram", + "parameters": { + "Enable_B": { + "value": "Use_ENB_Pin" + }, + "Memory_Type": { + "value": "True_Dual_Port_RAM" + }, + "Port_B_Clock": { + "value": "100" + }, + "Port_B_Enable_Rate": { + "value": "100" + }, + "Port_B_Write_Rate": { + "value": "50" + }, + "Use_RSTB_Pin": { + "value": "true" + }, + "use_bram_block": { + "value": "BRAM_Controller" + } + } + } + }, + "interface_nets": { + "microblaze_0_dlmb": { + "interface_ports": [ + "DLMB", + "dlmb_v10/LMB_M" + ] + }, + "microblaze_0_dlmb_bus": { + "interface_ports": [ + "dlmb_bram_if_cntlr/SLMB", + "dlmb_v10/LMB_Sl_0" + ] + }, + "microblaze_0_dlmb_cntlr": { + "interface_ports": [ + "dlmb_bram_if_cntlr/BRAM_PORT", + "lmb_bram/BRAM_PORTA" + ] + }, + "microblaze_0_ilmb": { + "interface_ports": [ + "ILMB", + "ilmb_v10/LMB_M" + ] + }, + "microblaze_0_ilmb_bus": { + "interface_ports": [ + "ilmb_bram_if_cntlr/SLMB", + "ilmb_v10/LMB_Sl_0" + ] + }, + "microblaze_0_ilmb_cntlr": { + "interface_ports": [ + "ilmb_bram_if_cntlr/BRAM_PORT", + "lmb_bram/BRAM_PORTB" + ] + } + }, + "nets": { + "SYS_Rst_1": { + "ports": [ + "SYS_Rst", + "dlmb_bram_if_cntlr/LMB_Rst", + "dlmb_v10/SYS_Rst", + "ilmb_bram_if_cntlr/LMB_Rst", + "ilmb_v10/SYS_Rst" + ] + }, + "microblaze_0_Clk": { + "ports": [ + "LMB_Clk", + "dlmb_bram_if_cntlr/LMB_Clk", + "dlmb_v10/LMB_Clk", + "ilmb_bram_if_cntlr/LMB_Clk", + "ilmb_v10/LMB_Clk" + ] + } + } + }, "axi_interconnect_0": { "vlnv": "xilinx.com:ip:axi_interconnect:2.1", "xci_path": "ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci", @@ -2331,8 +3405,8 @@ "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "design_1_xbar_0", - "xci_path": "ip/design_1_xbar_0/design_1_xbar_0.xci", + "xci_name": "design_1_xbar_3", + "xci_path": "ip/design_1_xbar_3/design_1_xbar_3.xci", "inst_hier_path": "axi_interconnect_0/xbar", "parameters": { "NUM_MI": { @@ -2809,23 +3883,924 @@ } } }, + "axi_interconnect_1": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci", + "inst_hier_path": "axi_interconnect_1", + "xci_name": "design_1_axi_interconnect_1_0", + "parameters": { + "M00_HAS_DATA_FIFO": { + "value": "0" + }, + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "4" + }, + "S00_HAS_DATA_FIFO": { + "value": "1" + }, + "S01_HAS_DATA_FIFO": { + "value": "1" + }, + "S02_HAS_DATA_FIFO": { + "value": "1" + }, + "S03_HAS_DATA_FIFO": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "undefined" + } + } + }, + "S01_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "undefined" + } + } + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S02_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "undefined" + } + } + }, + "S03_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "undefined" + } + } + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S01_ARESETN" + } + } + }, + "S01_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S02_ARESETN" + } + } + }, + "S02_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S03_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S03_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S03_ARESETN" + } + } + }, + "S03_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_1_xbar_4", + "xci_path": "ip/design_1_xbar_4/design_1_xbar_4.xci", + "inst_hier_path": "axi_interconnect_1/xbar", + "parameters": { + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "4" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + }, + "S01_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + }, + "S02_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + }, + "S03_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s00_data_fifo": { + "vlnv": "xilinx.com:ip:axi_data_fifo:2.1", + "xci_name": "design_1_s00_data_fifo_0", + "xci_path": "ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci", + "inst_hier_path": "axi_interconnect_1/s00_couplers/s00_data_fifo", + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + }, + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "design_1_auto_us_0", + "xci_path": "ip/design_1_auto_us_0/design_1_auto_us_0.xci", + "inst_hier_path": "axi_interconnect_1/s00_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "512" + }, + "SI_DATA_WIDTH": { + "value": "256" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s00_data_fifo": { + "interface_ports": [ + "s00_data_fifo/S_AXI", + "auto_us/M_AXI" + ] + }, + "s00_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + }, + "s00_data_fifo_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "s00_data_fifo/M_AXI" + ] + } + }, + "nets": { + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "s00_data_fifo/aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "s00_data_fifo/aresetn" + ] + }, + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + }, + "s01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s01_data_fifo": { + "vlnv": "xilinx.com:ip:axi_data_fifo:2.1", + "xci_name": "design_1_s01_data_fifo_0", + "xci_path": "ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci", + "inst_hier_path": "axi_interconnect_1/s01_couplers/s01_data_fifo", + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + }, + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "design_1_auto_us_1", + "xci_path": "ip/design_1_auto_us_1/design_1_auto_us_1.xci", + "inst_hier_path": "axi_interconnect_1/s01_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "512" + }, + "SI_DATA_WIDTH": { + "value": "256" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s01_data_fifo": { + "interface_ports": [ + "s01_data_fifo/S_AXI", + "auto_us/M_AXI" + ] + }, + "s01_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + }, + "s01_data_fifo_to_s01_couplers": { + "interface_ports": [ + "M_AXI", + "s01_data_fifo/M_AXI" + ] + } + }, + "nets": { + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "s01_data_fifo/aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "s01_data_fifo/aresetn" + ] + }, + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + }, + "s02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s02_data_fifo": { + "vlnv": "xilinx.com:ip:axi_data_fifo:2.1", + "xci_name": "design_1_s02_data_fifo_0", + "xci_path": "ip/design_1_s02_data_fifo_0/design_1_s02_data_fifo_0.xci", + "inst_hier_path": "axi_interconnect_1/s02_couplers/s02_data_fifo", + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + }, + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "design_1_auto_us_2", + "xci_path": "ip/design_1_auto_us_2/design_1_auto_us_2.xci", + "inst_hier_path": "axi_interconnect_1/s02_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "512" + }, + "SI_DATA_WIDTH": { + "value": "256" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s02_data_fifo": { + "interface_ports": [ + "s02_data_fifo/S_AXI", + "auto_us/M_AXI" + ] + }, + "s02_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + }, + "s02_data_fifo_to_s02_couplers": { + "interface_ports": [ + "M_AXI", + "s02_data_fifo/M_AXI" + ] + } + }, + "nets": { + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "s02_data_fifo/aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "s02_data_fifo/aresetn" + ] + }, + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + }, + "s03_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s03_data_fifo": { + "vlnv": "xilinx.com:ip:axi_data_fifo:2.1", + "xci_name": "design_1_s03_data_fifo_0", + "xci_path": "ip/design_1_s03_data_fifo_0/design_1_s03_data_fifo_0.xci", + "inst_hier_path": "axi_interconnect_1/s03_couplers/s03_data_fifo", + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + }, + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "design_1_auto_us_3", + "xci_path": "ip/design_1_auto_us_3/design_1_auto_us_3.xci", + "inst_hier_path": "axi_interconnect_1/s03_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "512" + }, + "SI_DATA_WIDTH": { + "value": "256" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s03_data_fifo": { + "interface_ports": [ + "s03_data_fifo/S_AXI", + "auto_us/M_AXI" + ] + }, + "s03_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + }, + "s03_data_fifo_to_s03_couplers": { + "interface_ports": [ + "M_AXI", + "s03_data_fifo/M_AXI" + ] + } + }, + "nets": { + "M_ACLK_1": { + "ports": [ + "M_ACLK", + "s03_data_fifo/aclk" + ] + }, + "M_ARESETN_1": { + "ports": [ + "M_ARESETN", + "s03_data_fifo/aresetn" + ] + }, + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "axi_interconnect_1_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "axi_interconnect_1_to_s01_couplers": { + "interface_ports": [ + "S01_AXI", + "s01_couplers/S_AXI" + ] + }, + "axi_interconnect_1_to_s02_couplers": { + "interface_ports": [ + "S02_AXI", + "s02_couplers/S_AXI" + ] + }, + "axi_interconnect_1_to_s03_couplers": { + "interface_ports": [ + "S03_AXI", + "s03_couplers/S_AXI" + ] + }, + "m00_couplers_to_axi_interconnect_1": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "s01_couplers_to_xbar": { + "interface_ports": [ + "s01_couplers/M_AXI", + "xbar/S01_AXI" + ] + }, + "s02_couplers_to_xbar": { + "interface_ports": [ + "s02_couplers/M_AXI", + "xbar/S02_AXI" + ] + }, + "s03_couplers_to_xbar": { + "interface_ports": [ + "s03_couplers/M_AXI", + "xbar/S03_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + } + }, + "nets": { + "axi_interconnect_1_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s01_couplers/S_ACLK", + "s02_couplers/S_ACLK", + "s03_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "s01_couplers/M_ACLK", + "s02_couplers/M_ACLK", + "s03_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m00_couplers/S_ACLK" + ] + }, + "axi_interconnect_1_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s01_couplers/S_ARESETN", + "s02_couplers/S_ARESETN", + "s03_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "s01_couplers/M_ARESETN", + "s02_couplers/M_ARESETN", + "s03_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m00_couplers/S_ARESETN" + ] + } + } + }, "axi_timer_0": { "vlnv": "xilinx.com:ip:axi_timer:2.0", "xci_name": "design_1_axi_timer_0_0", "xci_path": "ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci", "inst_hier_path": "axi_timer_0" }, - "axi_uartlite_0": { - "vlnv": "xilinx.com:ip:axi_uartlite:2.0", - "xci_name": "design_1_axi_uartlite_0_0", - "xci_path": "ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci", - "inst_hier_path": "axi_uartlite_0", - "parameters": { - "C_BAUDRATE": { - "value": "115200" - } - } - }, "clk_wiz_1": { "vlnv": "xilinx.com:ip:clk_wiz:6.0", "xci_name": "design_1_clk_wiz_1_0", @@ -2833,22 +4808,25 @@ "inst_hier_path": "clk_wiz_1", "parameters": { "CLKIN1_JITTER_PS": { - "value": "50.0" + "value": "100.0" }, "CLKOUT1_JITTER": { - "value": "106.024" + "value": "115.831" }, "CLKOUT1_PHASE_ERROR": { - "value": "82.655" + "value": "87.180" }, "MMCM_CLKFBOUT_MULT_F": { - "value": "6.000" + "value": "12.000" }, "MMCM_CLKIN1_PERIOD": { - "value": "5.000" + "value": "10.000" }, "MMCM_CLKIN2_PERIOD": { - "value": "10.0" + "value": "10.000" + }, + "PRIM_IN_FREQ": { + "value": "100" }, "PRIM_SOURCE": { "value": "Differential_clock_capable_pin" @@ -2865,7 +4843,18 @@ "vlnv": "xilinx.com:ip:mdm:3.2", "xci_name": "design_1_mdm_1_0", "xci_path": "ip/design_1_mdm_1_0/design_1_mdm_1_0.xci", - "inst_hier_path": "mdm_1" + "inst_hier_path": "mdm_1", + "parameters": { + "C_ADDR_SIZE": { + "value": "32" + }, + "C_M_AXI_ADDR_WIDTH": { + "value": "32" + }, + "C_USE_UART": { + "value": "1" + } + } }, "microblaze_0": { "vlnv": "xilinx.com:ip:microblaze:11.0", @@ -2983,7 +4972,7 @@ "xci_name": "design_1_microblaze_0_axi_periph_0", "parameters": { "NUM_MI": { - "value": "7" + "value": "9" }, "NUM_SI": { "value": "2" @@ -2995,6 +4984,11 @@ "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" }, + "S01_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, "M00_AXI": { "mode": "Master", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", @@ -3011,11 +5005,6 @@ } } }, - "S01_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, "M02_AXI": { "mode": "Master", "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", @@ -3070,6 +5059,28 @@ "value_src": "undefined" } } + }, + "M07_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "undefined" + } + } + }, + "M08_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_xdma_0_0_axi_aclk", + "value_src": "undefined" + } + } } }, "ports": { @@ -3102,6 +5113,22 @@ "type": "rst", "direction": "I" }, + "S01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S01_ARESETN" + } + } + }, + "S01_ARESETN": { + "type": "rst", + "direction": "I" + }, "M00_ACLK": { "type": "clk", "direction": "I", @@ -3134,22 +5161,6 @@ "type": "rst", "direction": "I" }, - "S01_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S01_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S01_ARESETN" - } - } - }, - "S01_ARESETN": { - "type": "rst", - "direction": "I" - }, "M02_ACLK": { "type": "clk", "direction": "I", @@ -3229,17 +5240,49 @@ "M06_ARESETN": { "type": "rst", "direction": "I" + }, + "M07_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M07_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M07_ARESETN" + } + } + }, + "M07_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M08_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M08_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M08_ARESETN" + } + } + }, + "M08_ARESETN": { + "type": "rst", + "direction": "I" } }, "components": { "xbar": { "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "design_1_xbar_1", - "xci_path": "ip/design_1_xbar_1/design_1_xbar_1.xci", + "xci_name": "design_1_xbar_5", + "xci_path": "ip/design_1_xbar_5/design_1_xbar_5.xci", "inst_hier_path": "microblaze_0_axi_periph/xbar", "parameters": { "NUM_MI": { - "value": "7" + "value": "9" }, "NUM_SI": { "value": "2" @@ -3259,7 +5302,9 @@ "M03_AXI", "M04_AXI", "M05_AXI", - "M06_AXI" + "M06_AXI", + "M07_AXI", + "M08_AXI" ] }, "S01_AXI": { @@ -3272,7 +5317,9 @@ "M03_AXI", "M04_AXI", "M05_AXI", - "M06_AXI" + "M06_AXI", + "M07_AXI", + "M08_AXI" ] } } @@ -3440,7 +5487,7 @@ "value": "32" }, "SI_DATA_WIDTH": { - "value": "256" + "value": "512" } }, "interface_ports": { @@ -3905,6 +5952,118 @@ ] } } + }, + "m07_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m07_couplers_to_m07_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m08_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m08_couplers_to_m08_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } } }, "interface_nets": { @@ -3950,6 +6109,18 @@ "m06_couplers/M_AXI" ] }, + "m07_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M07_AXI", + "m07_couplers/M_AXI" + ] + }, + "m08_couplers_to_microblaze_0_axi_periph": { + "interface_ports": [ + "M08_AXI", + "m08_couplers/M_AXI" + ] + }, "microblaze_0_axi_periph_to_s00_couplers": { "interface_ports": [ "S00_AXI", @@ -4015,6 +6186,18 @@ "xbar/M06_AXI", "m06_couplers/S_AXI" ] + }, + "xbar_to_m07_couplers": { + "interface_ports": [ + "xbar/M07_AXI", + "m07_couplers/S_AXI" + ] + }, + "xbar_to_m08_couplers": { + "interface_ports": [ + "xbar/M08_AXI", + "m08_couplers/S_AXI" + ] } }, "nets": { @@ -4102,6 +6285,30 @@ "m06_couplers/M_ARESETN" ] }, + "M07_ACLK_1": { + "ports": [ + "M07_ACLK", + "m07_couplers/M_ACLK" + ] + }, + "M07_ARESETN_1": { + "ports": [ + "M07_ARESETN", + "m07_couplers/M_ARESETN" + ] + }, + "M08_ACLK_1": { + "ports": [ + "M08_ACLK", + "m08_couplers/M_ACLK" + ] + }, + "M08_ARESETN_1": { + "ports": [ + "M08_ARESETN", + "m08_couplers/M_ARESETN" + ] + }, "S00_ACLK_1": { "ports": [ "S00_ACLK", @@ -4138,7 +6345,9 @@ "m03_couplers/S_ACLK", "m04_couplers/S_ACLK", "m05_couplers/S_ACLK", - "m06_couplers/S_ACLK" + "m06_couplers/S_ACLK", + "m07_couplers/S_ACLK", + "m08_couplers/S_ACLK" ] }, "microblaze_0_axi_periph_ARESETN_net": { @@ -4153,182 +6362,9 @@ "m03_couplers/S_ARESETN", "m04_couplers/S_ARESETN", "m05_couplers/S_ARESETN", - "m06_couplers/S_ARESETN" - ] - } - } - }, - "microblaze_0_local_memory": { - "interface_ports": { - "DLMB": { - "mode": "MirroredMaster", - "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", - "vlnv": "xilinx.com:interface:lmb_rtl:1.0" - }, - "ILMB": { - "mode": "MirroredMaster", - "vlnv_bus_definition": "xilinx.com:interface:lmb:1.0", - "vlnv": "xilinx.com:interface:lmb_rtl:1.0" - } - }, - "ports": { - "LMB_Clk": { - "type": "clk", - "direction": "I" - }, - "SYS_Rst": { - "type": "rst", - "direction": "I" - } - }, - "components": { - "dlmb_bram_if_cntlr": { - "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", - "xci_name": "design_1_dlmb_bram_if_cntlr_0", - "xci_path": "ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci", - "inst_hier_path": "microblaze_0_local_memory/dlmb_bram_if_cntlr", - "parameters": { - "C_ECC": { - "value": "0" - } - }, - "hdl_attributes": { - "BMM_INFO_ADDRESS_SPACE": { - "value": "byte 0x00000000 32 > design_1 microblaze_0_local_memory/lmb_bram", - "value_src": "default" - }, - "KEEP_HIERARCHY": { - "value": "yes", - "value_src": "default" - } - } - }, - "dlmb_v10": { - "vlnv": "xilinx.com:ip:lmb_v10:3.0", - "xci_name": "design_1_dlmb_v10_0", - "xci_path": "ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci", - "inst_hier_path": "microblaze_0_local_memory/dlmb_v10", - "interface_ports": { - "LMB_M": { - "vlnv": "xilinx.com:interface:lmb_rtl:1.0", - "mode": "MirroredMaster", - "bridges": [ - "LMB_Sl_0" - ] - } - } - }, - "ilmb_bram_if_cntlr": { - "vlnv": "xilinx.com:ip:lmb_bram_if_cntlr:4.0", - "xci_name": "design_1_ilmb_bram_if_cntlr_0", - "xci_path": "ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci", - "inst_hier_path": "microblaze_0_local_memory/ilmb_bram_if_cntlr", - "parameters": { - "C_ECC": { - "value": "0" - } - } - }, - "ilmb_v10": { - "vlnv": "xilinx.com:ip:lmb_v10:3.0", - "xci_name": "design_1_ilmb_v10_0", - "xci_path": "ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci", - "inst_hier_path": "microblaze_0_local_memory/ilmb_v10", - "interface_ports": { - "LMB_M": { - "vlnv": "xilinx.com:interface:lmb_rtl:1.0", - "mode": "MirroredMaster", - "bridges": [ - "LMB_Sl_0" - ] - } - } - }, - "lmb_bram": { - "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", - "xci_name": "design_1_lmb_bram_0", - "xci_path": "ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci", - "inst_hier_path": "microblaze_0_local_memory/lmb_bram", - "parameters": { - "Enable_B": { - "value": "Use_ENB_Pin" - }, - "Memory_Type": { - "value": "True_Dual_Port_RAM" - }, - "Port_B_Clock": { - "value": "100" - }, - "Port_B_Enable_Rate": { - "value": "100" - }, - "Port_B_Write_Rate": { - "value": "50" - }, - "Use_RSTB_Pin": { - "value": "true" - }, - "use_bram_block": { - "value": "BRAM_Controller" - } - } - } - }, - "interface_nets": { - "microblaze_0_dlmb": { - "interface_ports": [ - "DLMB", - "dlmb_v10/LMB_M" - ] - }, - "microblaze_0_dlmb_bus": { - "interface_ports": [ - "dlmb_bram_if_cntlr/SLMB", - "dlmb_v10/LMB_Sl_0" - ] - }, - "microblaze_0_dlmb_cntlr": { - "interface_ports": [ - "dlmb_bram_if_cntlr/BRAM_PORT", - "lmb_bram/BRAM_PORTA" - ] - }, - "microblaze_0_ilmb": { - "interface_ports": [ - "ILMB", - "ilmb_v10/LMB_M" - ] - }, - "microblaze_0_ilmb_bus": { - "interface_ports": [ - "ilmb_bram_if_cntlr/SLMB", - "ilmb_v10/LMB_Sl_0" - ] - }, - "microblaze_0_ilmb_cntlr": { - "interface_ports": [ - "ilmb_bram_if_cntlr/BRAM_PORT", - "lmb_bram/BRAM_PORTB" - ] - } - }, - "nets": { - "SYS_Rst_1": { - "ports": [ - "SYS_Rst", - "dlmb_bram_if_cntlr/LMB_Rst", - "dlmb_v10/SYS_Rst", - "ilmb_bram_if_cntlr/LMB_Rst", - "ilmb_v10/SYS_Rst" - ] - }, - "microblaze_0_Clk": { - "ports": [ - "LMB_Clk", - "dlmb_bram_if_cntlr/LMB_Clk", - "dlmb_v10/LMB_Clk", - "ilmb_bram_if_cntlr/LMB_Clk", - "ilmb_v10/LMB_Clk" + "m06_couplers/S_ARESETN", + "m07_couplers/S_ARESETN", + "m08_couplers/S_ARESETN" ] } } @@ -4341,6 +6377,9 @@ "parameters": { "NUM_PORTS": { "value": "3" + }, + "dout_width": { + "value": "3" } } }, @@ -4361,6 +6400,9 @@ "xci_path": "ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci", "inst_hier_path": "system_management_wiz_0", "parameters": { + "ANALOG_BANK_SELECTION": { + "value": "64" + }, "CHANNEL_AVERAGING": { "value": "16" }, @@ -4370,14 +6412,14 @@ "ENABLE_TEMP_BUS": { "value": "false" }, - "ENABLE_VCCPSAUX_ALARM": { - "value": "false" + "I2C_SCLK_LOC": { + "value": "AC18" }, - "ENABLE_VCCPSINTFP_ALARM": { - "value": "false" + "I2C_SDA_LOC": { + "value": "AA19" }, - "ENABLE_VCCPSINTLP_ALARM": { - "value": "false" + "INTERFACE_SELECTION": { + "value": "Enable_AXI" }, "OT_ALARM": { "value": "false" @@ -4388,6 +6430,102 @@ "USER_TEMP_ALARM": { "value": "false" }, + "VAUXN0_LOC": { + "value": "B19" + }, + "VAUXN10_LOC": { + "value": "C23" + }, + "VAUXN11_LOC": { + "value": "C22" + }, + "VAUXN12_LOC": { + "value": "D21" + }, + "VAUXN13_LOC": { + "value": "D19" + }, + "VAUXN14_LOC": { + "value": "H26" + }, + "VAUXN15_LOC": { + "value": "J22" + }, + "VAUXN1_LOC": { + "value": "C19" + }, + "VAUXN2_LOC": { + "value": "G26" + }, + "VAUXN3_LOC": { + "value": "D24" + }, + "VAUXN4_LOC": { + "value": "F20" + }, + "VAUXN5_LOC": { + "value": "H22" + }, + "VAUXN6_LOC": { + "value": "H24" + }, + "VAUXN7_LOC": { + "value": "K23" + }, + "VAUXN8_LOC": { + "value": "A21" + }, + "VAUXN9_LOC": { + "value": "A19" + }, + "VAUXP0_LOC": { + "value": "B18" + }, + "VAUXP10_LOC": { + "value": "D22" + }, + "VAUXP11_LOC": { + "value": "C21" + }, + "VAUXP12_LOC": { + "value": "D20" + }, + "VAUXP13_LOC": { + "value": "E19" + }, + "VAUXP14_LOC": { + "value": "J25" + }, + "VAUXP15_LOC": { + "value": "J21" + }, + "VAUXP1_LOC": { + "value": "C18" + }, + "VAUXP2_LOC": { + "value": "G25" + }, + "VAUXP3_LOC": { + "value": "E24" + }, + "VAUXP4_LOC": { + "value": "G20" + }, + "VAUXP5_LOC": { + "value": "H21" + }, + "VAUXP6_LOC": { + "value": "J24" + }, + "VAUXP7_LOC": { + "value": "K22" + }, + "VAUXP8_LOC": { + "value": "A20" + }, + "VAUXP9_LOC": { + "value": "A18" + }, "VCCAUX_ALARM": { "value": "false" }, @@ -4413,9 +6551,30 @@ "xci_path": "ip/design_1_xdma_0_0/design_1_xdma_0_0.xci", "inst_hier_path": "xdma_0", "parameters": { + "PF0_DEVICE_ID_mqdma": { + "value": "903F" + }, + "PF0_SRIOV_VF_DEVICE_ID": { + "value": "A03F" + }, + "PF2_DEVICE_ID_mqdma": { + "value": "923F" + }, + "PF3_DEVICE_ID_mqdma": { + "value": "933F" + }, "axi_addr_width": { "value": "40" }, + "axi_data_width": { + "value": "512_bit" + }, + "axisten_freq": { + "value": "250" + }, + "bridge_burst": { + "value": "true" + }, "c_s_axi_supports_narrow_burst": { "value": "true" }, @@ -4438,7 +6597,7 @@ "value": "Advanced" }, "pcie_blk_locn": { - "value": "X0Y0" + "value": "X0Y2" }, "pcie_id_if": { "value": "false" @@ -4446,15 +6605,30 @@ "pciebar2axibar_0": { "value": "0x0000000080000000" }, + "pf0_bar0_64bit": { + "value": "false" + }, "pf0_bar0_scale": { "value": "Megabytes" }, "pf0_bar0_size": { - "value": "32" + "value": "2" }, "pf0_base_class_menu": { "value": "Memory_controller" }, + "pf0_class_code_base": { + "value": "05" + }, + "pf0_class_code_interface": { + "value": "00" + }, + "pf0_class_code_sub": { + "value": "80" + }, + "pf0_device_id": { + "value": "903F" + }, "pf0_sub_class_interface_menu": { "value": "Other_memory_controller" }, @@ -4462,7 +6636,10 @@ "value": "8.0_GT/s" }, "pl_link_cap_max_link_width": { - "value": "X8" + "value": "X16" + }, + "plltype": { + "value": "QPLL1" }, "sys_reset_polarity": { "value": "ACTIVE_LOW" @@ -4530,3340 +6707,6 @@ "xci_name": "design_1_xlconstant_0_0", "xci_path": "ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci", "inst_hier_path": "xlconstant_0" - }, - "zynq_ultra_ps_e_0": { - "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.4", - "xci_name": "design_1_zynq_ultra_ps_e_0_0", - "xci_path": "ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xci", - "inst_hier_path": "zynq_ultra_ps_e_0", - "parameters": { - "CAN0_BOARD_INTERFACE": { - "value": "custom" - }, - "CAN1_BOARD_INTERFACE": { - "value": "custom" - }, - "CSU_BOARD_INTERFACE": { - "value": "custom" - }, - "DP_BOARD_INTERFACE": { - "value": "custom" - }, - "GEM0_BOARD_INTERFACE": { - "value": "custom" - }, - "GEM1_BOARD_INTERFACE": { - "value": "custom" - }, - "GEM2_BOARD_INTERFACE": { - "value": "custom" - }, - "GEM3_BOARD_INTERFACE": { - "value": "custom" - }, - "GPIO_BOARD_INTERFACE": { - "value": "custom" - }, - "IIC0_BOARD_INTERFACE": { - "value": "custom" - }, - "IIC1_BOARD_INTERFACE": { - "value": "custom" - }, - "NAND_BOARD_INTERFACE": { - "value": "custom" - }, - "PCIE_BOARD_INTERFACE": { - "value": "custom" - }, - "PJTAG_BOARD_INTERFACE": { - "value": "custom" - }, - "PMU_BOARD_INTERFACE": { - "value": "custom" - }, - "PSU_BANK_0_IO_STANDARD": { - "value": "LVCMOS33" - }, - "PSU_BANK_1_IO_STANDARD": { - "value": "LVCMOS33" - }, - "PSU_BANK_2_IO_STANDARD": { - "value": "LVCMOS33" - }, - "PSU_BANK_3_IO_STANDARD": { - "value": "LVCMOS33" - }, - "PSU_DDR_RAM_HIGHADDR": { - "value": "0xFFFFFFFF" - }, - "PSU_DDR_RAM_HIGHADDR_OFFSET": { - "value": "0x800000000" - }, - "PSU_DDR_RAM_LOWADDR_OFFSET": { - "value": "0x80000000" - }, - "PSU_MIO_0_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_0_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_0_SLEW": { - "value": "fast" - }, - "PSU_MIO_10_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_10_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_10_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_10_SLEW": { - "value": "fast" - }, - "PSU_MIO_11_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_11_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_11_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_11_SLEW": { - "value": "fast" - }, - "PSU_MIO_12_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_12_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_12_SLEW": { - "value": "fast" - }, - "PSU_MIO_13_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_13_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_13_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_13_SLEW": { - "value": "fast" - }, - "PSU_MIO_14_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_14_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_14_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_14_SLEW": { - "value": "fast" - }, - "PSU_MIO_15_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_15_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_15_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_15_SLEW": { - "value": "fast" - }, - "PSU_MIO_16_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_16_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_16_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_16_SLEW": { - "value": "fast" - }, - "PSU_MIO_17_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_17_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_17_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_17_SLEW": { - "value": "fast" - }, - "PSU_MIO_18_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_18_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_18_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_18_SLEW": { - "value": "fast" - }, - "PSU_MIO_19_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_19_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_19_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_19_SLEW": { - "value": "fast" - }, - "PSU_MIO_1_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_1_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_1_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_1_SLEW": { - "value": "fast" - }, - "PSU_MIO_20_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_20_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_20_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_20_SLEW": { - "value": "fast" - }, - "PSU_MIO_21_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_21_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_21_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_21_SLEW": { - "value": "fast" - }, - "PSU_MIO_22_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_22_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_22_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_22_SLEW": { - "value": "fast" - }, - "PSU_MIO_23_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_23_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_23_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_23_SLEW": { - "value": "fast" - }, - "PSU_MIO_24_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_24_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_24_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_24_SLEW": { - "value": "fast" - }, - "PSU_MIO_25_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_25_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_25_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_25_SLEW": { - "value": "fast" - }, - "PSU_MIO_26_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_26_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_26_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_26_SLEW": { - "value": "fast" - }, - "PSU_MIO_27_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_27_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_27_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_27_SLEW": { - "value": "fast" - }, - "PSU_MIO_28_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_28_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_28_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_28_SLEW": { - "value": "fast" - }, - "PSU_MIO_29_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_29_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_29_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_29_SLEW": { - "value": "fast" - }, - "PSU_MIO_2_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_2_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_2_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_2_SLEW": { - "value": "fast" - }, - "PSU_MIO_30_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_30_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_30_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_30_SLEW": { - "value": "fast" - }, - "PSU_MIO_31_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_31_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_31_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_31_SLEW": { - "value": "fast" - }, - "PSU_MIO_32_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_32_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_32_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_32_SLEW": { - "value": "fast" - }, - "PSU_MIO_33_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_33_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_33_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_33_SLEW": { - "value": "fast" - }, - "PSU_MIO_34_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_34_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_34_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_34_SLEW": { - "value": "fast" - }, - "PSU_MIO_35_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_35_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_35_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_35_SLEW": { - "value": "fast" - }, - "PSU_MIO_36_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_36_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_36_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_36_SLEW": { - "value": "fast" - }, - "PSU_MIO_37_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_37_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_37_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_37_SLEW": { - "value": "fast" - }, - "PSU_MIO_38_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_38_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_38_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_38_SLEW": { - "value": "fast" - }, - "PSU_MIO_39_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_39_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_39_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_39_SLEW": { - "value": "fast" - }, - "PSU_MIO_3_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_3_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_3_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_3_SLEW": { - "value": "fast" - }, - "PSU_MIO_40_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_40_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_40_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_40_SLEW": { - "value": "fast" - }, - "PSU_MIO_41_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_41_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_41_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_41_SLEW": { - "value": "fast" - }, - "PSU_MIO_42_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_42_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_43_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_43_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_43_SLEW": { - "value": "fast" - }, - "PSU_MIO_44_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_44_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_44_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_44_SLEW": { - "value": "fast" - }, - "PSU_MIO_45_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_45_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_45_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_45_SLEW": { - "value": "fast" - }, - "PSU_MIO_46_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_46_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_46_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_46_SLEW": { - "value": "fast" - }, - "PSU_MIO_47_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_47_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_47_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_47_SLEW": { - "value": "fast" - }, - "PSU_MIO_48_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_48_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_48_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_48_SLEW": { - "value": "fast" - }, - "PSU_MIO_49_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_49_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_49_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_49_SLEW": { - "value": "fast" - }, - "PSU_MIO_4_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_4_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_4_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_4_SLEW": { - "value": "fast" - }, - "PSU_MIO_50_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_50_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_50_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_50_SLEW": { - "value": "fast" - }, - "PSU_MIO_51_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_51_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_51_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_51_SLEW": { - "value": "fast" - }, - "PSU_MIO_52_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_52_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_52_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_52_SLEW": { - "value": "fast" - }, - "PSU_MIO_53_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_53_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_53_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_53_SLEW": { - "value": "fast" - }, - "PSU_MIO_54_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_54_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_54_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_54_SLEW": { - "value": "fast" - }, - "PSU_MIO_55_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_55_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_55_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_55_SLEW": { - "value": "fast" - }, - "PSU_MIO_56_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_56_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_56_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_56_SLEW": { - "value": "fast" - }, - "PSU_MIO_57_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_57_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_57_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_57_SLEW": { - "value": "fast" - }, - "PSU_MIO_58_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_58_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_58_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_58_SLEW": { - "value": "fast" - }, - "PSU_MIO_59_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_59_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_59_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_59_SLEW": { - "value": "fast" - }, - "PSU_MIO_5_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_5_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_5_SLEW": { - "value": "fast" - }, - "PSU_MIO_60_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_60_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_60_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_60_SLEW": { - "value": "fast" - }, - "PSU_MIO_61_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_61_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_61_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_61_SLEW": { - "value": "fast" - }, - "PSU_MIO_62_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_62_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_62_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_62_SLEW": { - "value": "fast" - }, - "PSU_MIO_63_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_63_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_63_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_63_SLEW": { - "value": "fast" - }, - "PSU_MIO_64_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_64_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_64_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_64_SLEW": { - "value": "fast" - }, - "PSU_MIO_65_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_65_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_65_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_65_SLEW": { - "value": "fast" - }, - "PSU_MIO_66_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_66_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_66_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_66_SLEW": { - "value": "fast" - }, - "PSU_MIO_67_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_67_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_67_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_67_SLEW": { - "value": "fast" - }, - "PSU_MIO_68_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_68_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_68_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_68_SLEW": { - "value": "fast" - }, - "PSU_MIO_69_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_69_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_69_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_69_SLEW": { - "value": "fast" - }, - "PSU_MIO_6_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_6_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_6_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_6_SLEW": { - "value": "fast" - }, - "PSU_MIO_70_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_70_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_70_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_70_SLEW": { - "value": "fast" - }, - "PSU_MIO_71_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_71_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_71_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_71_SLEW": { - "value": "fast" - }, - "PSU_MIO_72_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_72_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_72_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_72_SLEW": { - "value": "fast" - }, - "PSU_MIO_73_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_73_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_73_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_73_SLEW": { - "value": "fast" - }, - "PSU_MIO_74_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_74_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_74_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_74_SLEW": { - "value": "fast" - }, - "PSU_MIO_75_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_75_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_75_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_75_SLEW": { - "value": "fast" - }, - "PSU_MIO_76_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_76_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_76_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_76_SLEW": { - "value": "fast" - }, - "PSU_MIO_77_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_77_INPUT_TYPE": { - "value": "cmos" - }, - "PSU_MIO_77_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_77_SLEW": { - "value": "fast" - }, - "PSU_MIO_7_DRIVE_STRENGTH": { - "value": "12" - }, - "PSU_MIO_7_PULLUPDOWN": { - "value": "pullup" - }, - "PSU_MIO_7_SLEW": { - "value": "fast" - }, - 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"SUBPRESET1": { - "value": "Custom" - }, - "SUBPRESET2": { - "value": "Custom" - }, - "SWDT0_BOARD_INTERFACE": { - "value": "custom" - }, - "SWDT1_BOARD_INTERFACE": { - "value": "custom" - }, - "TRACE_BOARD_INTERFACE": { - "value": "custom" - }, - "TTC0_BOARD_INTERFACE": { - "value": "custom" - }, - "TTC1_BOARD_INTERFACE": { - "value": "custom" - }, - "TTC2_BOARD_INTERFACE": { - "value": "custom" - }, - "TTC3_BOARD_INTERFACE": { - "value": "custom" - }, - "UART0_BOARD_INTERFACE": { - "value": "custom" - }, - "UART1_BOARD_INTERFACE": { - "value": "custom" - }, - "USB0_BOARD_INTERFACE": { - "value": "custom" - }, - "USB1_BOARD_INTERFACE": { - "value": "custom" - }, - "preset": { - "value": "None" - } - }, - "interface_ports": { - "M_AXI_HPM0_LPD": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Master", - "address_space_ref": "Data", - "base_address": { - "minimum": "0x80000000", - "maximum": "0x9FFFFFFF", - "width": "40" - } - } - }, - "addressing": { - "address_spaces": { - "Data": { - "range": "1T", - "width": "40", - "local_memory_map": { - "name": "Data", - "description": "Address Space Segments", - "address_blocks": { - "M_AXI_HPM0_LPD:LPD_AFI_FS": { - "name": "M_AXI_HPM0_LPD:LPD_AFI_FS", - "display_name": "M_AXI_HPM0_LPD/LPD_AFI_FS", - "base_address": "0x80000000", - "range": "512M", - "width": "32", - "usage": "register" - }, - "M_AXI_HPM1_FPD:FPD_AFI_FS0_00": { - "name": "M_AXI_HPM1_FPD:FPD_AFI_FS0_00", - "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_00", - "base_address": "0xB0000000", - "range": "256M", - "width": "32", - "usage": "register" - }, - "M_AXI_HPM1_FPD:FPD_AFI_FS0_01": { - "name": "M_AXI_HPM1_FPD:FPD_AFI_FS0_01", - "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_01", - "base_address": "0x000500000000", - "range": "4G", - "width": "35", - "usage": "register" - }, - "M_AXI_HPM1_FPD:FPD_AFI_FS0_10": { - "name": "M_AXI_HPM1_FPD:FPD_AFI_FS0_10", - "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_10", - "base_address": "0x004800000000", - "range": "224G", - "width": "39", - "usage": "register" - }, - "M_AXI_HPM0_FPD:FPD_AFI_FS1_00": { - "name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_00", - "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_00", - "base_address": "0xA0000000", - "range": "256M", - "width": "32", - "usage": "register" - }, - "M_AXI_HPM0_FPD:FPD_AFI_FS1_01": { - "name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_01", - "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_01", - "base_address": "0x000400000000", - "range": "4G", - "width": "35", - "usage": "register" - }, - "M_AXI_HPM0_FPD:FPD_AFI_FS1_10": { - "name": "M_AXI_HPM0_FPD:FPD_AFI_FS1_10", - "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_10", - "base_address": "0x001000000000", - "range": "224G", - "width": "39", - "usage": "register" - } - } - } - } - } - } - }, - "axi_interconnect_1": { - "vlnv": "xilinx.com:ip:axi_interconnect:2.1", - "xci_path": "ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci", - "inst_hier_path": "axi_interconnect_1", - "xci_name": "design_1_axi_interconnect_1_0", - "parameters": { - "M00_HAS_DATA_FIFO": { - "value": "0" - }, - "NUM_MI": { - "value": "1" - }, - "NUM_SI": { - "value": "2" - }, - "S00_HAS_DATA_FIFO": { - "value": "1" - }, - "S01_HAS_DATA_FIFO": { - "value": "1" - } - }, - "interface_ports": { - "S00_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "CLK_DOMAIN": { - "value": "design_1_xdma_0_0_axi_aclk", - "value_src": "undefined" - } - } - }, - "M00_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S01_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "parameters": { - "CLK_DOMAIN": { - "value": "design_1_xdma_0_0_axi_aclk", - "value_src": "undefined" - } - } - } - }, - "ports": { - "ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_RESET": { - "value": "ARESETN" - } - } - }, - "ARESETN": { - "type": "rst", - "direction": "I" - }, - "S00_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S00_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S00_ARESETN" - } - } - }, - "S00_ARESETN": { - "type": "rst", - "direction": "I" - }, - "M00_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M00_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M00_ARESETN" - } - } - }, - "M00_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S01_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S01_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S01_ARESETN" - } - } - }, - "S01_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "components": { - "xbar": { - "vlnv": "xilinx.com:ip:axi_crossbar:2.1", - "xci_name": "design_1_xbar_2", - "xci_path": "ip/design_1_xbar_2/design_1_xbar_2.xci", - "inst_hier_path": "axi_interconnect_1/xbar", - "parameters": { - "NUM_MI": { - "value": "1" - }, - "NUM_SI": { - "value": "2" - }, - "STRATEGY": { - "value": "0" - } - }, - "interface_ports": { - "S00_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M00_AXI" - ] - }, - "S01_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M00_AXI" - ] - } - } - }, - "s00_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "components": { - "s00_data_fifo": { - "vlnv": "xilinx.com:ip:axi_data_fifo:2.1", - "xci_name": "design_1_s00_data_fifo_0", - "xci_path": "ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci", - "inst_hier_path": "axi_interconnect_1/s00_couplers/s00_data_fifo", - "interface_ports": { - "S_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M_AXI" - ] - } - } - } - }, - "interface_nets": { - "s00_couplers_to_s00_data_fifo": { - "interface_ports": [ - "S_AXI", - "s00_data_fifo/S_AXI" - ] - }, - "s00_data_fifo_to_s00_couplers": { - "interface_ports": [ - "M_AXI", - "s00_data_fifo/M_AXI" - ] - } - }, - "nets": { - "M_ACLK_1": { - "ports": [ - "M_ACLK", - "s00_data_fifo/aclk" - ] - }, - "M_ARESETN_1": { - "ports": [ - "M_ARESETN", - "s00_data_fifo/aresetn" - ] - } - } - }, - "s01_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "components": { - "s01_data_fifo": { - "vlnv": "xilinx.com:ip:axi_data_fifo:2.1", - "xci_name": "design_1_s01_data_fifo_0", - "xci_path": "ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci", - "inst_hier_path": "axi_interconnect_1/s01_couplers/s01_data_fifo", - "interface_ports": { - "S_AXI": { - "vlnv": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "Slave", - "bridges": [ - "M_AXI" - ] - } - } - } - }, - "interface_nets": { - "s01_couplers_to_s01_data_fifo": { - "interface_ports": [ - "S_AXI", - "s01_data_fifo/S_AXI" - ] - }, - "s01_data_fifo_to_s01_couplers": { - "interface_ports": [ - "M_AXI", - "s01_data_fifo/M_AXI" - ] - } - }, - "nets": { - "M_ACLK_1": { - "ports": [ - "M_ACLK", - "s01_data_fifo/aclk" - ] - }, - "M_ARESETN_1": { - "ports": [ - "M_ARESETN", - "s01_data_fifo/aresetn" - ] - } - } - }, - "m00_couplers": { - "interface_ports": { - "M_AXI": { - "mode": "Master", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - }, - "S_AXI": { - "mode": "Slave", - "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", - "vlnv": "xilinx.com:interface:aximm_rtl:1.0" - } - }, - "ports": { - "M_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "M_AXI" - }, - "ASSOCIATED_RESET": { - "value": "M_ARESETN" - } - } - }, - "M_ARESETN": { - "type": "rst", - "direction": "I" - }, - "S_ACLK": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "S_AXI" - }, - "ASSOCIATED_RESET": { - "value": "S_ARESETN" - } - } - }, - "S_ARESETN": { - "type": "rst", - "direction": "I" - } - }, - "interface_nets": { - "m00_couplers_to_m00_couplers": { - "interface_ports": [ - "S_AXI", - "M_AXI" - ] - } - } - } - }, - "interface_nets": { - "axi_interconnect_1_to_s00_couplers": { - "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" - ] - }, - "axi_interconnect_1_to_s01_couplers": { - "interface_ports": [ - "S01_AXI", - "s01_couplers/S_AXI" - ] - }, - "m00_couplers_to_axi_interconnect_1": { - "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" - ] - }, - "s00_couplers_to_xbar": { - "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" - ] - }, - "s01_couplers_to_xbar": { - "interface_ports": [ - "s01_couplers/M_AXI", - "xbar/S01_AXI" - ] - }, - "xbar_to_m00_couplers": { - "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" - ] - } - }, - "nets": { - "axi_interconnect_1_ACLK_net": { - "ports": [ - "ACLK", - "xbar/aclk", - "s00_couplers/S_ACLK", - "s01_couplers/S_ACLK", - "s00_couplers/M_ACLK", - "s01_couplers/M_ACLK", - "m00_couplers/M_ACLK", - "m00_couplers/S_ACLK" - ] - }, - "axi_interconnect_1_ARESETN_net": { - "ports": [ - "ARESETN", - "xbar/aresetn", - "s00_couplers/S_ARESETN", - "s01_couplers/S_ARESETN", - "s00_couplers/M_ARESETN", - "s01_couplers/M_ARESETN", - "m00_couplers/M_ARESETN", - "m00_couplers/S_ARESETN" - ] - } - } } }, "interface_nets": { @@ -7897,6 +6740,18 @@ "axi_interconnect_1/S01_AXI" ] }, + "S02_AXI_0_1": { + "interface_ports": [ + "pcie_m_axi2", + "axi_interconnect_1/S02_AXI" + ] + }, + "S03_AXI_0_1": { + "interface_ports": [ + "pcie_m_axi3", + "axi_interconnect_1/S03_AXI" + ] + }, "axi_interconnect_0_M00_AXI": { "interface_ports": [ "axi_interconnect_0/M00_AXI", @@ -7912,7 +6767,7 @@ "axi_interconnect_0_M02_AXI": { "interface_ports": [ "axi_interconnect_0/M02_AXI", - "axi_uartlite_0/S_AXI" + "mdm_1/S_AXI" ] }, "axi_interconnect_0_M03_AXI": { @@ -7933,12 +6788,6 @@ "xdma_0/S_AXI_B" ] }, - "axi_uartlite_0_UART": { - "interface_ports": [ - "UART_0", - "axi_uartlite_0/UART" - ] - }, "microblaze_0_axi_periph_M00_AXI": { "interface_ports": [ "microblaze_0_axi_periph/M00_AXI", @@ -7981,6 +6830,18 @@ "microblaze_0_axi_periph/M06_AXI" ] }, + "microblaze_0_axi_periph_M07_AXI": { + "interface_ports": [ + "axil_dma_ctrl2", + "microblaze_0_axi_periph/M07_AXI" + ] + }, + "microblaze_0_axi_periph_M08_AXI": { + "interface_ports": [ + "axil_dma_ctrl3", + "microblaze_0_axi_periph/M08_AXI" + ] + }, "microblaze_0_debug": { "interface_ports": [ "mdm_1/MBDEBUG_0", @@ -8023,17 +6884,21 @@ "ports": [ "xdma_0/axi_aresetn", "axi_pcie_aresetn", - "microblaze_0_axi_periph/M01_ARESETN", - "microblaze_0_axi_periph/M02_ARESETN", - "microblaze_0_axi_periph/M03_ARESETN", - "microblaze_0_axi_periph/S01_ARESETN", - "microblaze_0_axi_periph/M05_ARESETN", - "microblaze_0_axi_periph/M06_ARESETN", - "microblaze_0_axi_periph/M04_ARESETN", "axi_interconnect_1/ARESETN", "axi_interconnect_1/S00_ARESETN", "axi_interconnect_1/M00_ARESETN", - "axi_interconnect_1/S01_ARESETN" + "axi_interconnect_1/S01_ARESETN", + "microblaze_0_axi_periph/M01_ARESETN", + "microblaze_0_axi_periph/S01_ARESETN", + "microblaze_0_axi_periph/M02_ARESETN", + "microblaze_0_axi_periph/M03_ARESETN", + "microblaze_0_axi_periph/M04_ARESETN", + "microblaze_0_axi_periph/M05_ARESETN", + "microblaze_0_axi_periph/M06_ARESETN", + "axi_interconnect_1/S02_ARESETN", + "axi_interconnect_1/S03_ARESETN", + "microblaze_0_axi_periph/M07_ARESETN", + "microblaze_0_axi_periph/M08_ARESETN" ] }, "axi_timer_0_interrupt": { @@ -8042,12 +6907,6 @@ "microblaze_0_xlconcat/In1" ] }, - "axi_uartlite_0_interrupt": { - "ports": [ - "axi_uartlite_0/interrupt", - "microblaze_0_xlconcat/In0" - ] - }, "clk_wiz_1_locked": { "ports": [ "clk_wiz_1/locked", @@ -8064,22 +6923,22 @@ "ports": [ "clk_wiz_1/clk_out1", "axil_clk", + "microblaze_0_local_memory/LMB_Clk", "axi_interconnect_0/ACLK", + "axi_interconnect_0/S00_ACLK", "axi_interconnect_0/M00_ACLK", "axi_interconnect_0/M01_ACLK", "axi_interconnect_0/M02_ACLK", "axi_interconnect_0/M03_ACLK", "axi_interconnect_0/M04_ACLK", - "axi_interconnect_0/S00_ACLK", "axi_timer_0/s_axi_aclk", - "axi_uartlite_0/s_axi_aclk", "microblaze_0/Clk", - "microblaze_0_axi_intc/processor_clk", "microblaze_0_axi_intc/s_axi_aclk", + "microblaze_0_axi_intc/processor_clk", "microblaze_0_axi_periph/S00_ACLK", - "microblaze_0_local_memory/LMB_Clk", "rst_clk_wiz_1_100M/slowest_sync_clk", - "system_management_wiz_0/s_axi_aclk" + "system_management_wiz_0/s_axi_aclk", + "mdm_1/S_AXI_ACLK" ] }, "microblaze_0_intr": { @@ -8106,17 +6965,17 @@ "rst_clk_wiz_1_100M/peripheral_aresetn", "axil_resetn", "axi_interconnect_0/ARESETN", + "axi_interconnect_0/S00_ARESETN", "axi_interconnect_0/M00_ARESETN", "axi_interconnect_0/M01_ARESETN", "axi_interconnect_0/M02_ARESETN", "axi_interconnect_0/M03_ARESETN", "axi_interconnect_0/M04_ARESETN", - "axi_interconnect_0/S00_ARESETN", "axi_timer_0/s_axi_aresetn", - "axi_uartlite_0/s_axi_aresetn", "microblaze_0_axi_intc/s_axi_aresetn", "microblaze_0_axi_periph/S00_ARESETN", - "system_management_wiz_0/s_axi_aresetn" + "system_management_wiz_0/s_axi_aresetn", + "mdm_1/S_AXI_ARESETN" ] }, "sys_rst_n_0_1": { @@ -8153,26 +7012,30 @@ "ports": [ "xdma_0/axi_aclk", "axi_pcie_clk", - "microblaze_0_axi_periph/M00_ACLK", - "microblaze_0_axi_periph/M01_ACLK", - "microblaze_0_axi_periph/M02_ACLK", - "microblaze_0_axi_periph/M03_ACLK", - "microblaze_0_axi_periph/S01_ACLK", - "microblaze_0_axi_periph/M05_ACLK", - "microblaze_0_axi_periph/M06_ACLK", - "microblaze_0_axi_periph/M04_ACLK", - "microblaze_0_axi_periph/ACLK", "axi_interconnect_1/ACLK", "axi_interconnect_1/S00_ACLK", "axi_interconnect_1/M00_ACLK", - "axi_interconnect_1/S01_ACLK" + "axi_interconnect_1/S01_ACLK", + "microblaze_0_axi_periph/ACLK", + "microblaze_0_axi_periph/M00_ACLK", + "microblaze_0_axi_periph/M01_ACLK", + "microblaze_0_axi_periph/S01_ACLK", + "microblaze_0_axi_periph/M02_ACLK", + "microblaze_0_axi_periph/M03_ACLK", + "microblaze_0_axi_periph/M04_ACLK", + "microblaze_0_axi_periph/M05_ACLK", + "microblaze_0_axi_periph/M06_ACLK", + "axi_interconnect_1/S02_ACLK", + "axi_interconnect_1/S03_ACLK", + "microblaze_0_axi_periph/M07_ACLK", + "microblaze_0_axi_periph/M08_ACLK" ] }, "xdma_0_axi_ctl_aresetn": { "ports": [ "xdma_0/axi_ctl_aresetn", - "microblaze_0_axi_periph/M00_ARESETN", - "microblaze_0_axi_periph/ARESETN" + "microblaze_0_axi_periph/ARESETN", + "microblaze_0_axi_periph/M00_ARESETN" ] }, "xdma_0_cfg_ltssm_state": { @@ -8190,14 +7053,8 @@ "xlconstant_0_dout": { "ports": [ "xlconstant_0/dout", - "rst_clk_wiz_1_100M/aux_reset_in", - "rst_clk_wiz_1_100M/ext_reset_in" - ] - }, - "zynq_ultra_ps_e_0_pl_clk0": { - "ports": [ - "zynq_ultra_ps_e_0/pl_clk0", - "zynq_ultra_ps_e_0/maxihpm0_lpd_aclk" + "rst_clk_wiz_1_100M/ext_reset_in", + "rst_clk_wiz_1_100M/aux_reset_in" ] } }, @@ -8229,6 +7086,32 @@ "offset_high_param": "axibar_highaddr_0" } } + }, + "pcie_m_axi2": { + "range": "1T", + "width": "40", + "segments": { + "SEG_xdma_0_BAR0": { + "address_block": "/xdma_0/S_AXI_B/BAR0", + "offset": "0x0000000000", + "range": "1T", + "offset_base_param": "axibar_0", + "offset_high_param": "axibar_highaddr_0" + } + } + }, + "pcie_m_axi3": { + "range": "1T", + "width": "40", + "segments": { + "SEG_xdma_0_BAR0": { + "address_block": "/xdma_0/S_AXI_B/BAR0", + "offset": "0x0000000000", + "range": "1T", + "offset_base_param": "axibar_0", + "offset_high_param": "axibar_highaddr_0" + } + } } }, "memory_maps": { @@ -8272,6 +7155,26 @@ } } }, + "axil_dma_ctrl2": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register" + } + } + }, + "axil_dma_ctrl3": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register" + } + } + }, "axil_timing": { "address_blocks": { "Reg": { @@ -8303,14 +7206,9 @@ "offset": "0x40000000", "range": "64K" }, - "SEG_axi_uartlite_0_Reg": { - "address_block": "/axi_uartlite_0/S_AXI/Reg", - "offset": "0x40010000", - "range": "64K" - }, "SEG_axil_data_gen_Reg": { "address_block": "/axil_data_gen/Reg", - "offset": "0x80120000", + "offset": "0x80030000", "range": "64K" }, "SEG_axil_descriptors_Reg": { @@ -8320,22 +7218,32 @@ }, "SEG_axil_dma_ctrl0_Reg": { "address_block": "/axil_dma_ctrl0/Reg", - "offset": "0x81000000", + "offset": "0x80100000", "range": "64K" }, "SEG_axil_dma_ctrl1_Reg": { "address_block": "/axil_dma_ctrl1/Reg", - "offset": "0x81010000", + "offset": "0x80110000", + "range": "64K" + }, + "SEG_axil_dma_ctrl2_Reg": { + "address_block": "/axil_dma_ctrl2/Reg", + "offset": "0x80120000", + "range": "64K" + }, + "SEG_axil_dma_ctrl3_Reg": { + "address_block": "/axil_dma_ctrl3/Reg", + "offset": "0x80130000", "range": "64K" }, "SEG_axil_timing_Reg": { "address_block": "/axil_timing/Reg", - "offset": "0x80110000", + "offset": "0x80020000", "range": "64K" }, "SEG_axil_util_Reg": { "address_block": "/axil_util/Reg", - "offset": "0x80100000", + "offset": "0x80010000", "range": "64K" }, "SEG_dlmb_bram_if_cntlr_Mem": { @@ -8344,6 +7252,11 @@ "range": "32K", "offset_high_param": "C_HIGHADDR" }, + "SEG_mdm_1_Reg": { + "address_block": "/mdm_1/S_AXI/Reg", + "offset": "0x40010000", + "range": "4K" + }, "SEG_microblaze_0_axi_intc_Reg": { "address_block": "/microblaze_0_axi_intc/S_AXI/Reg", "offset": "0x40020000", @@ -8381,7 +7294,7 @@ "segments": { "SEG_axil_data_gen_Reg": { "address_block": "/axil_data_gen/Reg", - "offset": "0x0080120000", + "offset": "0x0080030000", "range": "64K" }, "SEG_axil_descriptors_Reg": { @@ -8391,22 +7304,32 @@ }, "SEG_axil_dma_ctrl0_Reg": { "address_block": "/axil_dma_ctrl0/Reg", - "offset": "0x0081000000", + "offset": "0x0080100000", "range": "64K" }, "SEG_axil_dma_ctrl1_Reg": { "address_block": "/axil_dma_ctrl1/Reg", - "offset": "0x0081010000", + "offset": "0x0080110000", + "range": "64K" + }, + "SEG_axil_dma_ctrl2_Reg": { + "address_block": "/axil_dma_ctrl2/Reg", + "offset": "0x0080120000", + "range": "64K" + }, + "SEG_axil_dma_ctrl3_Reg": { + "address_block": "/axil_dma_ctrl3/Reg", + "offset": "0x0080130000", "range": "64K" }, "SEG_axil_timing_Reg": { "address_block": "/axil_timing/Reg", - "offset": "0x0080110000", + "offset": "0x0080020000", "range": "64K" }, "SEG_axil_util_Reg": { "address_block": "/axil_util/Reg", - "offset": "0x0080100000", + "offset": "0x0080010000", "range": "64K" }, "SEG_xdma_0_CTL0": { diff --git a/project_1.srcs/sources_1/bd/design_1/design_1.bda b/project_1.srcs/sources_1/bd/design_1/design_1.bda index e1dc0e3..835e016 100644 --- a/project_1.srcs/sources_1/bd/design_1/design_1.bda +++ b/project_1.srcs/sources_1/bd/design_1/design_1.bda @@ -23,9 +23,27 @@ - 0x0080110000 + 0x80010000 C_BASEADDR - 0x008011FFFF + 0x8001FFFF + C_HIGHADDR + Data + /microblaze_0 + M_AXI_DP + SEG_axil_util_Reg + xilinx.com:ip:microblaze:11.0 + data + / + axil_util + Reg + ::design_1_imp: + register + AC + + + 0x0080020000 + C_BASEADDR + 0x008002FFFF C_HIGHADDR M_AXI_B /xdma_0 @@ -40,43 +58,61 @@ register AC - - 0x81010000 + + 0x40000000 C_BASEADDR - 0x8101FFFF + 0x4000FFFF C_HIGHADDR Data /microblaze_0 M_AXI_DP - SEG_axil_dma_ctrl1_Reg + SEG_axi_timer_0_Reg + xilinx.com:ip:microblaze:11.0 + data + /axi_timer_0 + S_AXI + Reg + xilinx.com:ip:axi_timer:2.0 + register + AC + + + 0x80000000 + C_BASEADDR + 0x8000FFFF + C_HIGHADDR + Data + /microblaze_0 + M_AXI_DP + SEG_axil_descriptors_Reg xilinx.com:ip:microblaze:11.0 data / - axil_dma_ctrl1 + axil_descriptors Reg ::design_1_imp: register AC - - 0x40030000 + + 0x0080000000 C_BASEADDR - 0x4003FFFF + 0x008000FFFF C_HIGHADDR - Data - /microblaze_0 - M_AXI_DP - SEG_system_management_wiz_0_Reg - xilinx.com:ip:microblaze:11.0 - data - /system_management_wiz_0 - S_AXI_LITE + M_AXI_B + /xdma_0 + M_AXI_B + SEG_axil_descriptors_Reg + xilinx.com:ip:xdma:4.1 + both + / + axil_descriptors Reg - xilinx.com:ip:system_management_wiz:1.3 + ::design_1_imp: register AC - + 0x0000000000 axibar_0 0xFFFFFFFFFF @@ -94,25 +130,48 @@ memory AC - - 0x0081010000 + + active + 2 + PM + + + 0x0000000000 + axibar_0 + 0xFFFFFFFFFF + axibar_highaddr_0 + pcie_m_axi3 + / + pcie_m_axi3 + SEG_xdma_0_BAR0 + ::: + both + /xdma_0 + S_AXI_B + BAR0 + xilinx.com:ip:xdma:4.1 + memory + AC + + + 0x0080010000 C_BASEADDR - 0x008101FFFF + 0x008001FFFF C_HIGHADDR M_AXI_B /xdma_0 M_AXI_B - SEG_axil_dma_ctrl1_Reg + SEG_axil_util_Reg xilinx.com:ip:xdma:4.1 both / - axil_dma_ctrl1 + axil_util Reg ::design_1_imp: register AC - + 0x40020000 C_BASEADDR 0x4002FFFF @@ -131,32 +190,50 @@ register AC - - 0x80100000 + + 0x80110000 C_BASEADDR - 0x8010FFFF + 0x8011FFFF C_HIGHADDR Data /microblaze_0 M_AXI_DP - SEG_axil_util_Reg + SEG_axil_dma_ctrl1_Reg xilinx.com:ip:microblaze:11.0 data / - axil_util + axil_dma_ctrl1 Reg ::design_1_imp: register AC - + + 0x0080130000 + C_BASEADDR + 0x008013FFFF + C_HIGHADDR + M_AXI_B + /xdma_0 + M_AXI_B + SEG_axil_dma_ctrl3_Reg + xilinx.com:ip:xdma:4.1 + both + / + axil_dma_ctrl3 + Reg + ::design_1_imp: + register + AC + + 0x0000000000 axibar_0 0xFFFFFFFFFF axibar_highaddr_0 - pcie_m_axi0 + pcie_m_axi2 / - pcie_m_axi0 + pcie_m_axi2 SEG_xdma_0_BAR0 ::: both @@ -167,102 +244,7 @@ memory AC - - 0x0083000000 - baseaddr - 0x0083FFFFFF - highaddr - M_AXI_B - /xdma_0 - M_AXI_B - SEG_xdma_0_CTL0 - xilinx.com:ip:xdma:4.1 - both - /xdma_0 - S_AXI_LITE - CTL0 - xilinx.com:ip:xdma:4.1 - memory - AC - - - 0x0081000000 - C_BASEADDR - 0x008100FFFF - C_HIGHADDR - M_AXI_B - /xdma_0 - M_AXI_B - SEG_axil_dma_ctrl0_Reg - xilinx.com:ip:xdma:4.1 - both - / - axil_dma_ctrl0 - Reg - ::design_1_imp: - register - AC - - - 0x0080000000 - C_BASEADDR - 0x008000FFFF - C_HIGHADDR - M_AXI_B - /xdma_0 - M_AXI_B - SEG_axil_descriptors_Reg - xilinx.com:ip:xdma:4.1 - both - / - axil_descriptors - Reg - ::design_1_imp: - register - AC - - - 2 - design_1 - VR - - - 0x81000000 - C_BASEADDR - 0x8100FFFF - C_HIGHADDR - Data - /microblaze_0 - M_AXI_DP - SEG_axil_dma_ctrl0_Reg - xilinx.com:ip:microblaze:11.0 - data - / - axil_dma_ctrl0 - Reg - ::design_1_imp: - register - AC - - 0x80110000 - C_BASEADDR - 0x8011FFFF - C_HIGHADDR - Data - /microblaze_0 - M_AXI_DP - SEG_axil_timing_Reg - xilinx.com:ip:microblaze:11.0 - data - / - axil_timing - Reg - ::design_1_imp: - register - AC - - 0x0080100000 C_BASEADDR 0x008010FFFF @@ -270,17 +252,111 @@ M_AXI_B /xdma_0 M_AXI_B - SEG_axil_util_Reg + SEG_axil_dma_ctrl0_Reg xilinx.com:ip:xdma:4.1 both / - axil_util + axil_dma_ctrl0 + Reg + ::design_1_imp: + register + AC + + + 0x0080110000 + C_BASEADDR + 0x008011FFFF + C_HIGHADDR + M_AXI_B + /xdma_0 + M_AXI_B + SEG_axil_dma_ctrl1_Reg + xilinx.com:ip:xdma:4.1 + both + / + axil_dma_ctrl1 Reg ::design_1_imp: register AC + 0x0080030000 + C_BASEADDR + 0x008003FFFF + C_HIGHADDR + M_AXI_B + /xdma_0 + M_AXI_B + SEG_axil_data_gen_Reg + xilinx.com:ip:xdma:4.1 + both + / + axil_data_gen + Reg + ::design_1_imp: + register + AC + + + 0x40010000 + C_BASEADDR + 0x40010FFF + C_HIGHADDR + Data + /microblaze_0 + M_AXI_DP + SEG_mdm_1_Reg + xilinx.com:ip:microblaze:11.0 + data + /mdm_1 + S_AXI + Reg + xilinx.com:ip:mdm:3.2 + register + AC + + + 0x40030000 + C_BASEADDR + 0x4003FFFF + C_HIGHADDR + Data + /microblaze_0 + M_AXI_DP + SEG_system_management_wiz_0_Reg + xilinx.com:ip:microblaze:11.0 + data + /system_management_wiz_0 + S_AXI_LITE + Reg + xilinx.com:ip:system_management_wiz:1.3 + register + AC + + + 0x0080120000 + C_BASEADDR + 0x008012FFFF + C_HIGHADDR + M_AXI_B + /xdma_0 + M_AXI_B + SEG_axil_dma_ctrl2_Reg + xilinx.com:ip:xdma:4.1 + both + / + axil_dma_ctrl2 + Reg + ::design_1_imp: + register + AC + + + design_1 + BC + + 0x00000000 C_BASEADDR 0x00007FFF @@ -298,14 +374,28 @@ memory AC - - design_1 - BC + + 0x0000000000 + axibar_0 + 0xFFFFFFFFFF + axibar_highaddr_0 + pcie_m_axi0 + / + pcie_m_axi0 + SEG_xdma_0_BAR0 + ::: + both + /xdma_0 + S_AXI_B + BAR0 + xilinx.com:ip:xdma:4.1 + memory + AC - - 0x80120000 + + 0x80030000 C_BASEADDR - 0x8012FFFF + 0x8003FFFF C_HIGHADDR Data /microblaze_0 @@ -320,17 +410,17 @@ register AC - - 0x83000000 + + 0x0083000000 baseaddr - 0x83FFFFFF + 0x0083FFFFFF highaddr - Data - /microblaze_0 - M_AXI_DP + M_AXI_B + /xdma_0 + M_AXI_B SEG_xdma_0_CTL0 - xilinx.com:ip:microblaze:11.0 - data + xilinx.com:ip:xdma:4.1 + both /xdma_0 S_AXI_LITE CTL0 @@ -338,25 +428,48 @@ memory AC - - 0x40000000 + + 0x80130000 C_BASEADDR - 0x4000FFFF + 0x8013FFFF C_HIGHADDR Data /microblaze_0 M_AXI_DP - SEG_axi_timer_0_Reg + SEG_axil_dma_ctrl3_Reg xilinx.com:ip:microblaze:11.0 data - /axi_timer_0 - S_AXI + / + axil_dma_ctrl3 Reg - xilinx.com:ip:axi_timer:2.0 + ::design_1_imp: register AC - + + 2 + design_1 + VR + + + 0x80020000 + C_BASEADDR + 0x8002FFFF + C_HIGHADDR + Data + /microblaze_0 + M_AXI_DP + SEG_axil_timing_Reg + xilinx.com:ip:microblaze:11.0 + data + / + axil_timing + Reg + ::design_1_imp: + register + AC + + 0x00000000 C_BASEADDR 0x00007FFF @@ -374,131 +487,144 @@ memory AC - - active - 2 - PM + + 0x83000000 + baseaddr + 0x83FFFFFF + highaddr + Data + /microblaze_0 + M_AXI_DP + SEG_xdma_0_CTL0 + xilinx.com:ip:microblaze:11.0 + data + /xdma_0 + S_AXI_LITE + CTL0 + xilinx.com:ip:xdma:4.1 + memory + AC - - 0x0080120000 + + 0x80120000 C_BASEADDR - 0x008012FFFF + 0x8012FFFF C_HIGHADDR - M_AXI_B - /xdma_0 - M_AXI_B - SEG_axil_data_gen_Reg - xilinx.com:ip:xdma:4.1 - both + Data + /microblaze_0 + M_AXI_DP + SEG_axil_dma_ctrl2_Reg + xilinx.com:ip:microblaze:11.0 + data / - axil_data_gen + axil_dma_ctrl2 Reg ::design_1_imp: register AC - - 0x80000000 + + 0x80100000 C_BASEADDR - 0x8000FFFF + 0x8010FFFF C_HIGHADDR Data /microblaze_0 M_AXI_DP - SEG_axil_descriptors_Reg + SEG_axil_dma_ctrl0_Reg xilinx.com:ip:microblaze:11.0 data / - axil_descriptors + axil_dma_ctrl0 Reg ::design_1_imp: register AC - - 0x40010000 - C_BASEADDR - 0x4001FFFF - C_HIGHADDR - Data - /microblaze_0 - M_AXI_DP - SEG_axi_uartlite_0_Reg - xilinx.com:ip:microblaze:11.0 - data - /axi_uartlite_0 - S_AXI - Reg - xilinx.com:ip:axi_uartlite:2.0 - register - AC - - - - + + + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + + 2 + + + 2 + + + 2 + + + 2 + + + 2 + + + 2 + + 2 diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0.xci index f984a8d..c7b34cb 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_cc_0/design_1_auto_cc_0.xci @@ -24,7 +24,7 @@ "Component_Name": [ { "value": "design_1_auto_cc_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -43,11 +43,11 @@ "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0.xci index 9c6039d..e2e8513 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0.xci @@ -12,7 +12,7 @@ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "SI_DATA_WIDTH": [ { "value": "256", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SI_DATA_WIDTH": [ { "value": "512", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MI_DATA_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "SI_ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -23,12 +23,12 @@ "Component_Name": [ { "value": "design_1_auto_ds_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_SUPPORTS_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_S_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -41,11 +41,11 @@ "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -82,8 +82,8 @@ "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ], "s_axi_awready": [ { "direction": "out" } ], - "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ], - "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ], "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ], "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ], "s_axi_wready": [ { "direction": "out" } ], @@ -104,7 +104,7 @@ "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ], "s_axi_arready": [ { "direction": "out" } ], "s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], - "s_axi_rdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axi_rlast": [ { "direction": "out" } ], "s_axi_rvalid": [ { "direction": "out" } ], @@ -151,7 +151,7 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "slave", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -173,7 +173,7 @@ "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -252,7 +252,7 @@ "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci index 29f44fe..d03c169 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci @@ -23,7 +23,7 @@ "Component_Name": [ { "value": "design_1_auto_pc_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_IGNORE_ID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -41,11 +41,11 @@ "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -153,7 +153,7 @@ "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -228,7 +228,7 @@ "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/design_1_auto_us_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/design_1_auto_us_0.xci new file mode 100644 index 0000000..d6953f7 --- /dev/null +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/design_1_auto_us_0.xci @@ -0,0 +1,265 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_auto_us_0", + "cell_name": "axi_interconnect_1/s00_couplers/auto_us", + "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1", + "ip_revision": "27", + "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_auto_us_0", + "parameters": { + "component_parameters": { + "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PACKING_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SI_DATA_WIDTH": [ { "value": "256", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MI_DATA_WIDTH": [ { "value": "512", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SI_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MAX_SPLIT_BEATS": [ { "value": "256", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FIFO_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ACLK_ASYNC": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ACLK_RATIO": [ { "value": "1:2", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "Component_Name": [ { "value": "design_1_auto_us_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], + "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SUPPORTS_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_M_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_READ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_FIFO_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MAX_SPLIT_BEATS": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PACKING_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "kintexuplus" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + 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"is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": 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"ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_3/design_1_auto_us_3.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_3/design_1_auto_us_3.xci new file mode 100644 index 0000000..7dbd2dd --- /dev/null +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_3/design_1_auto_us_3.xci @@ -0,0 +1,265 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": 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"16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWLEN": [ { "physical_name": "m_axi_awlen" } ], + "AWSIZE": [ { "physical_name": "m_axi_awsize" } ], + "AWBURST": [ { "physical_name": "m_axi_awburst" } ], + "AWLOCK": [ { "physical_name": "m_axi_awlock" } ], + "AWCACHE": [ { "physical_name": "m_axi_awcache" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWREGION": [ { "physical_name": "m_axi_awregion" } ], + "AWQOS": [ { "physical_name": "m_axi_awqos" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WLAST": [ { "physical_name": "m_axi_wlast" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ] + } + }, + "SI_CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "SI_RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci index 0f97667..8b18a57 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci @@ -325,11 +325,11 @@ "Component_Name": [ { "value": "design_1_axi_interconnect_0_0", "resolve_type": "user", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci index b813c29..b83c312 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_1_0/design_1_axi_interconnect_1_0.xci @@ -8,7 +8,7 @@ "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_interconnect_1_0", "parameters": { "component_parameters": { - "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_SI": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -164,8 +164,8 @@ "S15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "S00_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S01_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_HAS_DATA_FIFO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "S05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "S06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -325,11 +325,11 @@ "Component_Name": [ { "value": "design_1_axi_interconnect_1_0", "resolve_type": "user", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci index 5dc2a83..76061e4 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci @@ -18,7 +18,7 @@ "enable_timer2": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_COUNT_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ONE_TIMER_ONLY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_TRIG0_ASSERT": [ { "value": "1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], @@ -29,11 +29,11 @@ "C_S_AXI_ADDR_WIDTH": [ { "value": "5", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci deleted file mode 100644 index ee86754..0000000 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci +++ /dev/null @@ -1,364 +0,0 @@ -{ - "schema": "xilinx.com:schema:json_instance:1.0", - "ip_inst": { - "xci_name": "design_1_axi_uartlite_0_0", - "cell_name": "axi_uartlite_0", - "component_reference": "xilinx.com:ip:axi_uartlite:2.0", - "ip_revision": "31", - "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0", - "parameters": { - "component_parameters": { - "C_DATA_BITS": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], - "C_BAUDRATE": [ { "value": "115200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "C_S_AXI_ACLK_FREQ_HZ": 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"direction": "out", "size_left": "1", "size_right": "0" } ], - "s_axi_rvalid": [ { "direction": "out" } ], - "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ], - "rx": [ { "direction": "in", "driver_value": "0" } ], - "tx": [ { "direction": "out" } ] - }, - "interfaces": { - "S_AXI": { - "vlnv": "xilinx.com:interface:aximm:1.0", - "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "slave", - "parameters": { - "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "ARADDR": [ { "physical_name": "s_axi_araddr" } ], - "ARREADY": [ { "physical_name": "s_axi_arready" } ], - "ARVALID": [ { "physical_name": "s_axi_arvalid" } ], - "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], - "AWREADY": [ { "physical_name": "s_axi_awready" } ], - "AWVALID": [ { "physical_name": "s_axi_awvalid" } ], - "BREADY": [ { "physical_name": "s_axi_bready" } ], - "BRESP": [ { "physical_name": "s_axi_bresp" } ], - "BVALID": [ { "physical_name": "s_axi_bvalid" } ], - "RDATA": [ { "physical_name": "s_axi_rdata" } ], - "RREADY": [ { "physical_name": "s_axi_rready" } ], - "RRESP": [ { "physical_name": "s_axi_rresp" } ], - "RVALID": [ { "physical_name": "s_axi_rvalid" } ], - "WDATA": [ { "physical_name": "s_axi_wdata" } ], - "WREADY": [ { "physical_name": "s_axi_wready" } ], - "WSTRB": [ { "physical_name": "s_axi_wstrb" } ], - "WVALID": [ { "physical_name": "s_axi_wvalid" } ] - } - }, - "ACLK": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "slave", - "parameters": { - "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK": [ { "physical_name": "s_axi_aclk" } ] - } - }, - "ARESETN": { - "vlnv": "xilinx.com:signal:reset:1.0", - "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", - "mode": "slave", - "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "RST": [ { "physical_name": "s_axi_aresetn" } ] - } - }, - "INTERRUPT": { - "vlnv": "xilinx.com:signal:interrupt:1.0", - "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", - "mode": "master", - "parameters": { - "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "INTERRUPT": [ { "physical_name": "interrupt" } ] - } - }, - "UART": { - "vlnv": "xilinx.com:interface:uart:1.0", - "abstraction_type": "xilinx.com:interface:uart_rtl:1.0", - "mode": "master", - "parameters": { - "BOARD.ASSOCIATED_PARAM": [ { "value": "UARTLITE_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ] - }, - "port_maps": { - "RxD": [ { "physical_name": "rx" } ], - "TxD": [ { "physical_name": "tx" } ] - } - } - }, - "memory_maps": { - "S_AXI": { - "display_name": "S_AXI_MEM", - "description": "Memory Map for S_AXI", - "address_blocks": { - "Reg": { - "base_address": "0", - "range": "4096", - "display_name": "Reg", - "description": "Register Block", - "usage": "register", - "access": "read-write", - "registers": { - "RX_FIFO": { - "address_offset": "0x0", - "size": 32, - "display_name": "RX FIFO", - "description": "Receive data FIFO", - "is_volatile": true, - "access": "read-only", - "reset_value": "0x0", - "fields": { - "RX_DATA": { - "bit_offset": 0, - "bit_width": 8, - "display_name": "Receive Data", - "description": "UART Receive Data\n", - "is_volatile": true, - "access": "read-only" - } - } - }, - "TX_FIFO": { - "address_offset": "0x4", - "size": 32, - "display_name": "TX FIFO", - "description": "Transmit data FIFO", - "is_volatile": true, - "access": "write-only", - "reset_value": "0x0", - "fields": { - "TX_DATA": { - "bit_offset": 0, - "bit_width": 8, - "display_name": "Transmit Data", - "description": "UART Transmit Data\n", - "is_volatile": true, - "access": "write-only" - } - } - }, - "CTRL_REG": { - "address_offset": "0xC", - "size": 32, - "display_name": "Control Register", - "description": "UART Lite control register", - "is_volatile": true, - "access": "write-only", - "reset_value": "0x0", - "fields": { - "RST_TXFIFO": { - "bit_offset": 0, - "bit_width": 1, - "display_name": "Reset Tx FIFO", - "description": "Reset/clear the transmit FIFO\nWriting a 1 to this bit position clears the transmit FIFO\n 0 - Do nothing\n 1 - Clear the transmit FIFO\n", - "is_volatile": true, - "access": "write-only" - }, - "RST_RXFIFO": { - "bit_offset": 1, - "bit_width": 1, - "display_name": "Reset Rx FIFO", - "description": "Reset/clear the receive FIFO\nWriting a 1 to this bit position clears the receive FIFO\n 0 - Do nothing\n 1 - Clear the receive FIFO\n", - "is_volatile": true, - "access": "write-only" - }, - "Enable_Intr": { - "bit_offset": 4, - "bit_width": 1, - "display_name": "Enable interrupt", - "description": "Enable interrupt for the AXI UART Lite\n 0 - Disable interrupt signal\n 1 - Enable interrupt signal\n", - "is_volatile": true, - "access": "write-only" - } - } - }, - "STAT_REG": { - "address_offset": "0x8", - "size": 32, - "display_name": "Status Register", - "description": "UART Lite status register", - "is_volatile": true, - "access": "read-only", - "reset_value": "0x0", - "fields": { - "RX_FIFO_Valid_Data": { - "bit_offset": 0, - "bit_width": 1, - "display_name": "RX FIFO Valid Data", - "description": "Indicates if the receive FIFO has data.\n 0 - Receive FIFO is empty\n 1 - Receive FIFO has data\n", - "is_volatile": true, - "access": "read-only" - }, - "RX_FIFO_Full": { - "bit_offset": 1, - "bit_width": 1, - "display_name": "RX FIFO Full", - "description": "Indicates if the receive FIFO is full.\n 0 - Receive FIFO is not full\n 1 - Receive FIFO is full\n", - "is_volatile": true, - "access": "read-only" - }, - "TX_FIFO_Empty": { - "bit_offset": 2, - "bit_width": 1, - "display_name": "TX FIFO Empty", - "description": "Indicates if the transmit FIFO is empty.\n 0 - Transmit FIFO is not empty\n 1 - Transmit FIFO is empty\n", - "is_volatile": true, - "access": "read-only" - }, - "TX_FIFO_Full": { - "bit_offset": 3, - "bit_width": 1, - "display_name": "TX FIFO Full", - "description": "Indicates if the transmit FIFO is full.\n 0 - Transmit FIFO is not full\n 1 - Transmit FIFO is full\n", - "is_volatile": true, - "access": "read-only" - }, - "Intr_Enabled": { - "bit_offset": 4, - "bit_width": 1, - "display_name": "Interrupt Enabled", - "description": "Indicates that interrupts is enabled.\n 0 - Interrupt is disabled\n 1 - Interrupt is enabled\n", - "is_volatile": true, - "access": "read-only" - }, - "Overrun_Error": { - "bit_offset": 5, - "bit_width": 1, - "display_name": "Overrun Error", - "description": "Indicates that a overrun error has occurred after the last time the status register was read. Overrun is when a new character has been received but the receive FIFO is full. The received character is ignored and not written into the receive FIFO. This bit is cleared when the status register is read. 0 - No overrun error has occurred 1 - Overrun error has occurred\n", - "is_volatile": true, - "access": "read-only" - }, - "Frame_Error": { - "bit_offset": 6, - "bit_width": 1, - "display_name": "Frame Error", - "description": "Indicates that a frame error has occurred after the last time the status register was read. Frame error is defined as detection of a stop bit with the value 0. The receive character is ignored and not written to the receive FIFO. This bit is cleared when the status register is read. 0 - No frame error has occurred 1 - Frame error has occurred\n", - "is_volatile": true, - "access": "read-only" - }, - "Parity_Error": { - "bit_offset": 7, - "bit_width": 1, - "display_name": "Parity Error", - "description": "Indicates that a parity error has occurred after the last time the status register was read. If the UART is configured without any parity handling, this bit is always 0. The received character is written into the receive FIFO. This bit is cleared when the status register is read. 0 - No parity error has occurred 1 - Parity error has occurred\n", - "is_volatile": true, - "access": "read-only" - } - } - } - } - } - } - } - } - } - } -} \ No newline at end of file diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xci index 78a32bf..69f13f2 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xci @@ -33,7 +33,7 @@ "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], - "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "100", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], "PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ], @@ -49,7 +49,7 @@ "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "100.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -157,11 +157,11 @@ "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], - "MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], @@ -246,8 +246,8 @@ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_JITTER": [ { "value": "106.024", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_PHASE_ERROR": [ { "value": "82.655", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "115.831", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_PHASE_ERROR": [ { "value": "87.180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -308,7 +308,7 @@ "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ], "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRIM_IN_FREQ": [ { "value": "100", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ], "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -335,11 +335,11 @@ "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ], - "C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ], + "C_INCLK_SUM_ROW1": [ { "value": "__primary_____________100____________0.010", "resolve_type": "generated", "usage": "all" } ], "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__100.00000______0.000______50.0______106.024_____82.655", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__100.00000______0.000______50.0______115.831_____87.180", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], @@ -399,9 +399,9 @@ "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "C_MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ], @@ -503,7 +503,7 @@ "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ], "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ], "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ], - "C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ], @@ -584,11 +584,11 @@ "C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -624,7 +624,7 @@ "parameters": { "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "200000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + "FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "CLK_N": [ { "physical_name": "clk_in1_n" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci index 32e7fab..cddef1b 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci @@ -35,7 +35,7 @@ "Component_Name": [ { "value": "design_1_dlmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_HIGHADDR": [ { "value": "0x0000000000007FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -61,11 +61,11 @@ "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci index f355f78..69115f2 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci @@ -23,11 +23,11 @@ "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci index fdfa854..06dba39 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci @@ -35,7 +35,7 @@ "Component_Name": [ { "value": "design_1_ilmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_HIGHADDR": [ { "value": "0x0000000000007FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -61,11 +61,11 @@ "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci index 43d670c..5fc20ac 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci @@ -23,11 +23,11 @@ "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci index 55b087c..c447fdf 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci @@ -82,8 +82,8 @@ "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], - "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], + "C_XDEVICEFAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ], "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -159,11 +159,11 @@ "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 17.246228 mW", "resolve_type": "generated", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci index 95889e3..a69b0a2 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci @@ -19,17 +19,17 @@ "C_INTERCONNECT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], - "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], - "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "C_ADDR_SIZE": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_ADDR_SIZE": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_M_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_M_AXIS_ID_WIDTH": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "C_USE_UART": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_USE_UART": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -46,8 +46,8 @@ "Component_Name": [ { "value": "design_1_mdm_1_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], - "C_DEVICE": [ { "value": "xczu7ev", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], + "C_DEVICE": [ { "value": "xcku15p", "resolve_type": "generated", "usage": "all" } ], "C_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], "C_JTAG_CHAIN": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_BSCAN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -55,9 +55,9 @@ "C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_INTERCONNECT": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "C_INTERCONNECT": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_UART": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_UART": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -69,9 +69,9 @@ "C_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "C_TRACE_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "C_TRACE_ID": [ { "value": "110", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], @@ -82,11 +82,11 @@ "C_M_AXIS_ID_WIDTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -109,7 +109,27 @@ }, "boundary": { "ports": { + "S_AXI_ACLK": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_ARESETN": [ { "direction": "in", "driver_value": "0" } ], + "Interrupt": [ { "direction": "out" } ], "Debug_SYS_Rst": [ { "direction": "out" } ], + "S_AXI_AWADDR": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "S_AXI_AWVALID": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_AWREADY": [ { "direction": "out" } ], + "S_AXI_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "S_AXI_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "S_AXI_WVALID": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_WREADY": [ { "direction": "out" } ], + "S_AXI_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "S_AXI_BVALID": [ { "direction": "out" } ], + "S_AXI_BREADY": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_ARADDR": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "S_AXI_ARVALID": [ { "direction": "in", "driver_value": "0" } ], + "S_AXI_ARREADY": [ { "direction": "out" } ], + "S_AXI_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "S_AXI_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "S_AXI_RVALID": [ { "direction": "out" } ], + "S_AXI_RREADY": [ { "direction": "in", "driver_value": "0" } ], "Dbg_Clk_0": [ { "direction": "out" } ], "Dbg_TDI_0": [ { "direction": "out" } ], "Dbg_TDO_0": [ { "direction": "in", "driver_value": "0" } ], @@ -121,6 +141,94 @@ "Dbg_Disable_0": [ { "direction": "out" } ] }, "interfaces": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "memory_map_ref": "S_AXI", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "ARADDR": [ { "physical_name": "S_AXI_ARADDR" } ], + "ARREADY": [ { "physical_name": "S_AXI_ARREADY" } ], + "ARVALID": [ { "physical_name": "S_AXI_ARVALID" } ], + "AWADDR": [ { "physical_name": "S_AXI_AWADDR" } ], + "AWREADY": [ { "physical_name": "S_AXI_AWREADY" } ], + "AWVALID": [ { "physical_name": "S_AXI_AWVALID" } ], + "BREADY": [ { "physical_name": "S_AXI_BREADY" } ], + "BRESP": [ { "physical_name": "S_AXI_BRESP" } ], + "BVALID": [ { "physical_name": "S_AXI_BVALID" } ], + "RDATA": [ { "physical_name": "S_AXI_RDATA" } ], + "RREADY": [ { "physical_name": "S_AXI_RREADY" } ], + "RRESP": [ { "physical_name": "S_AXI_RRESP" } ], + "RVALID": [ { "physical_name": "S_AXI_RVALID" } ], + "WDATA": [ { "physical_name": "S_AXI_WDATA" } ], + "WREADY": [ { "physical_name": "S_AXI_WREADY" } ], + "WSTRB": [ { "physical_name": "S_AXI_WSTRB" } ], + "WVALID": [ { "physical_name": "S_AXI_WVALID" } ] + } + }, + "CLK.S_AXI_ACLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXI:MBDEBUG_AXI_0:MBDEBUG_AXI_1:MBDEBUG_AXI_2:MBDEBUG_AXI_3:MBDEBUG_AXI_4:MBDEBUG_AXI_5:MBDEBUG_AXI_6:MBDEBUG_AXI_7:MBDEBUG_AXI_8:MBDEBUG_AXI_9:MBDEBUG_AXI_10:MBDEBUG_AXI_11:MBDEBUG_AXI_12:MBDEBUG_AXI_13:MBDEBUG_AXI_14:MBDEBUG_AXI_15:MBDEBUG_AXI_16:MBDEBUG_AXI_17:MBDEBUG_AXI_18:MBDEBUG_AXI_19:MBDEBUG_AXI_20:MBDEBUG_AXI_21:MBDEBUG_AXI_22:MBDEBUG_AXI_23:MBDEBUG_AXI_24:MBDEBUG_AXI_25:MBDEBUG_AXI_26:MBDEBUG_AXI_27:MBDEBUG_AXI_28:MBDEBUG_AXI_29:MBDEBUG_AXI_30:MBDEBUG_AXI_31", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_clk_wiz_1_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "S_AXI_ACLK" } ] + } + }, + "RST.S_AXI_ARESETN": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "S_AXI_ARESETN" } ] + } + }, "RST.Debug_SYS_Rst": { "vlnv": "xilinx.com:signal:reset:1.0", "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", @@ -148,6 +256,19 @@ "TDO": [ { "physical_name": "Dbg_TDO_0" } ], "UPDATE": [ { "physical_name": "Dbg_Update_0" } ] } + }, + "INTERRUPT.INTERRUPT": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "SUGGESTED_PRIORITY": [ { "value": "HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "PortWidth": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ] + }, + "port_maps": { + "INTERRUPT": [ { "physical_name": "Interrupt" } ] + } } }, "memory_maps": { @@ -160,7 +281,141 @@ "display_name": "Reg", "description": "Register Block", "usage": "register", - "access": "read-write" + "access": "read-write", + "registers": { + "UART_Receive": { + "address_offset": "0x0", + "size": 8, + "display_name": "JTAG UART Receive Data", + "description": "JTAG UART Receive Data", + "is_volatile": true, + "access": "read-only", + "reset_value": "0", + "fields": { + "UART_RX": { + "bit_offset": 0, + "bit_width": 8, + "display_name": "UART_RX", + "description": "UART Receive Data.", + "is_volatile": true, + "access": "read-only" + } + } + }, + "UART_Transmit": { + "address_offset": "0x4", + "size": 8, + "display_name": "JTAG UART Transmit Data", + "description": "JTAG UART Transmit Data", + "is_volatile": true, + "access": "write-only", + "reset_value": "0", + "fields": { + "UART_TX": { + "bit_offset": 0, + "bit_width": 8, + "display_name": "UART_TX", + "description": "UART Transmit Data.", + "is_volatile": true, + "access": "write-only" + } + } + }, + "UART_Status": { + "address_offset": "0x8", + "size": 5, + "display_name": "JTAG UART Status Register", + "description": "JTAG UART Status Register", + "is_volatile": true, + "access": "read-only", + "reset_value": "0x0", + "fields": { + "RX_FIFO_Valid_Data": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "RX FIFO Valid Data", + "description": "Indicates if the receive FIFO has valid data:\n 0 - Receive FIFO is empty.\n 1 - Receive FIFO has valid data.\n", + "is_volatile": true, + "access": "read-only" + }, + "RX_FIFO_Full": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "RX FIFO Full", + "description": "Indicates if the receive FIFO is full:\n 0 - Receive FIFO is not full.\n 1 - Receive FIFO is full.\n", + "is_volatile": true, + "access": "read-only" + }, + "TX_FIFO_Empty": { + "bit_offset": 2, + "bit_width": 1, + "display_name": "TX FIFO Empty", + "description": "Indicates if the transmit FIFO is empty:\n 0 - Transmit FIFO is not empty.\n 1 - Transmit FIFO is empty.\n", + "is_volatile": true, + "access": "read-only" + }, + "TX_FIFO_Full": { + "bit_offset": 3, + "bit_width": 1, + "display_name": "TX FIFO Full", + "description": "Indicates if the transmit FIFO is full:\n 0 - Transmit FIFO is not full.\n 1 - Transmit FIFO is full.\n", + "is_volatile": true, + "access": "read-only" + }, + "Interrupt_Enabled": { + "bit_offset": 4, + "bit_width": 1, + "display_name": "Interrupt Enabled", + "description": "Indicates that interrupt is enabled:\n 0 - Interrupt is disabled.\n 1 - Interrupt is enabled.\n", + "is_volatile": true, + "access": "read-only" + } + } + }, + "UART_Control": { + "address_offset": "0xC", + "size": 5, + "display_name": "JTAG UART Control Register", + "description": "JTAG UART Control Register", + "is_volatile": true, + "access": "write-only", + "reset_value": "0x0", + "fields": { + "Reset_TX_FIFO": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Reset TX FIFO", + "description": "Reset/clear the transmit FIFO:\n 0 - Do nothing.\n 1 - Clear the transmit FIFO.\n", + "is_volatile": true, + "access": "write-only" + }, + "Reset_RX_FIFO": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "Reset RX FIFO", + "description": "Reset/clear the receive FIFO:\n 0 - Do nothing.\n 1 - Clear the receive FIFO.\n", + "is_volatile": true, + "access": "write-only" + }, + "Clear_EXT_BRK": { + "bit_offset": 2, + "bit_width": 1, + "display_name": "Clear EXT_BRK", + "description": "Clear the EXT_BRK signal set by JTAG:\n 0 - Do nothing.\n 1 - Clear the signal.\n", + "is_volatile": true, + "access": "write-only" + }, + "Interrupt_Enabled": { + "bit_offset": 4, + "bit_width": 1, + "display_name": "Interrupt Enabled", + "description": "Indicates interrupt for the MDM JTAG UART:\n 0 - Disable interrupt interrupt.\n 1 - Enable interrupt signal.\n", + "is_volatile": true, + "access": "write-only" + } + } + } + } } } } diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci index 3943322..cdceca1 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci @@ -237,7 +237,7 @@ "C_LOCKSTEP_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_TEMPORAL_DEPTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ENDIANNESS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_LMB_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INSTR_SIZE": [ { "value": "32", "format": "long", "usage": "all" } ], @@ -394,11 +394,11 @@ "C_M_AXI_DC_BUSER_WIDTH": [ { "value": "1", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci index b5f7d51..a17203b 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci @@ -18,7 +18,7 @@ "C_NUM_INTR_INPUTS": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_NUM_SW_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_KIND_OF_LVL": [ { "value": "0xFFFFFFFF", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "C_ASYNC_INTR": [ { "value": "0xFFFFFFF8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_ASYNC_INTR": [ { "value": "0xFFFFFFF9", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "C_NUM_SYNC_FF": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_IRQ_IS_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_KIND_OF_EDGE": [ { "value": "0xFFFFFFFF", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -38,7 +38,7 @@ "C_IRQ_CONNECTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_INSTANCE": [ { "value": "design_1_microblaze_0_axi_intc_0", "resolve_type": "generated", "usage": "all" } ], "C_S_AXI_ADDR_WIDTH": [ { "value": "9", "resolve_type": "dependent", "format": "long", "usage": "all" } ], "C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ], @@ -47,7 +47,7 @@ "C_KIND_OF_INTR": [ { "value": "0xfffffff9", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_KIND_OF_EDGE": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_KIND_OF_LVL": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_ASYNC_INTR": [ { "value": "0xFFFFFFF8", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_ASYNC_INTR": [ { "value": "0xFFFFFFF9", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_NUM_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_IVAR_RESET_VALUE": [ { "value": "0x0000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], @@ -66,11 +66,11 @@ "C_CASCADE_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -258,7 +258,7 @@ "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", "mode": "slave", "parameters": { - "SENSITIVITY": [ { "value": "LEVEL_HIGH:LEVEL_HIGH:EDGE_RISING", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "SENSITIVITY": [ { "value": "LEVEL_HIGH:LEVEL_HIGH:NULL", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "PortWidth": [ { "value": "3", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci index e09d4ce..0c9dc67 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci @@ -9,7 +9,7 @@ "parameters": { "component_parameters": { "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "NUM_MI": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_MI": [ { "value": "9", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -325,11 +325,11 @@ "Component_Name": [ { "value": "design_1_microblaze_0_axi_periph_0", "resolve_type": "user", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci index 3f2de03..a8c93c9 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci @@ -138,7 +138,7 @@ "IN125_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "IN126_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "IN127_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "dout_width": [ { "value": "3", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ] + "dout_width": [ { "value": "3", "value_src": "user", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ] }, "model_parameters": { "IN0_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -273,11 +273,11 @@ "NUM_PORTS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xci index 6271ccd..9613e71 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xci @@ -21,7 +21,7 @@ "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -32,11 +32,11 @@ "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci index d011591..8f6cdaa 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_s00_data_fifo_0/design_1_s00_data_fifo_0.xci @@ -11,7 +11,7 @@ "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -25,11 +25,11 @@ "Component_Name": [ { "value": "design_1_s00_data_fifo_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -44,11 +44,11 @@ "C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -84,8 +84,8 @@ "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ], "s_axi_awready": [ { "direction": "out" } ], - "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ], - "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ], "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ], "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ], "s_axi_wready": [ { "direction": "out" } ], @@ -103,8 +103,8 @@ "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "m_axi_awvalid": [ { "direction": "out" } ], "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ], - "m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ], - "m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "m_axi_wlast": [ { "direction": "out" } ], "m_axi_wvalid": [ { "direction": "out" } ], "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ], @@ -118,30 +118,30 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "slave", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -177,22 +177,22 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "master", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -200,7 +200,7 @@ "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci index 8c1cbd0..f8fc235 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_s01_data_fifo_0/design_1_s01_data_fifo_0.xci @@ -11,7 +11,7 @@ "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -25,11 +25,11 @@ "Component_Name": [ { "value": "design_1_s01_data_fifo_0", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -44,11 +44,11 @@ "C_AXI_READ_FIFO_DELAY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -84,8 +84,8 @@ "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ], "s_axi_awready": [ { "direction": "out" } ], - "s_axi_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ], - "s_axi_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0xFFFFFFFF" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ], "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ], "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ], "s_axi_wready": [ { "direction": "out" } ], @@ -103,8 +103,8 @@ "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "m_axi_awvalid": [ { "direction": "out" } ], "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ], - "m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ], - "m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "m_axi_wlast": [ { "direction": "out" } ], "m_axi_wvalid": [ { "direction": "out" } ], "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ], @@ -118,30 +118,30 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "slave", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -177,22 +177,22 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "master", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -200,7 +200,7 @@ "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0/design_1_s02_data_fifo_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0/design_1_s02_data_fifo_0.xci new file mode 100644 index 0000000..9bd5b7e --- /dev/null +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0/design_1_s02_data_fifo_0.xci @@ -0,0 +1,268 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "design_1_s02_data_fifo_0", + "cell_name": "axi_interconnect_1/s02_couplers/s02_data_fifo", + "component_reference": "xilinx.com:ip:axi_data_fifo:2.1", + "ip_revision": "26", + "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_s02_data_fifo_0", + "parameters": { + "component_parameters": { + "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WRITE_FIFO_DEPTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ], + "READ_FIFO_DEPTH": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WRITE_FIFO_DELAY": [ { "value": "0", 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"value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], + "AWLEN": [ { "physical_name": "s_axi_awlen" } ], + "AWSIZE": [ { "physical_name": "s_axi_awsize" } ], + "AWBURST": [ { "physical_name": "s_axi_awburst" } ], + "AWLOCK": [ { "physical_name": "s_axi_awlock" } ], + "AWCACHE": [ { "physical_name": "s_axi_awcache" } ], + "AWPROT": [ { "physical_name": "s_axi_awprot" } ], + "AWREGION": [ { "physical_name": "s_axi_awregion" } ], + "AWQOS": [ { "physical_name": "s_axi_awqos" } ], + "AWVALID": [ { "physical_name": "s_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "s_axi_awready" } ], + "WDATA": [ { "physical_name": "s_axi_wdata" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb" } ], + "WLAST": [ { "physical_name": "s_axi_wlast" } ], + "WVALID": [ { "physical_name": "s_axi_wvalid" } ], + "WREADY": [ { "physical_name": "s_axi_wready" } ], + "BRESP": [ { "physical_name": "s_axi_bresp" } ], + "BVALID": [ { "physical_name": "s_axi_bvalid" } ], + "BREADY": [ { "physical_name": "s_axi_bready" } ] + } + }, + "M_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "parameters": { + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWLEN": [ { "physical_name": "m_axi_awlen" } ], + "AWSIZE": [ { "physical_name": "m_axi_awsize" } ], + "AWBURST": [ { "physical_name": "m_axi_awburst" } ], + "AWLOCK": [ { "physical_name": "m_axi_awlock" } ], + "AWCACHE": [ { "physical_name": "m_axi_awcache" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWREGION": [ { "physical_name": "m_axi_awregion" } ], + "AWQOS": [ { "physical_name": "m_axi_awqos" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WLAST": [ { "physical_name": "m_axi_wlast" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ] + } + }, + "CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci index b8b236d..dd90871 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_management_wiz_0_0/design_1_system_management_wiz_0_0.xci @@ -9,7 +9,7 @@ "parameters": { "component_parameters": { "Component_Name": [ { "value": "design_1_system_management_wiz_0_0", "resolve_type": "user", "usage": "all" } ], - "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "VAUX0_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], "VAUX1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], @@ -134,7 +134,7 @@ "SEQUENCER_MODE": [ { "value": "Continuous", "resolve_type": "user", "usage": "all" } ], "ENABLE_CALIBRATION_AVERAGING": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ENABLE_DRP": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_RESET": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "ENABLE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "ENABLE_CONVST": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ], "ENABLE_CONVSTCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ENABLE_CHANNEL": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -169,9 +169,9 @@ "VBRAM_ALARM_LOWER": [ { "value": "0.86", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "VBRAM_ALARM_UPPER": [ { "value": "0.92", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "ENABLE_VCCPINT_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_VCCPSINTLP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_VCCPSAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_VCCPSINTFP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_VCCPSINTLP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "ENABLE_VCCPSAUX_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "ENABLE_VCCPSINTFP_ALARM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "ENABLE_VCCPAUX_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ENABLE_VCCDDRO_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "VCCDDRO_VOLT": [ { "value": "1_2", "resolve_type": "user", "usage": "all" } ], @@ -205,14 +205,14 @@ "DUAL_SEQ_TEMPERATURE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "CHANNEL_ENABLE_VCCINT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "DUAL_SEQ_VCCINT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "CHANNEL_ENABLE_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CHANNEL_ENABLE_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AVERAGE_ENABLE_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "DUAL_SEQ_VCCPSINTLP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "CHANNEL_ENABLE_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CHANNEL_ENABLE_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AVERAGE_ENABLE_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "DUAL_SEQ_VCCPSINTFP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AVERAGE_ENABLE_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "CHANNEL_ENABLE_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CHANNEL_ENABLE_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "DUAL_SEQ_VCCPSAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "CHANNEL_ENABLE_VCCAUX": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "DUAL_SEQ_VCCAUX": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], @@ -470,41 +470,41 @@ "SELECT_USER_SUPPLY1_SLAVE2_SSIT_LEVEL": [ { "value": "0.9", "resolve_type": "user", "enabled": false, "usage": "all" } ], "SELECT_USER_SUPPLY2_SLAVE2_SSIT_LEVEL": [ { "value": "1.8", "resolve_type": "user", "enabled": false, "usage": "all" } ], "SELECT_USER_SUPPLY3_SLAVE2_SSIT_LEVEL": [ { "value": "1.8", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "ANALOG_BANK_SELECTION": [ { "value": "28", "resolve_type": "user", "format": "long", "usage": "all" } ], - "VAUXN0_LOC": [ { "value": "B19", "resolve_type": "user", "usage": "all" } ], - "VAUXP0_LOC": [ { "value": "B18", "resolve_type": "user", "usage": "all" } ], - "VAUXN1_LOC": [ { "value": "C19", "resolve_type": "user", "usage": "all" } ], - "VAUXP1_LOC": [ { "value": "C18", "resolve_type": "user", "usage": "all" } ], - "VAUXN2_LOC": [ { "value": "G26", "resolve_type": "user", "usage": "all" } ], - "VAUXP2_LOC": [ { "value": "G25", "resolve_type": "user", "usage": "all" } ], - "VAUXN3_LOC": [ { "value": "D24", "resolve_type": "user", "usage": "all" } ], - "VAUXP3_LOC": [ { "value": "E24", "resolve_type": "user", "usage": "all" } ], - "VAUXN4_LOC": [ { "value": "F20", "resolve_type": "user", "usage": "all" } ], - "VAUXP4_LOC": [ { "value": "G20", "resolve_type": "user", "usage": "all" } ], - "VAUXN5_LOC": [ { "value": "H22", "resolve_type": "user", "usage": "all" } ], - "VAUXP5_LOC": [ { "value": "H21", "resolve_type": "user", "usage": "all" } ], - "VAUXN6_LOC": [ { "value": "H24", "resolve_type": "user", "usage": "all" } ], - "VAUXP6_LOC": [ { "value": "J24", "resolve_type": "user", "usage": "all" } ], - "VAUXN7_LOC": [ { "value": "K23", "resolve_type": "user", "usage": "all" } ], - "VAUXP7_LOC": [ { "value": "K22", "resolve_type": "user", "usage": "all" } ], - "VAUXN8_LOC": [ { "value": "A21", "resolve_type": "user", "usage": "all" } ], - "VAUXP8_LOC": [ { "value": "A20", "resolve_type": "user", "usage": "all" } ], - "VAUXN9_LOC": [ { "value": "A19", "resolve_type": "user", "usage": "all" } ], - "VAUXP9_LOC": [ { "value": "A18", "resolve_type": "user", "usage": "all" } ], - "VAUXN10_LOC": [ { "value": "C23", "resolve_type": "user", "usage": "all" } ], - "VAUXP10_LOC": [ { "value": "D22", "resolve_type": "user", "usage": "all" } ], - "VAUXN11_LOC": [ { "value": "C22", "resolve_type": "user", "usage": "all" } ], - "VAUXP11_LOC": [ { "value": "C21", "resolve_type": "user", "usage": "all" } ], - "VAUXN12_LOC": [ { "value": "D21", "resolve_type": "user", "usage": "all" } ], - "VAUXP12_LOC": [ { "value": "D20", "resolve_type": "user", "usage": "all" } ], - "VAUXN13_LOC": [ { "value": "D19", "resolve_type": "user", "usage": "all" } ], - "VAUXP13_LOC": [ { "value": "E19", "resolve_type": "user", "usage": "all" } ], - "VAUXN14_LOC": [ { "value": "H26", "resolve_type": "user", "usage": "all" } ], - "VAUXP14_LOC": [ { "value": "J25", "resolve_type": "user", "usage": "all" } ], - "VAUXN15_LOC": [ { "value": "J22", "resolve_type": "user", "usage": "all" } ], - "VAUXP15_LOC": [ { "value": "J21", "resolve_type": "user", "usage": "all" } ], - "I2C_SCLK_LOC": [ { "value": "AC18", "resolve_type": "user", "usage": "all" } ], - "I2C_SDA_LOC": [ { "value": "AA19", "resolve_type": "user", "usage": "all" } ], + "ANALOG_BANK_SELECTION": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "VAUXN0_LOC": [ { "value": "B19", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP0_LOC": [ { "value": "B18", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN1_LOC": [ { "value": "C19", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP1_LOC": [ { "value": "C18", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN2_LOC": [ { "value": "G26", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP2_LOC": [ { "value": "G25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN3_LOC": [ { "value": "D24", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP3_LOC": [ { "value": "E24", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN4_LOC": [ { "value": "F20", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP4_LOC": [ { "value": "G20", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN5_LOC": [ { "value": "H22", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP5_LOC": [ { "value": "H21", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN6_LOC": [ { "value": "H24", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP6_LOC": [ { "value": "J24", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN7_LOC": [ { "value": "K23", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP7_LOC": [ { "value": "K22", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN8_LOC": [ { "value": "A21", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP8_LOC": [ { "value": "A20", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN9_LOC": [ { "value": "A19", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP9_LOC": [ { "value": "A18", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN10_LOC": [ { "value": "C23", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP10_LOC": [ { "value": "D22", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN11_LOC": [ { "value": "C22", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP11_LOC": [ { "value": "C21", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN12_LOC": [ { "value": "D21", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP12_LOC": [ { "value": "D20", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN13_LOC": [ { "value": "D19", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP13_LOC": [ { "value": "E19", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN14_LOC": [ { "value": "H26", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP14_LOC": [ { "value": "J25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXN15_LOC": [ { "value": "J22", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "VAUXP15_LOC": [ { "value": "J21", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "I2C_SCLK_LOC": [ { "value": "AC18", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "I2C_SDA_LOC": [ { "value": "AA19", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "EXTERNAL_MUXADDR_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "REFERENCE": [ { "value": "Internal", "resolve_type": "user", "usage": "all" } ], "UNDER_OT_ALARM": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], @@ -571,7 +571,7 @@ "COMMON_N_SOURCE": [ { "value": "Vaux0", "resolve_type": "user", "enabled": false, "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_IS_DIABLO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DUAL0_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_DUAL1_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -585,7 +585,7 @@ "C_ENABLE_DUAL_SEQUENCE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "c_component_name": [ { "value": "design_1_system_management_wiz_0_0", "resolve_type": "generated", "usage": "all" } ], "C_SIM_FILE_SEL": [ { "value": "Default", "resolve_type": "generated", "usage": "all" } ], - "C_SIM_DEVICE": [ { "value": "ZYNQ_ULTRASCALE", "resolve_type": "generated", "usage": "all" } ], + "C_SIM_DEVICE": [ { "value": "ULTRASCALE_PLUS", "resolve_type": "generated", "usage": "all" } ], "C_SIM_FILE_REL_PATH": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ], "C_SIM_FILE_NAME": [ { "value": "design", "resolve_type": "generated", "usage": "all" } ], "C_HAS_DCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -892,11 +892,11 @@ "C_I2C_SDA_LOC": [ { "value": "AA19", "resolve_type": "generated", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci index e6dbae7..7dae403 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci @@ -30,11 +30,11 @@ "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_3/design_1_xbar_3.xci similarity index 99% rename from project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci rename to project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_3/design_1_xbar_3.xci index bf246d3..1e4bc1b 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_3/design_1_xbar_3.xci @@ -1,14 +1,14 @@ { "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { - "xci_name": "design_1_xbar_0", + "xci_name": "design_1_xbar_3", "cell_name": "axi_interconnect_0/xbar", "component_reference": "xilinx.com:ip:axi_crossbar:2.1", "ip_revision": "28", - "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_0", + "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_3", "parameters": { "component_parameters": { - "ADDR_RANGES": [ { "value": "5", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ADDR_RANGES": [ { "value": "3", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_MI": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -761,9 +761,9 @@ "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A00_BASE_ADDR": [ { "value": "0x0000000080000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A01_BASE_ADDR": [ { "value": "0x0000000080100000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M04_A02_BASE_ADDR": [ { "value": "0x0000000080120000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M04_A03_BASE_ADDR": [ { "value": "0x0000000081000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M04_A04_BASE_ADDR": [ { "value": "0x0000000083000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A02_BASE_ADDR": [ { "value": "0x0000000083000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A04_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A05_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A06_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A07_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -983,7 +983,7 @@ "M01_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M01_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M01_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M02_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M02_A00_ADDR_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1015,11 +1015,11 @@ "M03_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_A01_ADDR_WIDTH": [ { "value": "17", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_A02_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_A03_ADDR_WIDTH": [ { "value": "17", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_A04_ADDR_WIDTH": [ { "value": "24", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_A00_ADDR_WIDTH": [ { "value": "18", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_A01_ADDR_WIDTH": [ { "value": "18", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_A02_ADDR_WIDTH": [ { "value": "24", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_A03_ADDR_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_A04_ADDR_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_A05_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_A06_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_A07_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1207,19 +1207,19 @@ "M15_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Component_Name": [ { "value": "design_1_xbar_0", "resolve_type": "user", "usage": "all" } ] + "Component_Name": [ { "value": "design_1_xbar_3", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_NUM_SLAVE_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_NUM_MASTER_SLOTS": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_NUM_ADDR_RANGES": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_M_AXI_BASE_ADDR": [ { "value": "0x00000000830000000000000081000000000000008012000000000000801000000000000080000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040030000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040010000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000018000000110000001000000011000000100000000000000000000000000000000000000010000000000000000000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_NUM_ADDR_RANGES": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_M_AXI_BASE_ADDR": [ { "value": "0x000000008300000000000000801000000000000080000000ffffffffffffffffffffffffffffffff0000000040030000ffffffffffffffffffffffffffffffff0000000040010000ffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffff0000000040020000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000018000000120000001200000000000000000000001000000000000000000000000c000000000000000000000010000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_BASE_ID": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -1241,11 +1241,11 @@ "C_CONNECTIVITY_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -1259,9 +1259,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "28" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_0" } ], + "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_3" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] } diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_2/design_1_xbar_2.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_4/design_1_xbar_4.xci similarity index 86% rename from project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_2/design_1_xbar_2.xci rename to project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_4/design_1_xbar_4.xci index 1bf2a66..d0b495d 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_2/design_1_xbar_2.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_4/design_1_xbar_4.xci @@ -1,22 +1,22 @@ { "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { - "xci_name": "design_1_xbar_2", + "xci_name": "design_1_xbar_4", "cell_name": "axi_interconnect_1/xbar", "component_reference": "xilinx.com:ip:axi_crossbar:2.1", "ip_revision": "28", - "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_2", + "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_4", "parameters": { "component_parameters": { "ADDR_RANGES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_SI": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "STRATEGY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "CONNECTIVITY_MODE": [ { "value": "SAMD", "resolve_type": "user", "usage": "all" } ], - "ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -25,8 +25,8 @@ "R_REGISTER": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "M00_S00_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S01_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M00_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M00_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_S02_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_S03_READ_CONNECTIVITY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S04_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S05_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S06_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -281,8 +281,8 @@ "M15_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M00_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M00_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S04_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S05_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_S06_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -537,8 +537,8 @@ "M15_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S00_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], "S01_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S02_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S03_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], "S04_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], "S05_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], "S06_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -553,8 +553,8 @@ "S15_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], "S00_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S01_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S02_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S03_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_WRITE_ACCEPTANCE": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S04_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S05_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S06_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -569,8 +569,8 @@ "S15_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S00_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S01_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S02_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S03_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_READ_ACCEPTANCE": [ { "value": "2", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S04_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S05_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S06_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1207,45 +1207,45 @@ "M15_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Component_Name": [ { "value": "design_1_xbar_2", "resolve_type": "user", "usage": "all" } ] + "Component_Name": [ { "value": "design_1_xbar_4", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], - "C_NUM_SLAVE_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], + "C_NUM_SLAVE_SLOTS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_NUM_MASTER_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_NUM_ADDR_RANGES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_M_AXI_BASE_ADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000028", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_S_AXI_BASE_ID": [ { "value": "0x0000000100000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_S_AXI_BASE_ID": [ { "value": "0x00000003000000020000000100000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x00000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x00000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x0000000f", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_M_AXI_READ_CONNECTIVITY": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_R_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_S_AXI_SINGLE_THREAD": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_S_AXI_WRITE_ACCEPTANCE": [ { "value": "0x0000000800000008", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_S_AXI_READ_ACCEPTANCE": [ { "value": "0x0000000200000002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_S_AXI_SINGLE_THREAD": [ { "value": "0x00000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_S_AXI_WRITE_ACCEPTANCE": [ { "value": "0x00000008000000080000000800000008", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_S_AXI_READ_ACCEPTANCE": [ { "value": "0x00000002000000020000000200000002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_M_AXI_WRITE_ISSUING": [ { "value": "0x00000008", "resolve_type": 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"size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_wready": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "s_axi_bid": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], + "s_axi_bresp": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], + "s_axi_bvalid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "s_axi_bready": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arid": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ], + "s_axi_araddr": [ { "direction": "in", "size_left": "159", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000" } ], + "s_axi_arlen": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_arsize": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_arburst": [ { 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"size_left": "3", "size_right": "0" } ], + "s_axi_rvalid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "s_axi_rready": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_awid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ], "m_axi_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], "m_axi_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], @@ -1319,16 +1319,16 @@ "m_axi_awqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "m_axi_awvalid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], "m_axi_awready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "m_axi_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ], - "m_axi_wstrb": [ { "direction": "out", "size_left": "31", "size_right": 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"size_right": "0" } ], + "m_axi_arid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ], "m_axi_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], "m_axi_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], @@ -1340,8 +1340,8 @@ "m_axi_arqos": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "m_axi_arvalid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], "m_axi_arready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "m_axi_rid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "m_axi_rdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ], + "m_axi_rid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_rdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ], "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], "m_axi_rlast": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ], "m_axi_rvalid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], @@ -1384,22 +1384,22 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "slave", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": 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"constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1417,7 +1417,7 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { - "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "0", "physical_right": "0" } ], + "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "1", "physical_right": "0" } ], "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "39", "physical_right": "0" } ], "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "7", "physical_right": "0" } ], "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "2", "physical_right": "0" } ], @@ -1428,16 +1428,16 @@ "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "3", "physical_right": "0" } ], "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "0", "physical_right": "0" } ], "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "0", "physical_right": "0" } ], - "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "255", "physical_right": "0" } ], - "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "31", "physical_right": "0" } ], + "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "511", "physical_right": "0" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "63", "physical_right": "0" } ], "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "0", "physical_right": "0" } ], "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "0", "physical_right": "0" } ], "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "0", "physical_right": "0" } ], - "BID": [ { "physical_name": "s_axi_bid", "physical_left": "0", "physical_right": "0" } ], + "BID": [ { "physical_name": "s_axi_bid", "physical_left": "1", "physical_right": "0" } ], "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "1", "physical_right": "0" } ], "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "0", "physical_right": "0" } ], "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "0", "physical_right": "0" } ], - "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "0", "physical_right": "0" } ], + "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "1", "physical_right": "0" } ], "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "39", "physical_right": "0" } ], "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "7", "physical_right": "0" } ], "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "2", "physical_right": "0" } ], @@ -1448,8 +1448,8 @@ "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "3", "physical_right": "0" } ], "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "0", "physical_right": "0" } ], "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "0", "physical_right": "0" } ], - "RID": [ { "physical_name": "s_axi_rid", "physical_left": "0", "physical_right": "0" } ], - "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "255", "physical_right": "0" } ], + "RID": [ { "physical_name": "s_axi_rid", "physical_left": "1", "physical_right": "0" } ], + "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "511", "physical_right": "0" } ], "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "1", "physical_right": "0" } ], "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "0", "physical_right": "0" } ], "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "0", "physical_right": "0" } ], @@ -1461,10 +1461,10 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "master", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1472,11 +1472,11 @@ "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1494,7 +1494,7 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { - "AWID": [ { "physical_name": "m_axi_awid", "physical_left": "0", "physical_right": "0" } ], + "AWID": [ { "physical_name": "m_axi_awid", "physical_left": "1", "physical_right": "0" } ], "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "39", "physical_right": "0" } ], "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "7", "physical_right": "0" } ], "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "2", "physical_right": "0" } ], @@ -1506,16 +1506,16 @@ "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "3", "physical_right": "0" } ], "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "0", "physical_right": "0" } ], "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "0", "physical_right": "0" } ], - "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "255", "physical_right": "0" } ], - "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "31", "physical_right": "0" } ], + "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "511", "physical_right": "0" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "63", "physical_right": "0" } ], "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "0", "physical_right": "0" } ], "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "0", "physical_right": "0" } ], "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "0", "physical_right": "0" } ], - "BID": [ { "physical_name": "m_axi_bid", "physical_left": "0", "physical_right": "0" } ], + "BID": [ { "physical_name": "m_axi_bid", "physical_left": "1", "physical_right": "0" } ], "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "1", "physical_right": "0" } ], "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "0", "physical_right": "0" } ], "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "0", "physical_right": "0" } ], - "ARID": [ { "physical_name": "m_axi_arid", "physical_left": "0", "physical_right": "0" } ], + "ARID": [ { "physical_name": "m_axi_arid", "physical_left": "1", "physical_right": "0" } ], "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "39", "physical_right": "0" } ], "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "7", "physical_right": "0" } ], "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "2", "physical_right": "0" } ], @@ -1527,8 +1527,8 @@ "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "3", "physical_right": "0" } ], "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "0", "physical_right": "0" } ], "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "0", "physical_right": "0" } ], - "RID": [ { "physical_name": "m_axi_rid", "physical_left": "0", "physical_right": "0" } ], - "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "255", "physical_right": "0" } ], + "RID": [ { "physical_name": "m_axi_rid", "physical_left": "1", "physical_right": "0" } ], + "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "511", "physical_right": "0" } ], "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "1", "physical_right": "0" } ], "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "0", "physical_right": "0" } ], "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "0", "physical_right": "0" } ], @@ -1540,22 +1540,22 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "slave", "parameters": { - "DATA_WIDTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1573,7 +1573,7 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { - "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "1", "physical_right": "1" } ], + "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "3", "physical_right": "2" } ], "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "79", "physical_right": "40" } ], "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "15", "physical_right": "8" } ], "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "5", "physical_right": "3" } ], @@ -1584,16 +1584,16 @@ "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "7", "physical_right": "4" } ], "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "1", "physical_right": "1" } ], "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "1", "physical_right": "1" } ], - "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "511", "physical_right": "256" } ], - "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "63", "physical_right": "32" } ], + "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "1023", "physical_right": "512" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "127", "physical_right": "64" } ], "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "1", "physical_right": "1" } ], "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "1", "physical_right": "1" } ], "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "1", "physical_right": "1" } ], - "BID": [ { "physical_name": "s_axi_bid", "physical_left": "1", "physical_right": "1" } ], + "BID": [ { "physical_name": "s_axi_bid", "physical_left": "3", "physical_right": "2" } ], "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "3", "physical_right": "2" } ], "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "1", "physical_right": "1" } ], "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "1", "physical_right": "1" } ], - "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "1", "physical_right": "1" } ], + "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "3", "physical_right": "2" } ], "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "79", "physical_right": "40" } ], "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "15", "physical_right": "8" } ], "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "5", "physical_right": "3" } ], @@ -1604,13 +1604,167 @@ "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "7", "physical_right": "4" } ], "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "1", "physical_right": "1" } ], "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "1", "physical_right": "1" } ], - "RID": [ { "physical_name": "s_axi_rid", "physical_left": "1", "physical_right": "1" } ], - "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "511", "physical_right": "256" } ], + "RID": [ { "physical_name": "s_axi_rid", "physical_left": "3", "physical_right": "2" } ], + "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "1023", "physical_right": "512" } ], "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "3", "physical_right": "2" } ], "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "1", "physical_right": "1" } ], "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "1", "physical_right": "1" } ], "RREADY": [ { "physical_name": "s_axi_rready", "physical_left": "1", "physical_right": "1" } ] } + }, + "S02_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "parameters": { + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "5", "physical_right": "4" } ], + "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "119", "physical_right": "80" } ], + "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "23", "physical_right": "16" } ], + "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "8", "physical_right": "6" } ], + "AWBURST": [ { "physical_name": "s_axi_awburst", "physical_left": "5", "physical_right": "4" } ], + "AWLOCK": [ { "physical_name": "s_axi_awlock", "physical_left": "2", "physical_right": "2" } ], + "AWCACHE": [ { "physical_name": "s_axi_awcache", "physical_left": "11", "physical_right": "8" } ], + "AWPROT": [ { "physical_name": "s_axi_awprot", "physical_left": "8", "physical_right": "6" } ], + "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "11", "physical_right": "8" } ], + "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "2", "physical_right": "2" } ], + "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "2", "physical_right": "2" } ], + "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "1535", "physical_right": "1024" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "191", "physical_right": "128" } ], + "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "2", "physical_right": "2" } ], + "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "2", "physical_right": "2" } ], + "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "2", "physical_right": "2" } ], + "BID": [ { "physical_name": "s_axi_bid", "physical_left": "5", "physical_right": "4" } ], + "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "5", "physical_right": "4" } ], + "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "2", "physical_right": "2" } ], + "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "2", "physical_right": "2" } ], + "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "5", "physical_right": "4" } ], + "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "119", "physical_right": "80" } ], + "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "23", "physical_right": "16" } ], + "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "8", "physical_right": "6" } ], + "ARBURST": [ { "physical_name": "s_axi_arburst", "physical_left": "5", "physical_right": "4" } ], + "ARLOCK": [ { "physical_name": "s_axi_arlock", "physical_left": "2", "physical_right": "2" } ], + "ARCACHE": [ { "physical_name": "s_axi_arcache", "physical_left": "11", "physical_right": "8" } ], + "ARPROT": [ { "physical_name": "s_axi_arprot", "physical_left": "8", "physical_right": "6" } ], + "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "11", "physical_right": "8" } ], + "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "2", "physical_right": "2" } ], + "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "2", "physical_right": "2" } ], + "RID": [ { "physical_name": "s_axi_rid", "physical_left": "5", "physical_right": "4" } ], + "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "1535", "physical_right": "1024" } ], + "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "5", "physical_right": "4" } ], + "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "2", "physical_right": "2" } ], + "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "2", "physical_right": "2" } ], + "RREADY": [ { "physical_name": "s_axi_rready", "physical_left": "2", "physical_right": "2" } ] + } + }, + "S03_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "parameters": { + "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "7", "physical_right": "6" } ], + "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "159", "physical_right": "120" } ], + "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "31", "physical_right": "24" } ], + "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "11", "physical_right": "9" } ], + "AWBURST": [ { "physical_name": "s_axi_awburst", "physical_left": "7", "physical_right": "6" } ], + "AWLOCK": [ { "physical_name": "s_axi_awlock", "physical_left": "3", "physical_right": "3" } ], + "AWCACHE": [ { "physical_name": "s_axi_awcache", "physical_left": "15", "physical_right": "12" } ], + "AWPROT": [ { "physical_name": "s_axi_awprot", "physical_left": "11", "physical_right": "9" } ], + "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "15", "physical_right": "12" } ], + "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "3", "physical_right": "3" } ], + "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "3", "physical_right": "3" } ], + "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "2047", "physical_right": "1536" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "255", "physical_right": "192" } ], + "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "3", "physical_right": "3" } ], + "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "3", "physical_right": "3" } ], + "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "3", "physical_right": "3" } ], + "BID": [ { "physical_name": "s_axi_bid", "physical_left": "7", "physical_right": "6" } ], + "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "7", "physical_right": "6" } ], + "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "3", "physical_right": "3" } ], + "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "3", "physical_right": "3" } ], + "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "7", "physical_right": "6" } ], + "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "159", "physical_right": "120" } ], + "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "31", "physical_right": "24" } ], + "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "11", "physical_right": "9" } ], + "ARBURST": [ { "physical_name": "s_axi_arburst", "physical_left": "7", "physical_right": "6" } ], + "ARLOCK": [ { "physical_name": "s_axi_arlock", "physical_left": "3", "physical_right": "3" } ], + "ARCACHE": [ { "physical_name": "s_axi_arcache", "physical_left": "15", "physical_right": "12" } ], + "ARPROT": [ { "physical_name": "s_axi_arprot", "physical_left": "11", "physical_right": "9" } ], + "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "15", "physical_right": "12" } ], + "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "3", "physical_right": "3" } ], + "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "3", "physical_right": "3" } ], + "RID": [ { "physical_name": "s_axi_rid", "physical_left": "7", "physical_right": "6" } ], + "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "2047", "physical_right": "1536" } ], + "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "7", "physical_right": "6" } ], + "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "3", "physical_right": "3" } ], + "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "3", "physical_right": "3" } ], + "RREADY": [ { "physical_name": "s_axi_rready", "physical_left": "3", "physical_right": "3" } ] + } } } } diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/design_1_xbar_1.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_5/design_1_xbar_5.xci similarity index 92% rename from project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/design_1_xbar_1.xci rename to project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_5/design_1_xbar_5.xci index 2c5e713..76a41c3 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/design_1_xbar_1.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_5/design_1_xbar_5.xci @@ -1,16 +1,16 @@ { "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { - "xci_name": "design_1_xbar_1", + "xci_name": "design_1_xbar_5", "cell_name": "microblaze_0_axi_periph/xbar", "component_reference": "xilinx.com:ip:axi_crossbar:2.1", "ip_revision": "28", - "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_1", + "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_5", "parameters": { "component_parameters": { "ADDR_RANGES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_SI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "NUM_MI": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_MI": [ { "value": "9", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "STRATEGY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -135,8 +135,8 @@ "M06_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M07_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M07_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_S01_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S04_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -151,8 +151,8 @@ "M07_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M08_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M08_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_S01_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_S04_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -391,8 +391,8 @@ "M06_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M07_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M07_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S04_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -407,8 +407,8 @@ "M07_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M08_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M08_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_S04_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -590,8 +590,8 @@ "M04_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "M05_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "M06_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], - "M07_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M08_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "M08_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "M09_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M10_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M11_WRITE_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -606,8 +606,8 @@ "M04_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "M05_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "M06_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], - "M07_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M08_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "M08_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "M09_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M10_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M11_READ_ISSUING": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -727,7 +727,7 @@ "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M02_A00_BASE_ADDR": [ { "value": "0x0000000081000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A00_BASE_ADDR": [ { "value": "0x0000000080100000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -743,7 +743,7 @@ "M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M03_A00_BASE_ADDR": [ { "value": "0x0000000081010000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A00_BASE_ADDR": [ { "value": "0x0000000080110000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -759,7 +759,7 @@ "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M04_A00_BASE_ADDR": [ { "value": "0x0000000080100000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A00_BASE_ADDR": [ { "value": "0x0000000080010000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -775,7 +775,7 @@ "M04_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M05_A00_BASE_ADDR": [ { "value": "0x0000000080110000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M05_A00_BASE_ADDR": [ { "value": "0x0000000080020000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M05_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M05_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M05_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -791,7 +791,7 @@ "M05_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M05_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M05_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M06_A00_BASE_ADDR": [ { "value": "0x0000000080120000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M06_A00_BASE_ADDR": [ { "value": "0x0000000080030000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M06_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M06_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M06_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -807,7 +807,7 @@ "M06_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M06_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M06_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M07_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M07_A00_BASE_ADDR": [ { "value": "0x0000000080120000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M07_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M07_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M07_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -823,7 +823,7 @@ "M07_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M07_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M07_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M08_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M08_A00_BASE_ADDR": [ { "value": "0x0000000080130000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M08_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M08_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M08_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -1063,7 +1063,7 @@ "M06_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M07_A00_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1079,7 +1079,7 @@ "M07_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M08_A00_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M08_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1207,19 +1207,19 @@ "M15_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Component_Name": [ { "value": "design_1_xbar_1", "resolve_type": "user", "usage": "all" } ] + "Component_Name": [ { "value": "design_1_xbar_5", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "C_NUM_SLAVE_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_NUM_MASTER_SLOTS": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_NUM_MASTER_SLOTS": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_NUM_ADDR_RANGES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_M_AXI_BASE_ADDR": [ { "value": "0x0000000080120000000000008011000000000000801000000000000081010000000000008100000000000000800000000000000083000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_ADDR_WIDTH": [ { "value": "0x00000010000000100000001000000010000000100000001000000018", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_BASE_ADDR": [ { "value": "0x000000008013000000000000801200000000000080030000000000008002000000000000800100000000000080110000000000008010000000000000800000000000000083000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_ADDR_WIDTH": [ { "value": "0x000000100000001000000010000000100000001000000010000000100000001000000018", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_BASE_ID": [ { "value": "0x0000000100000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -1228,24 +1228,24 @@ "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x00000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_READ_CONNECTIVITY": [ { "value": "0x00000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x000000030000000300000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_READ_CONNECTIVITY": [ { "value": "0x000000030000000300000003000000030000000300000003000000030000000300000003", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_R_REGISTER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_SINGLE_THREAD": [ { "value": "0x0000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_WRITE_ACCEPTANCE": [ { "value": "0x0000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_READ_ACCEPTANCE": [ { "value": "0x0000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_WRITE_ISSUING": [ { "value": "0x00000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_READ_ISSUING": [ { "value": "0x00000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_WRITE_ISSUING": [ { "value": "0x000000010000000100000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_READ_ISSUING": [ { "value": "0x000000010000000100000001000000010000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_ARB_PRIORITY": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_SECURE": [ { "value": "0x00000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_SECURE": [ { "value": "0x000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_CONNECTIVITY_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -1259,9 +1259,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "28" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_1" } ], + "OUTPUTDIR": [ { "value": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_xbar_5" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../../project_1.srcs/sources_1/bd/design_1/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] } @@ -1289,25 +1289,25 @@ "s_axi_rresp": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "s_axi_rvalid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axi_rready": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], - "m_axi_awaddr": [ { "direction": "out", "size_left": "279", "size_right": "0" } ], - "m_axi_awprot": [ { "direction": "out", "size_left": "20", "size_right": "0" } ], - "m_axi_awvalid": [ { "direction": "out", "size_left": "6", "size_right": "0" } ], - "m_axi_awready": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_wdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ], - "m_axi_wstrb": [ { "direction": "out", "size_left": "27", "size_right": "0" } ], - "m_axi_wvalid": [ { "direction": "out", "size_left": "6", "size_right": "0" } ], - "m_axi_wready": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_bresp": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0x0000" } ], - "m_axi_bvalid": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_bready": [ { "direction": "out", "size_left": "6", "size_right": "0" } ], - "m_axi_araddr": [ { "direction": "out", "size_left": "279", "size_right": "0" } ], - "m_axi_arprot": [ { "direction": "out", "size_left": "20", "size_right": "0" } ], - "m_axi_arvalid": [ { "direction": "out", "size_left": "6", "size_right": "0" } ], - "m_axi_arready": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_rdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000" } ], - "m_axi_rresp": [ { "direction": "in", "size_left": "13", "size_right": "0", "driver_value": "0x0000" } ], - "m_axi_rvalid": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_rready": [ { "direction": "out", "size_left": "6", "size_right": "0" } ] + "m_axi_awaddr": [ { "direction": "out", "size_left": "359", "size_right": "0" } ], + "m_axi_awprot": [ { "direction": "out", "size_left": "26", "size_right": "0" } ], + "m_axi_awvalid": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_awready": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "287", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "35", "size_right": "0" } ], + "m_axi_wvalid": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_wready": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ], + "m_axi_bresp": [ { "direction": "in", "size_left": "17", "size_right": "0", "driver_value": "0x00000" } ], + "m_axi_bvalid": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ], + "m_axi_bready": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_araddr": [ { "direction": "out", "size_left": "359", "size_right": "0" } ], + "m_axi_arprot": [ { "direction": "out", "size_left": "26", "size_right": "0" } ], + "m_axi_arvalid": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_arready": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ], + "m_axi_rdata": [ { "direction": "in", "size_left": "287", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000000000000000" } ], + "m_axi_rresp": [ { "direction": "in", "size_left": "17", "size_right": "0", "driver_value": "0x00000" } ], + "m_axi_rvalid": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0x000" } ], + "m_axi_rready": [ { "direction": "out", "size_left": "8", "size_right": "0" } ] }, "interfaces": { "RSTIF": { @@ -1486,7 +1486,7 @@ "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1871,6 +1871,124 @@ "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "6", "physical_right": "6" } ], "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "6", "physical_right": "6" } ] } + }, + "M07_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "319", "physical_right": "280" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "23", "physical_right": "21" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "7", "physical_right": "7" } ], + "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "7", "physical_right": "7" } ], + "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "255", "physical_right": "224" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "31", "physical_right": "28" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "7", "physical_right": "7" } ], + "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "7", "physical_right": "7" } ], + "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "15", "physical_right": "14" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "7", "physical_right": "7" } ], + "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "7", "physical_right": "7" } ], + "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "319", "physical_right": "280" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "23", "physical_right": "21" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "7", "physical_right": "7" } ], + "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "7", "physical_right": "7" } ], + "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "255", "physical_right": "224" } ], + "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "15", "physical_right": "14" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "7", "physical_right": "7" } ], + "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "7", "physical_right": "7" } ] + } + }, + "M08_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "design_1_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "359", "physical_right": "320" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "26", "physical_right": "24" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "8", "physical_right": "8" } ], + "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "8", "physical_right": "8" } ], + "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "287", "physical_right": "256" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "35", "physical_right": "32" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "8", "physical_right": "8" } ], + "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "8", "physical_right": "8" } ], + "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "17", "physical_right": "16" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "8", "physical_right": "8" } ], + "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "8", "physical_right": "8" } ], + "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "359", "physical_right": "320" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "26", "physical_right": "24" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "8", "physical_right": "8" } ], + "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "8", "physical_right": "8" } ], + "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "287", "physical_right": "256" } ], + "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "17", "physical_right": "16" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "8", "physical_right": "8" } ], + "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "8", "physical_right": "8" } ] + } } } } diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xdma_0_0/design_1_xdma_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xdma_0_0/design_1_xdma_0_0.xci index 02e2dc2..190fc80 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xdma_0_0/design_1_xdma_0_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xdma_0_0/design_1_xdma_0_0.xci @@ -12,38 +12,38 @@ "functional_mode": [ { "value": "AXI_Bridge", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "mode_selection": [ { "value": "Advanced", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "usage": "all" } ], - "pcie_blk_locn": [ { "value": "X0Y0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "pl_link_cap_max_link_width": [ { "value": "X8", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pcie_blk_locn": [ { "value": "X0Y2", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pl_link_cap_max_link_width": [ { "value": "X16", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "pl_link_cap_max_link_speed": [ { "value": "8.0_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "ref_clk_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ], "drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "usage": "all" } ], "free_run_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ], "axi_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "axi_data_width": [ { "value": "256_bit", "resolve_type": "user", "usage": "all" } ], - "axisten_freq": [ { "value": "250", "resolve_type": "user", "usage": "all" } ], + "axi_data_width": [ { "value": "512_bit", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "axisten_freq": [ { "value": "250", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "en_axi_slave_if": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "en_axi_master_if": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "pipe_sim": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "en_ext_ch_gt_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "en_pcie_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "dedicate_perst": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "dedicate_perst": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "sys_reset_polarity": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "mcap_enablement": [ { "value": "None", "resolve_type": "user", "enabled": false, "usage": "all" } ], "mcap_fpga_bitstream_version": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], "ext_startup_primitive": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "enable_code": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ], "vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ], - "pf0_device_id": [ { "value": "9038", "resolve_type": "user", "usage": "all" } ], + "pf0_device_id": [ { "value": "903F", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "pf0_revision_id": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], "pf0_subsystem_vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ], "pf0_subsystem_id": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ], "pf0_Use_Class_Code_Lookup_Assistant": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], "pf0_base_class_menu": [ { "value": "Memory_controller", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "pf0_class_code_base": [ { "value": "05", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code_base": [ { "value": "05", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "pf0_sub_class_interface_menu": [ { "value": "Other_memory_controller", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "pf0_class_code_sub": [ { "value": "80", "resolve_type": "user", "usage": "all" } ], - "pf0_class_code_interface": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], - "pf0_class_code": [ { "value": "058000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pf0_class_code_sub": [ { "value": "80", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code_interface": [ { "value": "00", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code": [ { "value": "058000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "axilite_master_en": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], "axilite_master_size": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "axilite_master_scale": [ { "value": "Megabytes", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -74,7 +74,7 @@ "en_transceiver_status_ports": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "xdma_rnum_chnl": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], "xdma_wnum_chnl": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], - "xdma_axilite_slave": [ { "value": "true", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "xdma_axilite_slave": [ { "value": "true", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "xdma_num_usr_irq": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], "xdma_rnum_rids": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], "xdma_wnum_rids": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -82,13 +82,13 @@ "PCIE_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], "EGW_IS_PARENT_IP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], "en_gt_selection": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "select_quad": [ { "value": "GTH_Quad_224", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "select_quad": [ { "value": "GTY_Quad_130", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "RX_PPM_OFFSET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "INS_LOSS_NYQ": [ { "value": "15", "resolve_type": "user", "format": "float", "usage": "all" } ], "PHY_LP_TXPRESET": [ { "value": "4", "resolve_type": "user", "usage": "all" } ], - "coreclk_freq": [ { "value": "500", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "plltype": [ { "value": "QPLL1", "resolve_type": "user", "usage": "all" } ], + "coreclk_freq": [ { "value": "500", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "plltype": [ { "value": "QPLL1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "xdma_axi_intf_mm": [ { "value": "AXI_Memory_Mapped", "resolve_type": "user", "usage": "all" } ], "xdma_pcie_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "silicon_rev": [ { "value": "Pre-Production", "resolve_type": "user", "usage": "all" } ], @@ -153,7 +153,7 @@ "include_baroffset_reg": [ { "value": "true", "resolve_type": "user", "enabled": false, "usage": "all" } ], "BASEADDR": [ { "value": "0x83000000", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ], "HIGHADDR": [ { "value": "0x83FFFFFF", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ], - "s_axi_id_width": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "s_axi_id_width": [ { "value": "2", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "c_m_axi_num_write": [ { "value": "8", "resolve_type": "user", "usage": "all" } ], "c_m_axi_num_read": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ], "c_m_axi_num_readq": [ { "value": "2", "resolve_type": "user", "usage": "all" } ], @@ -163,9 +163,9 @@ "axi_aclk_loopback": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "pf0_bar0_enabled": [ { "value": "true", "resolve_type": "user", "usage": "all" } ], "pf0_bar0_type": [ { "value": "Memory", "resolve_type": "user", "usage": "all" } ], - "pf0_bar0_size": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "pf0_bar0_size": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "pf0_bar0_scale": [ { "value": "Megabytes", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "pf0_bar0_64bit": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], + "pf0_bar0_64bit": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "pf0_bar0_prefetchable": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ], "pf0_bar1_enabled": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], "pf0_bar1_type": [ { "value": "Memory", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -722,10 +722,10 @@ "pf1_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "pf2_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "pf3_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PF0_DEVICE_ID_mqdma": [ { "value": "9038", "resolve_type": "user", "usage": "all" } ], + "PF0_DEVICE_ID_mqdma": [ { "value": "903F", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PF1_DEVICE_ID_mqdma": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ], - "PF2_DEVICE_ID_mqdma": [ { "value": "9238", "resolve_type": "user", "usage": "all" } ], - "PF3_DEVICE_ID_mqdma": [ { "value": "9338", "resolve_type": "user", "usage": "all" } ], + "PF2_DEVICE_ID_mqdma": [ { "value": "923F", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PF3_DEVICE_ID_mqdma": [ { "value": "933F", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PF0_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], "PF1_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], "PF2_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], @@ -771,26 +771,26 @@ "PF0_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF0_SRIOV_FUNC_DEP_LINK": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ], "PF0_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], - "PF0_SRIOV_VF_DEVICE_ID": [ { "value": "A038", "resolve_type": "user", "usage": "all" } ], + "PF0_SRIOV_VF_DEVICE_ID": [ { "value": "A03F", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PF0_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ], "PF1_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF1_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF1_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "PF1_SRIOV_FUNC_DEP_LINK": [ { "value": "0001", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF1_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ], - "PF1_SRIOV_VF_DEVICE_ID": [ { "value": "A138", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PF1_SRIOV_VF_DEVICE_ID": [ { "value": "A13F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF2_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF2_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF2_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "PF2_SRIOV_FUNC_DEP_LINK": [ { "value": "0002", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF2_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ], - "PF2_SRIOV_VF_DEVICE_ID": [ { "value": "A238", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PF2_SRIOV_VF_DEVICE_ID": [ { "value": "A23F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF3_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF3_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF3_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "PF3_SRIOV_FUNC_DEP_LINK": [ { "value": "0003", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PF3_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ], - "PF3_SRIOV_VF_DEVICE_ID": [ { "value": "A338", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PF3_SRIOV_VF_DEVICE_ID": [ { "value": "A33F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "pf0_ari_enabled": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], "pf0_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], "pf1_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], @@ -942,12 +942,12 @@ "enable_error_injection": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "performance_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "descriptor_bypass_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "vdm_en": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "vdm_en": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "virtio_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "virtio_perf_exdes": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "bridge_burst": [ { "value": "true", "resolve_type": "user", "usage": "all" } ], + "bridge_burst": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "insert_cips": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], - "en_bridge_slv": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "en_bridge_slv": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "enable_clock_delay_grp": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "replace_uram_with_bram": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "errc_dec_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -961,28 +961,28 @@ "COMPONENT_NAME": [ { "value": "xdma_0", "resolve_type": "generated", "usage": "all" } ], "PL_UPSTREAM_FACING": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ], "TL_LEGACY_MODE_ENABLE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "PCIE_BLK_LOCN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "PCIE_BLK_LOCN": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], "PL_LINK_CAP_MAX_LINK_SPEED": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "REF_CLK_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "DRP_CLK_SEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "FREE_RUN_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "AXI_DATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], "CORE_CLK_FREQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "USER_CLK_FREQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "USER_CLK_FREQ": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "SILICON_REV": [ { "value": "Pre-Production", "resolve_type": "generated", "usage": "all" } ], "PIPE_SIM": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "VDM_EN": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ], "EXT_CH_GT_DRP": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "PCIE3_DRP": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "DEDICATE_PERST": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ], + "DEDICATE_PERST": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "SYS_RESET_POLARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "MCAP_ENABLEMENT": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], "EXT_STARTUP_PRIMITIVE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "PF0_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "PF0_DEVICE_ID": [ { "value": "0x9038", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "PF0_DEVICE_ID": [ { "value": "0x903F", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "PF0_REVISION_ID": [ { "value": "0x00", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "PF0_SUBSYSTEM_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "PF0_SUBSYSTEM_ID": [ { "value": "0x0007", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], @@ -1022,7 +1022,7 @@ "EN_TRANSCEIVER_STATUS_PORTS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "IS_BOARD_PROJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "EN_GT_SELECTION": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "SELECT_QUAD": [ { "value": "GTH_Quad_224", "resolve_type": "generated", "usage": "all" } ], + "SELECT_QUAD": [ { "value": "GTY_Quad_130", "resolve_type": "generated", "usage": "all" } ], "ULTRASCALE": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "ULTRASCALE_PLUS": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ], "VERSAL": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], @@ -1042,7 +1042,7 @@ "EGW_IS_PARENT_IP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_M_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXIBAR_NUM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ], + "C_FAMILY": [ { "value": "kintexuplus", "resolve_type": "generated", "usage": "all" } ], "XDMA_NUM_PCIE_TAG": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ], "EN_AXI_MASTER_IF": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ], "EN_WCHNL_0": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ], @@ -1117,16 +1117,16 @@ "C_INCLUDE_BAROFFSET_REG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_BASEADDR": [ { "value": "0x83000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_HIGHADDR": [ { "value": "0x83FFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ID_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_NUM_READ": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_M_AXI_NUM_READ": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_M_AXI_NUM_READQ": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_NUM_WRITE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_M_AXI_NUM_WRITE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_M_AXI_NUM_WRITE": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_M_AXI_NUM_WRITE_SCALE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "MSIX_IMPL_EXT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "AXI_ACLK_LOOPBACK": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "PF0_BAR0_APERTURE_SIZE": [ { "value": "0x12", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "PF0_BAR0_APERTURE_SIZE": [ { "value": "0x0E", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "PF0_BAR0_CONTROL": [ { "value": "0x4", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "PF0_BAR1_APERTURE_SIZE": [ { "value": "0x05", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "PF0_BAR1_CONTROL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], @@ -1276,11 +1276,11 @@ "ERRC_DEC_EN": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], @@ -1308,10 +1308,10 @@ "sys_rst_n": [ { "direction": "in", "driver_value": "1" } ], "cfg_ltssm_state": [ { "direction": "out", "size_left": "5", "size_right": "0" } ], "user_lnk_up": [ { "direction": "out" } ], - "pci_exp_txp": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], - "pci_exp_txn": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], - "pci_exp_rxp": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], - "pci_exp_rxn": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "pci_exp_txp": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "pci_exp_txn": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "pci_exp_rxp": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "pci_exp_rxn": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "axi_aclk": [ { "direction": "out" } ], "axi_aresetn": [ { "direction": "out" } ], "axi_ctl_aresetn": [ { "direction": "out" } ], @@ -1329,8 +1329,8 @@ "m_axib_awready": [ { "direction": "in", "driver_value": "0" } ], "m_axib_awlock": [ { "direction": "out" } ], "m_axib_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], - "m_axib_wdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ], - "m_axib_wstrb": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axib_wdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], + "m_axib_wstrb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "m_axib_wlast": [ { "direction": "out" } ], "m_axib_wvalid": [ { "direction": "out" } ], "m_axib_wready": [ { "direction": "in", "driver_value": "0" } ], @@ -1349,7 +1349,7 @@ "m_axib_arlock": [ { "direction": "out" } ], "m_axib_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "m_axib_rid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], - "m_axib_rdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ], + "m_axib_rdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ], "m_axib_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ], "m_axib_rlast": [ { "direction": "in", "driver_value": "0" } ], "m_axib_rvalid": [ { "direction": "in", "driver_value": "0" } ], @@ -1374,19 +1374,19 @@ "s_axil_rvalid": [ { "direction": "out" } ], "s_axil_rready": [ { "direction": "in", "driver_value": "0" } ], "interrupt_out": [ { "direction": "out" } ], - "s_axib_awid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "s_axib_awid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ], "s_axib_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ], "s_axib_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], "s_axib_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], "s_axib_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], "s_axib_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ], "s_axib_awvalid": [ { "direction": "in", "driver_value": "0" } ], - "s_axib_wdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ], - "s_axib_wstrb": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "s_axib_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ], + "s_axib_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ], "s_axib_wlast": [ { "direction": "in", "driver_value": "0" } ], "s_axib_wvalid": [ { "direction": "in", "driver_value": "0" } ], "s_axib_bready": [ { "direction": "in", "driver_value": "0" } ], - "s_axib_arid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "s_axib_arid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ], "s_axib_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ], "s_axib_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], "s_axib_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], @@ -1396,12 +1396,12 @@ "s_axib_rready": [ { "direction": "in", "driver_value": "0" } ], "s_axib_awready": [ { "direction": "out" } ], "s_axib_wready": [ { "direction": "out" } ], - "s_axib_bid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "s_axib_bid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axib_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axib_bvalid": [ { "direction": "out" } ], "s_axib_arready": [ { "direction": "out" } ], - "s_axib_rid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], - "s_axib_rdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ], + "s_axib_rid": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axib_rdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], "s_axib_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axib_rlast": [ { "direction": "out" } ], "s_axib_rvalid": [ { "direction": "out" } ] @@ -1412,7 +1412,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "design_1_util_ds_buf_0_0_IBUF_DS_ODIV2", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -1480,7 +1480,7 @@ "parameters": { "BOARD.ASSOCIATED_PARAM": [ { "value": "SYS_RST_N_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "TYPE": [ { "value": "PCIE_PERST", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { @@ -1529,10 +1529,10 @@ "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "256", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "250000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "2", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], @@ -1540,7 +1540,7 @@ "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], @@ -1599,14 +1599,14 @@ "address_space_ref": "M_AXI_B", "parameters": { "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "32", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "256", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "512", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "250000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "40", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], @@ -1679,7 +1679,7 @@ "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "250000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "250000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci index 29bceec..0d0dfa2 100644 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci +++ b/project_1.srcs/sources_1/bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci @@ -17,11 +17,11 @@ "CONST_VAL": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], + "ARCHITECTURE": [ { "value": "kintexuplus" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xczu7ev" } ], - "PACKAGE": [ { "value": "ffvc1156" } ], + "DEVICE": [ { "value": "xcku15p" } ], + "PACKAGE": [ { "value": "ffve1517" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], diff --git a/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xci b/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xci deleted file mode 100644 index e813b07..0000000 --- a/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xci +++ /dev/null @@ -1,2012 +0,0 @@ -{ - "schema": "xilinx.com:schema:json_instance:1.0", - "ip_inst": { - "xci_name": "design_1_zynq_ultra_ps_e_0_0", - "cell_name": "zynq_ultra_ps_e_0", - "component_reference": "xilinx.com:ip:zynq_ultra_ps_e:3.4", - "ip_revision": "1", - "gen_directory": "../../../../../../project_1.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0", - "parameters": { - "component_parameters": { - "PSU_VALUE_SILVERSION": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PSU__USE__DDR_INTF_REQUESTED": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PSU__EN_AXI_STATUS_PORTS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PSU__PSS_REF_CLK__FREQMHZ": [ { "value": "33.333", "value_src": "user", "resolve_type": "user", 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"maxigp2_awprot" } ], - "AWVALID": [ { "physical_name": "maxigp2_awvalid" } ], - "AWUSER": [ { "physical_name": "maxigp2_awuser" } ], - "AWREADY": [ { "physical_name": "maxigp2_awready" } ], - "WDATA": [ { "physical_name": "maxigp2_wdata" } ], - "WSTRB": [ { "physical_name": "maxigp2_wstrb" } ], - "WLAST": [ { "physical_name": "maxigp2_wlast" } ], - "WVALID": [ { "physical_name": "maxigp2_wvalid" } ], - "WREADY": [ { "physical_name": "maxigp2_wready" } ], - "BID": [ { "physical_name": "maxigp2_bid" } ], - "BRESP": [ { "physical_name": "maxigp2_bresp" } ], - "BVALID": [ { "physical_name": "maxigp2_bvalid" } ], - "BREADY": [ { "physical_name": "maxigp2_bready" } ], - "ARID": [ { "physical_name": "maxigp2_arid" } ], - "ARADDR": [ { "physical_name": "maxigp2_araddr" } ], - "ARLEN": [ { "physical_name": "maxigp2_arlen" } ], - "ARSIZE": [ { "physical_name": "maxigp2_arsize" } ], - "ARBURST": [ { "physical_name": "maxigp2_arburst" } ], - "ARLOCK": [ { "physical_name": "maxigp2_arlock" } ], - "ARCACHE": [ { "physical_name": "maxigp2_arcache" } ], - "ARPROT": [ { "physical_name": "maxigp2_arprot" } ], - "ARVALID": [ { "physical_name": "maxigp2_arvalid" } ], - "ARUSER": [ { "physical_name": "maxigp2_aruser" } ], - "ARREADY": [ { "physical_name": "maxigp2_arready" } ], - "RID": [ { "physical_name": "maxigp2_rid" } ], - "RDATA": [ { "physical_name": "maxigp2_rdata" } ], - "RRESP": [ { "physical_name": "maxigp2_rresp" } ], - "RLAST": [ { "physical_name": "maxigp2_rlast" } ], - "RVALID": [ { "physical_name": "maxigp2_rvalid" } ], - "RREADY": [ { "physical_name": "maxigp2_rready" } ], - "AWQOS": [ { "physical_name": "maxigp2_awqos" } ], - "ARQOS": [ { "physical_name": "maxigp2_arqos" } ] - } - }, - "M_AXI_HPM0_LPD_ACLK": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "slave", - "parameters": { - "ASSOCIATED_BUSIF": [ { "value": "M_AXI_HPM0_LPD", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "design_1_zynq_ultra_ps_e_0_0_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK": [ { "physical_name": "maxihpm0_lpd_aclk" } ] - } - }, - "PL_RESETN0": { - "vlnv": "xilinx.com:signal:reset:1.0", - "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", - "mode": "slave", - "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "RST": [ { "physical_name": "pl_resetn0" } ] - } - }, - "PL_CLK0": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "master", - "parameters": { - "FREQ_HZ": [ { "value": "96968727", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "design_1_zynq_ultra_ps_e_0_0_pl_clk0", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK": [ { "physical_name": "pl_clk0" } ] - } - } - }, - "address_spaces": { - "Data": { - "range": "1600000000000", - "display_name": "Data", - "width": "64", - "apertures": { - "M_AXI_HPM0_LPD/LPD_AFI_FS": [ { "offset": "0x0080000000", "range": "0x20000000", "display_name": "M_AXI_HPM0_LPD/LPD_AFI_FS", "description": "512M" } ], - "M_AXI_HPM1_FPD/FPD_AFI_FS0_00": [ { "offset": "0x00B0000000", "range": "0x10000000", "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_00", "description": "256M" } ], - "M_AXI_HPM1_FPD/FPD_AFI_FS0_01": [ { "offset": "0x0500000000", "range": "0x100000000", "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_01", "description": "4G" } ], - "M_AXI_HPM1_FPD/FPD_AFI_FS0_10": [ { "offset": "0x4800000000", "range": "0x3800000000", "display_name": "M_AXI_HPM1_FPD/FPD_AFI_FS0_10", "description": "224G" } ], - "M_AXI_HPM0_FPD/FPD_AFI_FS1_00": [ { "offset": "0x00A0000000", "range": "0x10000000", "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_00", "description": "256M" } ], - "M_AXI_HPM0_FPD/FPD_AFI_FS1_01": [ { "offset": "0x0400000000", "range": "0x100000000", "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_01", "description": "4G" } ], - "M_AXI_HPM0_FPD/FPD_AFI_FS1_10": [ { "offset": "0x1000000000", "range": "0x3800000000", "display_name": "M_AXI_HPM0_FPD/FPD_AFI_FS1_10", "description": "224G" } ] - } - } - } - }, - "contents": { - "cpus": { - "CortexA5x_0": { - "address_space_refs": "Data", - "parameters": { - "is_visible": [ { "value": "FALSE" } ], - "processor_type": [ { "value": "ARM" } ] - } - }, - "CortexA5x_1": { - "address_space_refs": "Data", - "parameters": { - "is_visible": [ { "value": "FALSE" } ], - "processor_type": [ { "value": "ARM" } ] - } - }, - "CortexA5x_2": { - "address_space_refs": "Data", - "parameters": { - "is_visible": [ { "value": "FALSE" } ], - "processor_type": [ { "value": "ARM" } ] - } - }, - "CortexA5x_3": { - "address_space_refs": "Data", - "parameters": { - "is_visible": [ { "value": "FALSE" } ], - "processor_type": [ { "value": "ARM" } ] - } - }, - "CortexR5_0": { - "address_space_refs": "Data", - "parameters": { - "is_visible": [ { "value": "FALSE" } ], - "processor_type": [ { "value": "ARM" } ] - } - }, - "CortexR5_1": { - "address_space_refs": "Data", - "parameters": { - "is_visible": [ { "value": "FALSE" } ], - "processor_type": [ { "value": "ARM" } ] - } - } - } - } - } -} \ No newline at end of file diff --git a/project_1.srcs/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.v b/project_1.srcs/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.v new file mode 100755 index 0000000..5275699 --- /dev/null +++ b/project_1.srcs/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.v @@ -0,0 +1,7800 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2022.2" +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +k8813guuBvPKpymEe9ir2tbQSCs1w/34n9neq78WixpY6HtGm+fnfxebbBPo9dy3DbfyipEgHCA6 +T6DL3f6o1oTBOU1oSRU0D8yxPppBevVhaS7ln6Io+DyhkT0ouavVSNVULitNUbCfDoLDUnpTxAVl +Uw3t22dYAFnN0OpB5TU= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +PWVCLWmcsp2IXlX313aPa6gkTHtRoHDDJ2JvQb/7u2SUwj2qo/IU4vAkr1qN93RutXrsNQVV7o0O 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= 76, bytes = 256) +`pragma protect key_block +PPBAkCinqqHfz/kuOR6PnIB1TvejmEf5OaBBvkLLoMy/M7dPJENhwuwJ4hI96yk8UlM2jZ8m556e +AKwAhyyNbzbYzIveNH4/f7iFzBMPwl9e4qZ+Otq2hhqdf2NM6YRgwEYx808DOZ2uz1Nhu2/dMVep +q5QZgkmXcMFX4duEGGZrcXvMTD7rUNKIvgBcZyvV2zWv11JKPXfQLD84htIu8j56S1Te3sPDv837 +wC8rSxV1GmTIf0HkGdDm4R6fFuJlOA6407rRE3JtrASXmp9rcP21tqZiAfI5gAgbTCXyL93Ikg9R +YMSFUkzgvl9p3C+cfDg3GUrg+gKxKAmM52qapA== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2021_07", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +LncwVyEP1qm4l8qwHEJsC0s+XAgx6X4v73bl3dd2pBTr8i10PP+x+e34trTuEkrAW173dLT2/XvK +ysr0Ug5lzaUTpdoUwhS88tHfMgX1sszKFpBPhSVv6+F27CZX2titRxWZW27dcKSM1I/jaUPBYzvb +1jvKvFsYkMoDRnjZQqlFpomQ/MJVaiTwL+zRB8a9Eygn0g44CL3pC1PMxl4Zi9Cr3NPOxxPjxrHP +Z0PmZWISzCQZxIyZAluN8thJAv62QqPRrQqBF/JEtnGoAq3ZEZozIa4TZP3Aja/ZsPkDXJenaXK2 +oNNR0dYg1+1PY8L5tgDmK1gPHj2kFNf57zAC3w== + +`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384) +`pragma protect key_block +xHhhgxhf6gA7yEpNnHKglFJ04W+0U+DyNoCzApZeasO7dgzjeOxe12bIW1s6kHgWdA3E1uTXWFpk +PtCPpmIuTzFW5ALWpn8nFslLCU6g9f7rnxmqfzEhCN2+am5aguDC3ScnGRvZC4VB2bh1/FT455rd +/NdqA6bLR1fKqGrBFllGh3L39OdDdOsHJ17rufoMhYaEGja0UX728pH+a23WGEzpDUfnjcHivnlG +3SXuxM2YB9LQF7mOGSyoihQIAjXXWCTeq8eJMB22yjBiyBaqxqLCtn17562NKvm9aXo0vHXX2F6v +oB1ByhegXqU67PQ1iWKwu2a5IRzDyK4sZU5vnyCBFKRzE1AZywxw0CHTXKpCUcD83kN3d+2iZnCq +xnc8UBM6B6aDBJmr7Lam3hZKoTf6UImZZkuA5YPyw8/U+VzaIy5TVXwfkBwi71pmcxrSH77oe6IL +GfmIOhYAw41Te2wOyDVlzn8Vo2G0hYfZKFy+fnKO6OiV1AMlIuHV7lml + +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +Krg+toNNjWTOtLB7J9ICpkNTWo6gRHAJDbjsDio2Lv1/WlEiq9ReTOYL6NyE9FJ3Wz0ynkqwFiIS +mAqyskjaVViOigLWIoJ4h1XW0479eObbDIEmbFayn41qWz8hJ+AvfHHjnkqcTkY/eqZ4atrP7j1l +st8VvyXxNZBNqFkasy2IbK+G+GV2CKpmj6KL1fD4q1EojcXfWRODBuvRPIPU0Zpem7T80e+SaDjR ++zY7ZcofKVqyQ3QNYQBRAYuAboy84ncmS6N/qC9s1xFYufcFh/q9AsWoHWjIFzRj5k3lfnZt8W11 +ar1/9CgDbvd+h9Mk/JXOfivCZddXg3niX3Ht4Q== + +`pragma protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +i/KxwiOmy3zGpwwTOmjI5Mf8vZRDNwRe/AWTgtOGFQJdFEz8i6w+Qim2sK8z/LaqnJ8cD8sSRZ0t +TP82M1p7pX3J/hwpFgN8HLS7IkiwwxNVel1czQbf9RQmtG0v1KLqltnIJ8e591AssJLoJCjrD3jM +2z91dX0Z697YH8T6biMwthpRfuN6mEx9fCZzbmexuVQNEmw8eA25XJYYAlKNve/4ejmRvsl/p3wB +lMPMMRun6SusaE8i6EwxXSlFrxxJQy3fTLYi+TF1hn2qC5ClqbDKPc8H1FPWh5tsPswTZZluZkvM +sqjk2jrXlLgufCxKs4ZXwkLei4A/IQg49Px3VQ== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +OCA61VYAWaBcZwd1Mg766emW5c94pNdxo2em8rWQA357twogpo3DbI+37q4TNaI3XlbdjgiuZAQX +/2OqdKqcuHBA0uNgUCqcovKJBTHLoXvLS7snfrxCb4IcCDjtPJrvxsI847HzRjicANZkoeyaD3tK +6byB+nfwrOttFQzqDjIt52+lWoMhWvmf/yxTTORbG66Qn0mvPxiao1QDdktQr0O4u4Ta5ceCx0vY +ypW7SUUyBF3bOPaokUXePeCi2r9EfD5OhH25tZ/VmQ7e/J48GM7A0n+wh3owefJGhRYhh2SOijwo +rLh48AhZiRrkJ84wVDDuxrdrnD0G6NY3+CYBgA== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 438576) +`pragma protect data_block +rQH1tT9hy9pHWcpbE9/8W2kiyoVQtDGfy2QCWl9zgnryLBpnYldJQYh41pzq9eQ8TSwd4xnGEsWX +fvY6PMFLbjBAZpSGLag7RiLJKkFyk7OciqcLIEdCJ/xdCr2QlyrU35Y/MjJJUngRY5E9ZZ5njG71 +gBYnG/SjSSc9Ttj2gRCxhikFb3eK6KW8x4hFObK8+4lBCoH1s/8FT/wfxWzHyt33/98Ptluru+NU +ZJo4v1z+i4BFgpKi5i1IvkJl80zQkLsMkmj3SdqgcCpEqmMkjnavxmLzDZprh+4YgS3FCf9QUNFi +NuB/V1Md/Jl9tZdANIbNG6H2sUjCLaGpsuPurP99hMc4DmqnyjYTHYrVGdgfRC0/KrV/m9tCxEXq +EjTtipPeJJB4BmQER6CMzLgaULkAblYW51XXW+tweS430hOSiAfoVPxiPJxMqJuyQdeSuny3PE1W +ejzrtSg9Qthf1hA8wTlv/j4GMcFWaWtuFGNjfRYa6zgYDoo1AZJozLLBkXlGwO9bNOSglIMoIupl ++ZtrJmJFADjklGSyMvx4VfhOTlpq7Szp1mFatEW/ITdWWt12wftEJfukJc+Q/dZXojuofgYBPcUs +4h8qbm/ZboojZzu2X4Xd0QSjmbU9wCRSimHuNxffGBV9xbg2F/XqRFKCHM4TMiIEiPBANnZRU4hZ +2d+Og08ILLCF66hawhvKpmO+LAGNrDnFeKZhppy5sdjoTy6/G4orhfraj/Bf5VZcCYeT0HOJEq6c +85N2HgKXW0qCHEkJkTW99QREsc7SO15wKCkNtW2ww1dhmHGd8w2Vv9FvMHZe8wlKgIke4DgAbu40 +yvqBudAuMDKgCSSi9Qw33jrKOPofFYtVI5xCjgNs0V19tX8bpMg5amSizbnHcNmjVi7FaRzqCfjQ +lFmrIlYmP5Qy70roh6m58vgsReLISVgrI6NZCBxhCb2Q0O3UYs14PlpThShxGk2G6vYDViyamG7x +cQyCkTtxw2DNJYSfCWg4xV/9a/QZf5KcFc83DxF7mD2p88Fqb83pWkU8M7xTRUZFKdwhqLHZlNBs +9vZXNZO1lo+nRhadalAF7sMc2gR6hmUHlXFXG1JEldid2dD+UmR4ztBSJUYzQ9jNUnEB7hPNTY1x +/dbENDk79uCwLhekHBXRNvYqBt6XWpyQPBisDfwzkM+mx6Zen85u5fKfU4d0PnDSu/kXFaqFfNw8 +Yotid1wVrmYy40GQzfdtN0oL/1GIH0Vlwu1UQYsOAm85NwWvltE/HiLhiqk135089265cH9F/pKX +jD6bpQyE/69++8nYN934mt5DyzqsJAFEIqoSTyGtbgkQZs73ILZIbT2hMBRRU+pGYJj+2XNoTdMS +N/S3shw1K1A8wUcnO199R3vECyWeunIfFDA5WwLH0Jm+P7D4uzrhB7hJT7wmEfPLLu4t72GhScNs +S5qcfH7oE6ul8iJ2d8WFJo89qUR6Z3oMsu1hSkMGhuHhm5QuC5t/Qoh9Dn761wNNXeLgtHOo949c +c+tGTF/luV7h43gcKsVtugIncMAHeWIEQ8e5/kqkjld10u3Y/3Dckg/ixKrY5sHAa5/68yonkC7L +sQgISWUOYG9fiyoYvFfcv9dDmq9CzYj48DH0g+oGgQTWu3uyyxiN8pPZsH50YIpDBJwzIEtdO16H ++Eo03X/pUzajRYVGZNpygL6Bhv0Nh9HNgx+Od5SORd/uJBGtN9k9DMsEGNqb2w1dlsiChjQKIovM +XXazbd1gCIrhXd4c3WzNGghjXch4NhOGPtpeD1lIpFmkTUVhMITBlm/g/DSxzDcipTdFHcz9r4NP +zYvEQwhgWH41d3n3WT3aG5epzWFBb3ZJolA0vuZf23iCRw9b7B5EmD4teoOns/64WrVTRozFZfcc +mVXfJV502rsJN+Y7JAkcOIksQTat07wFTmgsD3SphIQS0W55Tcc+NnsEtyciuRwykrGM7In4KBe0 +kLzqW4uhGVe6v2HOQrX27b0sFbGsT0RISNCQeqCAu1I2r6CBdapTNOb6/qncLFFkv0OEard5WZSr +IdVO6ns6CpB0ccXMg3CEOXuLZDlRJLEDxO0vXHSIOxTqCP6oSJH/dyW3DRvezS3EDjK33CqfQX/H +i1jxIiG7wyUEsCJYcui/GYzycV3PQ17CvW+PFKDXgU3uSwwaw5ybC5jP0Iif9kjrgJeVjm0lfgly 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+++ b/project_1.srcs/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.vhd @@ -0,0 +1,18860 @@ +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2022.2" +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +uS/dIpDTldS7400uyLsI6bJxO+WmZJrKXsU8qB+wpyI+d4PWZVO6Cm0qMQFNUZb63p6zCI5fvnQy +SxjaSP1nCte/oQZc55w1rQbTqy54T9kryRoH26nDjSBVZvJ8hffw7NONwiKrqeB6I7HJKX5RKw73 +wIJxNNH7BCiCEtRLIxc= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +L7q2sHnC0pU7uHs8shPm9nAcqyU+hUFnNkd6BPHl+ureEVBUvubWhEbLRLiFFJveufcmAfAXTzae +tWbKcVVt/zKzWEtv0onUXoSEgyS4+QaTAFeCPHR2bbnlP0aCCG2SYmC1dv16cFoAk/NLitClNXAv +h+UBGzod+suWv55DaNHeHtSZ/YLZxHdn/R47atTiQM+A1TWQkpa3faF/L9ANZISSe/OR6mPfQ/Zk +4AptHNmW/pWpd3JL4e06iK9P6ZLLRqSMR9mu6AFIeWYBVz+KkxgSIWgQO7/AHBUFjlIiMFhyQR5Y +UC1fo4CPZX7fMdUPwQiC+eZ7UtxMAUzovIzwEw== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +KZhqqPnSEvcItoYRHrFT/Wt2IEXHe7pq5lmAOfYqAaaoY8mpIG3Kd8B/C4s9kNUbktSOX78NnnrJ +brxcu/1EAlI9itnDH8ahxble+2Nt/Lj3dQ1/wbDy3HOKlwBVuOvVDArOpgho+BAnoLUZXrpsw8EI +FSIPKmsETVzLzZDw6m0= + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +WZbb0PsQl1vn7dY/rZzI8ZGsAP5Ad4C/d2cBXS49yTbQqKMTY7r1YHlrjBGteY6wrhKVmM92u/3/ +/UJWPyNVqwcsrRAHhR/Lp3Mg87NIhYzETdNAOpnc7rWC9ieIeEiyPM734sI7QtAMVrZxXoUXnCjp +fjQhaMqv+HsuEWpFhDail+v8Ftwmr5xP1JSpqPfxLz5a6+q8/lTxRGeWZokM7vP2YFKg7L7Yoowh +gOm5w3JhR2fXZsksWxfQk7885JzsI4yZOrU8dY667YWWhkjZE/SKo2TMksiasL22T6CpyUbMwQm2 +DJ+cMJbr9/8csBEifIsopc4V9zFbSU9eoxlqZA== + +`protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +Adid/GOKDljgmM7UpkmD6EVL+5rt6bnWK9P8RIZiI3EkLW96rM6eCs7jkLeKnEW/WPGRhlZrGw8p +C7Ni27oibJKJT5xUBJDymbO+yheaaTI0GaeDMIzks860gYA3qdvTPxTBotaOg6MIpnYd070NhTod +Qq5XNnxLuF7/s5rAZANJHyRQKwu4gVBfs5SU2FSjF546M5FvN7BX6G7B76ALW6vKqGyKxwoHkc52 +Bm8/jGTxJ6zbwn2v31NEfjO6nM5m6yYwY0476QLXWI6+7/ILkSvDVTt7B9HpcaRg3n3T4AEQDMyX +8bBPgm0qFbWZue0dlr9ljYOl0dgwaO8G9uYe9g== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2021_07", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +tq2b3cw7fnIOEbRUxnQIgAjXwRE3aRwj2IBVmS0S998fvCLPMUtm5MVXAqk0TwuEzKG3br/oRham +Oe5KAx6FauTTVpRhLH5RY3832M9OVTSW/bNq12/dXnJyOfYS76FQtd9HNFrSkVPMONGMD0ZQXRic +Yr0MaeflUHQmU6QUCt5OJkbG4F8qJLMWJsg03K7dNzDfkvev3QVf72bmHTm4SF6/cs94NXQl/NPr +CzQorTZ5BgCzVAui7mM0eu3mu6OPkecNQ3Ih+1zsJuGkAHWC7aFgh7ii6xEj1upD365TzJUF1ZCe +0jZj/Ub1m5OgZMbjbLYn/Fh5nqi+fAmL7jDAHQ== + +`protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +S+EkimFGNL3D/SKyjUVYhIZzRbEoTqlnv2kHD0e4rYYCt/O4IYecNmch6HRfd2U/WSZPkAoJ+xa7 +GKQSo51PL81HSvqURo2CxltObyTYiklnzGtbdWUMpOSCjDe8LpQjUNwhSksWjZjUQypyYXS4hbCR +VJy96ow8zi5m1XMzoLaVMDYoJYLtOVh7eaL7InaIL5gXJIHWkhoKYh9bR/O5HE6YTsgZl+Ofmx/3 +0mQ/bL5ZKSY6gBEUD8f5+SoMIjfXrGkjMj1+fEAIv0fO/wKyJQMKnDOgWMvcUw56dOJ7FWkbNvbC +kzquuXhk5LuzZfXWmhyDSyMGBWK1wN7iyMKMUg== + +`protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384) +`protect key_block +LQ4hjhkD/G9XJd+gVR5WF2vSll/p8/psR+nHjJ5/DHrtiRqVWFVc7B7T9XZuJBmTqrQV4iSBYWDo +zNaVdq26mGk6TTNo11Dcici0hEwC2Bg66k9kr1if+0iZo3VtB/ZuEOj2w7euhFo3ja1OovnDXxf0 +8t4WMUK68mfUiMuKgVcbOFhm3Jdnbnz4u7SggH2/rkfOS8jbon9q9n0EXlK23tz2NzDLCS8B7ERx +dYvwqwBiySKoP1/EcfSwFNIWpr6p7kbRo7iM/JbP6UwBbkDHgE8HGS+3lTXIUXsmGmsx6EDSr/gY +i7lHwZTmDuhuIEJaf6gTJgtqMSxVyDVsrnba5umKgV8z5OOWUkM3FjVWIXOG7Ef2iKFCzBPmp2Lk +8XbrXk/bb9H/jr4UR3hgdbizISTysLTJd4n5uyeDhDgkxAc+1FudacmuZyBlA/VTR1f0i9+cOgLI +kdqbo1u5hQwnMphluBKjdTA3nZ8VnpDbdq5R7hIF61tIrUfdjwQw02je + +`protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +JzhYMwmYowESMI19XNb+BEFcZw3IXZpwZO3gzrVg2CdSjbAR3tiIVbPHI5Rgu59SH7H8abU59Atd ++nrPiG37rmU6CD+cMV2mU8SHfCDLYsnrbd9YLZ1GEfqTovR0NZHQTHj+7c5dP7nqm30C/kg1adqd +DOV7F128PbmM5U45xRxOJKUgS/Waz0gvmYKKJejkiyFPOgGbN5f844mtysoOckLrAU/BzRs8SB9G +zzisK/a8hM5af8/opZ64TGhH44Npzy8kcP+gI+k+U0oF0SOqW7CjadKaJhr2oDkTScVVCbBqFEjc +2gH862vcCfZu5Cd0Sp2ALgoqVxA+91lAIHJp3Q== + +`protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +ooNS+XjsaWLRgvcrNWVpR3ihKtIJNT1oT4D5ivD5mCfw+4/SAyx9P4cmdvOotLNPE1eqvx1Smd9Q +LDImL/GqS7Cq3KEUtEBbvQAOp+0SjiW74cC6nyOqCA8NQcn5JM+vUzGSsORPnM5qP96axGmyEvSi +p3uL9Gmx+3S3KUJuAzfuqZwJD7gdcA0Zv3hPRl+xhx8qFtkPCfT5uj7wpFVaaJ8tTl1SDd2uRUIx +rgVgV+oERCg71oEVN7PqPK1y7pFVgSW9uhP1wuvO/EsbyrLYZV6HtBn3tJDcxhTsQWrrou3F1kFQ +cFnl9tcL1wXJo/F3wvsbYM1W0UPHv69XAsEUhg== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +d8YRbu+fllaHlNDedyRNDRtn9CBoVbO9fZCdhKpy0yf9dL6A08sFZuWVtVGljxF/L9volGB0IRjl +KbH2N/JBQA+tZWuh75kK5pjveAAKLVACS8A+Jmt/mrxzlolPWsruJ8o1Owrjq5tGWspdqmeDGS7U +/Ww7cN0C9ExUj4cjRDcKaqDS9MGwRtx4LfcQbQbRDZBk+cyRaWCchvmhjoum4uTizvqMq2u4oSym +t2zyKFjAuMO4zC2LbPbODeumm+FhlOKAHRyEBKA+VQeLB4apkMYparuD5AFWAuVvdWEbGq/L4cJ7 +pEGz+6Hqi68CfF/4tMNiyHveP1lxnyAaiW6Kjg== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1069024) +`protect data_block +Bx1lRc1LaVMCuk+5VmoIGiHApzmhLNh/zpjnVlHhx/KrZ/KnaE8Jn4Xz243Qk48Z4Dzr8itzBY0H +q9wBk69IoFiYUEqlrK70siemQW7kVQ4yKjvWfglOm2trXzEhspZdSVE/q9/ZkOlPNb5+b2tRPu4C +1yYq0cEiHfr1rDaV8MXeHFUiZeb6HX5c2Kuq9pn/8ooKAyHwy7YIXN+GswYpZ9wAV7oiCJR6YrZ+ +edDle4sfH+K0QIGEpZPWdLWQsmr2YdZBPfDViGYS2LzNG3tIE1NE7udiVbdWzQkFLwjfVZXdJh4O +bVLpkdsojbNZnOd02Bj+/MHukQXqBkd6EIIHUU6/bLTImWHNyy5I5CX6wu4EJT/er3R9T8eaHisq +MhCe2onV9pIsdDwzUFsxu96P5BevIUOl2xXgxj9IRe0R1HwM5eAo50zf5lVtbnIFdE8GKvrhVwq0 +7ht5DoK/d25o+d3ImLXLC1mDxk+hi5JQHi9LjtSuj+EqSg7ODT6zR8UTmsoOvPYW1MHu60PAhcVd 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All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_vlog_beh.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_vlog_beh.v + * | + * +-fifo_generator_v13_2_7_bhv_ver_as + * | + * +-fifo_generator_v13_2_7_bhv_ver_ss + * | + * +-fifo_generator_v13_2_7_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_vlog_beh + #( + //----------------------------------------------------------------------- + // Generic Declarations + //----------------------------------------------------------------------- + parameter C_COMMON_CLOCK = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "", + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 1, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "4kx4", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_PIPELINE_REG = 0, + parameter C_POWER_SAVING_MODE = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2, + + // AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3 + parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3 + parameter C_HAS_AXI_WR_CHANNEL = 0, + parameter C_HAS_AXI_RD_CHANNEL = 0, + parameter C_HAS_SLAVE_CE = 0, + parameter C_HAS_MASTER_CE = 0, + parameter C_ADD_NGC_CONSTRAINT = 0, + parameter C_USE_COMMON_UNDERFLOW = 0, + parameter C_USE_COMMON_OVERFLOW = 0, + parameter C_USE_DEFAULT_SETTINGS = 0, + + // AXI Full/Lite + parameter C_AXI_ID_WIDTH = 0, + parameter C_AXI_ADDR_WIDTH = 0, + parameter C_AXI_DATA_WIDTH = 0, + parameter C_AXI_LEN_WIDTH = 8, + parameter C_AXI_LOCK_WIDTH = 2, + parameter C_HAS_AXI_ID = 0, + parameter C_HAS_AXI_AWUSER = 0, + parameter C_HAS_AXI_WUSER = 0, + parameter C_HAS_AXI_BUSER = 0, + parameter C_HAS_AXI_ARUSER = 0, + parameter C_HAS_AXI_RUSER = 0, + parameter C_AXI_ARUSER_WIDTH = 0, + parameter C_AXI_AWUSER_WIDTH = 0, + parameter C_AXI_WUSER_WIDTH = 0, + parameter C_AXI_BUSER_WIDTH = 0, + parameter C_AXI_RUSER_WIDTH = 0, + + // AXI Streaming + parameter C_HAS_AXIS_TDATA = 0, + parameter C_HAS_AXIS_TID = 0, + parameter C_HAS_AXIS_TDEST = 0, + parameter C_HAS_AXIS_TUSER = 0, + parameter C_HAS_AXIS_TREADY = 0, + parameter C_HAS_AXIS_TLAST = 0, + parameter C_HAS_AXIS_TSTRB = 0, + parameter C_HAS_AXIS_TKEEP = 0, + parameter C_AXIS_TDATA_WIDTH = 1, + parameter C_AXIS_TID_WIDTH = 1, + parameter C_AXIS_TDEST_WIDTH = 1, + parameter C_AXIS_TUSER_WIDTH = 1, + parameter C_AXIS_TSTRB_WIDTH = 1, + parameter C_AXIS_TKEEP_WIDTH = 1, + + // AXI Channel Type + // WACH --> Write Address Channel + // WDCH --> Write Data Channel + // WRCH --> Write Response Channel + // RACH --> Read Address Channel + // RDCH --> Read Data Channel + // AXIS --> AXI Streaming + parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic + parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + + // AXI Implementation Type + // 1 = Common Clock Block RAM FIFO + // 2 = Common Clock Distributed RAM FIFO + // 11 = Independent Clock Block RAM FIFO + // 12 = Independent Clock Distributed RAM FIFO + parameter C_IMPLEMENTATION_TYPE_WACH = 0, + parameter C_IMPLEMENTATION_TYPE_WDCH = 0, + parameter C_IMPLEMENTATION_TYPE_WRCH = 0, + parameter C_IMPLEMENTATION_TYPE_RACH = 0, + parameter C_IMPLEMENTATION_TYPE_RDCH = 0, + parameter C_IMPLEMENTATION_TYPE_AXIS = 0, + + // AXI FIFO Type + // 0 = Data FIFO + // 1 = Packet FIFO + // 2 = Low Latency Sync FIFO + // 3 = Low Latency Async FIFO + parameter C_APPLICATION_TYPE_WACH = 0, + parameter C_APPLICATION_TYPE_WDCH = 0, + parameter C_APPLICATION_TYPE_WRCH = 0, + parameter C_APPLICATION_TYPE_RACH = 0, + parameter C_APPLICATION_TYPE_RDCH = 0, + parameter C_APPLICATION_TYPE_AXIS = 0, + + // AXI Built-in FIFO Primitive Type + // 512x36, 1kx18, 2kx9, 4kx4, etc + parameter C_PRIM_FIFO_TYPE_WACH = "512x36", + parameter C_PRIM_FIFO_TYPE_WDCH = "512x36", + parameter C_PRIM_FIFO_TYPE_WRCH = "512x36", + parameter C_PRIM_FIFO_TYPE_RACH = "512x36", + parameter C_PRIM_FIFO_TYPE_RDCH = "512x36", + parameter C_PRIM_FIFO_TYPE_AXIS = "512x36", + + // Enable ECC + // 0 = ECC disabled + // 1 = ECC enabled + parameter C_USE_ECC_WACH = 0, + parameter C_USE_ECC_WDCH = 0, + parameter C_USE_ECC_WRCH = 0, + parameter C_USE_ECC_RACH = 0, + parameter C_USE_ECC_RDCH = 0, + parameter C_USE_ECC_AXIS = 0, + + // ECC Error Injection Type + // 0 = No Error Injection + // 1 = Single Bit Error Injection + // 2 = Double Bit Error Injection + // 3 = Single Bit and Double Bit Error Injection + parameter C_ERROR_INJECTION_TYPE_WACH = 0, + parameter C_ERROR_INJECTION_TYPE_WDCH = 0, + parameter C_ERROR_INJECTION_TYPE_WRCH = 0, + parameter C_ERROR_INJECTION_TYPE_RACH = 0, + parameter C_ERROR_INJECTION_TYPE_RDCH = 0, + parameter C_ERROR_INJECTION_TYPE_AXIS = 0, + + // Input Data Width + // Accumulation of all AXI input signal's width + parameter C_DIN_WIDTH_WACH = 1, + parameter C_DIN_WIDTH_WDCH = 1, + parameter C_DIN_WIDTH_WRCH = 1, + parameter C_DIN_WIDTH_RACH = 1, + parameter C_DIN_WIDTH_RDCH = 1, + parameter C_DIN_WIDTH_AXIS = 1, + + parameter C_WR_DEPTH_WACH = 16, + parameter C_WR_DEPTH_WDCH = 16, + parameter C_WR_DEPTH_WRCH = 16, + parameter C_WR_DEPTH_RACH = 16, + parameter C_WR_DEPTH_RDCH = 16, + parameter C_WR_DEPTH_AXIS = 16, + + parameter C_WR_PNTR_WIDTH_WACH = 4, + parameter C_WR_PNTR_WIDTH_WDCH = 4, + parameter C_WR_PNTR_WIDTH_WRCH = 4, + parameter C_WR_PNTR_WIDTH_RACH = 4, + parameter C_WR_PNTR_WIDTH_RDCH = 4, + parameter C_WR_PNTR_WIDTH_AXIS = 4, + + parameter C_HAS_DATA_COUNTS_WACH = 0, + parameter C_HAS_DATA_COUNTS_WDCH = 0, + parameter C_HAS_DATA_COUNTS_WRCH = 0, + parameter C_HAS_DATA_COUNTS_RACH = 0, + parameter C_HAS_DATA_COUNTS_RDCH = 0, + parameter C_HAS_DATA_COUNTS_AXIS = 0, + + parameter C_HAS_PROG_FLAGS_WACH = 0, + parameter C_HAS_PROG_FLAGS_WDCH = 0, + parameter C_HAS_PROG_FLAGS_WRCH = 0, + parameter C_HAS_PROG_FLAGS_RACH = 0, + parameter C_HAS_PROG_FLAGS_RDCH = 0, + parameter C_HAS_PROG_FLAGS_AXIS = 0, + + parameter C_PROG_FULL_TYPE_WACH = 0, + parameter C_PROG_FULL_TYPE_WDCH = 0, + parameter C_PROG_FULL_TYPE_WRCH = 0, + parameter C_PROG_FULL_TYPE_RACH = 0, + parameter C_PROG_FULL_TYPE_RDCH = 0, + parameter C_PROG_FULL_TYPE_AXIS = 0, + + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0, + + parameter C_PROG_EMPTY_TYPE_WACH = 0, + parameter C_PROG_EMPTY_TYPE_WDCH = 0, + parameter C_PROG_EMPTY_TYPE_WRCH = 0, + parameter C_PROG_EMPTY_TYPE_RACH = 0, + parameter C_PROG_EMPTY_TYPE_RDCH = 0, + parameter C_PROG_EMPTY_TYPE_AXIS = 0, + + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0, + + parameter C_REG_SLICE_MODE_WACH = 0, + parameter C_REG_SLICE_MODE_WDCH = 0, + parameter C_REG_SLICE_MODE_WRCH = 0, + parameter C_REG_SLICE_MODE_RACH = 0, + parameter C_REG_SLICE_MODE_RDCH = 0, + parameter C_REG_SLICE_MODE_AXIS = 0 + + ) + + ( + //------------------------------------------------------------------------------ + // Input and Output Declarations + //------------------------------------------------------------------------------ + + // Conventional FIFO Interface Signals + input backup, + input backup_marker, + input clk, + input rst, + input srst, + input wr_clk, + input wr_rst, + input rd_clk, + input rd_rst, + input [C_DIN_WIDTH-1:0] din, + input wr_en, + input rd_en, + // Optional inputs + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh, + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert, + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate, + input int_clk, + input injectdbiterr, + input injectsbiterr, + input sleep, + + output [C_DOUT_WIDTH-1:0] dout, + output full, + output almost_full, + output wr_ack, + output overflow, + output empty, + output almost_empty, + output valid, + output underflow, + output [C_DATA_COUNT_WIDTH-1:0] data_count, + output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count, + output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count, + output prog_full, + output prog_empty, + output sbiterr, + output dbiterr, + output wr_rst_busy, + output rd_rst_busy, + + + // AXI Global Signal + input m_aclk, + input s_aclk, + input s_aresetn, + input s_aclk_en, + input m_aclk_en, + + // AXI Full/Lite Slave Write Channel (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen, + input [3-1:0] s_axi_awsize, + input [2-1:0] s_axi_awburst, + input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock, + input [4-1:0] s_axi_awcache, + input [3-1:0] s_axi_awprot, + input [4-1:0] s_axi_awqos, + input [4-1:0] s_axi_awregion, + input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input s_axi_awvalid, + output s_axi_awready, + input [C_AXI_ID_WIDTH-1:0] s_axi_wid, + input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input s_axi_wlast, + input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input s_axi_wvalid, + output s_axi_wready, + output [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output [2-1:0] s_axi_bresp, + output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output s_axi_bvalid, + input s_axi_bready, + + // AXI Full/Lite Master Write Channel (read side) + output [C_AXI_ID_WIDTH-1:0] m_axi_awid, + output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen, + output [3-1:0] m_axi_awsize, + output [2-1:0] m_axi_awburst, + output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock, + output [4-1:0] m_axi_awcache, + output [3-1:0] m_axi_awprot, + output [4-1:0] m_axi_awqos, + output [4-1:0] m_axi_awregion, + output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output m_axi_awvalid, + input m_axi_awready, + output [C_AXI_ID_WIDTH-1:0] m_axi_wid, + output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output m_axi_wlast, + output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output m_axi_wvalid, + input m_axi_wready, + input [C_AXI_ID_WIDTH-1:0] m_axi_bid, + input [2-1:0] m_axi_bresp, + input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input m_axi_bvalid, + output m_axi_bready, + + + // AXI Full/Lite Slave Read Channel (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen, + input [3-1:0] s_axi_arsize, + input [2-1:0] s_axi_arburst, + input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock, + input [4-1:0] s_axi_arcache, + input [3-1:0] s_axi_arprot, + input [4-1:0] s_axi_arqos, + input [4-1:0] s_axi_arregion, + input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input s_axi_arvalid, + output s_axi_arready, + output [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output [2-1:0] s_axi_rresp, + output s_axi_rlast, + output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output s_axi_rvalid, + input s_axi_rready, + + + + // AXI Full/Lite Master Read Channel (read side) + output [C_AXI_ID_WIDTH-1:0] m_axi_arid, + output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen, + output [3-1:0] m_axi_arsize, + output [2-1:0] m_axi_arburst, + output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock, + output [4-1:0] m_axi_arcache, + output [3-1:0] m_axi_arprot, + output [4-1:0] m_axi_arqos, + output [4-1:0] m_axi_arregion, + output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output m_axi_arvalid, + input m_axi_arready, + input [C_AXI_ID_WIDTH-1:0] m_axi_rid, + input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input [2-1:0] m_axi_rresp, + input m_axi_rlast, + input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input m_axi_rvalid, + output m_axi_rready, + + + // AXI Streaming Slave Signals (Write side) + input s_axis_tvalid, + output s_axis_tready, + input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, + input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb, + input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep, + input s_axis_tlast, + input [C_AXIS_TID_WIDTH-1:0] s_axis_tid, + input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, + input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, + + // AXI Streaming Master Signals (Read side) + output m_axis_tvalid, + input m_axis_tready, + output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, + output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb, + output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep, + output m_axis_tlast, + output [C_AXIS_TID_WIDTH-1:0] m_axis_tid, + output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, + output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser, + + + + + // AXI Full/Lite Write Address Channel signals + input axi_aw_injectsbiterr, + input axi_aw_injectdbiterr, + input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count, + output axi_aw_sbiterr, + output axi_aw_dbiterr, + output axi_aw_overflow, + output axi_aw_underflow, + output axi_aw_prog_full, + output axi_aw_prog_empty, + + + // AXI Full/Lite Write Data Channel signals + input axi_w_injectsbiterr, + input axi_w_injectdbiterr, + input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count, + output axi_w_sbiterr, + output axi_w_dbiterr, + output axi_w_overflow, + output axi_w_underflow, + output axi_w_prog_full, + output axi_w_prog_empty, + + + // AXI Full/Lite Write Response Channel signals + input axi_b_injectsbiterr, + input axi_b_injectdbiterr, + input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count, + output axi_b_sbiterr, + output axi_b_dbiterr, + output axi_b_overflow, + output axi_b_underflow, + output axi_b_prog_full, + output axi_b_prog_empty, + + + + // AXI Full/Lite Read Address Channel signals + input axi_ar_injectsbiterr, + input axi_ar_injectdbiterr, + input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh, + input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count, + output axi_ar_sbiterr, + output axi_ar_dbiterr, + output axi_ar_overflow, + output axi_ar_underflow, + output axi_ar_prog_full, + output axi_ar_prog_empty, + + + // AXI Full/Lite Read Data Channel Signals + input axi_r_injectsbiterr, + input axi_r_injectdbiterr, + input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh, + input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count, + output axi_r_sbiterr, + output axi_r_dbiterr, + output axi_r_overflow, + output axi_r_underflow, + output axi_r_prog_full, + output axi_r_prog_empty, + + + // AXI Streaming FIFO Related Signals + input axis_injectsbiterr, + input axis_injectdbiterr, + input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh, + input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count, + output axis_sbiterr, + output axis_dbiterr, + output axis_overflow, + output axis_underflow, + output axis_prog_full, + output axis_prog_empty + + ); + + wire BACKUP; + wire BACKUP_MARKER; + wire CLK; + wire RST; + wire SRST; + wire WR_CLK; + wire WR_RST; + wire RD_CLK; + wire RD_RST; + wire [C_DIN_WIDTH-1:0] DIN; + wire WR_EN; + wire RD_EN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire INT_CLK; + wire INJECTDBITERR; + wire INJECTSBITERR; + wire SLEEP; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire FULL; + wire ALMOST_FULL; + wire WR_ACK; + wire OVERFLOW; + wire EMPTY; + wire ALMOST_EMPTY; + wire VALID; + wire UNDERFLOW; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + wire PROG_FULL; + wire PROG_EMPTY; + wire SBITERR; + wire DBITERR; + wire WR_RST_BUSY; + wire RD_RST_BUSY; + wire M_ACLK; + wire S_ACLK; + wire S_ARESETN; + wire S_ACLK_EN; + wire M_ACLK_EN; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID; + wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR; + wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN; + wire [3-1:0] S_AXI_AWSIZE; + wire [2-1:0] S_AXI_AWBURST; + wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK; + wire [4-1:0] S_AXI_AWCACHE; + wire [3-1:0] S_AXI_AWPROT; + wire [4-1:0] S_AXI_AWQOS; + wire [4-1:0] S_AXI_AWREGION; + wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER; + wire S_AXI_AWVALID; + wire S_AXI_AWREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID; + wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA; + wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB; + wire S_AXI_WLAST; + wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER; + wire S_AXI_WVALID; + wire S_AXI_WREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; + wire [2-1:0] S_AXI_BRESP; + wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER; + wire S_AXI_BVALID; + wire S_AXI_BREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID; + wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR; + wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN; + wire [3-1:0] M_AXI_AWSIZE; + wire [2-1:0] M_AXI_AWBURST; + wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK; + wire [4-1:0] M_AXI_AWCACHE; + wire [3-1:0] M_AXI_AWPROT; + wire [4-1:0] M_AXI_AWQOS; + wire [4-1:0] M_AXI_AWREGION; + wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER; + wire M_AXI_AWVALID; + wire M_AXI_AWREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID; + wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA; + wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB; + wire M_AXI_WLAST; + wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER; + wire M_AXI_WVALID; + wire M_AXI_WREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID; + wire [2-1:0] M_AXI_BRESP; + wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER; + wire M_AXI_BVALID; + wire M_AXI_BREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID; + wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR; + wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN; + wire [3-1:0] S_AXI_ARSIZE; + wire [2-1:0] S_AXI_ARBURST; + wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK; + wire [4-1:0] S_AXI_ARCACHE; + wire [3-1:0] S_AXI_ARPROT; + wire [4-1:0] S_AXI_ARQOS; + wire [4-1:0] S_AXI_ARREGION; + wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER; + wire S_AXI_ARVALID; + wire S_AXI_ARREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; + wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA; + wire [2-1:0] S_AXI_RRESP; + wire S_AXI_RLAST; + wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER; + wire S_AXI_RVALID; + wire S_AXI_RREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID; + wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR; + wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN; + wire [3-1:0] M_AXI_ARSIZE; + wire [2-1:0] M_AXI_ARBURST; + wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK; + wire [4-1:0] M_AXI_ARCACHE; + wire [3-1:0] M_AXI_ARPROT; + wire [4-1:0] M_AXI_ARQOS; + wire [4-1:0] M_AXI_ARREGION; + wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER; + wire M_AXI_ARVALID; + wire M_AXI_ARREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID; + wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA; + wire [2-1:0] M_AXI_RRESP; + wire M_AXI_RLAST; + wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER; + wire M_AXI_RVALID; + wire M_AXI_RREADY; + wire S_AXIS_TVALID; + wire S_AXIS_TREADY; + wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA; + wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB; + wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP; + wire S_AXIS_TLAST; + wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID; + wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST; + wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER; + wire M_AXIS_TVALID; + wire M_AXIS_TREADY; + wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA; + wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB; + wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP; + wire M_AXIS_TLAST; + wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID; + wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST; + wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER; + wire AXI_AW_INJECTSBITERR; + wire AXI_AW_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT; + wire AXI_AW_SBITERR; + wire AXI_AW_DBITERR; + wire AXI_AW_OVERFLOW; + wire AXI_AW_UNDERFLOW; + wire AXI_AW_PROG_FULL; + wire AXI_AW_PROG_EMPTY; + wire AXI_W_INJECTSBITERR; + wire AXI_W_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT; + wire AXI_W_SBITERR; + wire AXI_W_DBITERR; + wire AXI_W_OVERFLOW; + wire AXI_W_UNDERFLOW; + wire AXI_W_PROG_FULL; + wire AXI_W_PROG_EMPTY; + wire AXI_B_INJECTSBITERR; + wire AXI_B_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT; + wire AXI_B_SBITERR; + wire AXI_B_DBITERR; + wire AXI_B_OVERFLOW; + wire AXI_B_UNDERFLOW; + wire AXI_B_PROG_FULL; + wire AXI_B_PROG_EMPTY; + wire AXI_AR_INJECTSBITERR; + wire AXI_AR_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT; + wire AXI_AR_SBITERR; + wire AXI_AR_DBITERR; + wire AXI_AR_OVERFLOW; + wire AXI_AR_UNDERFLOW; + wire AXI_AR_PROG_FULL; + wire AXI_AR_PROG_EMPTY; + wire AXI_R_INJECTSBITERR; + wire AXI_R_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT; + wire AXI_R_SBITERR; + wire AXI_R_DBITERR; + wire AXI_R_OVERFLOW; + wire AXI_R_UNDERFLOW; + wire AXI_R_PROG_FULL; + wire AXI_R_PROG_EMPTY; + wire AXIS_INJECTSBITERR; + wire AXIS_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT; + wire AXIS_SBITERR; + wire AXIS_DBITERR; + wire AXIS_OVERFLOW; + wire AXIS_UNDERFLOW; + wire AXIS_PROG_FULL; + wire AXIS_PROG_EMPTY; + wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in; + wire wr_rst_int; + wire rd_rst_int; + wire wr_rst_busy_o; + wire wr_rst_busy_ntve; + wire wr_rst_busy_axis; + wire wr_rst_busy_wach; + wire wr_rst_busy_wdch; + wire wr_rst_busy_wrch; + wire wr_rst_busy_rach; + wire wr_rst_busy_rdch; + + + + function integer find_log2; + input integer int_val; + integer i,j; + begin + i = 1; + j = 0; + for (i = 1; i < int_val; i = i*2) begin + j = j + 1; + end + find_log2 = j; + end + endfunction + + + + + // Conventional FIFO Interface Signals + assign BACKUP = backup; + assign BACKUP_MARKER = backup_marker; + assign CLK = clk; + assign RST = rst; + assign SRST = srst; + assign WR_CLK = wr_clk; + assign WR_RST = wr_rst; + assign RD_CLK = rd_clk; + assign RD_RST = rd_rst; + assign WR_EN = wr_en; + assign RD_EN = rd_en; + assign INT_CLK = int_clk; + assign INJECTDBITERR = injectdbiterr; + assign INJECTSBITERR = injectsbiterr; + assign SLEEP = sleep; + assign full = FULL; + assign almost_full = ALMOST_FULL; + assign wr_ack = WR_ACK; + assign overflow = OVERFLOW; + assign empty = EMPTY; + assign almost_empty = ALMOST_EMPTY; + assign valid = VALID; + assign underflow = UNDERFLOW; + assign prog_full = PROG_FULL; + assign prog_empty = PROG_EMPTY; + assign sbiterr = SBITERR; + assign dbiterr = DBITERR; +// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o; + assign wr_rst_busy = wr_rst_busy_o; + assign rd_rst_busy = RD_RST_BUSY; + assign M_ACLK = m_aclk; + assign S_ACLK = s_aclk; + assign S_ARESETN = s_aresetn; + assign S_ACLK_EN = s_aclk_en; + assign M_ACLK_EN = m_aclk_en; + assign S_AXI_AWVALID = s_axi_awvalid; + assign s_axi_awready = S_AXI_AWREADY; + assign S_AXI_WLAST = s_axi_wlast; + assign S_AXI_WVALID = s_axi_wvalid; + assign s_axi_wready = S_AXI_WREADY; + assign s_axi_bvalid = S_AXI_BVALID; + assign S_AXI_BREADY = s_axi_bready; + assign m_axi_awvalid = M_AXI_AWVALID; + assign M_AXI_AWREADY = m_axi_awready; + assign m_axi_wlast = M_AXI_WLAST; + assign m_axi_wvalid = M_AXI_WVALID; + assign M_AXI_WREADY = m_axi_wready; + assign M_AXI_BVALID = m_axi_bvalid; + assign m_axi_bready = M_AXI_BREADY; + assign S_AXI_ARVALID = s_axi_arvalid; + assign s_axi_arready = S_AXI_ARREADY; + assign s_axi_rlast = S_AXI_RLAST; + assign s_axi_rvalid = S_AXI_RVALID; + assign S_AXI_RREADY = s_axi_rready; + assign m_axi_arvalid = M_AXI_ARVALID; + assign M_AXI_ARREADY = m_axi_arready; + assign M_AXI_RLAST = m_axi_rlast; + assign M_AXI_RVALID = m_axi_rvalid; + assign m_axi_rready = M_AXI_RREADY; + assign S_AXIS_TVALID = s_axis_tvalid; + assign s_axis_tready = S_AXIS_TREADY; + assign S_AXIS_TLAST = s_axis_tlast; + assign m_axis_tvalid = M_AXIS_TVALID; + assign M_AXIS_TREADY = m_axis_tready; + assign m_axis_tlast = M_AXIS_TLAST; + assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr; + assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr; + assign axi_aw_sbiterr = AXI_AW_SBITERR; + assign axi_aw_dbiterr = AXI_AW_DBITERR; + assign axi_aw_overflow = AXI_AW_OVERFLOW; + assign axi_aw_underflow = AXI_AW_UNDERFLOW; + assign axi_aw_prog_full = AXI_AW_PROG_FULL; + assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY; + assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr; + assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr; + assign axi_w_sbiterr = AXI_W_SBITERR; + assign axi_w_dbiterr = AXI_W_DBITERR; + assign axi_w_overflow = AXI_W_OVERFLOW; + assign axi_w_underflow = AXI_W_UNDERFLOW; + assign axi_w_prog_full = AXI_W_PROG_FULL; + assign axi_w_prog_empty = AXI_W_PROG_EMPTY; + assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr; + assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr; + assign axi_b_sbiterr = AXI_B_SBITERR; + assign axi_b_dbiterr = AXI_B_DBITERR; + assign axi_b_overflow = AXI_B_OVERFLOW; + assign axi_b_underflow = AXI_B_UNDERFLOW; + assign axi_b_prog_full = AXI_B_PROG_FULL; + assign axi_b_prog_empty = AXI_B_PROG_EMPTY; + assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr; + assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr; + assign axi_ar_sbiterr = AXI_AR_SBITERR; + assign axi_ar_dbiterr = AXI_AR_DBITERR; + assign axi_ar_overflow = AXI_AR_OVERFLOW; + assign axi_ar_underflow = AXI_AR_UNDERFLOW; + assign axi_ar_prog_full = AXI_AR_PROG_FULL; + assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY; + assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr; + assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr; + assign axi_r_sbiterr = AXI_R_SBITERR; + assign axi_r_dbiterr = AXI_R_DBITERR; + assign axi_r_overflow = AXI_R_OVERFLOW; + assign axi_r_underflow = AXI_R_UNDERFLOW; + assign axi_r_prog_full = AXI_R_PROG_FULL; + assign axi_r_prog_empty = AXI_R_PROG_EMPTY; + assign AXIS_INJECTSBITERR = axis_injectsbiterr; + assign AXIS_INJECTDBITERR = axis_injectdbiterr; + assign axis_sbiterr = AXIS_SBITERR; + assign axis_dbiterr = AXIS_DBITERR; + assign axis_overflow = AXIS_OVERFLOW; + assign axis_underflow = AXIS_UNDERFLOW; + assign axis_prog_full = AXIS_PROG_FULL; + assign axis_prog_empty = AXIS_PROG_EMPTY; + + + assign DIN = din; + assign PROG_EMPTY_THRESH = prog_empty_thresh; + assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert; + assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate; + assign PROG_FULL_THRESH = prog_full_thresh; + assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert; + assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate; + assign dout = DOUT; + assign data_count = DATA_COUNT; + assign rd_data_count = RD_DATA_COUNT; + assign wr_data_count = WR_DATA_COUNT; + assign S_AXI_AWID = s_axi_awid; + assign S_AXI_AWADDR = s_axi_awaddr; + assign S_AXI_AWLEN = s_axi_awlen; + assign S_AXI_AWSIZE = s_axi_awsize; + assign S_AXI_AWBURST = s_axi_awburst; + assign S_AXI_AWLOCK = s_axi_awlock; + assign S_AXI_AWCACHE = s_axi_awcache; + assign S_AXI_AWPROT = s_axi_awprot; + assign S_AXI_AWQOS = s_axi_awqos; + assign S_AXI_AWREGION = s_axi_awregion; + assign S_AXI_AWUSER = s_axi_awuser; + assign S_AXI_WID = s_axi_wid; + assign S_AXI_WDATA = s_axi_wdata; + assign S_AXI_WSTRB = s_axi_wstrb; + assign S_AXI_WUSER = s_axi_wuser; + assign s_axi_bid = S_AXI_BID; + assign s_axi_bresp = S_AXI_BRESP; + assign s_axi_buser = S_AXI_BUSER; + assign m_axi_awid = M_AXI_AWID; + assign m_axi_awaddr = M_AXI_AWADDR; + assign m_axi_awlen = M_AXI_AWLEN; + assign m_axi_awsize = M_AXI_AWSIZE; + assign m_axi_awburst = M_AXI_AWBURST; + assign m_axi_awlock = M_AXI_AWLOCK; + assign m_axi_awcache = M_AXI_AWCACHE; + assign m_axi_awprot = M_AXI_AWPROT; + assign m_axi_awqos = M_AXI_AWQOS; + assign m_axi_awregion = M_AXI_AWREGION; + assign m_axi_awuser = M_AXI_AWUSER; + assign m_axi_wid = M_AXI_WID; + assign m_axi_wdata = M_AXI_WDATA; + assign m_axi_wstrb = M_AXI_WSTRB; + assign m_axi_wuser = M_AXI_WUSER; + assign M_AXI_BID = m_axi_bid; + assign M_AXI_BRESP = m_axi_bresp; + assign M_AXI_BUSER = m_axi_buser; + assign S_AXI_ARID = s_axi_arid; + assign S_AXI_ARADDR = s_axi_araddr; + assign S_AXI_ARLEN = s_axi_arlen; + assign S_AXI_ARSIZE = s_axi_arsize; + assign S_AXI_ARBURST = s_axi_arburst; + assign S_AXI_ARLOCK = s_axi_arlock; + assign S_AXI_ARCACHE = s_axi_arcache; + assign S_AXI_ARPROT = s_axi_arprot; + assign S_AXI_ARQOS = s_axi_arqos; + assign S_AXI_ARREGION = s_axi_arregion; + assign S_AXI_ARUSER = s_axi_aruser; + assign s_axi_rid = S_AXI_RID; + assign s_axi_rdata = S_AXI_RDATA; + assign s_axi_rresp = S_AXI_RRESP; + assign s_axi_ruser = S_AXI_RUSER; + assign m_axi_arid = M_AXI_ARID; + assign m_axi_araddr = M_AXI_ARADDR; + assign m_axi_arlen = M_AXI_ARLEN; + assign m_axi_arsize = M_AXI_ARSIZE; + assign m_axi_arburst = M_AXI_ARBURST; + assign m_axi_arlock = M_AXI_ARLOCK; + assign m_axi_arcache = M_AXI_ARCACHE; + assign m_axi_arprot = M_AXI_ARPROT; + assign m_axi_arqos = M_AXI_ARQOS; + assign m_axi_arregion = M_AXI_ARREGION; + assign m_axi_aruser = M_AXI_ARUSER; + assign M_AXI_RID = m_axi_rid; + assign M_AXI_RDATA = m_axi_rdata; + assign M_AXI_RRESP = m_axi_rresp; + assign M_AXI_RUSER = m_axi_ruser; + assign S_AXIS_TDATA = s_axis_tdata; + assign S_AXIS_TSTRB = s_axis_tstrb; + assign S_AXIS_TKEEP = s_axis_tkeep; + assign S_AXIS_TID = s_axis_tid; + assign S_AXIS_TDEST = s_axis_tdest; + assign S_AXIS_TUSER = s_axis_tuser; + assign m_axis_tdata = M_AXIS_TDATA; + assign m_axis_tstrb = M_AXIS_TSTRB; + assign m_axis_tkeep = M_AXIS_TKEEP; + assign m_axis_tid = M_AXIS_TID; + assign m_axis_tdest = M_AXIS_TDEST; + assign m_axis_tuser = M_AXIS_TUSER; + assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh; + assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh; + assign axi_aw_data_count = AXI_AW_DATA_COUNT; + assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT; + assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT; + assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh; + assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh; + assign axi_w_data_count = AXI_W_DATA_COUNT; + assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT; + assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT; + assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh; + assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh; + assign axi_b_data_count = AXI_B_DATA_COUNT; + assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT; + assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT; + assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh; + assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh; + assign axi_ar_data_count = AXI_AR_DATA_COUNT; + assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT; + assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT; + assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh; + assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh; + assign axi_r_data_count = AXI_R_DATA_COUNT; + assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT; + assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT; + assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh; + assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh; + assign axis_data_count = AXIS_DATA_COUNT; + assign axis_wr_data_count = AXIS_WR_DATA_COUNT; + assign axis_rd_data_count = AXIS_RD_DATA_COUNT; + + + generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo + + fifo_generator_v13_2_7_CONV_VER + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE) + ) + fifo_generator_v13_2_7_conv_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (wr_data_count_in), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .wr_rst_busy_o (wr_rst_busy_o), + .wr_rst_busy (wr_rst_busy_i), + .rd_rst_busy (rd_rst_busy), + .wr_rst_i_out (wr_rst_int), + .rd_rst_i_out (rd_rst_int) + ); + end endgenerate + + + + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + localparam C_AXI_SIZE_WIDTH = 3; + localparam C_AXI_BURST_WIDTH = 2; + localparam C_AXI_CACHE_WIDTH = 4; + localparam C_AXI_PROT_WIDTH = 3; + localparam C_AXI_QOS_WIDTH = 4; + localparam C_AXI_REGION_WIDTH = 4; + localparam C_AXI_BRESP_WIDTH = 2; + localparam C_AXI_RRESP_WIDTH = 2; + + localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0; + localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS; + localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET; + localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET; + localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET; + localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET; + localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET; + localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS); + localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH); + + + function [LOG_DEPTH_AXIS-1:0] bin2gray; + input [LOG_DEPTH_AXIS-1:0] x; + begin + bin2gray = x ^ (x>>1); + end + endfunction + + function [LOG_DEPTH_AXIS-1:0] gray2bin; + input [LOG_DEPTH_AXIS-1:0] x; + integer i; + begin + gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1]; + for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin + gray2bin[i] = gray2bin[i+1] ^ x[i]; + end + end + endfunction + +wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last; +wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ; +wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ; +reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0; +reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0; +reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0; +reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0; +wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad; +wire [LOG_WR_DEPTH : 0] r_inv_pad; +wire [LOG_WR_DEPTH-1 : 0] d_cnt; +reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0; +reg adj_w_cnt_rd_pad_0 = 0; +reg r_inv_pad_0 = 0; + + + genvar l; + + generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage + fifo_generator_v13_2_7_sync_stage + #( + .C_WIDTH (LOG_WR_DEPTH) + ) + rd_stg_inst + ( + .RST (rd_rst_int), + .CLK (RD_CLK), + .DIN (w_q[l-1]), + .DOUT (w_q[l]) + ); + end endgenerate // gpkt_cnt_sync_stage + + + + generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter + assign wr_eop_ad = WR_EN & !(FULL); + assign rd_eop_ad = RD_EN & !(EMPTY); + + + always @ (posedge wr_rst_int or posedge WR_CLK) + begin + if (wr_rst_int) + w_cnt <= 1'b0; + else if (wr_eop_ad) + w_cnt <= w_cnt + 1; + end + + always @ (posedge wr_rst_int or posedge WR_CLK) + begin + if (wr_rst_int) + w_cnt_gc <= 1'b0; + else + w_cnt_gc <= bin2gray(w_cnt); + end + + + assign w_q[0] = w_cnt_gc; + assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE]; + + + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + w_cnt_rd <= 1'b0; + else + w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last); + end + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + r_cnt <= 1'b0; + else if (rd_eop_ad) + r_cnt <= r_cnt + 1; + end + + + // Take the difference of write and read packet count + // Logic is similar to rd_pe_as + assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd; + assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt; + assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0; + assign r_inv_pad[0] = r_inv_pad_0; + + + always @ ( rd_eop_ad ) + begin + if (!rd_eop_ad) begin + adj_w_cnt_rd_pad_0 <= 1'b1; + r_inv_pad_0 <= 1'b1; + end else begin + adj_w_cnt_rd_pad_0 <= 1'b0; + r_inv_pad_0 <= 1'b0; + end + end + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + d_cnt_pad <= 1'b0; + else + d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ; + end + + assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ; + assign WR_DATA_COUNT = d_cnt; + + end endgenerate // fifo_ic_adapter + + generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter + assign WR_DATA_COUNT = wr_data_count_in; + + end endgenerate // fifo_icn_adapter + + + + wire inverted_reset = ~S_ARESETN; + wire axi_rs_rst; + wire [C_DIN_WIDTH_AXIS-1:0] axis_din ; + wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ; + wire axis_full ; + wire axis_almost_full ; + wire axis_empty ; + wire axis_s_axis_tready; + wire axis_m_axis_tvalid; + wire axis_wr_en ; + wire axis_rd_en ; + wire axis_we ; + wire axis_re ; + wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc; + reg axis_pkt_read = 1'b0; + wire axis_rd_rst; + wire axis_wr_rst; + + generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 || + C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst + reg rst_d1 = 0 ; + reg rst_d2 = 0 ; + reg [3:0] axi_rst = 4'h0 ; + always @ (posedge inverted_reset or posedge S_ACLK) begin + if (inverted_reset) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + axi_rst <= 4'hf; + end else begin + rst_d1 <= #`TCQ 1'b0; + rst_d2 <= #`TCQ rst_d1; + axi_rst <= #`TCQ {axi_rst[2:0],1'b0}; + end + end + + assign axi_rs_rst = axi_rst[3];//rst_d2; + end endgenerate // gaxi_rs_rst + + generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming + + // Write protection when almost full or prog_full is high + assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : + (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID; + + // Read protection when almost empty or prog_empty is high + assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY : + (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY; + assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we; + assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re; + + fifo_generator_v13_2_7_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_AXIS), + .C_WR_DEPTH (C_WR_DEPTH_AXIS), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), + .C_DOUT_WIDTH (C_DIN_WIDTH_AXIS), + .C_RD_DEPTH (C_WR_DEPTH_AXIS), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS), + .C_USE_ECC (C_USE_ECC_AXIS), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_7_axis_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (axis_wr_en), + .RD_EN (axis_rd_en), + .PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .INJECTDBITERR (AXIS_INJECTDBITERR), + .INJECTSBITERR (AXIS_INJECTSBITERR), + + .DIN (axis_din), + .DOUT (axis_dout), + .FULL (axis_full), + .EMPTY (axis_empty), + .ALMOST_FULL (axis_almost_full), + .PROG_FULL (AXIS_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXIS_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (AXIS_OVERFLOW), + .VALID (), + .UNDERFLOW (AXIS_UNDERFLOW), + .DATA_COUNT (axis_dc), + .RD_DATA_COUNT (AXIS_RD_DATA_COUNT), + .WR_DATA_COUNT (AXIS_WR_DATA_COUNT), + .SBITERR (AXIS_SBITERR), + .DBITERR (AXIS_DBITERR), + .wr_rst_busy (wr_rst_busy_axis), + .rd_rst_busy (rd_rst_busy_axis), + .wr_rst_i_out (axis_wr_rst), + .rd_rst_i_out (axis_rd_rst), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full; + assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read; + assign S_AXIS_TREADY = axis_s_axis_tready; + assign M_AXIS_TVALID = axis_m_axis_tvalid; + + end endgenerate // axi_streaming + + wire axis_wr_eop; + reg axis_wr_eop_d1 = 1'b0; + wire axis_rd_eop; + integer axis_pkt_cnt; + + generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc + assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; + assign axis_rd_eop = axis_rd_en & axis_dout[0]; + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_pkt_read <= 1'b0; + else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1) + axis_pkt_read <= 1'b0; + else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty)) + axis_pkt_read <= 1'b1; + end + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_wr_eop_d1 <= 1'b0; + else + axis_wr_eop_d1 <= axis_wr_eop; + end + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_pkt_cnt <= 0; + else if (axis_wr_eop_d1 && ~axis_rd_eop) + axis_pkt_cnt <= axis_pkt_cnt + 1; + else if (axis_rd_eop && ~axis_wr_eop_d1) + axis_pkt_cnt <= axis_pkt_cnt - 1; + end + end endgenerate // gaxis_pkt_fifo_cc + + +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0; +wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last; +wire axis_rd_has_rst; +wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ; +wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ; +wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0; +wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ; +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0; +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0; +reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0; +wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad; +wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad; +wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt; +reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0; +reg adj_axis_wpkt_cnt_rd_pad_0 = 0; +reg rpkt_inv_pad_0 = 0; +wire axis_af_rd ; + +generate if (C_HAS_RST == 1) begin : rst_blk_has + assign axis_rd_has_rst = axis_rd_rst; +end endgenerate //rst_blk_has + +generate if (C_HAS_RST == 0) begin :rst_blk_no + assign axis_rd_has_rst = 1'b0; +end endgenerate //rst_blk_no + + genvar i; + + generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage + fifo_generator_v13_2_7_sync_stage + #( + .C_WIDTH (LOG_DEPTH_AXIS) + ) + rd_stg_inst + ( + .RST (axis_rd_has_rst), + .CLK (M_ACLK), + .DIN (wpkt_q[i-1]), + .DOUT (wpkt_q[i]) + ); + + fifo_generator_v13_2_7_sync_stage + #( + .C_WIDTH (1) + ) + wr_stg_inst + ( + .RST (axis_rd_has_rst), + .CLK (M_ACLK), + .DIN (axis_af_q[i-1]), + .DOUT (axis_af_q[i]) + ); + end endgenerate // gpkt_cnt_sync_stage + + + generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic + assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; + assign axis_rd_eop = axis_rd_en & axis_dout[0]; + + always @ (posedge axis_rd_has_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_pkt_read <= 1'b0; + else if (axis_rd_eop && (diff_pkt_cnt == 1)) + axis_pkt_read <= 1'b0; + else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty)) + axis_pkt_read <= 1'b1; + end + + always @ (posedge axis_wr_rst or posedge S_ACLK) + begin + if (axis_wr_rst) + axis_wpkt_cnt <= 1'b0; + else if (axis_wr_eop) + axis_wpkt_cnt <= axis_wpkt_cnt + 1; + end + + always @ (posedge axis_wr_rst or posedge S_ACLK) + begin + if (axis_wr_rst) + axis_wpkt_cnt_gc <= 1'b0; + else + axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt); + end + + + assign wpkt_q[0] = axis_wpkt_cnt_gc; + assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE]; + assign axis_af_q[0] = axis_almost_full; + //assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE]; + assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE]; + + + + always @ (posedge axis_rd_has_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_wpkt_cnt_rd <= 1'b0; + else + axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last); + end + + always @ (posedge axis_rd_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_rpkt_cnt <= 1'b0; + else if (axis_rd_eop) + axis_rpkt_cnt <= axis_rpkt_cnt + 1; + end + + + // Take the difference of write and read packet count + // Logic is similar to rd_pe_as + assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd; + assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt; + assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0; + assign rpkt_inv_pad[0] = rpkt_inv_pad_0; + + + always @ ( axis_rd_eop ) + begin + if (!axis_rd_eop) begin + adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1; + rpkt_inv_pad_0 <= 1'b1; + end else begin + adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0; + rpkt_inv_pad_0 <= 1'b0; + end + end + + always @ (posedge axis_rd_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + diff_pkt_cnt_pad <= 1'b0; + else + diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ; + end + + assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ; + + + + + + end endgenerate // gaxis_pkt_fifo_ic + + + + + // Generate the accurate data count for axi stream packet fifo configuration + reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0; + generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_dc_pkt_fifo <= 0; + else if (axis_wr_en && (~axis_rd_en)) + axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1; + else if (~axis_wr_en && axis_rd_en) + axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1; + end + assign AXIS_DATA_COUNT = axis_dc_pkt_fifo; + end endgenerate // gdc_pkt + + generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt + assign AXIS_DATA_COUNT = 0; + end endgenerate // gndc_pkt + + generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc + assign AXIS_DATA_COUNT = axis_dc; + end endgenerate // gdc + + // Register Slice for Write Address Channel + generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice + assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID; + assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY; + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_AXIS), + .C_REG_CONFIG (C_REG_SLICE_MODE_AXIS) + ) + axis_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (axis_din), + .S_VALID (axis_wr_en), + .S_READY (S_AXIS_TREADY), + + // Master side + .M_PAYLOAD_DATA (axis_dout), + .M_VALID (M_AXIS_TVALID), + .M_READY (axis_rd_en) + ); + end endgenerate // gaxis_reg_slice + + + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata + assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA; + assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb + assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB; + assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep + assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP; + assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid + assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID; + assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest + assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST; + assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser + assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER; + assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast + assign axis_din[0] = S_AXIS_TLAST; + assign M_AXIS_TLAST = axis_dout[0]; + end endgenerate + + //########################################################################### + // AXI FULL Write Channel (axi_write_channel) + //########################################################################### + + localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0; + localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0; + + localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + + localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + + localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0; + localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0; + localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0; + localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0; + localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0; + + localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH; + localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH; + localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET; + localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET; + localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET; + localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET; + localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET; + localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH; + localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH; + localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET; + localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET; + + localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH; + localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH; + localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8; + localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET; + + localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH; + localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH; + localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET; + + + wire [C_DIN_WIDTH_WACH-1:0] wach_din ; + wire [C_DIN_WIDTH_WACH-1:0] wach_dout ; + wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ; + wire wach_full ; + wire wach_almost_full ; + wire wach_prog_full ; + wire wach_empty ; + wire wach_almost_empty ; + wire wach_prog_empty ; + wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ; + wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ; + wire wdch_full ; + wire wdch_almost_full ; + wire wdch_prog_full ; + wire wdch_empty ; + wire wdch_almost_empty ; + wire wdch_prog_empty ; + wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ; + wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ; + wire wrch_full ; + wire wrch_almost_full ; + wire wrch_prog_full ; + wire wrch_empty ; + wire wrch_almost_empty ; + wire wrch_prog_empty ; + wire axi_aw_underflow_i; + wire axi_w_underflow_i ; + wire axi_b_underflow_i ; + wire axi_aw_overflow_i ; + wire axi_w_overflow_i ; + wire axi_b_overflow_i ; + wire axi_wr_underflow_i; + wire axi_wr_overflow_i ; + wire wach_s_axi_awready; + wire wach_m_axi_awvalid; + wire wach_wr_en ; + wire wach_rd_en ; + wire wdch_s_axi_wready ; + wire wdch_m_axi_wvalid ; + wire wdch_wr_en ; + wire wdch_rd_en ; + wire wrch_s_axi_bvalid ; + wire wrch_m_axi_bready ; + wire wrch_wr_en ; + wire wrch_rd_en ; + wire txn_count_up ; + wire txn_count_down ; + wire awvalid_en ; + wire awvalid_pkt ; + wire awready_pkt ; + integer wr_pkt_count ; + wire wach_we ; + wire wach_re ; + wire wdch_we ; + wire wdch_re ; + wire wrch_we ; + wire wrch_re ; + + generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel + // Write protection when almost full or prog_full is high + assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID; + + // Read protection when almost empty or prog_empty is high + assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? + wach_m_axi_awvalid & awready_pkt & awvalid_en : + (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? + M_AXI_AWREADY && wach_m_axi_awvalid : + (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? + awready_pkt & awvalid_en : + (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? + M_AXI_AWREADY : 1'b0; + assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we; + assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re; + + fifo_generator_v13_2_7_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WACH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_WR_DEPTH (C_WR_DEPTH_WACH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WACH), + .C_RD_DEPTH (C_WR_DEPTH_WACH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH), + .C_USE_ECC (C_USE_ECC_WACH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0), + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_7_wach_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wach_wr_en), + .RD_EN (wach_rd_en), + .PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .INJECTDBITERR (AXI_AW_INJECTDBITERR), + .INJECTSBITERR (AXI_AW_INJECTSBITERR), + + .DIN (wach_din), + .DOUT (wach_dout_pkt), + .FULL (wach_full), + .EMPTY (wach_empty), + .ALMOST_FULL (), + .PROG_FULL (AXI_AW_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXI_AW_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_aw_overflow_i), + .VALID (), + .UNDERFLOW (axi_aw_underflow_i), + .DATA_COUNT (AXI_AW_DATA_COUNT), + .RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT), + .SBITERR (AXI_AW_SBITERR), + .DBITERR (AXI_AW_DBITERR), + .wr_rst_busy (wr_rst_busy_wach), + .rd_rst_busy (rd_rst_busy_wach), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full; + assign wach_m_axi_awvalid = ~wach_empty; + assign S_AXI_AWREADY = wach_s_axi_awready; + + assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0; + assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0; + + end endgenerate // axi_write_address_channel + + // Register Slice for Write Address Channel + generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WACH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WACH) + ) + wach_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wach_din), + .S_VALID (S_AXI_AWVALID), + .S_READY (S_AXI_AWREADY), + + // Master side + .M_PAYLOAD_DATA (wach_dout), + .M_VALID (M_AXI_AWVALID), + .M_READY (M_AXI_AWREADY) + ); + end endgenerate // gwach_reg_slice + + generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WACH), + .C_REG_CONFIG (1) + ) + wach_pkt_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wach_dout_pkt), + .S_VALID (awvalid_pkt), + .S_READY (awready_pkt), + + // Master side + .M_PAYLOAD_DATA (wach_dout), + .M_VALID (M_AXI_AWVALID), + .M_READY (M_AXI_AWREADY) + ); + + assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en; + + assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; + assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en; + + always@(posedge S_ACLK or posedge inverted_reset) begin + if(inverted_reset == 1) begin + wr_pkt_count <= 0; + end else begin + if(txn_count_up == 1 && txn_count_down == 0) begin + wr_pkt_count <= wr_pkt_count + 1; + end else if(txn_count_up == 0 && txn_count_down == 1) begin + wr_pkt_count <= wr_pkt_count - 1; + end + end + end //Always end + assign awvalid_en = (wr_pkt_count > 0)?1:0; + end endgenerate + + generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr + assign awvalid_en = 1; + assign wach_dout = wach_dout_pkt; + assign M_AXI_AWVALID = wach_m_axi_awvalid; + end + endgenerate + + + + generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel + // Write protection when almost full or prog_full is high + assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID; + + // Read protection when almost empty or prog_empty is high + assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY; + assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we; + assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re; + + + fifo_generator_v13_2_7_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WDCH), + .C_WR_DEPTH (C_WR_DEPTH_WDCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WDCH), + .C_RD_DEPTH (C_WR_DEPTH_WDCH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH), + .C_USE_ECC (C_USE_ECC_WDCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_7_wdch_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wdch_wr_en), + .RD_EN (wdch_rd_en), + .PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .INJECTDBITERR (AXI_W_INJECTDBITERR), + .INJECTSBITERR (AXI_W_INJECTSBITERR), + + .DIN (wdch_din), + .DOUT (wdch_dout), + .FULL (wdch_full), + .EMPTY (wdch_empty), + .ALMOST_FULL (), + .PROG_FULL (AXI_W_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXI_W_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_w_overflow_i), + .VALID (), + .UNDERFLOW (axi_w_underflow_i), + .DATA_COUNT (AXI_W_DATA_COUNT), + .RD_DATA_COUNT (AXI_W_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_W_WR_DATA_COUNT), + .SBITERR (AXI_W_SBITERR), + .DBITERR (AXI_W_DBITERR), + .wr_rst_busy (wr_rst_busy_wdch), + .rd_rst_busy (rd_rst_busy_wdch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full; + assign wdch_m_axi_wvalid = ~wdch_empty; + assign S_AXI_WREADY = wdch_s_axi_wready; + assign M_AXI_WVALID = wdch_m_axi_wvalid; + + assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0; + assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0; + + end endgenerate // axi_write_data_channel + + // Register Slice for Write Data Channel + generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WDCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WDCH) + ) + wdch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wdch_din), + .S_VALID (S_AXI_WVALID), + .S_READY (S_AXI_WREADY), + + // Master side + .M_PAYLOAD_DATA (wdch_dout), + .M_VALID (M_AXI_WVALID), + .M_READY (M_AXI_WREADY) + ); + end endgenerate // gwdch_reg_slice + + generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel + // Write protection when almost full or prog_full is high + assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID; + + // Read protection when almost empty or prog_empty is high + assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY; + assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we; + assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re; + + fifo_generator_v13_2_7_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WRCH), + .C_WR_DEPTH (C_WR_DEPTH_WRCH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WRCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_RD_DEPTH (C_WR_DEPTH_WRCH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH), + .C_USE_ECC (C_USE_ECC_WRCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_7_wrch_dut + ( + .CLK (S_ACLK), + .WR_CLK (M_ACLK), + .RD_CLK (S_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wrch_wr_en), + .RD_EN (wrch_rd_en), + .PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .INJECTDBITERR (AXI_B_INJECTDBITERR), + .INJECTSBITERR (AXI_B_INJECTSBITERR), + + .DIN (wrch_din), + .DOUT (wrch_dout), + .FULL (wrch_full), + .EMPTY (wrch_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_B_PROG_FULL), + .PROG_EMPTY (AXI_B_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_b_overflow_i), + .VALID (), + .UNDERFLOW (axi_b_underflow_i), + .DATA_COUNT (AXI_B_DATA_COUNT), + .RD_DATA_COUNT (AXI_B_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_B_WR_DATA_COUNT), + .SBITERR (AXI_B_SBITERR), + .DBITERR (AXI_B_DBITERR), + .wr_rst_busy (wr_rst_busy_wrch), + .rd_rst_busy (rd_rst_busy_wrch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wrch_s_axi_bvalid = ~wrch_empty; + assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full; + assign S_AXI_BVALID = wrch_s_axi_bvalid; + assign M_AXI_BREADY = wrch_m_axi_bready; + + assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0; + assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0; + end endgenerate // axi_write_resp_channel + + // Register Slice for Write Response Channel + generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WRCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WRCH) + ) + wrch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wrch_din), + .S_VALID (M_AXI_BVALID), + .S_READY (M_AXI_BREADY), + + // Master side + .M_PAYLOAD_DATA (wrch_dout), + .M_VALID (S_AXI_BVALID), + .M_READY (S_AXI_BREADY) + ); + end endgenerate // gwrch_reg_slice + + + assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0; + assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0; + + generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output + assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET]; + assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET]; + assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET]; + assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET]; + assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET]; + assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET]; + assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET]; + assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET]; + assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR; + assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN; + assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE; + assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST; + assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK; + assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE; + assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT; + assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS; + end endgenerate // axi_wach_output + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion + assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET]; + end endgenerate // axi_awregion + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion + assign M_AXI_AWREGION = 0; + end endgenerate // naxi_awregion + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser + assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET]; + end endgenerate // axi_awuser + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser + assign M_AXI_AWUSER = 0; + end endgenerate // naxi_awuser + + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid + assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET]; + end endgenerate //axi_awid + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid + assign M_AXI_AWID = 0; + end endgenerate //naxi_awid + + generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output + assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET]; + assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; + assign M_AXI_WLAST = wdch_dout[0]; + assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA; + assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB; + assign wdch_din[0] = S_AXI_WLAST; + end endgenerate // axi_wdch_output + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin + assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET]; + end endgenerate + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin + assign M_AXI_WID = 0; + end endgenerate + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin + assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET]; + end endgenerate + generate if (C_HAS_AXI_WUSER == 0) begin + assign M_AXI_WUSER = 0; + end endgenerate + + generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output + assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; + assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP; + end endgenerate // axi_wrch_output + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser + assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET]; + end endgenerate // axi_buser + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser + assign S_AXI_BUSER = 0; + end endgenerate // naxi_buser + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid + assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET]; + end endgenerate // axi_bid + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid + assign S_AXI_BID = 0 ; + end endgenerate // naxi_bid + + + generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1 + assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT}; + assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET]; + assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET]; + end endgenerate // axi_wach_output1 + + generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1 + assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB}; + assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET]; + assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; + end endgenerate // axi_wdch_output1 + + generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1 + assign wrch_din = M_AXI_BRESP; + assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; + end endgenerate // axi_wrch_output1 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1 + assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER; + end endgenerate // gwach_din1 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2 + assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID; + end endgenerate // gwach_din2 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3 + assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION; + end endgenerate // gwach_din3 + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1 + assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER; + end endgenerate // gwdch_din1 + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2 + assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID; + end endgenerate // gwdch_din2 + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1 + assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER; + end endgenerate // gwrch_din1 + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2 + assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID; + end endgenerate // gwrch_din2 + + //end of axi_write_channel + + //########################################################################### + // AXI FULL Read Channel (axi_read_channel) + //########################################################################### + wire [C_DIN_WIDTH_RACH-1:0] rach_din ; + wire [C_DIN_WIDTH_RACH-1:0] rach_dout ; + wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ; + wire rach_full ; + wire rach_almost_full ; + wire rach_prog_full ; + wire rach_empty ; + wire rach_almost_empty ; + wire rach_prog_empty ; + wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ; + wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ; + wire rdch_full ; + wire rdch_almost_full ; + wire rdch_prog_full ; + wire rdch_empty ; + wire rdch_almost_empty ; + wire rdch_prog_empty ; + wire axi_ar_underflow_i ; + wire axi_r_underflow_i ; + wire axi_ar_overflow_i ; + wire axi_r_overflow_i ; + wire axi_rd_underflow_i ; + wire axi_rd_overflow_i ; + wire rach_s_axi_arready ; + wire rach_m_axi_arvalid ; + wire rach_wr_en ; + wire rach_rd_en ; + wire rdch_m_axi_rready ; + wire rdch_s_axi_rvalid ; + wire rdch_wr_en ; + wire rdch_rd_en ; + wire arvalid_pkt ; + wire arready_pkt ; + wire arvalid_en ; + wire rdch_rd_ok ; + wire accept_next_pkt ; + integer rdch_free_space ; + integer rdch_commited_space ; + wire rach_we ; + wire rach_re ; + wire rdch_we ; + wire rdch_re ; + + localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH; + localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH; + localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET; + localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET; + localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET; + localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET; + localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET; + localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH; + localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH; + localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET; + localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET; + + localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH; + localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH; + localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH; + localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET; + + + generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel + + // Write protection when almost full or prog_full is high + assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID; + + // Read protection when almost empty or prog_empty is high +// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en; + assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? + rach_m_axi_arvalid & arready_pkt & arvalid_en : + (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? + M_AXI_ARREADY && rach_m_axi_arvalid : + (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? + arready_pkt & arvalid_en : + (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? + M_AXI_ARREADY : 1'b0; + assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we; + assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re; + + + fifo_generator_v13_2_7_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_RACH), + .C_WR_DEPTH (C_WR_DEPTH_RACH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_DOUT_WIDTH (C_DIN_WIDTH_RACH), + .C_RD_DEPTH (C_WR_DEPTH_RACH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH), + .C_USE_ECC (C_USE_ECC_RACH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_7_rach_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (rach_wr_en), + .RD_EN (rach_rd_en), + .PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .INJECTDBITERR (AXI_AR_INJECTDBITERR), + .INJECTSBITERR (AXI_AR_INJECTSBITERR), + + .DIN (rach_din), + .DOUT (rach_dout_pkt), + .FULL (rach_full), + .EMPTY (rach_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_AR_PROG_FULL), + .PROG_EMPTY (AXI_AR_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_ar_overflow_i), + .VALID (), + .UNDERFLOW (axi_ar_underflow_i), + .DATA_COUNT (AXI_AR_DATA_COUNT), + .RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT), + .SBITERR (AXI_AR_SBITERR), + .DBITERR (AXI_AR_DBITERR), + .wr_rst_busy (wr_rst_busy_rach), + .rd_rst_busy (rd_rst_busy_rach), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full; + assign rach_m_axi_arvalid = ~rach_empty; + assign S_AXI_ARREADY = rach_s_axi_arready; + + assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0; + assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0; + + end endgenerate // axi_read_addr_channel + + // Register Slice for Read Address Channel + generate if (C_RACH_TYPE == 1) begin : grach_reg_slice + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RACH), + .C_REG_CONFIG (C_REG_SLICE_MODE_RACH) + ) + rach_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rach_din), + .S_VALID (S_AXI_ARVALID), + .S_READY (S_AXI_ARREADY), + + // Master side + .M_PAYLOAD_DATA (rach_dout), + .M_VALID (M_AXI_ARVALID), + .M_READY (M_AXI_ARREADY) + ); + end endgenerate // grach_reg_slice + + // Register Slice for Read Address Channel for MM Packet FIFO + generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RACH), + .C_REG_CONFIG (1) + ) + reg_slice_mm_pkt_fifo_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rach_dout_pkt), + .S_VALID (arvalid_pkt), + .S_READY (arready_pkt), + + // Master side + .M_PAYLOAD_DATA (rach_dout), + .M_VALID (M_AXI_ARVALID), + .M_READY (M_AXI_ARREADY) + ); + end endgenerate // grach_reg_slice_mm_pkt_fifo + + + generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid + assign M_AXI_ARVALID = rach_m_axi_arvalid; + assign rach_dout = rach_dout_pkt; + end endgenerate // grach_m_axi_arvalid + + + generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd + assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en; + assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en; + assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en; + + always@(posedge S_ACLK or posedge inverted_reset) begin + if(inverted_reset) begin + rdch_commited_space <= 0; + end else begin + if(rdch_rd_ok && !accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space-1; + end else if(!rdch_rd_ok && accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1); + end else if(rdch_rd_ok && accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]); + end + end + end //Always end + + always@(*) begin + rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1)); + end + + assign arvalid_en = (rdch_free_space >= 0)?1:0; + end + endgenerate + + generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd + assign arvalid_en = 1; + end + endgenerate + + generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel + + // Write protection when almost full or prog_full is high + assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID; + + // Read protection when almost empty or prog_empty is high + assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY; + assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we; + assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re; + + fifo_generator_v13_2_7_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_RDCH), + .C_WR_DEPTH (C_WR_DEPTH_RDCH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_RDCH), + .C_RD_DEPTH (C_WR_DEPTH_RDCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH), + .C_USE_ECC (C_USE_ECC_RDCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_7_rdch_dut + ( + .CLK (S_ACLK), + .WR_CLK (M_ACLK), + .RD_CLK (S_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (rdch_wr_en), + .RD_EN (rdch_rd_en), + .PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .INJECTDBITERR (AXI_R_INJECTDBITERR), + .INJECTSBITERR (AXI_R_INJECTSBITERR), + + .DIN (rdch_din), + .DOUT (rdch_dout), + .FULL (rdch_full), + .EMPTY (rdch_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_R_PROG_FULL), + .PROG_EMPTY (AXI_R_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_r_overflow_i), + .VALID (), + .UNDERFLOW (axi_r_underflow_i), + .DATA_COUNT (AXI_R_DATA_COUNT), + .RD_DATA_COUNT (AXI_R_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_R_WR_DATA_COUNT), + .SBITERR (AXI_R_SBITERR), + .DBITERR (AXI_R_DBITERR), + .wr_rst_busy (wr_rst_busy_rdch), + .rd_rst_busy (rd_rst_busy_rdch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign rdch_s_axi_rvalid = ~rdch_empty; + assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full; + assign S_AXI_RVALID = rdch_s_axi_rvalid; + assign M_AXI_RREADY = rdch_m_axi_rready; + + assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0; + assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0; + + end endgenerate //axi_read_data_channel + + // Register Slice for read Data Channel + generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice + + fifo_generator_v13_2_7_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RDCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_RDCH) + ) + rdch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rdch_din), + .S_VALID (M_AXI_RVALID), + .S_READY (M_AXI_RREADY), + + // Master side + .M_PAYLOAD_DATA (rdch_dout), + .M_VALID (S_AXI_RVALID), + .M_READY (S_AXI_RREADY) + ); + end endgenerate // grdch_reg_slice + + + assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0; + assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0; + + + generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output + assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET]; + assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET]; + assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET]; + assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET]; + assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET]; + assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET]; + assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET]; + assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET]; + assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR; + assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN; + assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE; + assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST; + assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK; + assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE; + assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT; + assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS; + end endgenerate // axi_full_rach_output + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion + assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET]; + end endgenerate // axi_arregion + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion + assign M_AXI_ARREGION = 0; + end endgenerate // naxi_arregion + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser + assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET]; + end endgenerate // axi_aruser + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser + assign M_AXI_ARUSER = 0; + end endgenerate // naxi_aruser + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid + assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET]; + end endgenerate // axi_arid + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid + assign M_AXI_ARID = 0; + end endgenerate // naxi_arid + + generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output + assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET]; + assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; + assign S_AXI_RLAST = rdch_dout[0]; + assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA; + assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP; + assign rdch_din[0] = M_AXI_RLAST; + end endgenerate // axi_full_rdch_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output + assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET]; + end endgenerate // axi_full_ruser_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output + assign S_AXI_RUSER = 0; + end endgenerate // axi_full_nruser_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid + assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET]; + end endgenerate // axi_rid + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid + assign S_AXI_RID = 0; + end endgenerate // naxi_rid + + generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1 + assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT}; + assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET]; + assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET]; + end endgenerate // axi_lite_rach_output + + generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1 + assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP}; + assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET]; + assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; + end endgenerate // axi_lite_rdch_output + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1 + assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER; + end endgenerate // grach_din1 + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2 + assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID; + end endgenerate // grach_din2 + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin + assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION; + end endgenerate + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1 + assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER; + end endgenerate // grdch_din1 + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2 + assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID; + end endgenerate // grdch_din2 + + //end of axi_read_channel + + generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf + assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) : + (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i : + (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0; + end endgenerate // gaxi_comm_uf + + generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of + assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) : + (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i : + (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0; + end endgenerate // gaxi_comm_of + + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + // Pass Through Logic or Wiring Logic + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + + //------------------------------------------------------------------------- + // Pass Through Logic for Read Channel + //------------------------------------------------------------------------- + + // Wiring logic for Write Address Channel + generate if (C_WACH_TYPE == 2) begin : gwach_pass_through + assign M_AXI_AWID = S_AXI_AWID; + assign M_AXI_AWADDR = S_AXI_AWADDR; + assign M_AXI_AWLEN = S_AXI_AWLEN; + assign M_AXI_AWSIZE = S_AXI_AWSIZE; + assign M_AXI_AWBURST = S_AXI_AWBURST; + assign M_AXI_AWLOCK = S_AXI_AWLOCK; + assign M_AXI_AWCACHE = S_AXI_AWCACHE; + assign M_AXI_AWPROT = S_AXI_AWPROT; + assign M_AXI_AWQOS = S_AXI_AWQOS; + assign M_AXI_AWREGION = S_AXI_AWREGION; + assign M_AXI_AWUSER = S_AXI_AWUSER; + assign S_AXI_AWREADY = M_AXI_AWREADY; + assign M_AXI_AWVALID = S_AXI_AWVALID; + end endgenerate // gwach_pass_through; + + // Wiring logic for Write Data Channel + generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through + assign M_AXI_WID = S_AXI_WID; + assign M_AXI_WDATA = S_AXI_WDATA; + assign M_AXI_WSTRB = S_AXI_WSTRB; + assign M_AXI_WLAST = S_AXI_WLAST; + assign M_AXI_WUSER = S_AXI_WUSER; + assign S_AXI_WREADY = M_AXI_WREADY; + assign M_AXI_WVALID = S_AXI_WVALID; + end endgenerate // gwdch_pass_through; + + // Wiring logic for Write Response Channel + generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through + assign S_AXI_BID = M_AXI_BID; + assign S_AXI_BRESP = M_AXI_BRESP; + assign S_AXI_BUSER = M_AXI_BUSER; + assign M_AXI_BREADY = S_AXI_BREADY; + assign S_AXI_BVALID = M_AXI_BVALID; + end endgenerate // gwrch_pass_through; + + //------------------------------------------------------------------------- + // Pass Through Logic for Read Channel + //------------------------------------------------------------------------- + + // Wiring logic for Read Address Channel + generate if (C_RACH_TYPE == 2) begin : grach_pass_through + assign M_AXI_ARID = S_AXI_ARID; + assign M_AXI_ARADDR = S_AXI_ARADDR; + assign M_AXI_ARLEN = S_AXI_ARLEN; + assign M_AXI_ARSIZE = S_AXI_ARSIZE; + assign M_AXI_ARBURST = S_AXI_ARBURST; + assign M_AXI_ARLOCK = S_AXI_ARLOCK; + assign M_AXI_ARCACHE = S_AXI_ARCACHE; + assign M_AXI_ARPROT = S_AXI_ARPROT; + assign M_AXI_ARQOS = S_AXI_ARQOS; + assign M_AXI_ARREGION = S_AXI_ARREGION; + assign M_AXI_ARUSER = S_AXI_ARUSER; + assign S_AXI_ARREADY = M_AXI_ARREADY; + assign M_AXI_ARVALID = S_AXI_ARVALID; + end endgenerate // grach_pass_through; + + // Wiring logic for Read Data Channel + generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through + assign S_AXI_RID = M_AXI_RID; + assign S_AXI_RLAST = M_AXI_RLAST; + assign S_AXI_RUSER = M_AXI_RUSER; + assign S_AXI_RDATA = M_AXI_RDATA; + assign S_AXI_RRESP = M_AXI_RRESP; + assign S_AXI_RVALID = M_AXI_RVALID; + assign M_AXI_RREADY = S_AXI_RREADY; + end endgenerate // grdch_pass_through; + + // Wiring logic for AXI Streaming + generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through + assign M_AXIS_TDATA = S_AXIS_TDATA; + assign M_AXIS_TSTRB = S_AXIS_TSTRB; + assign M_AXIS_TKEEP = S_AXIS_TKEEP; + assign M_AXIS_TID = S_AXIS_TID; + assign M_AXIS_TDEST = S_AXIS_TDEST; + assign M_AXIS_TUSER = S_AXIS_TUSER; + assign M_AXIS_TLAST = S_AXIS_TLAST; + assign S_AXIS_TREADY = M_AXIS_TREADY; + assign M_AXIS_TVALID = S_AXIS_TVALID; + end endgenerate // gaxis_pass_through; + + +endmodule //fifo_generator_v13_2_7 + + + +/******************************************************************************* + * Declaration of top-level module for Conventional FIFO + ******************************************************************************/ +module fifo_generator_v13_2_7_CONV_VER + #( + parameter C_COMMON_CLOCK = 0, + parameter C_INTERFACE_TYPE = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "virtex7", //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_FIFO_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2, + parameter C_AXI_TYPE = 0 + ) + + ( + input BACKUP, + input BACKUP_MARKER, + input CLK, + input RST, + input SRST, + input WR_CLK, + input WR_RST, + input RD_CLK, + input RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input WR_EN, + input RD_EN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input INT_CLK, + input INJECTDBITERR, + input INJECTSBITERR, + + output [C_DOUT_WIDTH-1:0] DOUT, + output FULL, + output ALMOST_FULL, + output WR_ACK, + output OVERFLOW, + output EMPTY, + output ALMOST_EMPTY, + output VALID, + output UNDERFLOW, + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_FULL, + output PROG_EMPTY, + output SBITERR, + output DBITERR, + output wr_rst_busy_o, + output wr_rst_busy, + output rd_rst_busy, + output wr_rst_i_out, + output rd_rst_i_out + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + //---------------------------------------------------------------------------- + //- Internal Signals for delayed input signals + //- All the input signals except Clock are delayed by 100 ps and then given to + //- the models. + //---------------------------------------------------------------------------- + + reg rst_delayed ; + reg empty_fb ; + reg srst_delayed ; + reg wr_rst_delayed ; + reg rd_rst_delayed ; + reg wr_en_delayed ; + reg rd_en_delayed ; + reg [C_DIN_WIDTH-1:0] din_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ; + reg injectdbiterr_delayed ; + reg injectsbiterr_delayed ; + wire empty_p0_out; + + always @* rst_delayed <= #`TCQ RST ; + always @* empty_fb <= #`TCQ empty_p0_out ; + always @* srst_delayed <= #`TCQ SRST ; + always @* wr_rst_delayed <= #`TCQ WR_RST ; + always @* rd_rst_delayed <= #`TCQ RD_RST ; + always @* din_delayed <= #`TCQ DIN ; + always @* wr_en_delayed <= #`TCQ WR_EN ; + always @* rd_en_delayed <= #`TCQ RD_EN ; + always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ; + always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; + always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; + always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ; + always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ; + always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ; + always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ; + always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ; + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + // 2 = Low Latency Synchronous FIFO + // 3 = Low Latency Asynchronous FIFO + localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 : + (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + + //Internal reset signals + reg rd_rst_asreg = 1'b0; + reg rd_rst_asreg_d1 = 1'b0; + reg rd_rst_asreg_d2 = 1'b0; + reg rd_rst_asreg_d3 = 1'b0; + reg rd_rst_reg = 1'b0; + reg rd_rst_comb = 1'b1; + reg rd_rst_comb_d1 = 1'b0; + reg wr_rst_d0 = 1'b0; + reg wr_rst_d1 = 1'b0; + reg wr_rst_d2 = 1'b0; + reg rd_rst_d0 = 1'b0; + reg rd_rst_d1 = 1'b0; + reg rd_rst_d2 = 1'b0; + reg rd_rst_d3 = 1'b0; + reg wrrst_done = 1'b0; + reg rdrst_done = 1'b0; + reg wr_rst_asreg = 1'b0; + reg wr_rst_asreg_d1 = 1'b0; + reg wr_rst_asreg_d2 = 1'b0; + reg wr_rst_asreg_d3 = 1'b0; + reg rd_rst_wr_d0 = 1'b0; + reg rd_rst_wr_d1 = 1'b0; + reg rd_rst_wr_d2 = 1'b0; + reg wr_rst_reg = 1'b0; + reg rst_active_i = 1'b1; + reg rst_delayed_d1 = 1'b1; + reg rst_delayed_d2 = 1'b1; + reg wr_rst_comb = 1'b1; + reg wr_rst_comb_d1 = 1'b0; + wire wr_rst_i; + wire rd_rst_i; + wire rst_i; + + //Internal reset signals + reg rst_asreg = 1'b0; + reg srst_asreg = 1'b0; + reg rst_asreg_d1 = 1'b0; + reg rst_asreg_d2 = 1'b0; + reg srst_asreg_d1 = 1'b0; + reg srst_asreg_d2 = 1'b0; + reg rst_reg = 1'b0; + reg srst_reg = 1'b0; + reg rst_comb = 1'b1; + reg rst_comb_d1 = 1'b0; + wire srst_comb; + reg rst_full_gen_i = 0; + reg rst_full_ff_i = 0; + reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}}; + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire fifo_empty_fb; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + wire inject_sbit_err; + wire inject_dbit_err; + wire sckt_wr_rst_i; + wire sckt_rd_rst_i; + reg sckt_wr_rst_i_q = 1'b0; + + wire w_fab_read_data_valid_i; + wire w_read_data_valid_i; + wire w_ram_valid_i; + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + injectsbiterr_delayed : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + injectdbiterr_delayed : 0; + + assign wr_rst_i_out = wr_rst_i; + assign rd_rst_i_out = rd_rst_i; + assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2]; + generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o + wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK; + always @ (posedge clk_i) + sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; + end endgenerate +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) + + localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; +generate +case (C_VERILOG_IMPL) +0 : begin : block1_ss + //Common Clock Behavioral Model + fifo_generator_v13_2_7_bhv_ver_ss + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_SRST (C_EN_SAFETY_CKT?1:C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + gen_ss + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .CLK (CLK), + .RST (C_EN_SAFETY_CKT?1'b0:rst_i), + .SRST (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .USER_EMPTY_FB (empty_fb), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1_as + //Independent Clocks Behavioral Model + fifo_generator_v13_2_7_bhv_ver_as + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + gen_as + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .SAFETY_CKT_RD_RST (sckt_rd_rst_i), + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .fab_read_data_valid_i (w_fab_read_data_valid_i), + .read_data_valid_i (w_read_data_valid_i), + .ram_valid_i (w_ram_valid_i), + .DBITERR (dbiterr_fifo_out) + ); +end + +2 : begin : ll_afifo_inst + fifo_generator_v13_2_7_beh_ver_ll_afifo + #( + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + gen_ll_afifo + ( + .DIN (din_delayed), + .RD_CLK (RD_CLK), + .RD_EN (rd_en_delayed), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .WR_CLK (WR_CLK), + .WR_EN (wr_en_delayed), + .DOUT (DOUT), + .EMPTY (EMPTY), + .FULL (FULL) + ); +end +default : begin : block1_as + //Independent Clocks Behavioral Model + fifo_generator_v13_2_7_bhv_ver_as + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + gen_as + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .SAFETY_CKT_RD_RST (sckt_rd_rst_i), + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + wire rd_en_to_fwft_fifo; + wire sbiterr_fwft; + wire dbiterr_fwft; + wire [C_DOUT_WIDTH-1:0] dout_fwft; + wire empty_fwft; + wire rd_en_fifo_in; + wire stage2_reg_en_i; + wire [1:0] valid_stages_i; + wire rst_fwft; + //wire empty_p0_out; + reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1; + + localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; + localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0; + localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0; + assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0; + + generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft + + + fifo_generator_v13_2_7_bhv_ver_preload0 + #( + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_HAS_RST (C_HAS_RST), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_HAS_SRST (C_HAS_SRST), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_ECC (C_USE_ECC), + .C_USERVALID_LOW (C_VALID_LOW), + .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + fgpl0 + ( + .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (srst_delayed), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + // Output + .USERDATA (dout_fwft), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (empty_fwft), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (), + .FIFORDEN (rd_en_fifo_in), + .USERSBITERR (sbiterr_fwft), + .USERDBITERR (dbiterr_fwft), + .STAGE2_REG_EN (stage2_reg_en_i), + .fab_read_data_valid_i_o (w_fab_read_data_valid_i), + .read_data_valid_i_o (w_read_data_valid_i), + .ram_valid_i_o (w_ram_valid_i), + .VALID_STAGES (valid_stages_i) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; + assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; + assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign VALID = VALID_P0_OUT ; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = rd_en_fifo_in; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out; +// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ; + end else begin + SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= 0; + end else begin + //if (srst_delayed && (C_HAS_SRST == 1) ) begin + if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + end endgenerate // : block2 + + // AXI Streaming Packet FIFO + reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0; + reg partial_packet = 0; + reg stage1_eop_d1 = 0; + reg rd_en_fifo_in_d1 = 0; + reg eop_at_stage2 = 0; + reg ram_pkt_empty = 0; + reg ram_pkt_empty_d1 = 0; + + wire [C_DOUT_WIDTH-1:0] dout_p0_out; + wire packet_empty_wr; + wire wr_rst_fwft_pkt_fifo; + wire dummy_wr_eop; + wire ram_wr_en_pkt_fifo; + wire wr_eop; + wire ram_rd_en_compare; + wire stage1_eop; + wire pkt_ready_to_read; + wire rd_en_2_stage2; + + // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming) + // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP + // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of + // write packet count + generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + partial_packet <= 1'b0; + else begin + if (srst_delayed | wr_rst_busy | rd_rst_busy) + partial_packet <= #`TCQ 1'b0; + else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0])) + partial_packet <= #`TCQ 1'b1; + else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo) + partial_packet <= #`TCQ 1'b0; + end + end + end endgenerate // gdummy_wr_eop + + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft + assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0; + assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet); + assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1]; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + stage1_eop_d1 <= 1'b0; + rd_en_fifo_in_d1 <= 1'b0; + end else begin + if (srst_delayed | wr_rst_busy | rd_rst_busy) begin + stage1_eop_d1 <= #`TCQ 1'b0; + rd_en_fifo_in_d1 <= #`TCQ 1'b0; + end else begin + stage1_eop_d1 <= #`TCQ stage1_eop; + rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in; + end + end + end + assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1; + assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT); + assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop); + assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop; + + + fifo_generator_v13_2_7_bhv_ver_preload0 + #( + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USERVALID_LOW (C_VALID_LOW), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_FIFO_TYPE (2) // Enable low latency fwft logic + ) + pkt_fifo_fwft + ( + .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (rst_fwft), + .SRST (srst_delayed), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .RD_EN (rd_en_delayed), + .FIFOEMPTY (pkt_ready_to_read), + .FIFODATA (dout_fwft), + .FIFOSBITERR (sbiterr_fwft), + .FIFODBITERR (dbiterr_fwft), + // Output + .USERDATA (dout_p0_out), + .USERVALID (), + .USEREMPTY (empty_p0_out), + .USERALMOSTEMPTY (), + .USERUNDERFLOW (), + .RAMVALID (), + .FIFORDEN (rd_en_2_stage2), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR), + .STAGE2_REG_EN (), + .VALID_STAGES () + ); + + assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2)); + assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + eop_at_stage2 <= 1'b0; + else if (stage2_reg_en_i) + eop_at_stage2 <= #`TCQ stage1_eop; + end + + //--------------------------------------------------------------------------- + // Write and Read Packet Count + //--------------------------------------------------------------------------- + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + wr_pkt_count <= 0; + else if (srst_delayed | wr_rst_busy | rd_rst_busy) + wr_pkt_count <= #`TCQ 0; + else if (wr_eop) + wr_pkt_count <= #`TCQ wr_pkt_count + 1; + end + + end endgenerate //: gpkt_fifo_fwft + + assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out; + assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out; + + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + rd_pkt_count <= 0; + rd_pkt_count_plus1 <= 1; + end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin + rd_pkt_count <= #`TCQ 0; + rd_pkt_count_plus1 <= #`TCQ 1; + end else if (stage2_reg_en_i && stage1_eop) begin + rd_pkt_count <= #`TCQ rd_pkt_count + 1; + rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1; + end + end + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + ram_pkt_empty <= 1'b1; + ram_pkt_empty_d1 <= 1'b1; + end else if (SRST | wr_rst_busy | rd_rst_busy) begin + ram_pkt_empty <= #`TCQ 1'b1; + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin + ram_pkt_empty <= #`TCQ 1'b0; + ram_pkt_empty_d1 <= #`TCQ 1'b0; + end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin + ram_pkt_empty <= #`TCQ 1'b1; + end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end + end + end endgenerate //grss_pkt_cnt + + localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH; + reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0; + wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd; + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt + // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + wr_pkt_count_b2g <= 0; + else + wr_pkt_count_b2g <= #`TCQ wr_pkt_count; + end + + // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + wr_pkt_count_q <= 0; + else + wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g}; + end + + always @* begin + if (stage1_eop) + rd_pkt_count <= rd_pkt_count_reg + 1; + else + rd_pkt_count <= rd_pkt_count_reg; + end + + assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH]; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + rd_pkt_count_reg <= 0; + else if (rd_en_fifo_in) + rd_pkt_count_reg <= #`TCQ rd_pkt_count; + end + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + ram_pkt_empty <= 1'b1; + ram_pkt_empty_d1 <= 1'b1; + end else if (rd_pkt_count != wr_pkt_count_rd) begin + ram_pkt_empty <= #`TCQ 1'b0; + ram_pkt_empty_d1 <= #`TCQ 1'b0; + end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin + ram_pkt_empty <= #`TCQ 1'b1; + end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end + end + + // Synchronize the empty in write domain + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + pkt_empty_sync <= 'b1; + else + pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out}; + end + + end endgenerate //gras_pkt_cnt + + generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = rd_en_delayed; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end endgenerate // STD_FIFO + + generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO + assign empty_p0_out = empty_fwft; + assign SBITERR = sbiterr_fwft; + assign DBITERR = dbiterr_fwft; + assign DOUT = dout_fwft; + assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; + + end endgenerate // NO_PKT_FIFO + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3 + if (C_COMMON_CLOCK == 0) begin : block_ic + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block_ic + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30 + if (C_COMMON_CLOCK == 0) begin : block_ic + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block30 + endgenerate + + + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both + if (C_COMMON_CLOCK == 0) begin : block_ic_both + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT)); + end + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block30_both + endgenerate + + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both + if (C_COMMON_CLOCK == 0) begin : block_ic_both + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT)); + end //block_ic_both + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block3_both + endgenerate + + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + /************************************************************************** + * find_log2 + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function integer find_log2; + input integer int_val; + integer i,j; + begin + i = 1; + j = 0; + for (i = 1; i < int_val; i = i*2) begin + j = j + 1; + end + find_log2 = j; + end + endfunction + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."); + $finish; + end + + if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin + $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."); + $finish; + end + + if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin + $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."); + $finish; + end + + if (C_USE_ECC == 1) begin + if (C_DIN_WIDTH != C_DOUT_WIDTH) begin + $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration."); + $finish; + end + if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin + $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection."); + $finish; + end + end + + end //initial + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0; + assign rst_i = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0; + + wire rst_2_sync; + wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; + + localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5; + localparam RST_BUSY_LEN = 4; + reg wr_rst_busy_i = 0; + reg rd_rst_busy_i = 0; + generate + if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync + always @* begin + wr_rst_reg <= wr_rst_delayed; + rd_rst_reg <= rd_rst_delayed; + rst_reg <= 1'b0; + srst_reg <= 1'b0; + end + assign rst_2_sync = wr_rst_delayed; + assign wr_rst_busy = 1'b0; + assign wr_rst_busy_o = 1'b0; + assign rd_rst_busy = 1'b0; + assign sckt_wr_rst_i = 1'b0; + assign sckt_rd_rst_i = 1'b0; + end // gnrst_sync + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt + reg [1:0] arst_sync_wr = 2'b11; + reg [1:0] arst_sync_rd = 2'b11; + reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0; + reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0; + reg [3:0] rd_rst_wr_ext = 0; + reg [1:0] wr_rst_rd_ext = 0; + reg sckt_wr_rst_ic = 0; + reg sckt_rd_rst_ic = 0; + + assign rst_2_sync = arst_sync_wr[1]; + + always @(posedge WR_CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_wr <= #`TCQ 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed}; + end + + always @(posedge RD_CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_rd <= #`TCQ 2'b11; + else + arst_sync_rd <= #`TCQ {arst_sync_rd[0], rst_delayed}; + end + always @(posedge WR_CLK) begin + sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic}; + end + always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin + if (arst_sync_wr[1]) begin + sckt_wr_rst_ic <= #`TCQ 1'b1; + wr_rst_busy_i <= #`TCQ 1'b1; + rd_rst_wr_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}}; + end else begin + rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]}; + if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0]) + sckt_wr_rst_ic <= #`TCQ 1'b0; + else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2]) + wr_rst_busy_i <= #`TCQ 1'b0; + end + end + always @(posedge RD_CLK) begin + sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic}; + end + always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin + if (arst_sync_rd[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b1; + rd_rst_busy_i <= #`TCQ 1'b1; + wr_rst_rd_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}}; + end else begin + wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]}; + if (wr_rst_rd_ext[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b0; + rd_rst_busy_i <= #`TCQ 1'b0; + end + end + end + + assign rd_rst_busy = rd_rst_busy_i; + assign wr_rst_busy = wr_rst_busy_i; + assign wr_rst_busy_o = wr_rst_busy_i; + assign sckt_wr_rst_i = sckt_wr_rst_ic|arst_sync_wr[1]; + assign sckt_rd_rst_i = sckt_rd_rst_ic|arst_sync_rd[1]; + end // g7s_ic_rst_nsckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt + reg [RST_SYNC_STAGES-1:0] arst_sync_wr = {RST_SYNC_STAGES{1'b1}}; + reg [RST_SYNC_STAGES-1:0] arst_sync_rd = {RST_SYNC_STAGES{1'b1}}; + reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0; + reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0; + reg [3:0] rd_rst_wr_ext = 0; + reg [1:0] wr_rst_rd_ext = 0; + reg sckt_wr_rst_ic = 0; + reg sckt_rd_rst_ic = 0; + + always @(posedge WR_CLK) begin + arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic}; + rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]}; + if (arst_sync_wr[RST_SYNC_STAGES-1]) begin + sckt_wr_rst_ic <= #`TCQ 1'b1; + wr_rst_busy_i <= #`TCQ 1'b1; + end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0]) + sckt_wr_rst_ic <= #`TCQ 1'b0; + else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2]) + wr_rst_busy_i <= #`TCQ 1'b0; + end + always @(posedge RD_CLK) begin + arst_sync_rd <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]}; + if (arst_sync_rd[RST_SYNC_STAGES-1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b1; + rd_rst_busy_i <= #`TCQ 1'b1; + end else if (wr_rst_rd_ext[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b0; + rd_rst_busy_i <= #`TCQ 1'b0; + end + end + + assign rd_rst_busy = rd_rst_busy_i; + assign wr_rst_busy = wr_rst_busy_i; + assign wr_rst_busy_o = wr_rst_busy_i; + assign sckt_wr_rst_i = sckt_wr_rst_ic; + assign sckt_rd_rst_i = sckt_rd_rst_ic; + end // g7s_ic_rst_sckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt + reg [1:0] arst_sync_wr = 0; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + assign rst_2_sync = arst_sync_wr[1]; + + always @(posedge CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_wr <= #`TCQ 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed}; + end + + always @(posedge CLK) begin + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + end + + assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; + assign sckt_rd_rst_i = sckt_wr_rst_i; + assign wr_rst_busy = |sckt_wr_rst_cc | arst_sync_wr[1]; + assign rd_rst_busy = |sckt_wr_rst_cc; + assign wr_rst_busy_o = |sckt_wr_rst_cc; + end // g7s_cc_rst_nsckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt + reg [RST_SYNC_STAGES-1:0] arst_sync_wr = 0; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + + always @(posedge CLK) begin + arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + end + + assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; + assign sckt_rd_rst_i = sckt_wr_rst_i; + assign wr_rst_busy = |sckt_wr_rst_cc; + assign rd_rst_busy = |sckt_wr_rst_cc; + assign wr_rst_busy_o = |sckt_wr_rst_cc; + end // g7s_cc_rst_sckt + else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst + assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i; + assign rd_rst_busy = rst_reg; + assign rst_2_sync = srst_delayed; + assign sckt_wr_rst_i = rst_reg; + always @* rst_full_ff_i <= 1'b0; + always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0; + + always @(posedge CLK) begin + rst_delayed_d1 <= #`TCQ srst_delayed; + rst_delayed_d2 <= #`TCQ rst_delayed_d1; + if (rst_reg || rst_delayed_d2) begin + rst_active_i <= #`TCQ 1'b1; + end else begin + rst_active_i <= #`TCQ rst_reg; + end + end + always @(posedge CLK) begin + if (~rst_reg && srst_delayed) begin + rst_reg <= #`TCQ 1'b1; + end else if (rst_reg) begin + rst_reg <= #`TCQ 1'b0; + end else begin + rst_reg <= #`TCQ rst_reg; + end + end + end // g8s_cc_rst + else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst + assign wr_rst_busy = srst_delayed; + assign rd_rst_busy = srst_delayed; + assign rst_2_sync = srst_delayed; + assign sckt_wr_rst_i = srst_delayed; + always @* rst_full_ff_i <= 1'b0; + end // g7s_cc_srst + endgenerate + + reg rst_d1 = 1'b0; + reg rst_d2 = 1'b0; + reg rst_d3 = 1'b0; + reg rst_d4 = 1'b0; + generate + if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 + // RST_FULL_GEN replaces the reset falling edge detection used to de-assert + // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. + + // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & + // PROG_FULL + + always @ (posedge rst_2_sync or posedge clk_2_sync) begin + if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + rst_d3 <= 1'b1; + rst_d4 <= 1'b0; + end else begin + if (srst_delayed) begin + rst_d1 <= #`TCQ 1'b1; + rst_d2 <= #`TCQ 1'b1; + rst_d3 <= #`TCQ 1'b1; + rst_d4 <= #`TCQ 1'b0; + end else begin + rst_d1 <= #`TCQ wr_rst_busy;//1'b0; + rst_d2 <= #`TCQ rst_d1; + rst_d3 <= #`TCQ rst_d2 | sckt_wr_rst_i; + rst_d4 <= #`TCQ rst_d3; + end + end + end + + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i; + always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3; + + end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + always @* rst_full_gen_i <= 1'b0; + end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + always @* rst_full_gen_i <= 1'b0; + end + endgenerate // grstd1 + +endmodule //fifo_generator_v13_2_7_CONV_VER + + +module fifo_generator_v13_2_7_sync_stage + #( + parameter C_WIDTH = 10 + ) + ( + input RST, + input CLK, + input [C_WIDTH-1:0] DIN, + output reg [C_WIDTH-1:0] DOUT = 0 + ); + always @ (posedge RST or posedge CLK) begin + if (RST) + DOUT <= 0; + else + DOUT <= #`TCQ DIN; + end +endmodule // fifo_generator_v13_2_7_sync_stage + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v13_2_7_bhv_ver_as + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_FAMILY = "virtex7", + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input SAFETY_CKT_WR_RST, + input SAFETY_CKT_RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_CLK, + input RD_EN, + input RD_EN_USER, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input USER_EMPTY_FB, + input fab_read_data_valid_i, + input read_data_valid_i, + input ram_valid_i, + output reg ALMOST_EMPTY = 1'b1, + output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, + output [C_DOUT_WIDTH-1:0] DOUT, + output reg EMPTY = 1'b1, + output reg EMPTY_FB = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output UNDERFLOW, + output WR_ACK, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output SBITERR, + output DBITERR + ); + + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + localparam C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + localparam C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); + + localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i = WR_RST; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i = RD_RST; + wire ram_rd_en; + wire empty_int; + wire almost_empty_int; + wire ram_wr_en; + wire full_int; + wire almost_full_int; + reg ram_rd_en_d1 = 1'b0; + reg fab_rd_en_d1 = 1'b0; + + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + generate + if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1 + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + end + end + endgenerate + + + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY <= 1'b1; + ALMOST_EMPTY <= 1'b1; + rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; + end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin + EMPTY <= 1'b1; + ALMOST_EMPTY <= 1'b1; + rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY_FB <= 1'b1; + end else begin + if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) + EMPTY_FB <= #`TCQ 1'b1; + else if (empty_int) + EMPTY_FB <= #`TCQ 1'b1; + else + EMPTY_FB <= #`TCQ 1'b0; + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge RST_FULL_FF) + begin + if (RST_FULL_FF & C_HAS_RST) begin + FULL <= C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; + end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin + FULL <= C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; + end else begin + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (RST_FULL_GEN) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + always @ (posedge WR_CLK or posedge wr_rst_i) + begin + if (wr_rst_i) begin + wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= 0; + stage2_valid <= 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out1; + wire valid_out2; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [1:0] err_type_both = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = C_OVERFLOW_LOW; + reg ideal_underflow = C_UNDERFLOW_LOW; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg valid_d2 = 0; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) begin + $display("FAILURE : Data width must be >= 2 for double bit error injection."); + $finish; + end else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + err_type_d1 = 0; + err_type_both = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + valid_d2 = 1'b0; + ideal_overflow = C_OVERFLOW_LOW; + ideal_underflow = C_UNDERFLOW_LOW; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + //*************************************************************************** + // Safety-ckt logic with embedded reg/fabric reg + //*************************************************************************** + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + // if (C_HAS_VALID == 1) begin + // assign valid_out = valid_d1; + // end + + always@(posedge RD_CLK) + begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) + begin + if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + + always@(posedge rst_delayed_sft2 or posedge RD_CLK) + begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + else begin + if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1[0] <= #`TCQ err_type[0]; + err_type_d1[1] <= #`TCQ err_type[1]; + end + end + end + end + endgenerate + +//*************************************************************************** + // Safety-ckt logic with embedded reg + fabric reg + //*************************************************************************** + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin + if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) + ram_rd_en_d1 <= #`TCQ 1'b0; + else begin + ram_rd_en_d1 <= #`TCQ ram_rd_en; + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + end + end + + always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both[0] <= #`TCQ err_type[0]; + err_type_both[1] <= #`TCQ err_type[1]; + end + + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1[0] <= #`TCQ err_type_both[0]; + err_type_d1[1] <= #`TCQ err_type_both[1]; + end + end + end + end + endgenerate + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out1 = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)? + valid_d1: valid_i; + assign valid_out2 = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)? + valid_d2: valid_i; + assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + end + endgenerate + + + generate if (C_USE_EMBEDDED_REG == 3) begin + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1; + // assign diff_rd_wr_1 = diff_rd_wr +2'h2; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1))) + // rdc_fwft_ext_as <= 1'b0; + //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) + // rdc_fwft_ext_as <= 1'b1; + //else + rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ; + end + + + +end +end +end +endgenerate + + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= 1'b0; + valid_d2 <= 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + valid_d2 <= #`TCQ valid_d1; + end +// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin + // valid_d2 <= #`TCQ valid_d1; + // end + end + end + endgenerate + + //Capture delayed version of dout + /************************************************************************** + *embedded/fabric reg with no safety ckt + **************************************************************************/ + generate + if (C_USE_EMBEDDED_REG < 3) begin + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout <= #`TCQ dout_reset_val; + end + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + +end +endgenerate +/************************************************************************** + *embedded + fabric reg with no safety ckt + **************************************************************************/ + +generate + if (C_USE_EMBEDDED_REG == 3) begin + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both <= #`TCQ err_type; + end + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1 <= #`TCQ err_type_both; + end + end + end + end +endgenerate + + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw + always @(posedge WR_CLK) begin + //ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i); + ideal_overflow <= #`TCQ WR_EN & (FULL ); + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ (EMPTY) & RD_EN; + //ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write/Read Pointer Synchronization + **************************************************************************/ + localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1; + wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; + wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; + genvar gss; + + generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst + fifo_generator_v13_2_7_sync_stage + #( + .C_WIDTH (C_WR_PNTR_WIDTH) + ) + rd_stg_inst + ( + .RST (rd_rst_i), + .CLK (RD_CLK), + .DIN (wr_pntr_sync_stgs[gss-1]), + .DOUT (wr_pntr_sync_stgs[gss]) + ); + + fifo_generator_v13_2_7_sync_stage + #( + .C_WIDTH (C_RD_PNTR_WIDTH) + ) + wr_stg_inst + ( + .RST (wr_rst_i), + .CLK (WR_CLK), + .DIN (rd_pntr_sync_stgs[gss-1]), + .DOUT (rd_pntr_sync_stgs[gss]) + ); + end endgenerate // Sync_stage_inst + + assign wr_pntr_sync_stgs[0] = wr_pntr_rd1; + assign rd_pntr_sync_stgs[0] = rd_pntr_wr1; + always@* begin + wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; + rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; + end + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp + if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0) + wr_pntr <= 0; + else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1) + wr_pntr <= #`TCQ 0; + end + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits = 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + ideal_wr_count <= 0; + tmp_wr_listsize = 0; + rd_ptr_wrclk_next <= 0; + wr_pntr_rd1 <= 0; + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // gen_fifo_w + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val; + wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val; + + generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT + assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC; + assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC; + end else begin // STD + assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL; + assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL; + end endgenerate + + always @(posedge WR_CLK or posedge wr_rst_i) begin + + if (wr_rst_i == 1'b1) begin + diff_pntr <= 0; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + end + end + + + always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf + + if (RST_FULL_FF & C_HAS_RST) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + end else begin + + if (RST_FULL_GEN) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < pf_thr_negate_val) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val; + wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i & C_HAS_RST) begin + diff_pntr_rd <= 0; + ideal_prog_empty <= 1'b1; + end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin + diff_pntr_rd <= 0; + ideal_prog_empty <= 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + end // gen_pe + + generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH; + end endgenerate // single_pe_thr_input + + generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT; + assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE; + end endgenerate // multiple_pe_thr_input + + generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL; + assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL; + end endgenerate // single_multiple_pe_thr_const + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + rd_pntr <= 0; + else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1) + rd_pntr <= #`TCQ 0; + end + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i & C_HAS_RST) begin + num_rd_bits <= 0; + next_num_rd_bits = 0; + rd_ptr <= C_RD_DEPTH -1; + rd_pntr_wr1 <= 0; + wr_ptr_rdclk <= C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= 1'b0; + ideal_rd_count <= 0; + + end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin + num_rd_bits <= 0; + next_num_rd_bits = 0; + rd_ptr <= C_RD_DEPTH -1; + rd_pntr_wr1 <= 0; + wr_ptr_rdclk <= C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= 1'b0; + ideal_rd_count <= 0; + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always gen_fifo_r_as + +endmodule // fifo_generator_v13_2_7_bhv_ver_as + + +/******************************************************************************* + * Declaration of Low Latency Asynchronous FIFO + ******************************************************************************/ +module fifo_generator_v13_2_7_beh_ver_ll_afifo + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_USE_DOUT_RST = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_FIFO_TYPE = 0 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input [C_DIN_WIDTH-1:0] DIN, + input RD_CLK, + input RD_EN, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + output reg [C_DOUT_WIDTH-1:0] DOUT = 0, + output reg EMPTY = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL + ); + + //----------------------------------------------------------------------------- + // Low Latency Asynchronous FIFO + //----------------------------------------------------------------------------- + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + integer i; + initial begin + for (i = 0; i < C_WR_DEPTH; i = i + 1) + memory[i] = 0; + end + + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0; + wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0; + reg ll_afifo_full = 1'b0; + reg ll_afifo_empty = 1'b1; + wire write_allow; + wire read_allow; + + assign write_allow = WR_EN & ~ll_afifo_full; + assign read_allow = RD_EN & ~ll_afifo_empty; + + //----------------------------------------------------------------------------- + // Write Pointer Generation + //----------------------------------------------------------------------------- + always @(posedge WR_CLK or posedge WR_RST) begin + if (WR_RST) + wr_pntr_ll_afifo <= 0; + else if (write_allow) + wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1; + end + + //----------------------------------------------------------------------------- + // Read Pointer Generation + //----------------------------------------------------------------------------- + always @(posedge RD_CLK or posedge RD_RST) begin + if (RD_RST) + rd_pntr_ll_afifo_q <= 0; + else + rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo; + end + assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q; + + //----------------------------------------------------------------------------- + // Fill the Memory + //----------------------------------------------------------------------------- + always @(posedge WR_CLK) begin + if (write_allow) + memory[wr_pntr_ll_afifo] <= #`TCQ DIN; + end + + //----------------------------------------------------------------------------- + // Generate DOUT + //----------------------------------------------------------------------------- + always @(posedge RD_CLK) begin + DOUT <= #`TCQ memory[rd_pntr_ll_afifo]; + end + + //----------------------------------------------------------------------------- + // Generate EMPTY + //----------------------------------------------------------------------------- + always @(posedge RD_CLK or posedge RD_RST) begin + if (RD_RST) + ll_afifo_empty <= 1'b1; + else + ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | + (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1)))); + end + + //----------------------------------------------------------------------------- + // Generate FULL + //----------------------------------------------------------------------------- + always @(posedge WR_CLK or posedge WR_RST) begin + if (WR_RST) + ll_afifo_full <= 1'b1; + else + ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | + (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2)))); + end + + always @* begin + FULL <= ll_afifo_full; + EMPTY <= ll_afifo_empty; + end + +endmodule // fifo_generator_v13_2_7_beh_ver_ll_afifo + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v13_2_7_bhv_ver_ss + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + #( + parameter C_FAMILY = "virtex7", + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_FIFO_TYPE = 0 + ) + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + ( + //Inputs + input SAFETY_CKT_WR_RST, + input CLK, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_EN, + input RD_EN_USER, + input USER_EMPTY_FB, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input SRST, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input WR_RST_BUSY, + input RD_RST_BUSY, + + //Outputs + output ALMOST_EMPTY, + output ALMOST_FULL, + output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0, + output [C_DOUT_WIDTH-1:0] DOUT, + output EMPTY, + output reg EMPTY_FB = 1'b1, + output FULL, + output OVERFLOW, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output UNDERFLOW, + output WR_ACK, + output SBITERR, + output DBITERR + ); + + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss; + wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + localparam C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + localparam C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; + + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); + localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + //localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); + + localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); + + localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + localparam C_HAS_FAST_FIFO = 0; + localparam C_FIFO_WR_DEPTH = C_WR_DEPTH; + localparam C_FIFO_RD_DEPTH = C_RD_DEPTH; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH; + localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1; + localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; + localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + + wire ram_rd_en; + wire empty_int; + wire almost_empty_int; + wire ram_wr_en; + wire full_int; + wire almost_full_int; + reg ram_rd_en_reg = 1'b0; + reg ram_rd_en_d1 = 1'b0; + reg fab_rd_en_d1 = 1'b0; + wire srst_rrst_busy; + + + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [1:0] err_type_both = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = C_OVERFLOW_LOW; + reg ideal_underflow = C_UNDERFLOW_LOW; + + reg full_i = C_FULL_FLAGS_RST_VAL; + reg full_i_temp = 0; + reg empty_i = 1; + reg almost_full_i = 0; + reg almost_empty_i = 1; + reg prog_full_i = 0; + reg prog_empty_i = 1; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0; + + reg write_allow_q = 0; + reg read_allow_q = 0; + reg valid_d1 = 0; + reg valid_both = 0; + reg valid_d2 = 0; + wire rst_i; + wire srst_i; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin + case (def_data[7:0]) + 8'b00000000 : begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) begin + if ((index*4)+j < C_DOUT_WIDTH) begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + //reg valid_d1 = 0; + + + //user specified value for reseting the size of the fifo + //reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) begin + $display("FAILURE : Data width must be >= 2 for double bit error injection."); + $finish; + end else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + + end + endtask + + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + err_type_d1 = 0; + err_type_both = 0; + ideal_dout_d1 = dout_reset_val; + ideal_dout_both = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + valid_both = 1'b0; + ideal_overflow = C_OVERFLOW_LOW; + ideal_underflow = C_UNDERFLOW_LOW; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + // Assign ALMOST_EPMTY + generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae + assign ALMOST_EMPTY = almost_empty_i; + end else begin : gnae + assign ALMOST_EMPTY = 0; + end endgenerate // gae + + // Assign ALMOST_FULL + generate if (C_HAS_ALMOST_FULL==1) begin : gaf + assign ALMOST_FULL = almost_full_i; + end else begin : gnaf + assign ALMOST_FULL = 0; + end endgenerate // gaf + + // Dout may change behavior based on latency + localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = empty_i; + assign FULL = full_i; + //saftey_ckt with one register + + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge CLK) + begin + rst_delayed_sft1 <= #`TCQ rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) + begin + if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + valid_d1 <= #`TCQ 1'b0; + end + else begin + ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); + valid_d1 <= #`TCQ valid_i; + end + end + + always@(posedge rst_delayed_sft2 or posedge CLK) + begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + else if (srst_rrst_busy == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1[0] <= #`TCQ err_type[0]; + err_type_d1[1] <= #`TCQ err_type[1]; + end + end + end //if + endgenerate + +//safety ckt with both registers + +generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge CLK) begin + rst_delayed_sft1 <= #`TCQ rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin + if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + valid_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + valid_both <= #`TCQ valid_i; + valid_d1 <= #`TCQ valid_both; + end + end + + always@(posedge rst_delayed_sft2 or posedge CLK) begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else if (srst_rrst_busy == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both[0] <= #`TCQ err_type[0]; + err_type_both[1] <= #`TCQ err_type[1]; + end + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1[0] <= #`TCQ err_type_both[0]; + err_type_d1[1] <= #`TCQ err_type_both[1]; + end + end + end + end //if + endgenerate + + + //Overflow may be active-low + generate if (C_HAS_OVERFLOW==1) begin : gof + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end else begin : gnof + assign OVERFLOW = 0; + end endgenerate // gof + + assign PROG_EMPTY = prog_empty_i; + assign PROG_FULL = prog_full_i; + + //Valid may change behavior based on latency or active-low + generate if (C_HAS_VALID==1) begin : gvalid + assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ? + valid_d1 : valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end else begin : gnvalid + assign VALID = 0; + end endgenerate // gvalid + + //Trim data count differently depending on set widths + generate if (C_HAS_DATA_COUNT == 1) begin : gdc + always @* begin + diff_count <= wr_pntr - rd_pntr; + if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin + DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count; + DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; + end else begin + DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end + end +// end else begin : gndc +// always @* DATA_COUNT <= 0; + end endgenerate // gdc + + //Underflow may change behavior based on latency or active-low + generate if (C_HAS_UNDERFLOW==1) begin : guf + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end else begin : gnuf + assign UNDERFLOW = 0; + end endgenerate // guf + + + //Write acknowledge may be active low + generate if (C_HAS_WR_ACK==1) begin : gwr_ack + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end else begin : gnwr_ack + assign WR_ACK = 0; + end endgenerate // gwr_ack + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0; + assign rst_i = C_HAS_RST ? RST : 0; + assign srst_wrst_busy = srst_i; + assign srst_rrst_busy = srst_i; + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + if (srst_rrst_busy) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate // blockVL20 + + generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + valid_both <= 1'b0; + end else begin + if (srst_rrst_busy) begin + valid_d1 <= #`TCQ 1'b0; + valid_both <= #`TCQ 1'b0; + + end else begin + valid_both <= #`TCQ valid_i; + valid_d1 <= #`TCQ valid_both; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate // blockVL20 + + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge CLK or posedge rst_i) begin + if (rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + ram_rd_en_d1 <= #`TCQ 1'b0; + if (C_USE_DOUT_RST == 1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; + if (srst_rrst_busy) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + if (C_USE_DOUT_RST == 1) begin + // @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1 ) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + end // always +end +endgenerate + +//no safety ckt with both registers + generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + fab_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + + end + if (C_USE_DOUT_RST == 1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end else begin + if (srst_rrst_busy) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + fab_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + if (C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; + fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1); + if (ram_rd_en_d1 ) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both <= #`TCQ err_type; + end + if (fab_rd_en_d1 ) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1 <= #`TCQ err_type_both; + end + end + end + end // always +end +endgenerate + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & full_i; + end + end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw + always @(posedge CLK) begin + //ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i); + ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i); + end + end endgenerate // blockOF20 + + generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw + always @(posedge CLK) begin + ideal_underflow <= #`TCQ empty_i & RD_EN; + end + end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw + always @(posedge CLK) begin + //ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN; + ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN; + end + end endgenerate // blockUF20 + + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + wire write_allow; + wire read_allow; + wire read_allow_dc; + wire write_only; + wire read_only; + //wire write_only_q; + reg write_only_q; + //wire read_only_q; + reg read_only_q; + reg full_reg; + reg rst_full_ff_reg1; + reg rst_full_ff_reg2; + wire ram_full_comb; + wire carry; + + assign write_allow = WR_EN & ~full_i; + assign read_allow = RD_EN & ~empty_i; + assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB; + //assign write_only = write_allow & ~read_allow; + //assign write_only_q = write_allow_q; + //assign read_only = read_allow & ~write_allow; + //assign read_only_q = read_allow_q ; + wire [C_WR_PNTR_WIDTH-1:0] diff_pntr; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0; + reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0; + wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ; + wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max; + + assign diff_pntr_pe_max = DIFF_MAX_RD; + assign diff_pntr_max = DIFF_MAX_WR; + + + + generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym + assign write_only = write_allow & ~read_allow; + assign read_only = read_allow & ~write_allow; + end endgenerate + generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd + assign read_only = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow; + assign write_only = write_allow & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])); + end endgenerate + generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr + assign read_only = read_allow & ~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + assign write_only = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow; + end endgenerate + + + //----------------------------------------------------------------------------- + // Write and Read pointer generation + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i && C_EN_SAFETY_CKT == 0) begin + wr_pntr <= 0; + rd_pntr <= 0; + end else begin + if (srst_i) begin + wr_pntr <= #`TCQ 0; + rd_pntr <= #`TCQ 0; + end else begin + if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1; + if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1; + end + end + end + + generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout + always @(posedge CLK) begin + if (write_allow) begin + if (ENABLE_ERR_INJECTION == 1) + memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN}; + else + memory[wr_pntr] <= #`TCQ DIN; + end + end + + reg [C_DATA_WIDTH-1:0] dout_tmp_q; + reg [C_DATA_WIDTH-1:0] dout_tmp = 0; + reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0; + always @(posedge CLK) begin + dout_tmp_q <= #`TCQ ideal_dout; + end + + + + always @* begin + if (read_allow) + ideal_dout <= memory[rd_pntr]; + else + ideal_dout <= dout_tmp_q; + end + end endgenerate // gll_dm_dout + + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + assign ram_rd_en = RD_EN & !EMPTY; + + //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + generate if (C_FIFO_TYPE != 2) begin : gnll_din + always @(posedge CLK or posedge rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + + end else begin //rst_i==0 + if (srst_wrst_busy) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + end else begin//srst_i=0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + end else begin + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + ideal_wr_count <= num_write_words_sized_i; + + //end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //srst_i==0 + end //wr_rst_i==0 + end // gen_fifo_w + end endgenerate + + generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout + always @(posedge CLK) begin + if (rst_i || srst_rrst_busy) begin + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end + end + end endgenerate + + + + + generate if (C_FIFO_TYPE != 2) begin : gnll_dout + always @(posedge CLK or posedge rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + //rd_pntr_wr1 <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= #`TCQ 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + if (srst_rrst_busy) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + //rd_pntr_wr1 <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets synchronously + if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= #`TCQ 0; + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + end //srst_i + else begin + + //rd_pntr_wr1 <= #`TCQ rd_pntr; + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + if (RD_EN == 1'b1) begin + + if (EMPTY == 1'b1) begin + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end + else + begin + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + end + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //s_rst_i==0 + end //rd_rst_i==0 + end //always + end endgenerate + + //----------------------------------------------------------------------------- + // Generate diff_pntr for PROG_FULL generation + // Generate diff_pntr_pe for PROG_EMPTY generation + //----------------------------------------------------------------------------- + generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow + always @(posedge CLK ) begin + if (rst_i) begin + write_only_q <= 1'b0; + read_only_q <= 1'b0; + diff_pntr_reg1 <= 0; + diff_pntr_pe_reg1 <= 0; + diff_pntr_reg2 <= 0; + diff_pntr_pe_reg2 <= 0; + end else begin + if (srst_i || srst_wrst_busy || srst_rrst_busy) begin + if (srst_rrst_busy) begin + read_only_q <= #`TCQ 1'b0; + diff_pntr_pe_reg1 <= #`TCQ 0; + diff_pntr_pe_reg2 <= #`TCQ 0; + end + if (srst_wrst_busy) begin + write_only_q <= #`TCQ 1'b0; + diff_pntr_reg1 <= #`TCQ 0; + diff_pntr_reg2 <= #`TCQ 0; + end + end else begin + write_only_q <= #`TCQ write_only; + read_only_q <= #`TCQ read_only; + diff_pntr_reg2 <= #`TCQ diff_pntr_reg1; + diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1; + + // Add 1 to the difference pointer value when only write happens. + if (write_only) + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1; + else + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; + + // Add 1 to the difference pointer value when write or both write & read or no write & read happen. + if (read_only) + diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1; + else + diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr; + end + end + end + assign diff_pntr_pe = diff_pntr_pe_reg1; + assign diff_pntr = diff_pntr_reg1; + end endgenerate // reg_write_allow + + generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym + assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1}; + assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1}; + always @(posedge CLK ) begin + if (rst_i) begin + diff_pntr_pe_asym <= 0; + diff_pntr_reg1 <= 0; + full_reg <= 0; + rst_full_ff_reg1 <= 1; + rst_full_ff_reg2 <= 1; + diff_pntr_pe_reg1 <= 0; + end else begin + if (srst_i || srst_wrst_busy || srst_rrst_busy) begin + if (srst_wrst_busy) + diff_pntr_reg1 <= #`TCQ 0; + if (srst_rrst_busy) + full_reg <= #`TCQ 0; + rst_full_ff_reg1 <= #`TCQ 1; + rst_full_ff_reg2 <= #`TCQ 1; + diff_pntr_pe_asym <= #`TCQ 0; + diff_pntr_pe_reg1 <= #`TCQ 0; + end else begin + diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym; + full_reg <= #`TCQ full_i; + rst_full_ff_reg1 <= #`TCQ RST_FULL_FF; + rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1; + if (~full_i) begin + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; + end + end + end + end + assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1]))); + assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1]; + assign diff_pntr = diff_pntr_reg1; + end endgenerate // reg_write_allow_asym + + + //----------------------------------------------------------------------------- + // Generate FULL flag + //----------------------------------------------------------------------------- + wire comp0; + wire comp1; + wire going_full; + wire leaving_full; + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad + assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0; + end endgenerate + + generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim + assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end endgenerate + + assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1)); + assign comp0 = (adj_rd_pntr_wr == wr_pntr); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp + assign going_full = (comp1 & write_allow & ~read_allow); + assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN; + end endgenerate + + // Write data width is bigger than read data width + // Write depth is smaller than read depth + // One write could be equal to 2 or 4 or 8 reads + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym + assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); + assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp + assign going_full = (comp1 & write_allow & ~read_allow); + assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN; + end endgenerate + + + assign ram_full_comb = going_full | (~leaving_full & full_i); + + generate if (C_HAS_RST == 1) begin : grst_full + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF & C_HAS_RST) + full_i <= C_FULL_FLAGS_RST_VAL; + else + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + generate if (C_HAS_SRST == 1) begin : gsrst_full + always @(posedge CLK) begin + if (srst_wrst_busy) + full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full + always @(posedge CLK) begin + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + //----------------------------------------------------------------------------- + // Generate EMPTY flag + //----------------------------------------------------------------------------- + wire ecomp0; + wire ecomp1; + wire going_empty; + wire leaving_empty; + wire ram_empty_comb; + + + generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad + assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0; + end endgenerate + + generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim + assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end endgenerate + + assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1)); + assign ecomp0 = (adj_wr_pntr_rd == rd_pntr); + + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp + assign going_empty = (ecomp1 & ~write_allow & read_allow); + assign leaving_empty = (ecomp0 & write_allow); + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp + assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); + assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + end endgenerate + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp + assign going_empty = (ecomp1 & ~write_allow & read_allow); + assign leaving_empty =(ecomp0 & write_allow); + end endgenerate + + + + assign ram_empty_comb = going_empty | (~leaving_empty & empty_i); + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + empty_i <= 1'b1; + else if (srst_rrst_busy) + empty_i <= #`TCQ 1'b1; + else + empty_i <= #`TCQ ram_empty_comb; + end + always @(posedge CLK or posedge rst_i) begin + if (rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY_FB <= 1'b1; + end else begin + if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT)) + EMPTY_FB <= #`TCQ 1'b1; + else + EMPTY_FB <= #`TCQ ram_empty_comb; + end + end // always + + //----------------------------------------------------------------------------- + // Generate Read and write data counts for asymmetic common clock + //----------------------------------------------------------------------------- + + reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; + wire [C_GRTR_PNTR_WIDTH :0] ratio; + wire decr_by_one; + wire incr_by_ratio; + wire incr_by_one; + wire decr_by_ratio; + + localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr + assign ratio = C_DEPTH_RATIO_RD; + assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow; + assign incr_by_ratio = write_allow; + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + count_dc <= #`TCQ 0; + else if (srst_wrst_busy) + count_dc <= #`TCQ 0; + else begin + if (decr_by_one) begin + if (!incr_by_ratio) + count_dc <= #`TCQ count_dc - 1; + else + count_dc <= #`TCQ count_dc - 1 + ratio ; + end + else begin + if (!incr_by_ratio) + count_dc <= #`TCQ count_dc ; + else + count_dc <= #`TCQ count_dc + ratio ; + end + end + end + + assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc; + assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + + end endgenerate + + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd + assign ratio = C_DEPTH_RATIO_WR; + assign incr_by_one = write_allow; + assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow; + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + count_dc <= #`TCQ 0; + else if (srst_wrst_busy) + count_dc <= #`TCQ 0; + else begin + if (incr_by_one) begin + if (!decr_by_ratio) + count_dc <= #`TCQ count_dc + 1; + else + count_dc <= #`TCQ count_dc + 1 - ratio ; + end + else begin + if (!decr_by_ratio) + count_dc <= #`TCQ count_dc ; + else + count_dc <= #`TCQ count_dc - ratio ; + end + end + end + + assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc; + assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + + end endgenerate + + + + + + + //----------------------------------------------------------------------------- + // Generate WR_ACK flag + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + ideal_wr_ack <= 1'b0; + else if (srst_wrst_busy) + ideal_wr_ack <= #`TCQ 1'b0; + else if (WR_EN & ~full_i) + ideal_wr_ack <= #`TCQ 1'b1; + else + ideal_wr_ack <= #`TCQ 1'b0; + end + + //----------------------------------------------------------------------------- + // Generate VALID flag + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + ideal_valid <= 1'b0; + else if (srst_rrst_busy) + ideal_valid <= #`TCQ 1'b0; + else if (RD_EN & ~empty_i) + ideal_valid <= #`TCQ 1'b1; + else + ideal_valid <= #`TCQ 1'b0; + end + + + //----------------------------------------------------------------------------- + // Generate ALMOST_FULL flag + //----------------------------------------------------------------------------- + //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss + + wire fcomp2; + wire going_afull; + wire leaving_afull; + wire ram_afull_comb; + + + assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2)); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp + assign going_afull = (fcomp2 & write_allow & ~read_allow); + assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN; + end endgenerate + + // Write data width is bigger than read data width + // Write depth is smaller than read depth + // One write could be equal to 2 or 4 or 8 reads + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym + assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); + assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp + assign going_afull = (fcomp2 & write_allow & ~read_allow); + assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN; + end endgenerate + + assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i); + + + generate if (C_HAS_RST == 1) begin : grst_afull + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF & C_HAS_RST) + almost_full_i <= C_FULL_FLAGS_RST_VAL; + else + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + generate if (C_HAS_SRST == 1) begin : gsrst_afull + always @(posedge CLK) begin + if (srst_wrst_busy) + almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull + always @(posedge CLK) begin + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + //----------------------------------------------------------------------------- + // Generate ALMOST_EMPTY flag + //----------------------------------------------------------------------------- + //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss + + wire ecomp2; + wire going_aempty; + wire leaving_aempty; + wire ram_aempty_comb; + + assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2)); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp + assign going_aempty = (ecomp2 & ~write_allow & read_allow); + assign leaving_aempty = (ecomp1 & write_allow & ~read_allow); + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp + assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); + assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + end endgenerate + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp + assign going_aempty = (ecomp2 & ~write_allow & read_allow); + assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow); + end endgenerate + + + assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i); + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + almost_empty_i <= 1'b1; + else if (srst_rrst_busy) + almost_empty_i <= #`TCQ 1'b1; + else + almost_empty_i <= #`TCQ ram_aempty_comb; + end + // end endgenerate // gae_ss + + //----------------------------------------------------------------------------- + // Generate PROG_FULL + //----------------------------------------------------------------------------- + + localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT + C_PROG_FULL_THRESH_ASSERT_VAL; // STD + localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT + C_PROG_FULL_THRESH_NEGATE_VAL; // STD + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for single programmable threshold constant + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL; + generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~RST_FULL_GEN ) begin + if (diff_pntr>= C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b1; + else if ((diff_pntr) < C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ 1'b0; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + end + end + end endgenerate // single_pf_const + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for multiple programmable threshold constants + //----------------------------------------------------------------------------- + generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const + always @(posedge CLK or posedge RST_FULL_FF) begin + //if (RST_FULL_FF) + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~RST_FULL_GEN ) begin + if (diff_pntr >= C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < C_PF_NEGATE_VAL) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + end + end + end endgenerate //multiple_pf_const + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for single programmable threshold input port + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? + PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT + PROG_FULL_THRESH; // STD + generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input + + always @(posedge CLK or posedge RST_FULL_FF) begin//0 + //if (RST_FULL_FF) + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin //1 + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin//2 + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~almost_full_i) begin//3 + if (diff_pntr > pf3_assert_val) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == pf3_assert_val) begin//4 + if (read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ 1'b1; + end else//4 + prog_full_i <= #`TCQ 1'b0; + end else//3 + prog_full_i <= #`TCQ prog_full_i; + end //2 + else begin//5 + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~full_i ) begin//6 + if (diff_pntr >= pf3_assert_val ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < pf3_assert_val) begin//7 + prog_full_i <= #`TCQ 1'b0; + end//7 + end//6 + else + prog_full_i <= #`TCQ prog_full_i; + end//5 + end//1 + end//0 + end endgenerate //single_pf_input + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for multiple programmable threshold input ports + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT + PROG_FULL_THRESH_ASSERT; // STD + wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT + PROG_FULL_THRESH_NEGATE; // STD + + generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~almost_full_i) begin + if (diff_pntr >= pf_assert_val) + prog_full_i <= #`TCQ 1'b1; + else if ((diff_pntr == pf_negate_val && read_only_q) || + diff_pntr < pf_negate_val) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~full_i ) begin + if (diff_pntr >= pf_assert_val ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < pf_negate_val) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + + end + end + end endgenerate //multiple_pf_inputs + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY + //----------------------------------------------------------------------------- + localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT + C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD + localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT + C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for single programmable threshold constant + //----------------------------------------------------------------------------- + generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (~rst_i ) begin + if (diff_pntr_pe <= C_PE_ASSERT_VAL) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > C_PE_ASSERT_VAL) + prog_empty_i <= #`TCQ 1'b0; + end + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + end + end endgenerate // single_pe_const + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for multiple programmable threshold constants + //----------------------------------------------------------------------------- + generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (~rst_i ) begin + if (diff_pntr_pe <= C_PE_ASSERT_VAL ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > C_PE_NEGATE_VAL) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else + prog_empty_i <= #`TCQ prog_empty_i; + end + + end + + end + end endgenerate //multiple_pe_const + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for single programmable threshold input port + //----------------------------------------------------------------------------- + wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH -2) : // FWFT + PROG_EMPTY_THRESH; // STD + generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (~almost_full_i) begin + if (diff_pntr_pe < pe3_assert_val) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == pe3_assert_val) begin + if (write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ 1'b1; + end else + prog_empty_i <= #`TCQ 1'b0; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (diff_pntr_pe <= pe3_assert_val ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > pe3_assert_val) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + + end + end endgenerate // single_pe_input + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for multiple programmable threshold input ports + //----------------------------------------------------------------------------- + wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT + PROG_EMPTY_THRESH_ASSERT; // STD + wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT + PROG_EMPTY_THRESH_NEGATE; // STD + generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (~almost_full_i) begin + if (diff_pntr_pe <= pe4_assert_val) + prog_empty_i <= #`TCQ 1'b1; + else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || + (diff_pntr_pe > pe4_negate_val)) begin + prog_empty_i <= #`TCQ 1'b0; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (diff_pntr_pe <= pe4_assert_val ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > pe4_negate_val) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + end + end endgenerate // multiple_pe_inputs + +endmodule // fifo_generator_v13_2_7_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v13_2_7_bhv_ver_preload0 + #( + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_HAS_RST = 0, + parameter C_ENABLE_RST_SYNC = 0, + parameter C_HAS_SRST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USERVALID_LOW = 0, + parameter C_USERUNDERFLOW_LOW = 0, + parameter C_MEMORY_TYPE = 0, + parameter C_FIFO_TYPE = 0 + ) + ( + //Inputs + input SAFETY_CKT_RD_RST, + input RD_CLK, + input RD_RST, + input SRST, + input WR_RST_BUSY, + input RD_RST_BUSY, + input RD_EN, + input FIFOEMPTY, + input [C_DOUT_WIDTH-1:0] FIFODATA, + input FIFOSBITERR, + input FIFODBITERR, + + //Outputs + output reg [C_DOUT_WIDTH-1:0] USERDATA, + output USERVALID, + output USERUNDERFLOW, + output USEREMPTY, + output USERALMOSTEMPTY, + output RAMVALID, + output FIFORDEN, + output reg USERSBITERR, + output reg USERDBITERR, + output reg STAGE2_REG_EN, + output fab_read_data_valid_i_o, + output read_data_valid_i_o, + output ram_valid_i_o, + output [1:0] VALID_STAGES + ); + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg fab_valid; + reg read_data_valid_i; + reg fab_read_data_valid_i; + reg fab_read_data_valid_i_1; + reg ram_valid_i_d; + reg read_data_valid_i_d; + reg fab_read_data_valid_i_d; + wire ram_regout_en; + reg ram_regout_en_d1; + reg ram_regout_en_d2; + wire fab_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_sckt = 1'b1; + reg sckt_rrst_q = 1'b0; + reg sckt_rrst_done = 1'b0; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + reg [C_DOUT_WIDTH-1:0] userdata_both; + wire uservalid_both; + wire uservalid_one; + reg user_sbiterr_both = 1'b0; + reg user_dbiterr_both = 1'b0; + +assign ram_valid_i_o = ram_valid_i; +assign read_data_valid_i_o = read_data_valid_i; +assign fab_read_data_valid_i_o = fab_read_data_valid_i; + + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + fab_valid = 1'b0; + read_data_valid_i = 1'b0; + fab_read_data_valid_i = 1'b0; + fab_read_data_valid_i_1 = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + userdata_both = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + user_sbiterr_both = 1'b0; + user_dbiterr_both = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0; + + reg sckt_rd_rst_fwft = 1'b0; + reg fwft_rst_done_i = 1'b0; + wire fwft_rst_done; + assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1; + always @ (posedge RD_CLK) begin + sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST; + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i) + fwft_rst_done_i <= 1'b0; + else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST) + fwft_rst_done_i <= #`TCQ 1'b1; + end + + localparam INVALID = 0; + localparam STAGE1_VALID = 2; + localparam STAGE2_VALID = 1; + localparam BOTH_STAGES_VALID = 3; + + reg [1:0] curr_fwft_state = INVALID; + reg [1:0] next_fwft_state = INVALID; + + +generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin + always @* begin + case (curr_fwft_state) + INVALID: begin + if (~FIFOEMPTY) + next_fwft_state <= STAGE1_VALID; + else + next_fwft_state <= INVALID; + end + STAGE1_VALID: begin + if (FIFOEMPTY) + next_fwft_state <= STAGE2_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + STAGE2_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= INVALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE1_VALID; + else if (~FIFOEMPTY && ~RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= STAGE2_VALID; + end + BOTH_STAGES_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE2_VALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + default: next_fwft_state <= INVALID; + endcase + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + curr_fwft_state <= INVALID; + else if (srst_i) + curr_fwft_state <= #`TCQ INVALID; + else + curr_fwft_state <= #`TCQ next_fwft_state; + end + + always @* begin + case (curr_fwft_state) + INVALID: STAGE2_REG_EN <= 1'b0; + STAGE1_VALID: STAGE2_REG_EN <= 1'b1; + STAGE2_VALID: STAGE2_REG_EN <= 1'b0; + BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; + default: STAGE2_REG_EN <= 1'b0; + endcase + end + + + assign VALID_STAGES = curr_fwft_state; + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); + + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + end +endgenerate // gnll_fifo + + reg curr_state = 0; + reg next_state = 0; + reg leaving_empty_fwft = 0; + reg going_empty_fwft = 0; + reg empty_i_q = 0; + reg ram_rd_en_fwft = 0; + generate if (C_FIFO_TYPE == 2) begin : gll_fifo + always @* begin // FSM fo FWFT + case (curr_state) + 1'b0: begin + if (~FIFOEMPTY) + next_state <= 1'b1; + else + next_state <= 1'b0; + end + 1'b1: begin + if (FIFOEMPTY && RD_EN) + next_state <= 1'b0; + else + next_state <= 1'b1; + end + default: next_state <= 1'b0; + endcase + end + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + empty_i <= 1'b1; + empty_i_q <= 1'b1; + ram_valid_i <= 1'b0; + end else if (srst_i) begin + empty_i <= #`TCQ 1'b1; + empty_i_q <= #`TCQ 1'b1; + ram_valid_i <= #`TCQ 1'b0; + end else begin + empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i); + empty_i_q <= #`TCQ FIFOEMPTY; + ram_valid_i <= #`TCQ next_state; + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + curr_state <= 1'b0; + end else if (srst_i) begin + curr_state <= #`TCQ 1'b0; + end else begin + curr_state <= #`TCQ next_state; + end + end //always + + wire fe_of_empty; + assign fe_of_empty = empty_i_q & ~FIFOEMPTY; + + always @* begin // Finding leaving empty + case (curr_state) + 1'b0: leaving_empty_fwft <= fe_of_empty; + 1'b1: leaving_empty_fwft <= 1'b1; + default: leaving_empty_fwft <= 1'b0; + endcase + end + + always @* begin // Finding going empty + case (curr_state) + 1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN; + default: going_empty_fwft <= 1'b0; + endcase + end + + always @* begin // Generating FWFT rd_en + case (curr_state) + 1'b0: ram_rd_en_fwft <= ~FIFOEMPTY; + 1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN; + default: ram_rd_en_fwft <= 1'b0; + endcase + end + + assign ram_regout_en = ram_rd_en_fwft; + //assign ram_regout_en_d1 = ram_rd_en_fwft; + //assign ram_regout_en_d2 = ram_rd_en_fwft; + assign ram_rd_en = ram_rd_en_fwft; + end endgenerate // gll_fifo + + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + end endgenerate // gnll_fifo_ram_valid + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + + generate if(C_USE_EMBEDDED_REG < 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always +end +endgenerate + + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + end endgenerate // gnll_fifo_empty + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + generate if ( C_USE_EMBEDDED_REG < 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always +end +endgenerate + + + + // BRAM resets synchronously + generate + if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin + always @ ( posedge rd_rst_i) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + end //if + endgenerate +//safety ckt with one register +generate + if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) + begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) + //@(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end + else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1) begin + // @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + end //if +endgenerate + + +generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin + + + always @* begin + case (curr_fwft_state) + INVALID: begin + if (~FIFOEMPTY) + next_fwft_state <= STAGE1_VALID; + else + next_fwft_state <= INVALID; + end + STAGE1_VALID: begin + if (FIFOEMPTY) + next_fwft_state <= STAGE2_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + STAGE2_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= INVALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE1_VALID; + else if (~FIFOEMPTY && ~RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= STAGE2_VALID; + end + BOTH_STAGES_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE2_VALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + default: next_fwft_state <= INVALID; + endcase + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + curr_fwft_state <= INVALID; + else if (srst_i) + curr_fwft_state <= #`TCQ INVALID; + else + curr_fwft_state <= #`TCQ next_fwft_state; + end + + always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay + if (rd_rst_i == 1) begin + ram_regout_en_d1 <= #`TCQ 1'b0; + end + else begin + if (srst_i == 1'b1) + ram_regout_en_d1 <= #`TCQ 1'b0; + else + ram_regout_en_d1 <= #`TCQ ram_regout_en; + end + end //always + // assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i)); + assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0; + + always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1 + if (rd_rst_i == 1) begin + ram_regout_en_d2 <= #`TCQ 1'b0; + end + else begin + if (srst_i == 1'b1) + ram_regout_en_d2 <= #`TCQ 1'b0; + else + ram_regout_en_d2 <= #`TCQ ram_regout_en_d1; + end + end //always + + + + always @* begin + case (curr_fwft_state) + INVALID: STAGE2_REG_EN <= 1'b0; + STAGE1_VALID: STAGE2_REG_EN <= 1'b1; + STAGE2_VALID: STAGE2_REG_EN <= 1'b0; + BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; + default: STAGE2_REG_EN <= 1'b0; + endcase + end + + always @ (posedge RD_CLK) begin + ram_valid_i_d <= #`TCQ ram_valid_i; + read_data_valid_i_d <= #`TCQ read_data_valid_i; + fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i; + + end + assign VALID_STAGES = curr_fwft_state; + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1; + end + endgenerate // gnll_fifo + + + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid + + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + fab_valid <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + fab_valid <= #`TCQ 1'b0; + end else begin + if (ram_regout_en == 1'b1) begin + fab_valid <= #`TCQ 1'b1; + end else begin + if (fab_regout_en == 1'b1) + fab_valid <= #`TCQ 1'b0; + else + fab_valid <= #`TCQ fab_valid; + end + end //srst_i + end //rd_rst_i + end //always + end endgenerate // gnll_fifo_fab_valid + + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + generate if(C_USE_EMBEDDED_REG == 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else begin + if (ram_regout_en == 1'b1) begin + read_data_valid_i <= #`TCQ 1'b1; + end else begin + if (fab_regout_en == 1'b1) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ read_data_valid_i; + end + end + end //always +end +endgenerate + +//generate if(C_USE_EMBEDDED_REG == 3) begin +// always @ (posedge RD_CLK or posedge rd_rst_i) begin +// if (rd_rst_i) +// read_data_valid_i <= #`TCQ 1'b0; +// else if (srst_i) +// read_data_valid_i <= #`TCQ 1'b0; +// +// if (ram_regout_en == 1'b1) begin +// fab_read_data_valid_i <= #`TCQ 1'b0; +// end else begin +// if (fab_regout_en == 1'b1) +// fab_read_data_valid_i <= #`TCQ 1'b1; +// else +// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i; +// end +// end //always +//end +//endgenerate + + generate if(C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid + if (rd_rst_i) + fab_read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + fab_read_data_valid_i <= #`TCQ 1'b0; + else + fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN); + end //always +end +endgenerate + +always @ (posedge RD_CLK ) begin : proc_del1 + begin + fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i; + end + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN); + end + end + end //always + end endgenerate // gnll_fifo_empty_both + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + reg FIFOEMPTY_1; + generate if (C_USE_EMBEDDED_REG == 3 ) begin + always @(posedge RD_CLK) begin + FIFOEMPTY_1 <= #`TCQ FIFOEMPTY; + end + end +endgenerate + generate if (C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ (~ram_valid_i); + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always +end +endgenerate + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + empty_sckt <= #`TCQ 1'b1; + sckt_rrst_q <= #`TCQ 1'b0; + sckt_rrst_done <= #`TCQ 1'b0; + end else begin + sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST; + if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin + sckt_rrst_done <= #`TCQ 1'b1; + end else if (sckt_rrst_done) begin + // rising clock edge + empty_sckt <= #`TCQ 1'b0; + end + end + end //always + + +// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i; + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i; + assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0); + assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0); + assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; +//no safety ckt with both reg +generate + if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin + if (fwft_rst_done) begin + if (ram_regout_en) begin + userdata_both <= #`TCQ FIFODATA; + user_dbiterr_both <= #`TCQ FIFODBITERR; + user_sbiterr_both <= #`TCQ FIFOSBITERR; + end + if (fab_regout_en) begin + USERDATA <= #`TCQ userdata_both; + USERDBITERR <= #`TCQ user_dbiterr_both; + USERSBITERR <= #`TCQ user_sbiterr_both; + end + end + end + end + end //always + end //if + endgenerate + +//safety_ckt with both registers + generate + if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always @ (posedge RD_CLK) begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + userdata_both <= #`TCQ FIFODATA; + user_dbiterr_both <= #`TCQ FIFODBITERR; + user_sbiterr_both <= #`TCQ FIFOSBITERR; + end + if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + USERDATA <= #`TCQ userdata_both; + USERDBITERR <= #`TCQ user_dbiterr_both; + USERSBITERR <= #`TCQ user_sbiterr_both; + end + end + end + end //always + end //if +endgenerate + +endmodule //fifo_generator_v13_2_7_bhv_ver_preload0 + + +//----------------------------------------------------------------------------- +// +// Register Slice +// Register one AXI channel on forward and/or reverse signal path +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// reg_slice +// +//-------------------------------------------------------------------------- + +module fifo_generator_v13_2_7_axic_reg_slice # + ( + parameter C_FAMILY = "virtex7", + parameter C_DATA_WIDTH = 32, + parameter C_REG_CONFIG = 32'h00000000 + ) + ( + // System Signals + input wire ACLK, + input wire ARESET, + + // Slave side + input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, + input wire S_VALID, + output wire S_READY, + + // Master side + output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, + output wire M_VALID, + input wire M_READY + ); + + localparam RST_SYNC_STAGES = 5; + localparam RST_BUSY_LEN = 6; + reg [1:0] arst_sync_wr = 2'b11; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + wire sync_reset; + wire extnd_reset; + + + always @(posedge ARESET or posedge ACLK) begin + if (ARESET) + arst_sync_wr <= 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0}; + end + + always @(posedge ACLK) begin + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]}; + end + + assign sync_reset = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; + assign extnd_reset = |sckt_wr_rst_cc | arst_sync_wr[1]; + generate + //////////////////////////////////////////////////////////////////// + // + // Both FWD and REV mode + // + //////////////////////////////////////////////////////////////////// + if (C_REG_CONFIG == 32'h00000000) + begin + reg [1:0] state; + localparam [1:0] + ZERO = 2'b10, + ONE = 2'b11, + TWO = 2'b01; + + reg [C_DATA_WIDTH-1:0] storage_data1 = 0; + reg [C_DATA_WIDTH-1:0] storage_data2 = 0; + reg load_s1; + wire load_s2; + wire load_s1_from_s2; + reg s_ready_i; //local signal of output + wire m_valid_i; //local signal of output + + // assign local signal to its output signal + assign S_READY = s_ready_i; + assign M_VALID = m_valid_i; + + reg areset_d1; // Reset delay register + always @(posedge ACLK) begin + areset_d1 <= extnd_reset; + end + + // Load storage1 with either slave side data or from storage2 + always @(posedge ACLK) + begin + if (load_s1) + if (load_s1_from_s2) + storage_data1 <= storage_data2; + else + storage_data1 <= S_PAYLOAD_DATA; + end + + // Load storage2 with slave side data + always @(posedge ACLK) + begin + if (load_s2) + storage_data2 <= S_PAYLOAD_DATA; + end + + assign M_PAYLOAD_DATA = storage_data1; + + // Always load s2 on a valid transaction even if it's unnecessary + assign load_s2 = S_VALID & s_ready_i; + + // Loading s1 + always @ * + begin + if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction + // Load when ONE if we both have read and write at the same time + ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || + // Load when TWO and we have a transaction on Master side + ((state == TWO) && (M_READY == 1))) + load_s1 = 1'b1; + else + load_s1 = 1'b0; + end // always @ * + + assign load_s1_from_s2 = (state == TWO); + + // State Machine for handling output signals + always @(posedge ACLK) begin + if (sync_reset || extnd_reset) begin + s_ready_i <= 1'b0; + state <= ZERO; + end else if (areset_d1 && ~extnd_reset) begin + s_ready_i <= 1'b1; + end else begin + case (state) + // No transaction stored locally + ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE + + // One transaction stored locally + ONE: begin + if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO + if (~M_READY & S_VALID) begin + state <= TWO; // Got another one so move to TWO + s_ready_i <= 1'b0; + end + end + + // TWO transaction stored locally + TWO: if (M_READY) begin + state <= ONE; // Read out one so move to ONE + s_ready_i <= 1'b1; + end + endcase // case (state) + end + end // always @ (posedge ACLK) + + assign m_valid_i = state[0]; + + end // if (C_REG_CONFIG == 1) + //////////////////////////////////////////////////////////////////// + // + // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining + // Operates same as 1-deep FIFO + // + //////////////////////////////////////////////////////////////////// + else if (C_REG_CONFIG == 32'h00000001) + begin + reg [C_DATA_WIDTH-1:0] storage_data1 = 0; + reg s_ready_i; //local signal of output + reg m_valid_i; //local signal of output + + // assign local signal to its output signal + assign S_READY = s_ready_i; + assign M_VALID = m_valid_i; + + reg areset_d1; // Reset delay register + always @(posedge ACLK) begin + areset_d1 <= extnd_reset; + end + + // Load storage1 with slave side data + always @(posedge ACLK) + begin + if (sync_reset || extnd_reset) begin + s_ready_i <= 1'b0; + m_valid_i <= 1'b0; + end else if (areset_d1 && ~extnd_reset) begin + s_ready_i <= 1'b1; + end else if (m_valid_i & M_READY) begin + s_ready_i <= 1'b1; + m_valid_i <= 1'b0; + end else if (S_VALID & s_ready_i) begin + s_ready_i <= 1'b0; + m_valid_i <= 1'b1; + end + if (~m_valid_i) begin + storage_data1 <= S_PAYLOAD_DATA; + end + end + assign M_PAYLOAD_DATA = storage_data1; + end // if (C_REG_CONFIG == 7) + + else begin : default_case + // Passthrough + assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; + assign M_VALID = S_VALID; + assign S_READY = M_READY; + end + + endgenerate +endmodule // reg_slice diff --git a/project_1.srcs/sources_1/bd/design_1/ipshared/c40e/hdl/axi_crossbar_v2_1_vl_rfs.v b/project_1.srcs/sources_1/bd/design_1/ipshared/c40e/hdl/axi_crossbar_v2_1_vl_rfs.v new file mode 100755 index 0000000..d7c20ec --- /dev/null +++ b/project_1.srcs/sources_1/bd/design_1/ipshared/c40e/hdl/axi_crossbar_v2_1_vl_rfs.v @@ -0,0 +1,5804 @@ +// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// File name: addr_arbiter_sasd.v +// +// Description: +// Hybrid priority + round-robin arbiter. +// Read & write requests combined (read preferred) at each slot +// Muxes AR and AW channel payload inputs based on arbitration results. +//----------------------------------------------------------------------------- +// +// Structure: +// addr_arbiter_sasd +// mux_enc +//----------------------------------------------------------------------------- + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_crossbar_v2_1_28_addr_arbiter_sasd # + ( + parameter C_FAMILY = "none", + parameter integer C_NUM_S = 1, + parameter integer C_NUM_S_LOG = 1, + parameter integer C_AMESG_WIDTH = 1, + parameter C_GRANT_ENC = 0, + parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}} + // Arbitration priority among each SI slot. + // Higher values indicate higher priority. + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 'h0-'hF. + ) + ( + // Global Signals + input wire ACLK, + input wire ARESET, + // Slave Ports + input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_AWMESG, + input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_ARMESG, + input wire [C_NUM_S-1:0] S_AWVALID, + output wire [C_NUM_S-1:0] S_AWREADY, + input wire [C_NUM_S-1:0] S_ARVALID, + output wire [C_NUM_S-1:0] S_ARREADY, + // Master Ports + output wire [C_AMESG_WIDTH-1:0] M_AMESG, + output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, + output wire [C_NUM_S-1:0] M_GRANT_HOT, + output wire M_GRANT_RNW, + output wire M_GRANT_ANY, + output wire M_AWVALID, + input wire M_AWREADY, + output wire M_ARVALID, + input wire M_ARREADY + ); + + // Generates a mask for all input slots that are priority based + function [C_NUM_S-1:0] f_prio_mask + ( + input integer null_arg + ); + reg [C_NUM_S-1:0] mask; + integer i; + begin + mask = 0; + for (i=0; i < C_NUM_S; i=i+1) begin + mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0); + end + f_prio_mask = mask; + end + endfunction + + // Convert 16-bit one-hot to 4-bit binary + function [3:0] f_hot2enc + ( + input [15:0] one_hot + ); + begin + f_hot2enc[0] = |(one_hot & 16'b1010101010101010); + f_hot2enc[1] = |(one_hot & 16'b1100110011001100); + f_hot2enc[2] = |(one_hot & 16'b1111000011110000); + f_hot2enc[3] = |(one_hot & 16'b1111111100000000); + end + endfunction + + localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0); + + reg m_valid_i = 1'b0; + reg [C_NUM_S-1:0] s_ready_i = 0; + reg [C_NUM_S-1:0] s_awvalid_reg = 0; + reg [C_NUM_S-1:0] s_arvalid_reg = 0; + wire [15:0] s_avalid; + wire m_aready; + wire [C_NUM_S-1:0] rnw; + reg grant_rnw; + reg [C_NUM_S_LOG-1:0] m_grant_enc_i; + reg [C_NUM_S-1:0] m_grant_hot_i; + reg [C_NUM_S-1:0] last_rr_hot; + reg any_grant; + reg any_prio; + reg [C_NUM_S-1:0] which_prio_hot; + reg [C_NUM_S_LOG-1:0] which_prio_enc; + reg [4:0] current_highest; + reg [15:0] next_prio_hot; + reg [C_NUM_S_LOG-1:0] next_prio_enc; + reg found_prio; + wire [C_NUM_S-1:0] valid_rr; + reg [15:0] next_rr_hot; + reg [C_NUM_S_LOG-1:0] next_rr_enc; + reg [C_NUM_S*C_NUM_S-1:0] carry_rr; + reg [C_NUM_S*C_NUM_S-1:0] mask_rr; + reg found_rr; + wire [C_NUM_S-1:0] next_hot; + wire [C_NUM_S_LOG-1:0] next_enc; + integer i; + wire [C_AMESG_WIDTH-1:0] amesg_mux; + reg [C_AMESG_WIDTH-1:0] m_amesg_i; + wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg; + genvar gen_si; + + always @(posedge ACLK) begin + if (ARESET) begin + s_awvalid_reg <= 0; + s_arvalid_reg <= 0; + end else if (|s_ready_i) begin + s_awvalid_reg <= 0; + s_arvalid_reg <= 0; + end else begin + s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg; + s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg); + end + end + + assign s_avalid = S_AWVALID | S_ARVALID; + assign M_AWVALID = m_valid_i & ~grant_rnw; + assign M_ARVALID = m_valid_i & grant_rnw; + assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}}; + assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}}; + assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0; + assign M_GRANT_HOT = m_grant_hot_i; + assign M_GRANT_RNW = grant_rnw; + assign rnw = S_ARVALID & ~s_awvalid_reg; + assign M_AMESG = m_amesg_i; + assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY; + + generate + for (gen_si=0; gen_si1) begin : gen_arbiter + + ///////////////////////////////////////////////////////////////////////////// + // Grant a new request when there is none still pending. + // If no qualified requests found, de-assert M_VALID. + ///////////////////////////////////////////////////////////////////////////// + + assign M_GRANT_ANY = any_grant; + assign next_hot = found_prio ? next_prio_hot : next_rr_hot; + assign next_enc = found_prio ? next_prio_enc : next_rr_enc; + + always @(posedge ACLK) begin + if (ARESET) begin + m_valid_i <= 0; + s_ready_i <= 0; + m_grant_hot_i <= 0; + m_grant_enc_i <= 0; + any_grant <= 1'b0; + last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}}; + grant_rnw <= 1'b0; + end else begin + s_ready_i <= 0; + if (m_valid_i) begin + // Stall 1 cycle after each master-side completion. + if (m_aready) begin // Master-side completion + m_valid_i <= 1'b0; + m_grant_hot_i <= 0; + any_grant <= 1'b0; + end + end else if (any_grant) begin + m_valid_i <= 1'b1; + s_ready_i <= m_grant_hot_i; // Assert S_AW/READY for 1 cycle to complete SI address transfer + end else begin + if (found_prio | found_rr) begin + m_grant_hot_i <= next_hot; + m_grant_enc_i <= next_enc; + any_grant <= 1'b1; + grant_rnw <= |(rnw & next_hot); + if (~found_prio) begin + last_rr_hot <= next_rr_hot; + end + end + end + end + end + + ///////////////////////////////////////////////////////////////////////////// + // Fixed Priority arbiter + // Selects next request to grant from among inputs with PRIO > 0, if any. + ///////////////////////////////////////////////////////////////////////////// + + always @ * begin : ALG_PRIO + integer ip; + any_prio = 1'b0; + which_prio_hot = 0; + which_prio_enc = 0; + current_highest = 0; + for (ip=0; ip < C_NUM_S; ip=ip+1) begin + if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin + if (s_avalid[ip]) begin + current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4]; + any_prio = 1'b1; + which_prio_hot = 1'b1 << ip; + which_prio_enc = ip; + end + end + end + found_prio = any_prio; + next_prio_hot = which_prio_hot; + next_prio_enc = which_prio_enc; + end + + ///////////////////////////////////////////////////////////////////////////// + // Round-robin arbiter + // Selects next request to grant from among inputs with PRIO = 0, if any. + ///////////////////////////////////////////////////////////////////////////// + + assign valid_rr = ~P_PRIO_MASK & s_avalid; + + always @ * begin : ALG_RR + integer ir, jr, nr; + next_rr_hot = 0; + for (ir=0;ir0) ? (ir-1) : (C_NUM_S-1); + carry_rr[ir*C_NUM_S] = last_rr_hot[nr]; + mask_rr[ir*C_NUM_S] = ~valid_rr[nr]; + for (jr=1;jr 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1); + carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]); + if (jr < C_NUM_S-1) begin + mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr]; + end + end + next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1]; + end + next_rr_enc = f_hot2enc(next_rr_hot); + found_rr = |(next_rr_hot); + end + + generic_baseblocks_v2_1_0_mux_enc # + ( + .C_FAMILY ("rtl"), + .C_RATIO (C_NUM_S), + .C_SEL_WIDTH (C_NUM_S_LOG), + .C_DATA_WIDTH (C_AMESG_WIDTH) + ) si_amesg_mux_inst + ( + .S (next_enc), + .A (s_amesg), + .O (amesg_mux), + .OE (1'b1) + ); + + always @(posedge ACLK) begin + if (ARESET) begin + m_amesg_i <= 0; + end else if (~any_grant) begin + m_amesg_i <= amesg_mux; + end + end + + end else begin : gen_no_arbiter + + assign M_GRANT_ANY = m_grant_hot_i; + + always @ (posedge ACLK) begin + if (ARESET) begin + m_valid_i <= 1'b0; + s_ready_i <= 1'b0; + m_grant_enc_i <= 0; + m_grant_hot_i <= 1'b0; + grant_rnw <= 1'b0; + end else begin + s_ready_i <= 1'b0; + if (m_valid_i) begin + if (m_aready) begin + m_valid_i <= 1'b0; + m_grant_hot_i <= 1'b0; + end + end else if (m_grant_hot_i) begin + m_valid_i <= 1'b1; + s_ready_i[0] <= 1'b1; // Assert S_AW/READY for 1 cycle to complete SI address transfer + end else if (s_avalid[0]) begin + m_grant_hot_i <= 1'b1; + grant_rnw <= rnw[0]; + end + end + end + + always @ (posedge ACLK) begin + if (ARESET) begin + m_amesg_i <= 0; + end else if (~m_grant_hot_i) begin + m_amesg_i <= s_amesg; + end + end + + end // gen_arbiter + endgenerate +endmodule + +`default_nettype wire + + +// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// File name: addr_arbiter.v +// +// Description: +// Instantiates generic priority encoder. +// Each request is qualified if its target has not reached its issuing limit. +// Muxes mesg and target inputs based on arbitration results. +//----------------------------------------------------------------------------- +// +// Structure: +// addr_arbiter +// mux_enc +//----------------------------------------------------------------------------- + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_crossbar_v2_1_28_addr_arbiter # + ( + parameter C_FAMILY = "none", + parameter integer C_NUM_S = 1, + parameter integer C_NUM_S_LOG = 1, + parameter integer C_NUM_M = 1, + parameter integer C_MESG_WIDTH = 1, + parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}} + // Arbitration priority among each SI slot. + // Higher values indicate higher priority. + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 'h0-'hF. + ) + ( + // Global Signals + input wire ACLK, + input wire ARESET, + // Slave Ports + input wire [C_NUM_S*C_MESG_WIDTH-1:0] S_MESG, + input wire [C_NUM_S*C_NUM_M-1:0] S_TARGET_HOT, + input wire [C_NUM_S-1:0] S_VALID, + input wire [C_NUM_S-1:0] S_VALID_QUAL, + output wire [C_NUM_S-1:0] S_READY, + // Master Ports + output wire [C_MESG_WIDTH-1:0] M_MESG, + output wire [C_NUM_M-1:0] M_TARGET_HOT, + output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, + output wire M_VALID, + input wire M_READY, + // Sideband input + input wire [C_NUM_M-1:0] ISSUING_LIMIT + ); + + // Generates a mask for all input slots that are priority based + function [C_NUM_S-1:0] f_prio_mask + ( + input integer null_arg + ); + reg [C_NUM_S-1:0] mask; + integer i; + begin + mask = 0; + for (i=0; i < C_NUM_S; i=i+1) begin + mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0); + end + f_prio_mask = mask; + end + endfunction + + // Convert 16-bit one-hot to 4-bit binary + function [3:0] f_hot2enc + ( + input [15:0] one_hot + ); + begin + f_hot2enc[0] = |(one_hot & 16'b1010101010101010); + f_hot2enc[1] = |(one_hot & 16'b1100110011001100); + f_hot2enc[2] = |(one_hot & 16'b1111000011110000); + f_hot2enc[3] = |(one_hot & 16'b1111111100000000); + end + endfunction + + localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0); + + reg m_valid_i = 1'b0; + reg [C_NUM_S-1:0] s_ready_i = 0; + reg [C_NUM_S-1:0] qual_reg; + reg [C_NUM_S-1:0] grant_hot; + reg [C_NUM_S-1:0] last_rr_hot; + reg any_grant; + reg any_prio; + reg found_prio; + reg [C_NUM_S-1:0] which_prio_hot; + reg [C_NUM_S-1:0] next_prio_hot; + reg [C_NUM_S_LOG-1:0] which_prio_enc; + reg [C_NUM_S_LOG-1:0] next_prio_enc; + reg [4:0] current_highest; + wire [C_NUM_S-1:0] valid_rr; + reg [15:0] next_rr_hot; + reg [C_NUM_S_LOG-1:0] next_rr_enc; + reg [C_NUM_S*C_NUM_S-1:0] carry_rr; + reg [C_NUM_S*C_NUM_S-1:0] mask_rr; + reg found_rr; + wire [C_NUM_S-1:0] next_hot; + wire [C_NUM_S_LOG-1:0] next_enc; + reg prio_stall; + integer i; + wire [C_NUM_S-1:0] valid_qual_i; + reg [C_NUM_S_LOG-1:0] m_grant_enc_i; + reg [C_NUM_M-1:0] m_target_hot_i; + wire [C_NUM_M-1:0] m_target_hot_mux; + reg [C_MESG_WIDTH-1:0] m_mesg_i; + wire [C_MESG_WIDTH-1:0] m_mesg_mux; + genvar gen_si; + + assign M_VALID = m_valid_i; + assign S_READY = s_ready_i; + assign M_GRANT_ENC = m_grant_enc_i; + assign M_MESG = m_mesg_i; + assign M_TARGET_HOT = m_target_hot_i; + + generate + if (C_NUM_S>1) begin : gen_arbiter + + always @(posedge ACLK) begin + if (ARESET) begin + qual_reg <= 0; + end else begin + qual_reg <= valid_qual_i | ~S_VALID; // Don't disqualify when bus not VALID (valid_qual_i would be garbage) + end + end + + for (gen_si=0; gen_si 0, if any. + ///////////////////////////////////////////////////////////////////////////// + + always @ * begin : ALG_PRIO + integer ip; + any_prio = 1'b0; + prio_stall = 1'b0; + which_prio_hot = 0; + which_prio_enc = 0; + current_highest = 0; + for (ip=0; ip < C_NUM_S; ip=ip+1) begin + // Disqualify slot if target hit issuing limit (pass to lower prio slot). + if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin + if ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin + current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4]; + // Stall 1 cycle when highest prio is recovering from SI-side handshake. + // (Do not allow lower-prio slot to win arbitration.) + if (s_ready_i[ip]) begin + any_prio = 1'b0; + prio_stall = 1'b1; + which_prio_hot = 0; + which_prio_enc = 0; + end else begin + any_prio = 1'b1; + which_prio_hot = 1'b1 << ip; + which_prio_enc = ip; + end + end + end + end + found_prio = any_prio; + next_prio_hot = which_prio_hot; + next_prio_enc = which_prio_enc; + end + + ///////////////////////////////////////////////////////////////////////////// + // Round-robin arbiter + // Selects next request to grant from among inputs with PRIO = 0, if any. + ///////////////////////////////////////////////////////////////////////////// + + // Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot). + // Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i), + // and allow arbitration to pass to any other RR requester. + assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg; + + always @ * begin : ALG_RR + integer ir, jr, nr; + next_rr_hot = 0; + for (ir=0;ir0) ? (ir-1) : (C_NUM_S-1); + carry_rr[ir*C_NUM_S] = last_rr_hot[nr]; + mask_rr[ir*C_NUM_S] = ~valid_rr[nr]; + for (jr=1;jr 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1); + carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]); + if (jr < C_NUM_S-1) begin + mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr]; + end + end + next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1]; + end + next_rr_enc = f_hot2enc(next_rr_hot); + found_rr = |(next_rr_hot); + end + + generic_baseblocks_v2_1_0_mux_enc # + ( + .C_FAMILY ("rtl"), + .C_RATIO (C_NUM_S), + .C_SEL_WIDTH (C_NUM_S_LOG), + .C_DATA_WIDTH (C_MESG_WIDTH) + ) mux_mesg + ( + .S (m_grant_enc_i), + .A (S_MESG), + .O (m_mesg_mux), + .OE (1'b1) + ); + + generic_baseblocks_v2_1_0_mux_enc # + ( + .C_FAMILY ("rtl"), + .C_RATIO (C_NUM_S), + .C_SEL_WIDTH (C_NUM_S_LOG), + .C_DATA_WIDTH (C_NUM_M) + ) si_amesg_mux_inst + ( + .S (next_enc), + .A (S_TARGET_HOT), + .O (m_target_hot_mux), + .OE (1'b1) + ); + + always @(posedge ACLK) begin + if (ARESET) begin + m_mesg_i <= 0; + end else if (~m_valid_i) begin + m_mesg_i <= m_mesg_mux; + end + end + + end else begin : gen_no_arbiter + + assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT); + + always @ (posedge ACLK) begin + if (ARESET) begin + m_valid_i <= 1'b0; + s_ready_i <= 1'b0; + m_grant_enc_i <= 0; + end else begin + s_ready_i <= 1'b0; + if (m_valid_i) begin + if (M_READY) begin + m_valid_i <= 1'b0; + end + end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin + m_valid_i <= 1'b1; + s_ready_i <= 1'b1; + m_target_hot_i <= S_TARGET_HOT; + end + end + end + always @(posedge ACLK) begin + if (ARESET) begin + m_mesg_i <= 0; + end else if (~m_valid_i) begin + m_mesg_i <= S_MESG; + end + end + + + end // gen_arbiter + endgenerate +endmodule + +`default_nettype wire + + +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Addr Decoder +// Each received address is compared to base and high address pairs for each +// of a set of decode targets. +// The matching target's index (if any) is output combinatorially. +// If the decode is successful (matches any target), the MATCH output is asserted. +// For each target, a set of alternative address ranges may be specified. +// The base and high address pairs are formatted as a pair of 2-dimensional arrays, +// alternative address ranges iterate within each target. +// The alternative range which matches the address is also output as REGION. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// addr_decoder +// comparator_static +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_crossbar_v2_1_28_addr_decoder # + ( + parameter C_FAMILY = "none", + parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16] + parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS) + parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that + // can match each target [1:16] + parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of + // each base and high address [2:64] + parameter integer C_TARGET_ENC = 0, // Enable encoded target output + parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output + parameter integer C_REGION_ENC = 0, // Enable REGION output + parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}}, + parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}}, + parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}}, + // Indicates whether each target has connectivity. + // Format: C_NUM_TARGETS{Bit1}. + parameter integer C_RESOLUTION = 0, + // Number of low-order ADDR bits that can be ignored when decoding. + parameter integer C_COMPARATOR_THRESHOLD = 6 + // Number of decoded ADDR bits above which will implement comparator_static. + ) + ( + input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand + output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot) + output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded) + output wire MATCH, // Decode successful + output wire [3:0] REGION // Range within target matching address (encoded) + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + genvar target_cnt; + genvar region_cnt; + + + ///////////////////////////////////////////////////////////////////////////// + // Function to detect addrs is in the addressable range. + // Only compare 4KB page address (ignore low-order 12 bits) + function decode_address; + input [C_ADDR_WIDTH-1:0] base, high, addr; + reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask; + reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page; + reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page; + reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page; + begin + addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; + base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; + high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; + if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin + decode_address = 1'b0; + end else begin + mask = base_page ^ high_page; + if ( (base_page & ~mask) == (addr_page & ~mask) ) begin + decode_address = 1'b1; + end else begin + decode_address = 1'b0; + end + end + end + endfunction + + // Generates a binary coded from onehotone encoded + function [3:0] f_hot2enc + ( + input [15:0] one_hot + ); + begin + f_hot2enc[0] = |(one_hot & 16'b1010101010101010); + f_hot2enc[1] = |(one_hot & 16'b1100110011001100); + f_hot2enc[2] = |(one_hot & 16'b1111000011110000); + f_hot2enc[3] = |(one_hot & 16'b1111111100000000); + end + endfunction + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot). + wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot). + wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot). + wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot). + wire [3:0] TARGET_ENC_I; // Internal version of encoded hit. + ///////////////////////////////////////////////////////////////////////////// + // Generate detection per region per target. + generate + for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target + for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region + // Detect if this is an address hit (including used region decoding). + if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static + if (C_TARGET_QUAL[target_cnt] && + ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) || + (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range + generic_baseblocks_v2_1_0_comparator_static # + ( + .C_FAMILY("rtl"), + .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]), + .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION) + ) addr_decode_comparator + ( + .CIN(1'b1), + .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] & + ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^ + C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])), + .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]) + ); + end else begin : gen_null_range + assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0; + end + end else begin : gen_no_comparator_static + assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? + decode_address( + C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], + C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], + ADDR) + : 1'b0; + end // gen_comparator_static + assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]; + end // gen_region + + // All regions are non-overlapping + // => Or all the region detections for this target to determine if it is a hit. + assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES]; + end // gen_target + + for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or + assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS]; + end // gen_region_or + endgenerate + + + ///////////////////////////////////////////////////////////////////////////// + // All regions are non-overlapping + // => Or all the target hit detections if it is a match. + assign MATCH = | TARGET_HOT_I; + + + ///////////////////////////////////////////////////////////////////////////// + // Assign conditional onehot target output signal. + generate + if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT + assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1; + end else begin : NO_TARGET_ONEHOT + assign TARGET_HOT = {C_NUM_TARGETS{1'b0}}; + end + endgenerate + + + ///////////////////////////////////////////////////////////////////////////// + // Assign conditional encoded target output signal. + generate + if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED + assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I); + assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0]; + end else begin : NO_TARGET_ENCODED + assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}}; + end + endgenerate + + + ///////////////////////////////////////////////////////////////////////////// + // Assign conditional encoded region output signal. + generate + if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED + assign REGION = f_hot2enc(REGION_HOT); + end else begin : NO_REGION_ENCODED + assign REGION = 4'b0; + end + endgenerate + + +endmodule + + +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Round-Robin Arbiter for R and B channel responses +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// arbiter_resp +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_crossbar_v2_1_28_arbiter_resp # + ( + parameter C_FAMILY = "none", + parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16] + parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S) + parameter integer C_GRANT_ENC = 0, // Enable encoded grant output + parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output + ) + ( + // Global Inputs + input wire ACLK, + input wire ARESET, + // Slave Ports + input wire [C_NUM_S-1:0] S_VALID, // Request from each slave + output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave + // Master Ports + output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded) + output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot) + output wire M_VALID, // Grant event + input wire M_READY + ); + + // Generates a binary coded from onehotone encoded + function [4:0] f_hot2enc + ( + input [16:0] one_hot + ); + begin + f_hot2enc[0] = |(one_hot & 17'b01010101010101010); + f_hot2enc[1] = |(one_hot & 17'b01100110011001100); + f_hot2enc[2] = |(one_hot & 17'b01111000011110000); + f_hot2enc[3] = |(one_hot & 17'b01111111100000000); + f_hot2enc[4] = |(one_hot & 17'b10000000000000000); + end + endfunction + + (* use_clock_enable = "yes" *) + reg [C_NUM_S-1:0] chosen = 0; + + wire [C_NUM_S-1:0] grant_hot; + wire master_selected; + wire active_master; + wire need_arbitration; + wire m_valid_i; + wire [C_NUM_S-1:0] s_ready_i; + wire access_done; + reg [C_NUM_S-1:0] last_rr_hot; + wire [C_NUM_S-1:0] valid_rr; + reg [C_NUM_S-1:0] next_rr_hot; + reg [C_NUM_S*C_NUM_S-1:0] carry_rr; + reg [C_NUM_S*C_NUM_S-1:0] mask_rr; + integer i; + integer j; + integer n; + + ///////////////////////////////////////////////////////////////////////////// + // + // Implementation of the arbiter outputs independant of arbitration + // + ///////////////////////////////////////////////////////////////////////////// + + // Mask the current requests with the chosen master + assign grant_hot = chosen & S_VALID; + + // See if we have a selected master + assign master_selected = |grant_hot[0+:C_NUM_S]; + + // See if we have current requests + assign active_master = |S_VALID; + + // Access is completed + assign access_done = m_valid_i & M_READY; + + // Need to handle if we drive S_ready combinatorial and without an IDLE state + + // Drive S_READY on the master who has been chosen when we get a M_READY + assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S]; + + // Drive M_VALID if we have a selected master + assign m_valid_i = master_selected; + + // If we have request and not a selected master, we need to arbitrate a new chosen + assign need_arbitration = (active_master & ~master_selected) | access_done; + + // need internal signals of the output signals + assign M_VALID = m_valid_i; + assign S_READY = s_ready_i; + + ///////////////////////////////////////////////////////////////////////////// + // Assign conditional onehot target output signal. + assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}}; + ///////////////////////////////////////////////////////////////////////////// + // Assign conditional encoded target output signal. + assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}}; + + ///////////////////////////////////////////////////////////////////////////// + // Select a new chosen when we need to arbitrate + // If we don't have a new chosen, keep the old one since it's a good chance + // that it will do another request + always @(posedge ACLK) + begin + if (ARESET) begin + chosen <= {C_NUM_S{1'b0}}; + last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}}; + end else if (need_arbitration) begin + chosen <= next_rr_hot; + if (|next_rr_hot) last_rr_hot <= next_rr_hot; + end + end + + assign valid_rr = S_VALID; + + ///////////////////////////////////////////////////////////////////////////// + // Round-robin arbiter + // Selects next request to grant from among inputs with PRIO = 0, if any. + ///////////////////////////////////////////////////////////////////////////// + + always @ * begin + next_rr_hot = 0; + for (i=0;i0) ? (i-1) : (C_NUM_S-1); + carry_rr[i*C_NUM_S] = last_rr_hot[n]; + mask_rr[i*C_NUM_S] = ~valid_rr[n]; + for (j=1;j 0) ? (i-j-1) : (C_NUM_S+i-j-1); + carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]); + if (j < C_NUM_S-1) begin + mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n]; + end + end + next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1]; + end + end + +endmodule + + +// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// File name: crossbar_sasd.v +// +// Description: +// This module is a M-master to N-slave AXI axi_crossbar_v2_1_28_crossbar switch. +// Single transaction issuing, single arbiter (both W&R), single data pathways. +// The interface of this module consists of a vectored slave and master interface +// in which all slots are sized and synchronized to the native width and clock +// of the interconnect, and are all AXI4 protocol. +// All width, clock and protocol conversions are done outside this block, as are +// any pipeline registers or data FIFOs. +// This module contains all arbitration, decoders and channel multiplexing logic. +// It also contains the diagnostic registers and control interface. +// +//-------------------------------------------------------------------------- +// +// Structure: +// crossbar_sasd +// addr_arbiter_sasd +// mux_enc +// addr_decoder +// comparator_static +// splitter +// mux_enc +// axic_register_slice +// decerr_slave +// +//----------------------------------------------------------------------------- +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_crossbar_v2_1_28_crossbar_sasd # + ( + parameter C_FAMILY = "none", + parameter integer C_NUM_SLAVE_SLOTS = 1, + parameter integer C_NUM_MASTER_SLOTS = 1, + parameter integer C_NUM_ADDR_RANGES = 1, + parameter integer C_AXI_ID_WIDTH = 1, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_PROTOCOL = 0, + parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, + parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, + parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, + parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}}, + parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}}, + parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}}, + parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}}, + parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}}, + parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}}, + parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}, + parameter integer C_R_REGISTER = 0, + parameter integer C_RANGE_CHECK = 0, + parameter integer C_ADDR_DECODE = 0, + parameter integer C_DEBUG = 1 + ) + ( + // Global Signals + input wire ACLK, + input wire ARESETN, + // Slave Interface Write Address Ports + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE, + input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST, + input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT, +// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, + input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID, + output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY, + // Slave Interface Write Data Ports + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, + input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID, + output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY, + // Slave Interface Write Response Ports + output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID, + output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP, + output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, + output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID, + input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY, + // Slave Interface Read Address Ports + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, + input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE, + input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST, + input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT, +// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, + input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID, + output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY, + // Slave Interface Read Data Ports + output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID, + output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, + output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP, + output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST, + output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, + output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID, + input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY, + // Master Interface Write Address Port + output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID, + output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, + output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN, + output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE, + output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST, + output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK, + output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE, + output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT, + output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION, + output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS, + output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, + output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID, + input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY, + // Master Interface Write Data Ports + output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID, + output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, + output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, + output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST, + output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, + output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID, + input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY, + // Master Interface Write Response Ports + input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, // Unused + input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP, + input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, + input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID, + output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY, + // Master Interface Read Address Port + output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID, + output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, + output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN, + output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE, + output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST, + output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK, + output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE, + output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT, + output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION, + output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS, + output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, + output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID, + input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY, + // Master Interface Read Data Ports + input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, // Unused + input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, + input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP, + input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST, + input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, + input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID, + output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY + ); + + localparam integer P_AXI4 = 0; + localparam integer P_AXI3 = 1; + localparam integer P_AXILITE = 2; + localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS; + localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1; + localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1; + localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1; + localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH; + localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; + localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4; + localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; + localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH; + localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; + localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001; + localparam integer P_NONSECURE_BIT = 1; + localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots + localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0); // Mask of axilite rule-check MI-slots + localparam [1:0] P_FIXED = 2'b00; + localparam integer P_BYPASS = 0; + localparam integer P_LIGHTWT = 7; + localparam integer P_FULLY_REG = 1; + localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ? // "Automatic" reg-slice + (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) : // Bypass if no R-channel mux + C_R_REGISTER; + localparam P_DECERR = 2'b11; + + //--------------------------------------------------------------------------- + // Functions + //--------------------------------------------------------------------------- + // Ceiling of log2(x) + function integer f_ceil_log2 + ( + input integer x + ); + integer acc; + begin + acc=0; + while ((2**acc) < x) + acc = acc + 1; + f_ceil_log2 = acc; + end + endfunction + + // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value + // only for end-point SI-slots + function [C_AXI_ID_WIDTH-1:0] f_extend_ID + ( + input [C_AXI_ID_WIDTH-1:0] s_id, + input integer slot + ); + begin + f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); + end + endfunction + + // Convert Bit32 vector of range [0,1] to Bit1 vector on MI + function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi + (input [C_NUM_MASTER_SLOTS*32-1:0] vec32); + integer mi; + begin + for (mi=0; mi1) begin : gen_wmux + // SI WVALID mux. + generic_baseblocks_v2_1_0_mux_enc # + ( + .C_FAMILY ("rtl"), + .C_RATIO (C_NUM_SLAVE_SLOTS), + .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), + .C_DATA_WIDTH (1) + ) si_w_valid_mux_inst + ( + .S (aa_grant_enc), + .A (S_AXI_WVALID), + .O (aa_wvalid), + .OE (w_transfer_en) + ); + + // SI W-channel payload mux + generic_baseblocks_v2_1_0_mux_enc # + ( + .C_FAMILY ("rtl"), + .C_RATIO (C_NUM_SLAVE_SLOTS), + .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), + .C_DATA_WIDTH (P_WMESG_WIDTH) + ) si_w_payload_mux_inst + ( + .S (aa_grant_enc), + .A (si_wmesg), + .O (mi_wmesg), + .OE (1'b1) + ); + + for (gen_si_slot=0; gen_si_slot1) ? C_NUM_SLAVE_SLOTS : 2); + localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; + localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH; + localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH; + localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH; + localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH; + localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; + localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH; + localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; + localparam [31:0] P_BYPASS = 32'h00000000; + localparam [31:0] P_FWD_REV = 32'h00000001; + localparam [31:0] P_SIMPLE = 32'h00000007; + localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]}; + localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]}; + localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; + localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; + localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0); + localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0); + localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; + localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; + localparam P_DECERR = 2'b11; + + //--------------------------------------------------------------------------- + // Functions + //--------------------------------------------------------------------------- + // Ceiling of log2(x) + function integer f_ceil_log2 + ( + input integer x + ); + integer acc; + begin + acc=0; + while ((2**acc) < x) + acc = acc + 1; + f_ceil_log2 = acc; + end + endfunction + + // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value + // only for end-point SI-slots + function [C_AXI_ID_WIDTH-1:0] f_extend_ID + ( + input [C_AXI_ID_WIDTH-1:0] s_id, + input integer slot + ); + begin + f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); + end + endfunction + + // Write connectivity array transposed + function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity + ( + input integer null_arg + ); + integer si_slot; + integer mi_slot; + reg [C_NUM_SLAVE_SLOTS*32-1:0] result; + begin + result = {C_NUM_SLAVE_SLOTS*32{1'b1}}; + for (si_slot=0; si_slot1) begin : gen_rid_decoder + axi_crossbar_v2_1_28_addr_decoder # + ( + .C_FAMILY (C_FAMILY), + .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), + .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), + .C_NUM_RANGES (1), + .C_ADDR_WIDTH (C_AXI_ID_WIDTH), + .C_TARGET_ENC (C_DEBUG), + .C_TARGET_HOT (1), + .C_REGION_ENC (0), + .C_BASE_ADDR (C_S_AXI_BASE_ID), + .C_HIGH_ADDR (C_S_AXI_HIGH_ID), + .C_TARGET_QUAL (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), + .C_RESOLUTION (0) + ) + rid_decoder_inst + ( + .ADDR (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), + .TARGET_HOT (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), + .TARGET_ENC (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), + .MATCH (rid_match[gen_mi_slot]), + .REGION () + ); + end else begin : gen_no_rid_decoder + assign tmp_mr_rid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot. + assign rid_match[gen_mi_slot] = 1'b1; + end + + assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = { + st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], + st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], + st_mr_rresp[gen_mi_slot*2+:2] + }; + end else begin : gen_no_mi_read + assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; + assign rid_match[gen_mi_slot] = 1'b0; + assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0; + end // gen_mi_read + + if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write + if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder + axi_crossbar_v2_1_28_addr_decoder # + ( + .C_FAMILY (C_FAMILY), + .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), + .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), + .C_NUM_RANGES (1), + .C_ADDR_WIDTH (C_AXI_ID_WIDTH), + .C_TARGET_ENC (C_DEBUG), + .C_TARGET_HOT (1), + .C_REGION_ENC (0), + .C_BASE_ADDR (C_S_AXI_BASE_ID), + .C_HIGH_ADDR (C_S_AXI_HIGH_ID), + .C_TARGET_QUAL (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), + .C_RESOLUTION (0) + ) + bid_decoder_inst + ( + .ADDR (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), + .TARGET_HOT (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), + .TARGET_ENC (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), + .MATCH (bid_match[gen_mi_slot]), + .REGION () + ); + end else begin : gen_no_bid_decoder + assign tmp_mr_bid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot. + assign bid_match[gen_mi_slot] = 1'b1; + end + + axi_crossbar_v2_1_28_wdata_mux # // "WM": Write data Mux, per MI-slot (incl error-handler) + ( + .C_FAMILY (C_FAMILY), + .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), + .C_SELECT_WIDTH (P_NUM_SLAVE_SLOTS_LOG), + .C_WMESG_WIDTH (P_WR_WMESG_WIDTH), + .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]) + ) + wdata_mux_w + ( + .ACLK (ACLK), + .ARESET (reset), + // Vector of write transfer inputs from each SI-slot's W-router + .S_WMESG (wr_wm_wmesg), + .S_WLAST (wr_wm_wlast), + .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), + .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), + // Write transfer output to the current MI-slot + .M_WMESG (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]), + .M_WLAST (wm_mr_wlast[gen_mi_slot]), + .M_WVALID (wm_mr_wvalid[gen_mi_slot]), + .M_WREADY (wm_mr_wready[gen_mi_slot]), + // AW command push from AW arbiter output + .S_ASELECT (aa_wm_awgrant_enc), // SI-slot selected by arbiter + .S_AVALID (sa_wm_awvalid[gen_mi_slot]), + .S_AREADY (sa_wm_awready[gen_mi_slot]) + ); + + if (C_DEBUG) begin : gen_debug_w + // DEBUG WRITE BEAT COUNTER + always @(posedge ACLK) begin + if (reset) begin + debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; + end else begin + if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin + if (mi_wlast[gen_mi_slot]) begin + debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; + end else begin + debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1; + end + end + end + end // clocked process + + // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE + axi_data_fifo_v2_1_26_axic_srl_fifo # + ( + .C_FAMILY (C_FAMILY), + .C_FIFO_WIDTH (8), + .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]), + .C_USE_FULL (0) + ) + debug_w_seq_fifo + ( + .ACLK (ACLK), + .ARESET (reset), + .S_MESG (debug_aw_trans_seq_i), + .S_VALID (sa_wm_awvalid[gen_mi_slot]), + .S_READY (), + .M_MESG (debug_w_trans_seq_i[gen_mi_slot*8+:8]), + .M_VALID (), + .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot]) + ); + end // gen_debug_w + + assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH]; + assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8]; + assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH]; + assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH]; + assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = { + st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH], + st_mr_bresp[gen_mi_slot*2+:2] + }; + end else begin : gen_no_mi_write + assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; + assign bid_match[gen_mi_slot] = 1'b0; + assign wm_mr_wvalid[gen_mi_slot] = 0; + assign wm_mr_wlast[gen_mi_slot] = 0; + assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; + assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0; + assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0; + assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; + assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0; + assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; + assign sa_wm_awready[gen_mi_slot] = 0; + end // gen_mi_write + + for (gen_si_slot=0; gen_si_slot 0) ? C_THREAD_ID_WIDTH : 1; + localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH; + localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE; + localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots + + // Ceiling of log2(x) + function integer f_ceil_log2 + ( + input integer x + ); + integer acc; + begin + acc=0; + while ((2**acc) < x) + acc = acc + 1; + f_ceil_log2 = acc; + end + endfunction + + // AxiLite protocol flag vector + function [C_NUM_M-1:0] f_m_axilite + ( + input integer null_arg + ); + integer mi; + begin + for (mi=0; mi1) begin : gen_wmux + // SI-side write command queue + axi_data_fifo_v2_1_26_axic_reg_srl_fifo # + ( + .C_FAMILY (C_FAMILY), + .C_FIFO_WIDTH (C_SELECT_WIDTH), + .C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG), + .C_USE_FULL (0) + ) + wmux_aw_fifo + ( + .ACLK (ACLK), + .ARESET (ARESET), + .S_MESG (S_ASELECT), + .S_VALID (S_AVALID), + .S_READY (S_AREADY), + .M_MESG (m_select_enc), + .M_VALID (m_avalid), + .M_READY (m_aready) + ); + + assign m_select_hot = f_decoder(m_select_enc); + + // Instantiate MUX + generic_baseblocks_v2_1_0_mux_enc # + ( + .C_FAMILY ("rtl"), + .C_RATIO (C_NUM_SLAVE_SLOTS), + .C_SEL_WIDTH (C_SELECT_WIDTH), + .C_DATA_WIDTH (C_WMESG_WIDTH) + ) mux_w + ( + .S (m_select_enc), + .A (S_WMESG), + .O (M_WMESG), + .OE (1'b1) + ); + + assign m_last_i = |(S_WLAST & m_select_hot); + assign m_valid_i = |(S_WVALID & m_select_hot); + + assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY; + assign M_WLAST = m_last_i; + assign M_WVALID = m_valid_i & m_avalid; + assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}}; + end else begin : gen_no_wmux + assign S_AREADY = 1'b1; + assign M_WVALID = S_WVALID; + assign S_WREADY = M_WREADY; + assign M_WLAST = S_WLAST; + assign M_WMESG = S_WMESG; + end + endgenerate + +endmodule + +`default_nettype wire + + +// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// File name: wdata_router.v +// +// Description: +// Contains SI-side write command queue. +// Target MI-slot index is pushed onto queue when S_AVALID transfer is received. +// Queue is popped when WLAST data beat is transferred. +// W-channel input is transferred to MI-slot output selected by queue output. +//-------------------------------------------------------------------------- +// +// Structure: +// wdata_router +// axic_reg_srl_fifo +// +//----------------------------------------------------------------------------- + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_crossbar_v2_1_28_wdata_router # + ( + parameter C_FAMILY = "none", // FPGA Family. + parameter integer C_WMESG_WIDTH = 1, // Width of all data signals + parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports. + parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT. + parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG. + ) + ( + // System Signals + input wire ACLK, + input wire ARESET, + // Slave Data Ports + input wire [C_WMESG_WIDTH-1:0] S_WMESG, + input wire S_WLAST, + input wire S_WVALID, + output wire S_WREADY, + // Master Data Ports + output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots + output wire M_WLAST, // Broadcast to all MI-slots + output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot + input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot + // Address Arbiter Ports + input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command + input wire S_AVALID, + output wire S_AREADY + ); + + localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32 + + // Decode select input to 1-hot + function [C_NUM_MASTER_SLOTS-1:0] f_decoder ( + input [C_SELECT_WIDTH-1:0] sel + ); + integer i; + begin + for (i=0; i 0. + // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000. + // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}. + // Range: 0 - C_AXI_ADDR_WIDTH. + parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000, + // Base ID of each SI slot. + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 0 to 2**C_AXI_ID_WIDTH-1. + parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000, + // Number of low-order ID bits a connected master may vary to select a transaction thread. + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 0 - C_AXI_ID_WIDTH. + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + // 1 = Propagate all USER signals, 0 = Dont propagate. + parameter integer C_AXI_AWUSER_WIDTH = 1, + // Width of AWUSER signals for all SI slots and MI slots. + // Range: 1-1024. + parameter integer C_AXI_ARUSER_WIDTH = 1, + // Width of ARUSER signals for all SI slots and MI slots. + // Range: 1-1024. + parameter integer C_AXI_WUSER_WIDTH = 1, + // Width of WUSER signals for all SI slots and MI slots. + // Range: 1-1024. + parameter integer C_AXI_RUSER_WIDTH = 1, + // Width of RUSER signals for all SI slots and MI slots. + // Range: 1-1024. + parameter integer C_AXI_BUSER_WIDTH = 1, + // Width of BUSER signals for all SI slots and MI slots. + // Range: 1-1024. + parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, + // Multi-pathway write connectivity from each SI slot (N) to each + // MI slot (M): + // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) + // Format: C_NUM_MASTER_SLOTS{Bit32}; + parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, + // Multi-pathway read connectivity from each SI slot (N) to each + // MI slot (M): + // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) + // Format: C_NUM_MASTER_SLOTS{Bit32}; + parameter integer C_R_REGISTER = 0, + // Insert register slice on R channel in the crossbar. (Valid only for SASD) + // Range: Reg-slice type (0-8). + parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000, + // 0 = Implement separate command queues per ID thread. + // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD) + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 0, 1 + parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002, + // Maximum number of active write transactions that each SI + // slot can accept. (Valid only for SAMD) + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 1-32. + parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002, + // Maximum number of active read transactions that each SI + // slot can accept. (Valid only for SAMD) + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 1-32. + parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004, + // Maximum number of data-active write transactions that + // each MI slot can generate at any one time. (Valid only for SAMD) + // Format: C_NUM_MASTER_SLOTS{Bit32}; + // Range: 1-32. + parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004, + // Maximum number of active read transactions that + // each MI slot can generate at any one time. (Valid only for SAMD) + // Format: C_NUM_MASTER_SLOTS{Bit32}; + // Range: 1-32. + parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000, + // Arbitration priority among each SI slot. + // Higher values indicate higher priority. + // Format: C_NUM_SLAVE_SLOTS{Bit32}; + // Range: 0-15. + parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000, + // Indicates whether each MI slot connects to a secure slave + // (allows only TrustZone secure access). + // Format: C_NUM_MASTER_SLOTS{Bit32}. + // Range: 0, 1 + parameter integer C_CONNECTIVITY_MODE = 1 + // 0 = Shared-Address Shared-Data (SASD). + // 1 = Shared-Address Multi-Data (SAMD). + // Default 1 (on) for simulation; default 0 (off) for implementation. +) +( + // Global Signals + input wire aclk, + input wire aresetn, + // Slave Interface Write Address Ports + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize, + input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst, + input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot, +// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid, + output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready, + // Slave Interface Write Data Ports + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid, + output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready, + // Slave Interface Write Response Ports + output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp, + output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid, + input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready, + // Slave Interface Read Address Ports + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize, + input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst, + input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache, + input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot, +// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion, + input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos, + input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid, + output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready, + // Slave Interface Read Data Ports + output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp, + output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast, + output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid, + input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready, + // Master Interface Write Address Port + output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize, + output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst, + output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache, + output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot, + output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion, + output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos, + output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid, + input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready, + // Master Interface Write Data Ports + output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid, + output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast, + output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid, + input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready, + // Master Interface Write Response Ports + input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp, + input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid, + output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready, + // Master Interface Read Address Port + output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize, + output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst, + output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache, + output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot, + output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion, + output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos, + output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid, + input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready, + // Master Interface Read Data Ports + input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp, + input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast, + input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid, + output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready +); + + localparam [64:0] P_ONES = {65{1'b1}}; + localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0); + localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0); + localparam integer P_AXI4 = 0; + localparam integer P_AXI3 = 1; + localparam integer P_AXILITE = 2; + localparam [2:0] P_AXILITE_SIZE = 3'b010; + localparam [1:0] P_INCR = 2'b01; + localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0); + localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0); + localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0); + localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0); + localparam integer C_DEBUG = 1; + localparam integer P_RANGE_CHECK = 1; + // 1 (non-zero) = Detect and issue DECERR on the following conditions: + // a. address range mismatch (no valid MI slot) + // b. Burst or >32-bit transfer to AxiLite slave + // c. TrustZone access violation + // d. R/W direction unsupported by target + // 0 = Pass all transactions (no DECERR): + // a. Omit DECERR detection and response logic + // b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION + // when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1. + // c. Unpredictable target MI-slot if address mismatch and >1 MI-slot + // d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave + // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0. + localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1 + localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}; + // Transaction error detection (per MI-slot) + // 0 = None; 1 = AXI4Lite burst violation + // Format: C_NUM_MASTER_SLOTS{Bit32}; + localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8; + localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1; + localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl"; + + function integer f_ceil_log2 + ( + input integer x + ); + integer acc; + begin + acc=0; + while ((2**acc) < x) + acc = acc + 1; + f_ceil_log2 = acc; + end + endfunction + + // Widths of all write issuance counters implemented in axi_crossbar_v2_1_28_crossbar (before counter carry-out bit) + function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec + (input null_arg); + integer mi; + reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result; + begin + result = 0; + for (mi=0; mi= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : + (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})); + end + f_high_id = result; + end + endfunction + + // Construct P_M_HIGH_ADDR vector + function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr + (input null_arg); + integer ar; + reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result; + begin + result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}; + for (ar=0; ar= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} : + (C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]})); + end + f_high_addr = result; + end + endfunction + + // Generate a mask of valid ID bits for a given SI slot. + function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask + (input integer si); + begin + f_thread_id_mask = + (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : + ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : + ({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})); + end + endfunction + + // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value + // only for end-point SI-slots + function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( + input [C_AXI_ID_WIDTH-1:0] s_id, + input integer si + ); + begin + f_extend_ID = + (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] : + ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id : + (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}))); + end + endfunction + + // Bit vector of SI slots with at least one write connection. + function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write + (input null_arg); + integer mi; + reg [C_NUM_SLAVE_SLOTS-1:0] result; + begin + result = {C_NUM_SLAVE_SLOTS{1'b0}}; + for (mi=0; mi