updates

cpp/test_data_recorder.cpp

@@ -1,3 +1,15 @@
+// sudo setpci -s 0000:05:00.0 0x78.w=293f
+/*
+https://forums.developer.nvidia.com/t/the-devctl-maxpayload-is-lower-than-devcap/319292
+Some example for how to use setpci.
+
+sudo setpci -s 0005:00:00.0 74.w (device capabilities register for x4)
+sudo setpci -s 0005:00:00.0 78.w ( Device Control register for x4) and write value for bits 7:5 as (001b) for 256 Bytes MPS
+
+You have to change 0005:00:00.0 to the device you are using here.
+
+*/
+
 #include "data_recorder.h"
 int main() {
     // Instantiate the class
@@ -6,16 +18,21 @@ int main() {
     printf("Test Reg Read - 0x%x\n", dr.read_reg(UTIL_REG_BASE + 0x0));
 
     // Setup Timing Engine and data generator to test
-    float pri = 90e-6;
     uint32_t n_pulses = 128;
     float inter_cpi = 100e-6;
+    float pri = 84e-6;
     uint32_t n_samples = 8192;
+    // float pri = 40e-6;
+    // uint32_t n_samples = 4096;
 
     float cpi_time = n_pulses * pri + inter_cpi;
     float cpi_num_bytes = n_pulses * n_samples * 16;
 
     float expected_data_rate = cpi_num_bytes / cpi_time / 1e6;
-    // PCIe Gen3 x4 Therotecial Max is 4GBPS
+    // PCIe Gen3 x4 Therotecial Max is 4GBPS, 
+    // 128B/120B encoding drops that to 3938 MBPS
+    // Assuming an MSP of 128 bytes (86.5% effeciency), that further drops to 3406 MBPS
+    // Currently achieving 3092 MBPS without errors which is ~90% of 3406 MBPS
     printf("Expected Data Rate - %.2f MBps Per Channel, Total %.2f\n", expected_data_rate, expected_data_rate * NUM_DMA_CH);
 
     dr.write_reg(TIMING_REG_BASE + 0x0, 1);