updates
This commit is contained in:
@@ -59,15 +59,15 @@ DataRecorder::DataRecorder() {
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allocate_memory();
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// Prep access to PL registers
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plfd = open("/dev/wsrpl0", O_RDWR);
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plfd = open("/dev/drexpl0", O_RDWR);
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if (plfd < 0){
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printf("Failed to open %s\n", "/dev/wsrpl0");
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printf("Failed to open %s\n", "/dev/drexpl0");
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}
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plmmap = (uint32_t *)mmap(NULL, 0x1000000, PROT_WRITE | PROT_READ, MAP_SHARED, plfd, 0);
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if (plmmap < (uint32_t *)0){
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printf("Failed to mmap %s\n", "/dev/wsrpl0");
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printf("Failed to mmap %s\n", "/dev/drexpl0");
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close(plfd);
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}
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@@ -266,7 +266,7 @@ void DataRecorder::set_validate_cnt_data(bool enable, uint32_t pri, uint32_t int
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void DataRecorder::get_data(int ch_ind, int save_to_disk) {
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char* file;
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asprintf(&file, "/dev/wsrdma%d", ch_ind);
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asprintf(&file, "/dev/drexdma%d", ch_ind);
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// Start write to disk thread
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if (save_to_disk) {
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@@ -279,27 +279,27 @@ void DataRecorder::get_data(int ch_ind, int save_to_disk) {
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return;
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}
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wsrpcie_ioctl_t wsrpcie_ioctl;
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drexpcie_ioctl_t drexpcie_ioctl;
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wsrpcie_ioctl.cmd = WSRDMA_SET_NUM_BYTES;
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wsrpcie_ioctl.offset = 0;
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wsrpcie_ioctl.value = BUFFER_SIZE;
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ioctl(fd, 0, &wsrpcie_ioctl);
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drexpcie_ioctl.cmd = DREXDMA_SET_NUM_BYTES;
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drexpcie_ioctl.offset = 0;
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drexpcie_ioctl.value = BUFFER_SIZE;
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ioctl(fd, 0, &drexpcie_ioctl);
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wsrpcie_ioctl.cmd = WSRDMA_SET_NUM_BUFS;
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wsrpcie_ioctl.offset = 0;
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wsrpcie_ioctl.value = NUM_BUFFERS;
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ioctl(fd, 0, &wsrpcie_ioctl);
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drexpcie_ioctl.cmd = DREXDMA_SET_NUM_BUFS;
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drexpcie_ioctl.offset = 0;
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drexpcie_ioctl.value = NUM_BUFFERS;
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ioctl(fd, 0, &drexpcie_ioctl);
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wsrpcie_ioctl.cmd = WSRDMA_DMA_INIT;
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wsrpcie_ioctl.offset = 0;
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wsrpcie_ioctl.value = 0;
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ioctl(fd, 0, &wsrpcie_ioctl);
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drexpcie_ioctl.cmd = DREXDMA_DMA_INIT;
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drexpcie_ioctl.offset = 0;
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drexpcie_ioctl.value = 0;
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ioctl(fd, 0, &drexpcie_ioctl);
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wsrpcie_ioctl.cmd = WSRDMA_DMA_START;
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wsrpcie_ioctl.offset = 0;
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wsrpcie_ioctl.value = 0;
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ioctl(fd, 0, &wsrpcie_ioctl);
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drexpcie_ioctl.cmd = DREXDMA_DMA_START;
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drexpcie_ioctl.offset = 0;
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drexpcie_ioctl.value = 0;
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ioctl(fd, 0, &drexpcie_ioctl);
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struct timespec ts_now;
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@@ -394,17 +394,17 @@ void DataRecorder::get_data(int ch_ind, int save_to_disk) {
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}
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wsrpcie_ioctl.cmd = WSRDMA_DMA_STOP;
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wsrpcie_ioctl.offset = 0;
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wsrpcie_ioctl.value = 0;
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drexpcie_ioctl.cmd = DREXDMA_DMA_STOP;
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drexpcie_ioctl.offset = 0;
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drexpcie_ioctl.value = 0;
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ioctl(fd, 0, &wsrpcie_ioctl);
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ioctl(fd, 0, &drexpcie_ioctl);
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wsrpcie_ioctl.cmd = WSRDMA_DMA_CLEAR;
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wsrpcie_ioctl.offset = 0;
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wsrpcie_ioctl.value = 0;
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drexpcie_ioctl.cmd = DREXDMA_DMA_CLEAR;
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drexpcie_ioctl.offset = 0;
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drexpcie_ioctl.value = 0;
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ioctl(fd, 0, &wsrpcie_ioctl);
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ioctl(fd, 0, &drexpcie_ioctl);
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// Make sure write thread is done before closing file handle
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if (writer[ch_ind].joinable()) {
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@@ -16,21 +16,21 @@
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#define TIMING_REG_BASE 0x20000
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#define DATA_GEN_REG_BASE 0x30000
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#define WSRDMA_DMA_INIT 0
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#define WSRDMA_DMA_CLEAR 1
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#define WSRDMA_DMA_START 2
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#define WSRDMA_DMA_STOP 3
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#define WSRDMA_SET_NUM_BUFS 4
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#define WSRDMA_SET_NUM_BYTES 5
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#define WSRDMA_GET_NUM_BUFS 6
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#define WSRDMA_GET_NUM_BYTES 7
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#define WSRDMA_GET_FREE_BUFS 8
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#define DREXDMA_DMA_INIT 0
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#define DREXDMA_DMA_CLEAR 1
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#define DREXDMA_DMA_START 2
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#define DREXDMA_DMA_STOP 3
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#define DREXDMA_SET_NUM_BUFS 4
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#define DREXDMA_SET_NUM_BYTES 5
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#define DREXDMA_GET_NUM_BUFS 6
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#define DREXDMA_GET_NUM_BYTES 7
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#define DREXDMA_GET_FREE_BUFS 8
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typedef struct {
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unsigned int cmd;
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unsigned int offset;
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unsigned int value;
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} wsrpcie_ioctl_t;
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} drexpcie_ioctl_t;
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#define NUM_DMA_CH 4
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#define BUFFER_SIZE (4 * 1024 * 1024)
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@@ -11,8 +11,13 @@ int main() {
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uint32_t n_pulses = 128;
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float inter_cpi = 100e-6;
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// float pri = 75e-6;
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float pri = 200e-6;
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float pri = 100e-6;
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uint32_t n_samples = 16384;
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int test_time_ms = 10000;
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// Set false to just pull data across the pcie and run the data validator.
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// Set true to save data to disk
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bool save_to_disk = false;
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float cpi_time = n_pulses * pri + inter_cpi;
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float cpi_num_bytes = n_pulses * n_samples * 16;
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@@ -40,13 +45,12 @@ int main() {
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dr.set_validate_cnt_data(true, dr.read_reg(TIMING_REG_BASE + 0x4) + 1, dr.read_reg(TIMING_REG_BASE + 0x10) + 1, n_pulses);
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// Start listening for data
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// dr.start_recording("test.bin", 1);
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dr.start_recording("/media/hptnvme/test.bin", 1);
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dr.start_recording("/media/hptnvme/test.bin", save_to_disk);
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sleep(1);
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// Start the timing engine so data starts flowing
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dr.write_reg(TIMING_REG_BASE + 0x0, 0);
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// Wait a while
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std::this_thread::sleep_for(std::chrono::milliseconds(2000));
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std::this_thread::sleep_for(std::chrono::milliseconds(test_time_ms));
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dr.write_reg(TIMING_REG_BASE + 0x0, 1);
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sleep(2);
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dr.stop_recording();
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