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Brian Kiedinger
2025-03-30 21:43:59 -05:00
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2
vitis/radar/.gitignore vendored Executable file
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26
vitis/radar/.project Executable file
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178
vitis/radar/_ide/bitstream/top.mmi Normal file
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<!-- Product Version: Vivado v2022.2 (64-bit) -->
<!-- SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Oct 14 2022 -->
<!-- -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
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1
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72
vitis/radar/_ide/launch/Debugger_radar-sw only.launch Executable file
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@@ -0,0 +1,72 @@
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vitis/radar/_ide/launch/IBERT.launch Executable file
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@@ -0,0 +1,72 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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vitis/radar/radar.prj Executable file
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@@ -0,0 +1,11 @@
<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="8781df679aa71a5344fa22cfacec20c4">
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</sdkproject:SdkProject>

10
vitis/radar/src/.vscode/settings.json vendored Executable file
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@@ -0,0 +1,10 @@
{
"files.associations": {
"cstdlib": "c",
"radar_manager_icd.h": "c",
"compare": "c",
"adi_cms_api_common.h": "c",
"stdarg.h": "c",
"project.h": "c"
}
}

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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_ad9081.h Executable file
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288
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_impala_tc.h Executable file
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@@ -0,0 +1,288 @@
/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:25 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_IMPALA_TC_H__
#define __ADI_AD9081_BF_IMPALA_TC_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_POWERDOWN_REG_0_ADDR 0x000000E0
#define BF_D_PD_DIV8_INFO 0x00000100
#define BF_D_PD_DIV8(val) (val & 0x00000001)
#define BF_D_PD_DIV8_GET(val) (val & 0x00000001)
#define BF_D_PD_VCO_DIV_INFO 0x00000101
#define BF_D_PD_VCO_DIV(val) ((val & 0x00000001) << 0x00000001)
#define BF_D_PD_VCO_DIV_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_D_PD_VCO_DRIVER_INFO 0x00000102
#define BF_D_PD_VCO_DRIVER(val) ((val & 0x00000001) << 0x00000002)
#define BF_D_PD_VCO_DRIVER_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_D_PD_VCO_BUF_INFO 0x00000103
#define BF_D_PD_VCO_BUF(val) ((val & 0x00000001) << 0x00000003)
#define BF_D_PD_VCO_BUF_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_D_PD_CURR_INFO 0x00000304
#define BF_D_PD_CURR(val) ((val & 0x00000007) << 0x00000004)
#define BF_D_PD_CURR_GET(val) ((val >> 0x00000004) & 0x00000007)
#define BF_D_PD_REG_INFO 0x00000107
#define BF_D_PD_REG(val) ((val & 0x00000001) << 0x00000007)
#define BF_D_PD_REG_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_POWERDOWN_REG_1_ADDR 0x000000E1
#define BF_D_PD_REFCLK_DIV_INFO 0x00000100
#define BF_D_PD_REFCLK_DIV(val) (val & 0x00000001)
#define BF_D_PD_REFCLK_DIV_GET(val) (val & 0x00000001)
#define BF_D_PD_VCM_C_INFO 0x00000101
#define BF_D_PD_VCM_C(val) ((val & 0x00000001) << 0x00000001)
#define BF_D_PD_VCM_C_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_D_PD_VCM_F_INFO 0x00000102
#define BF_D_PD_VCM_F(val) ((val & 0x00000001) << 0x00000002)
#define BF_D_PD_VCM_F_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_D_PD_COARSE_BUFF_INFO 0x00000103
#define BF_D_PD_COARSE_BUFF(val) ((val & 0x00000001) << 0x00000003)
#define BF_D_PD_COARSE_BUFF_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_D_PD_CP_INFO 0x00000104
#define BF_D_PD_CP(val) ((val & 0x00000001) << 0x00000004)
#define BF_D_PD_CP_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_RESET_REG_ADDR 0x000000E2
#define BF_D_RESET_VCO_DIV_INFO 0x00000100
#define BF_D_RESET_VCO_DIV(val) (val & 0x00000001)
#define BF_D_RESET_VCO_DIV_GET(val) (val & 0x00000001)
#define BF_D_CAL_RESET_INFO 0x00000101
#define BF_D_CAL_RESET(val) ((val & 0x00000001) << 0x00000001)
#define BF_D_CAL_RESET_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_D_PFD_RESET_INFO 0x00000102
#define BF_D_PFD_RESET(val) ((val & 0x00000001) << 0x00000002)
#define BF_D_PFD_RESET_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_D_RESET_REF_DIV_INFO 0x00000103
#define BF_D_RESET_REF_DIV(val) ((val & 0x00000001) << 0x00000003)
#define BF_D_RESET_REF_DIV_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_D_RESET_FEEDBACK_DIV_INFO 0x00000104
#define BF_D_RESET_FEEDBACK_DIV(val) ((val & 0x00000001) << 0x00000004)
#define BF_D_RESET_FEEDBACK_DIV_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_INPUT_MISC_REG_ADDR 0x000000E3
#define BF_D_REFIN_DIV_INFO 0x00000200
#define BF_D_REFIN_DIV(val) (val & 0x00000003)
#define BF_D_REFIN_DIV_GET(val) (val & 0x00000003)
#define BF_D_CLK_EDGE_INFO 0x00000102
#define BF_D_CLK_EDGE(val) ((val & 0x00000001) << 0x00000002)
#define BF_D_CLK_EDGE_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_D_PFD_DELAY_INFO 0x00000303
#define BF_D_PFD_DELAY(val) ((val & 0x00000007) << 0x00000003)
#define BF_D_PFD_DELAY_GET(val) ((val >> 0x00000003) & 0x00000007)
#define BF_D_COARSE_CONTROL_INFO 0x00000106
#define BF_D_COARSE_CONTROL(val) ((val & 0x00000001) << 0x00000006)
#define BF_D_COARSE_CONTROL_GET(val) ((val >> 0x00000006) & 0x00000001)
#define REG_CHARGEPUMP_REG_0_ADDR 0x000000E4
#define BF_D_CP_CURRENT_INFO 0x00000600
#define BF_D_CP_CURRENT(val) (val & 0x0000003F)
#define BF_D_CP_CURRENT_GET(val) (val & 0x0000003F)
#define BF_D_CP_CAL_EN_INFO 0x00000106
#define BF_D_CP_CAL_EN(val) ((val & 0x00000001) << 0x00000006)
#define BF_D_CP_CAL_EN_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_D_CP_CALIBRATE_INFO 0x00000107
#define BF_D_CP_CALIBRATE(val) ((val & 0x00000001) << 0x00000007)
#define BF_D_CP_CALIBRATE_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_CHARGEPUMP_REG_1_ADDR 0x000000E5
#define BF_D_CP_CALBITS_INFO 0x00000400
#define BF_D_CP_CALBITS(val) (val & 0x0000000F)
#define BF_D_CP_CALBITS_GET(val) (val & 0x0000000F)
#define BF_D_CP_OFFSET_DNB_INFO 0x00000104
#define BF_D_CP_OFFSET_DNB(val) ((val & 0x00000001) << 0x00000004)
#define BF_D_CP_OFFSET_DNB_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_D_CP_RECONF_INFO 0x00000105
#define BF_D_CP_RECONF(val) ((val & 0x00000001) << 0x00000005)
#define BF_D_CP_RECONF_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_D_CP_TEST_INFO 0x00000206
#define BF_D_CP_TEST(val) ((val & 0x00000003) << 0x00000006)
#define BF_D_CP_TEST_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_VCM_CONTROL_REG_ADDR 0x000000E6
#define BF_D_VCM_C_CONTROL_INFO 0x00000400
#define BF_D_VCM_C_CONTROL(val) (val & 0x0000000F)
#define BF_D_VCM_C_CONTROL_GET(val) (val & 0x0000000F)
#define BF_D_VCM_F_CONTROL_INFO 0x00000404
#define BF_D_VCM_F_CONTROL(val) ((val & 0x0000000F) << 0x00000004)
#define BF_D_VCM_F_CONTROL_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_BIAS_REG_0_ADDR 0x000000E7
#define BF_D_BIAS_FIXED_TRIM_INFO 0x00000600
#define BF_D_BIAS_FIXED_TRIM(val) (val & 0x0000003F)
#define BF_D_BIAS_FIXED_TRIM_GET(val) (val & 0x0000003F)
#define BF_D_REG_SLICE_SEL_INFO 0x00000206
#define BF_D_REG_SLICE_SEL(val) ((val & 0x00000003) << 0x00000006)
#define BF_D_REG_SLICE_SEL_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_BIAS_REG_1_ADDR 0x000000E8
#define BF_D_BIAS_POLY_TRIM_INFO 0x00000600
#define BF_D_BIAS_POLY_TRIM(val) (val & 0x0000003F)
#define BF_D_BIAS_POLY_TRIM_GET(val) (val & 0x0000003F)
#define BF_D_REG_BYPASS_FIT_INFO 0x00000106
#define BF_D_REG_BYPASS_FIT(val) ((val & 0x00000001) << 0x00000006)
#define BF_D_REG_BYPASS_FIT_GET(val) ((val >> 0x00000006) & 0x00000001)
#define REG_DIVIDER_REG_ADDR 0x000000E9
#define BF_D_DIVIDE_CONTROL_INFO 0x00000600
#define BF_D_DIVIDE_CONTROL(val) (val & 0x0000003F)
#define BF_D_DIVIDE_CONTROL_GET(val) (val & 0x0000003F)
#define REG_VCO_CAL_CONTROL_REG_0_ADDR 0x000000EA
#define BF_D_IMPALA_CAL_CONTROL_INFO 0x00001000
#define BF_D_IMPALA_CAL_CONTROL(val) (val & 0x0000FFFF)
#define BF_D_IMPALA_CAL_CONTROL_GET(val) (val & 0x0000FFFF)
#define REG_VCO_CAL_CONTROL_REG_1_ADDR 0x000000EB
#define REG_VCO_CAL_LOCK_REG_ADDR 0x000000EC
#define BF_D_CAL_OVERRIDE_INFO 0x00000100
#define BF_D_CAL_OVERRIDE(val) (val & 0x00000001)
#define BF_D_CAL_OVERRIDE_GET(val) (val & 0x00000001)
#define BF_D_PLL_LOCK_CONTROL_INFO 0x00000201
#define BF_D_PLL_LOCK_CONTROL(val) ((val & 0x00000003) << 0x00000001)
#define BF_D_PLL_LOCK_CONTROL_GET(val) ((val >> 0x00000001) & 0x00000003)
#define BF_D_FREQUENCY_LOCK_OOR_INFO 0x00000103
#define BF_D_FREQUENCY_LOCK_OOR(val) ((val & 0x00000001) << 0x00000003)
#define BF_D_FREQUENCY_LOCK_OOR_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_D_CONTROL_HS_FB_DIV_INFO 0x00000204
#define BF_D_CONTROL_HS_FB_DIV(val) ((val & 0x00000003) << 0x00000004)
#define BF_D_CONTROL_HS_FB_DIV_GET(val) ((val >> 0x00000004) & 0x00000003)
#define REG_VCO_CAL_MOMCAP_REG_0_ADDR 0x000000ED
#define REG_VCO_CAL_MOMCAP_REG_1_ADDR 0x000000EE
#define BF_D_VCO_MOMCAP_INFO 0x00000B00
#define BF_D_VCO_MOMCAP(val) (val & 0x000007FF)
#define BF_D_VCO_MOMCAP_GET(val) (val & 0x000007FF)
#define BF_D_IMPALA_TEMP_INFO 0x00000203
#define BF_D_IMPALA_TEMP(val) ((val & 0x00000003) << 0x00000003)
#define BF_D_IMPALA_TEMP_GET(val) ((val >> 0x00000003) & 0x00000003)
#define BF_D_VCO_CAL_TYPE_INFO 0x00000105
#define BF_D_VCO_CAL_TYPE(val) ((val & 0x00000001) << 0x00000005)
#define BF_D_VCO_CAL_TYPE_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_D_VCO_FINE_CAP_PRE_INFO 0x00000206
#define BF_D_VCO_FINE_CAP_PRE(val) ((val & 0x00000003) << 0x00000006)
#define BF_D_VCO_FINE_CAP_PRE_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_VCO_CAL_MOMCAP_PRE_REG_0_ADDR 0x000000EF
#define REG_VCO_CAL_MOMCAP_PRE_REG_1_ADDR 0x000000F0
#define BF_D_VCO_MOMCAP_PRE_INFO 0x00000B00
#define BF_D_VCO_MOMCAP_PRE(val) (val & 0x000007FF)
#define BF_D_VCO_MOMCAP_PRE_GET(val) (val & 0x000007FF)
#define BF_D_EN_VAR_COARSE_PRE_INFO 0x00000103
#define BF_D_EN_VAR_COARSE_PRE(val) ((val & 0x00000001) << 0x00000003)
#define BF_D_EN_VAR_COARSE_PRE_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_D_EN_VAR_FINE_PRE_INFO 0x00000104
#define BF_D_EN_VAR_FINE_PRE(val) ((val & 0x00000001) << 0x00000004)
#define BF_D_EN_VAR_FINE_PRE_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_D_VCO_COARSE_CAP_PRE_INFO 0x00000205
#define BF_D_VCO_COARSE_CAP_PRE(val) ((val & 0x00000003) << 0x00000005)
#define BF_D_VCO_COARSE_CAP_PRE_GET(val) ((val >> 0x00000005) & 0x00000003)
#define REG_VCO_CAL_STATE_REG_ADDR 0x000000F1
#define BF_D_VCO_CAL_INCREMENT_INFO 0x00000100
#define BF_D_VCO_CAL_INCREMENT(val) (val & 0x00000001)
#define BF_D_VCO_CAL_INCREMENT_GET(val) (val & 0x00000001)
#define BF_D_IMPALA_CAL_STATE_INFO 0x00000401
#define BF_D_IMPALA_CAL_STATE(val) ((val & 0x0000000F) << 0x00000001)
#define BF_D_IMPALA_CAL_STATE_GET(val) ((val >> 0x00000001) & 0x0000000F)
#define BF_D_REGULATOR_CAL_WAIT_INFO 0x00000205
#define BF_D_REGULATOR_CAL_WAIT(val) ((val & 0x00000003) << 0x00000005)
#define BF_D_REGULATOR_CAL_WAIT_GET(val) ((val >> 0x00000005) & 0x00000003)
#define BF_D_VCO_SEL_INFO 0x00000107
#define BF_D_VCO_SEL(val) ((val & 0x00000001) << 0x00000007)
#define BF_D_VCO_SEL_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_VCO_CAL_CYCLES_REG_ADDR 0x000000F2
#define BF_D_VCO_PULLH_INFO 0x00000100
#define BF_D_VCO_PULLH(val) (val & 0x00000001)
#define BF_D_VCO_PULLH_GET(val) (val & 0x00000001)
#define BF_D_VCO_CAL_CYCLES_INFO 0x00000201
#define BF_D_VCO_CAL_CYCLES(val) ((val & 0x00000003) << 0x00000001)
#define BF_D_VCO_CAL_CYCLES_GET(val) ((val >> 0x00000001) & 0x00000003)
#define BF_D_VCO_CAL_WAIT_INFO 0x00000203
#define BF_D_VCO_CAL_WAIT(val) ((val & 0x00000003) << 0x00000003)
#define BF_D_VCO_CAL_WAIT_GET(val) ((val >> 0x00000003) & 0x00000003)
#define BF_D_MOMCAP_DUAL_START_INFO 0x00000305
#define BF_D_MOMCAP_DUAL_START(val) ((val & 0x00000007) << 0x00000005)
#define BF_D_MOMCAP_DUAL_START_GET(val) ((val >> 0x00000005) & 0x00000007)
#define REG_VCO_COUNT_DIFF_REG_0_ADDR 0x000000F3
#define BF_D_VCO_COUNT_DIFF_INFO 0x00001000
#define BF_D_VCO_COUNT_DIFF(val) (val & 0x0000FFFF)
#define BF_D_VCO_COUNT_DIFF_GET(val) (val & 0x0000FFFF)
#define REG_VCO_COUNT_DIFF_REG_1_ADDR 0x000000F4
#define REG_VCM_CONTROL_C_REG_ADDR 0x000000F5
#define BF_D_VCM_C_CONTROL_C_INFO 0x00000400
#define BF_D_VCM_C_CONTROL_C(val) (val & 0x0000000F)
#define BF_D_VCM_C_CONTROL_C_GET(val) (val & 0x0000000F)
#define BF_D_VCM_F_CONTROL_C_INFO 0x00000404
#define BF_D_VCM_F_CONTROL_C(val) ((val & 0x0000000F) << 0x00000004)
#define BF_D_VCM_F_CONTROL_C_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_VCM_CONTROL_H_REG_ADDR 0x000000F6
#define BF_D_VCM_C_CONTROL_H_INFO 0x00000400
#define BF_D_VCM_C_CONTROL_H(val) (val & 0x0000000F)
#define BF_D_VCM_C_CONTROL_H_GET(val) (val & 0x0000000F)
#define BF_D_VCM_F_CONTROL_H_INFO 0x00000404
#define BF_D_VCM_F_CONTROL_H(val) ((val & 0x0000000F) << 0x00000004)
#define BF_D_VCM_F_CONTROL_H_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_CHARGEPUMP_REG_2_ADDR 0x000000F7
#define BF_D_CP_BLEED_INFO 0x00000600
#define BF_D_CP_BLEED(val) (val & 0x0000003F)
#define BF_D_CP_BLEED_GET(val) (val & 0x0000003F)
#define REG_FASTV_COMP_LOWL_REG_0_ADDR 0x000000F8
#define BF_D_FASTV_COMP_LOWL_INFO 0x00000B00
#define BF_D_FASTV_COMP_LOWL(val) (val & 0x000007FF)
#define BF_D_FASTV_COMP_LOWL_GET(val) (val & 0x000007FF)
#define REG_FASTV_COMP_LOWL_REG_1_ADDR 0x000000F9
#define REG_FASTV_COMP_HIGHL_REG_0_ADDR 0x000000FA
#define BF_D_FASTV_COMP_HIGHL_INFO 0x00000B00
#define BF_D_FASTV_COMP_HIGHL(val) (val & 0x000007FF)
#define BF_D_FASTV_COMP_HIGHL_GET(val) (val & 0x000007FF)
#define REG_FASTV_COMP_HIGHL_REG_1_ADDR 0x000000FB
#define REG_SLOWV_COMP_LOWL_REG_0_ADDR 0x000000FC
#define BF_D_SLOWV_COMP_LOWL_INFO 0x00000B00
#define BF_D_SLOWV_COMP_LOWL(val) (val & 0x000007FF)
#define BF_D_SLOWV_COMP_LOWL_GET(val) (val & 0x000007FF)
#define REG_SLOWV_COMP_LOWL_REG_1_ADDR 0x000000FD
#define REG_SLOWV_COMP_HIGHL_REG_0_ADDR 0x000000FE
#define BF_D_SLOWV_COMP_HIGHL_INFO 0x00000B00
#define BF_D_SLOWV_COMP_HIGHL(val) (val & 0x000007FF)
#define BF_D_SLOWV_COMP_HIGHL_GET(val) (val & 0x000007FF)
#define REG_SLOWV_COMP_HIGHL_REG_1_ADDR 0x000000FF
#define REG_IMPALA_REV_ID_ADDR 0x00000100
#define BF_D_IMPALA_REV_ID_INFO 0x00000800
#define BF_D_IMPALA_REV_ID(val) (val & 0x000000FF)
#define BF_D_IMPALA_REV_ID_GET(val) (val & 0x000000FF)
#endif /* __ADI_AD9081_BF_IMPALA_TC_H__ */
/*! @} */

420
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_jrxa_des.h Executable file
View File

@@ -0,0 +1,420 @@
/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:25 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_JRXA_DES_H__
#define __ADI_AD9081_BF_JRXA_DES_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_MASTER_PD_ADDR 0x00000400
#define BF_PD_MASTER_RC_INFO 0x00000100
#define BF_PD_MASTER_RC(val) (val & 0x00000001)
#define BF_PD_MASTER_RC_GET(val) (val & 0x00000001)
#define REG_PHY_PD_ADDR 0x00000401
#define BF_PD_DES_RC_CH_INFO 0x00000800
#define BF_PD_DES_RC_CH(val) (val & 0x000000FF)
#define BF_PD_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_GENERIC_PD_ADDR 0x00000402
#define BF_PD_SYNCB_RC_INFO 0x00000100
#define BF_PD_SYNCB_RC(val) (val & 0x00000001)
#define BF_PD_SYNCB_RC_GET(val) (val & 0x00000001)
#define BF_PD_SYNCA_RC_INFO 0x00000101
#define BF_PD_SYNCA_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_PD_SYNCA_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_CENTRAL_BIAS_ADDR 0x00000403
#define BF_PD_CENTRAL_BIASDIST_DES_RC_INFO 0x00000100
#define BF_PD_CENTRAL_BIASDIST_DES_RC(val) (val & 0x00000001)
#define BF_PD_CENTRAL_BIASDIST_DES_RC_GET(val) (val & 0x00000001)
#define BF_SEL_CENTRAL_BIASDIST_BG_DES_RC_INFO 0x00000101
#define BF_SEL_CENTRAL_BIASDIST_BG_DES_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_SEL_CENTRAL_BIASDIST_BG_DES_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_PDB_BIAS_DES_VDD1P0_INFO 0x00000102
#define BF_PDB_BIAS_DES_VDD1P0(val) ((val & 0x00000001) << 0x00000002)
#define BF_PDB_BIAS_DES_VDD1P0_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_TRIM_CENTRAL_BIASDIST_DES_RC_INFO 0x00000204
#define BF_TRIM_CENTRAL_BIASDIST_DES_RC(val) ((val & 0x00000003) << 0x00000004)
#define BF_TRIM_CENTRAL_BIASDIST_DES_RC_GET(val) ((val >> 0x00000004) & 0x00000003)
#define REG_CDR_RESET_ADDR 0x00000405
#define BF_RSTB_DES_RC_INFO 0x00000100
#define BF_RSTB_DES_RC(val) (val & 0x00000001)
#define BF_RSTB_DES_RC_GET(val) (val & 0x00000001)
#define REG_CBUS_ADDR_JRX_ADDR 0x00000406
#define BF_CBUS_ADDR_DES_RC_INFO 0x00000800
#define BF_CBUS_ADDR_DES_RC(val) (val & 0x000000FF)
#define BF_CBUS_ADDR_DES_RC_GET(val) (val & 0x000000FF)
#define REG_CBUS_WRSTROBE_PHY_ADDR 0x00000407
#define BF_CBUS_WSTROBE_DES_RC_CH_INFO 0x00000800
#define BF_CBUS_WSTROBE_DES_RC_CH(val) (val & 0x000000FF)
#define BF_CBUS_WSTROBE_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_CBUS_WDATA_JRX_ADDR 0x00000408
#define BF_CBUS_WDATA_DES_RC_INFO 0x00000800
#define BF_CBUS_WDATA_DES_RC(val) (val & 0x000000FF)
#define BF_CBUS_WDATA_DES_RC_GET(val) (val & 0x000000FF)
#define REG_CBUS_REN_PHY_ADDR 0x00000409
#define BF_CBUS_REN_DES_RC_CH_INFO 0x00000800
#define BF_CBUS_REN_DES_RC_CH(val) (val & 0x000000FF)
#define BF_CBUS_REN_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_CBUS_RDATA_JRX_ADDR 0x0000040A
#define BF_CBUS_RDATA_DES_RS_INFO 0x00000800
#define BF_CBUS_RDATA_DES_RS(val) (val & 0x000000FF)
#define BF_CBUS_RDATA_DES_RS_GET(val) (val & 0x000000FF)
#define REG_EYEM_EN_ADDR 0x0000040B
#define BF_EN_EYEM_DES_RC_CH_INFO 0x00000800
#define BF_EN_EYEM_DES_RC_CH(val) (val & 0x000000FF)
#define BF_EN_EYEM_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_EYEM_FSM_ADDR 0x0000040C
#define BF_EN_EYEM_FSM_DES_RC_CH_INFO 0x00000800
#define BF_EN_EYEM_FSM_DES_RC_CH(val) (val & 0x000000FF)
#define BF_EN_EYEM_FSM_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_EYEM_CLEAR_ADDR 0x0000040D
#define BF_EYEM_CLEAR_EYEMON_REGS_DES_RC_CH_INFO 0x00000800
#define BF_EYEM_CLEAR_EYEMON_REGS_DES_RC_CH(val) (val & 0x000000FF)
#define BF_EYEM_CLEAR_EYEMON_REGS_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_EYEM_MODE_CH0_1_ADDR 0x0000040E
#define BF_SEL_EYEM_MODE_DES_RC_CH0_INFO 0x00000300
#define BF_SEL_EYEM_MODE_DES_RC_CH0(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH0_GET(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH1_INFO 0x00000304
#define BF_SEL_EYEM_MODE_DES_RC_CH1(val) ((val & 0x00000007) << 0x00000004)
#define BF_SEL_EYEM_MODE_DES_RC_CH1_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_EYEM_MODE_CH2_3_ADDR 0x0000040F
#define BF_SEL_EYEM_MODE_DES_RC_CH2_INFO 0x00000300
#define BF_SEL_EYEM_MODE_DES_RC_CH2(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH2_GET(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH3_INFO 0x00000304
#define BF_SEL_EYEM_MODE_DES_RC_CH3(val) ((val & 0x00000007) << 0x00000004)
#define BF_SEL_EYEM_MODE_DES_RC_CH3_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_EYEM_MODE_CH4_5_ADDR 0x00000410
#define BF_SEL_EYEM_MODE_DES_RC_CH4_INFO 0x00000300
#define BF_SEL_EYEM_MODE_DES_RC_CH4(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH4_GET(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH5_INFO 0x00000304
#define BF_SEL_EYEM_MODE_DES_RC_CH5(val) ((val & 0x00000007) << 0x00000004)
#define BF_SEL_EYEM_MODE_DES_RC_CH5_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_EYEM_MODE_CH6_7_ADDR 0x00000411
#define BF_SEL_EYEM_MODE_DES_RC_CH6_INFO 0x00000300
#define BF_SEL_EYEM_MODE_DES_RC_CH6(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH6_GET(val) (val & 0x00000007)
#define BF_SEL_EYEM_MODE_DES_RC_CH7_INFO 0x00000304
#define BF_SEL_EYEM_MODE_DES_RC_CH7(val) ((val & 0x00000007) << 0x00000004)
#define BF_SEL_EYEM_MODE_DES_RC_CH7_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_EYEM_STARTMEAS_ADDR 0x00000413
#define BF_SEL_EYEM_STARTMEAS_DES_RC_CH_INFO 0x00000800
#define BF_SEL_EYEM_STARTMEAS_DES_RC_CH(val) (val & 0x000000FF)
#define BF_SEL_EYEM_STARTMEAS_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_EYEM_EQSWEEP_DONE_ADDR 0x00000414
#define BF_EYEM_EQSWEEPDONE_DES_RS_CH_INFO 0x00000800
#define BF_EYEM_EQSWEEPDONE_DES_RS_CH(val) (val & 0x000000FF)
#define BF_EYEM_EQSWEEPDONE_DES_RS_CH_GET(val) (val & 0x000000FF)
#define REG_EYEM_HORZ_ALARM_ADDR 0x00000415
#define BF_EYEM_HORZEYEALARM_DES_RS_CH_INFO 0x00000800
#define BF_EYEM_HORZEYEALARM_DES_RS_CH(val) (val & 0x000000FF)
#define BF_EYEM_HORZEYEALARM_DES_RS_CH_GET(val) (val & 0x000000FF)
#define REG_EYEM_HORZ_DONE_ADDR 0x00000416
#define BF_EYEM_HORZEYEDONE_DES_RS_CH_INFO 0x00000800
#define BF_EYEM_HORZEYEDONE_DES_RS_CH(val) (val & 0x000000FF)
#define BF_EYEM_HORZEYEDONE_DES_RS_CH_GET(val) (val & 0x000000FF)
#define REG_CDR_OPERATING_MODE_REG_2_ADDR 0x00000417
#define BF_SEL_LF_PARCKEDGE_DES_RC_CH_INFO 0x00000800
#define BF_SEL_LF_PARCKEDGE_DES_RC_CH(val) (val & 0x000000FF)
#define BF_SEL_LF_PARCKEDGE_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_CDR_BITINVERSE_ADDR 0x00000419
#define BF_SEL_LF_PARDATAINV_DES_RC_CH_INFO 0x00000800
#define BF_SEL_LF_PARDATAINV_DES_RC_CH(val) (val & 0x000000FF)
#define BF_SEL_LF_PARDATAINV_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_EQ_BOOST_PHY_3_0_ADDR 0x0000041B
#define BF_SEL_EQ_PEQ_DES_RC_CH0_INFO 0x00000200
#define BF_SEL_EQ_PEQ_DES_RC_CH0(val) (val & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH0_GET(val) (val & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH1_INFO 0x00000202
#define BF_SEL_EQ_PEQ_DES_RC_CH1(val) ((val & 0x00000003) << 0x00000002)
#define BF_SEL_EQ_PEQ_DES_RC_CH1_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH2_INFO 0x00000204
#define BF_SEL_EQ_PEQ_DES_RC_CH2(val) ((val & 0x00000003) << 0x00000004)
#define BF_SEL_EQ_PEQ_DES_RC_CH2_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH3_INFO 0x00000206
#define BF_SEL_EQ_PEQ_DES_RC_CH3(val) ((val & 0x00000003) << 0x00000006)
#define BF_SEL_EQ_PEQ_DES_RC_CH3_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_EQ_BOOST_PHY_7_4_ADDR 0x0000041C
#define BF_SEL_EQ_PEQ_DES_RC_CH4_INFO 0x00000200
#define BF_SEL_EQ_PEQ_DES_RC_CH4(val) (val & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH4_GET(val) (val & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH5_INFO 0x00000202
#define BF_SEL_EQ_PEQ_DES_RC_CH5(val) ((val & 0x00000003) << 0x00000002)
#define BF_SEL_EQ_PEQ_DES_RC_CH5_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH6_INFO 0x00000204
#define BF_SEL_EQ_PEQ_DES_RC_CH6(val) ((val & 0x00000003) << 0x00000004)
#define BF_SEL_EQ_PEQ_DES_RC_CH6_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_SEL_EQ_PEQ_DES_RC_CH7_INFO 0x00000206
#define BF_SEL_EQ_PEQ_DES_RC_CH7(val) ((val & 0x00000003) << 0x00000006)
#define BF_SEL_EQ_PEQ_DES_RC_CH7_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_EQ_GAIN_PHY_3_0_ADDR 0x0000041D
#define BF_SEL_EQ_GAIN_DES_RC_CH0_INFO 0x00000200
#define BF_SEL_EQ_GAIN_DES_RC_CH0(val) (val & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH0_GET(val) (val & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH1_INFO 0x00000202
#define BF_SEL_EQ_GAIN_DES_RC_CH1(val) ((val & 0x00000003) << 0x00000002)
#define BF_SEL_EQ_GAIN_DES_RC_CH1_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH2_INFO 0x00000204
#define BF_SEL_EQ_GAIN_DES_RC_CH2(val) ((val & 0x00000003) << 0x00000004)
#define BF_SEL_EQ_GAIN_DES_RC_CH2_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH3_INFO 0x00000206
#define BF_SEL_EQ_GAIN_DES_RC_CH3(val) ((val & 0x00000003) << 0x00000006)
#define BF_SEL_EQ_GAIN_DES_RC_CH3_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_EQ_GAIN_PHY_7_4_ADDR 0x0000041E
#define BF_SEL_EQ_GAIN_DES_RC_CH4_INFO 0x00000200
#define BF_SEL_EQ_GAIN_DES_RC_CH4(val) (val & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH4_GET(val) (val & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH5_INFO 0x00000202
#define BF_SEL_EQ_GAIN_DES_RC_CH5(val) ((val & 0x00000003) << 0x00000002)
#define BF_SEL_EQ_GAIN_DES_RC_CH5_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH6_INFO 0x00000204
#define BF_SEL_EQ_GAIN_DES_RC_CH6(val) ((val & 0x00000003) << 0x00000004)
#define BF_SEL_EQ_GAIN_DES_RC_CH6_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_SEL_EQ_GAIN_DES_RC_CH7_INFO 0x00000206
#define BF_SEL_EQ_GAIN_DES_RC_CH7(val) ((val & 0x00000003) << 0x00000006)
#define BF_SEL_EQ_GAIN_DES_RC_CH7_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_EQ_FB_PHY_0_ADDR 0x0000041F
#define BF_SEL_EQ_FB_DES_RC_CH0_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH0(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH0_GET(val) (val & 0x0000001F)
#define REG_EQ_FB_PHY_1_ADDR 0x00000420
#define BF_SEL_EQ_FB_DES_RC_CH1_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH1(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH1_GET(val) (val & 0x0000001F)
#define REG_EQ_FB_PHY_2_ADDR 0x00000421
#define BF_SEL_EQ_FB_DES_RC_CH2_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH2(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH2_GET(val) (val & 0x0000001F)
#define REG_EQ_FB_PHY_3_ADDR 0x00000422
#define BF_SEL_EQ_FB_DES_RC_CH3_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH3(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH3_GET(val) (val & 0x0000001F)
#define REG_EQ_FB_PHY_4_ADDR 0x00000423
#define BF_SEL_EQ_FB_DES_RC_CH4_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH4(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH4_GET(val) (val & 0x0000001F)
#define REG_EQ_FB_PHY_5_ADDR 0x00000424
#define BF_SEL_EQ_FB_DES_RC_CH5_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH5(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH5_GET(val) (val & 0x0000001F)
#define REG_EQ_FB_PHY_6_ADDR 0x00000425
#define BF_SEL_EQ_FB_DES_RC_CH6_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH6(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH6_GET(val) (val & 0x0000001F)
#define REG_EQ_FB_PHY_7_ADDR 0x00000426
#define BF_SEL_EQ_FB_DES_RC_CH7_INFO 0x00000500
#define BF_SEL_EQ_FB_DES_RC_CH7(val) (val & 0x0000001F)
#define BF_SEL_EQ_FB_DES_RC_CH7_GET(val) (val & 0x0000001F)
#define REG_LBT_REG_CNTRL_1_ADDR 0x00000428
#define BF_EN_LBT_HALFRATE_DES_RC_INFO 0x00000101
#define BF_EN_LBT_HALFRATE_DES_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_EN_LBT_HALFRATE_DES_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_SYNCA_ADDR 0x00000429
#define BF_SEL_SYNCA_MODE_RC_INFO 0x00000100
#define BF_SEL_SYNCA_MODE_RC(val) (val & 0x00000001)
#define BF_SEL_SYNCA_MODE_RC_GET(val) (val & 0x00000001)
#define REG_SYNCB_ADDR 0x0000042A
#define BF_SEL_SYNCB_MODE_RC_INFO 0x00000100
#define BF_SEL_SYNCB_MODE_RC(val) (val & 0x00000001)
#define BF_SEL_SYNCB_MODE_RC_GET(val) (val & 0x00000001)
#define REG_PHFWD_EN_ADDR 0x0000042B
#define BF_EN_PHFWD_DES_RC_CH_INFO 0x00000800
#define BF_EN_PHFWD_DES_RC_CH(val) (val & 0x000000FF)
#define BF_EN_PHFWD_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_PHFWD_MASTERMODE_ADDR 0x0000042C
#define BF_EN_PHFWD_MASTERMODE_DES_RC_CH_INFO 0x00000800
#define BF_EN_PHFWD_MASTERMODE_DES_RC_CH(val) (val & 0x000000FF)
#define BF_EN_PHFWD_MASTERMODE_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_PHFWD_R_PHY_0_3_ADDR 0x00000431
#define BF_EN_PHFWD_R_DES_RC_CH0_INFO 0x00000200
#define BF_EN_PHFWD_R_DES_RC_CH0(val) (val & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH0_GET(val) (val & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH1_INFO 0x00000202
#define BF_EN_PHFWD_R_DES_RC_CH1(val) ((val & 0x00000003) << 0x00000002)
#define BF_EN_PHFWD_R_DES_RC_CH1_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH2_INFO 0x00000204
#define BF_EN_PHFWD_R_DES_RC_CH2(val) ((val & 0x00000003) << 0x00000004)
#define BF_EN_PHFWD_R_DES_RC_CH2_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH3_INFO 0x00000206
#define BF_EN_PHFWD_R_DES_RC_CH3(val) ((val & 0x00000003) << 0x00000006)
#define BF_EN_PHFWD_R_DES_RC_CH3_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_PHFWD_R_PHY_4_7_ADDR 0x00000432
#define BF_EN_PHFWD_R_DES_RC_CH4_INFO 0x00000200
#define BF_EN_PHFWD_R_DES_RC_CH4(val) (val & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH4_GET(val) (val & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH5_INFO 0x00000202
#define BF_EN_PHFWD_R_DES_RC_CH5(val) ((val & 0x00000003) << 0x00000002)
#define BF_EN_PHFWD_R_DES_RC_CH5_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH6_INFO 0x00000204
#define BF_EN_PHFWD_R_DES_RC_CH6(val) ((val & 0x00000003) << 0x00000004)
#define BF_EN_PHFWD_R_DES_RC_CH6_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_EN_PHFWD_R_DES_RC_CH7_INFO 0x00000206
#define BF_EN_PHFWD_R_DES_RC_CH7(val) ((val & 0x00000003) << 0x00000006)
#define BF_EN_PHFWD_R_DES_RC_CH7_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_PHFWD_L_PHY_0_3_ADDR 0x00000433
#define BF_EN_PHFWD_L_DES_RC_CH0_INFO 0x00000200
#define BF_EN_PHFWD_L_DES_RC_CH0(val) (val & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH0_GET(val) (val & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH1_INFO 0x00000202
#define BF_EN_PHFWD_L_DES_RC_CH1(val) ((val & 0x00000003) << 0x00000002)
#define BF_EN_PHFWD_L_DES_RC_CH1_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH2_INFO 0x00000204
#define BF_EN_PHFWD_L_DES_RC_CH2(val) ((val & 0x00000003) << 0x00000004)
#define BF_EN_PHFWD_L_DES_RC_CH2_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH3_INFO 0x00000206
#define BF_EN_PHFWD_L_DES_RC_CH3(val) ((val & 0x00000003) << 0x00000006)
#define BF_EN_PHFWD_L_DES_RC_CH3_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_PHFWD_L_PHY_4_7_ADDR 0x00000434
#define BF_EN_PHFWD_L_DES_RC_CH4_INFO 0x00000200
#define BF_EN_PHFWD_L_DES_RC_CH4(val) (val & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH4_GET(val) (val & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH5_INFO 0x00000202
#define BF_EN_PHFWD_L_DES_RC_CH5(val) ((val & 0x00000003) << 0x00000002)
#define BF_EN_PHFWD_L_DES_RC_CH5_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH6_INFO 0x00000204
#define BF_EN_PHFWD_L_DES_RC_CH6(val) ((val & 0x00000003) << 0x00000004)
#define BF_EN_PHFWD_L_DES_RC_CH6_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_EN_PHFWD_L_DES_RC_CH7_INFO 0x00000206
#define BF_EN_PHFWD_L_DES_RC_CH7(val) ((val & 0x00000003) << 0x00000006)
#define BF_EN_PHFWD_L_DES_RC_CH7_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_PHFWD_INITERRFLAG_RB_ADDR 0x00000435
#define BF_PHFWD_INITERRFLAG_DES_RS_CH_INFO 0x00000800
#define BF_PHFWD_INITERRFLAG_DES_RS_CH(val) (val & 0x000000FF)
#define BF_PHFWD_INITERRFLAG_DES_RS_CH_GET(val) (val & 0x000000FF)
#define REG_PHFWD_INITERRFLAG_STICKY_ADDR 0x00000436
#define BF_PHFWD_INITERRFLAG_STICKY_DES_RS_CH_INFO 0x00000800
#define BF_PHFWD_INITERRFLAG_STICKY_DES_RS_CH(val) (val & 0x000000FF)
#define BF_PHFWD_INITERRFLAG_STICKY_DES_RS_CH_GET(val) (val & 0x000000FF)
#define REG_PHFWD_CLR_INITERRFLAG_STICKY_ADDR 0x00000437
#define BF_CLR_PHFWD_INITERRFLAGSTICKY_DES_RC_CH_INFO 0x00000800
#define BF_CLR_PHFWD_INITERRFLAGSTICKY_DES_RC_CH(val) (val & 0x000000FF)
#define BF_CLR_PHFWD_INITERRFLAGSTICKY_DES_RC_CH_GET(val) (val & 0x000000FF)
#define REG_DATA_PN_SWAP_ADDR 0x00000440
#define BF_DATA_PN_SWAP_CORR_DES_RC_INFO 0x00000800
#define BF_DATA_PN_SWAP_CORR_DES_RC(val) (val & 0x000000FF)
#define BF_DATA_PN_SWAP_CORR_DES_RC_GET(val) (val & 0x000000FF)
#define REG_TERM_FLOAT_ADDR 0x00000446
#define BF_EN_TERM_FLOATVTT_DES_RC_INFO 0x00000100
#define BF_EN_TERM_FLOATVTT_DES_RC(val) (val & 0x00000001)
#define BF_EN_TERM_FLOATVTT_DES_RC_GET(val) (val & 0x00000001)
#define REG_TERMCAL_0_ADDR 0x00000447
#define BF_EN_TERMCAL_RHOFSM_DES_RC_INFO 0x00000100
#define BF_EN_TERMCAL_RHOFSM_DES_RC(val) (val & 0x00000001)
#define BF_EN_TERMCAL_RHOFSM_DES_RC_GET(val) (val & 0x00000001)
#define BF_EN_TERMCAL_RHOBYPASS_DES_RC_INFO 0x00000102
#define BF_EN_TERMCAL_RHOBYPASS_DES_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_EN_TERMCAL_RHOBYPASS_DES_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_CK_TERMCAL_RHOBYPASS_DES_RC_INFO 0x00000103
#define BF_CK_TERMCAL_RHOBYPASS_DES_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_CK_TERMCAL_RHOBYPASS_DES_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_TRIM_TERMCAL_RHOBYPASSVAL_DES_RC_INFO 0x00000404
#define BF_TRIM_TERMCAL_RHOBYPASSVAL_DES_RC(val) ((val & 0x0000000F) << 0x00000004)
#define BF_TRIM_TERMCAL_RHOBYPASSVAL_DES_RC_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_TERMCAL_1_ADDR 0x00000448
#define BF_TRIM_TERMCAL_RHO_DES_RS_INFO 0x00000400
#define BF_TRIM_TERMCAL_RHO_DES_RS(val) (val & 0x0000000F)
#define BF_TRIM_TERMCAL_RHO_DES_RS_GET(val) (val & 0x0000000F)
#define BF_TRIM_TERMCAL_CMPOUT_DES_RS_INFO 0x00000104
#define BF_TRIM_TERMCAL_CMPOUT_DES_RS(val) ((val & 0x00000001) << 0x00000004)
#define BF_TRIM_TERMCAL_CMPOUT_DES_RS_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_LF_PARDATAMODE_DES_RC0_ADDR 0x00000457
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH0_INFO 0x00000200
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH0(val) (val & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH0_GET(val) (val & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH1_INFO 0x00000202
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH1(val) ((val & 0x00000003) << 0x00000002)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH1_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH2_INFO 0x00000204
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH2(val) ((val & 0x00000003) << 0x00000004)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH2_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH3_INFO 0x00000206
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH3(val) ((val & 0x00000003) << 0x00000006)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH3_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_LF_PARDATAMODE_DES_RC1_ADDR 0x00000458
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH4_INFO 0x00000200
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH4(val) (val & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH4_GET(val) (val & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH5_INFO 0x00000202
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH5(val) ((val & 0x00000003) << 0x00000002)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH5_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH6_INFO 0x00000204
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH6(val) ((val & 0x00000003) << 0x00000004)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH6_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH7_INFO 0x00000206
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH7(val) ((val & 0x00000003) << 0x00000006)
#define BF_SEL_LF_PARDATAMODE_DES_RC_CH7_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_LF_QUARTERRATE_DES_RC_ADDR 0x00000459
#define BF_SEL_LF_QUARTERRATE_DES_RC_INFO 0x00000800
#define BF_SEL_LF_QUARTERRATE_DES_RC(val) (val & 0x000000FF)
#define BF_SEL_LF_QUARTERRATE_DES_RC_GET(val) (val & 0x000000FF)
#endif /* __ADI_AD9081_BF_JRXA_DES_H__ */
/*! @} */

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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_jtx_dual_link.h Executable file
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/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:25 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_JTX_DUAL_LINK_H__
#define __ADI_AD9081_BF_JTX_DUAL_LINK_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_JTX_CORE_0_CONV15_ADDR 0x0000060F
#define BF_JTX_CONV_SEL_0_INFO 0x00000700
#define BF_JTX_CONV_SEL_0(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_0_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_0_INFO 0x00000107
#define BF_JTX_CONV_MASK_0(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_0_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV14_ADDR 0x0000060E
#define BF_JTX_CONV_SEL_1_INFO 0x00000700
#define BF_JTX_CONV_SEL_1(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_1_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_1_INFO 0x00000107
#define BF_JTX_CONV_MASK_1(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_1_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV13_ADDR 0x0000060D
#define BF_JTX_CONV_SEL_2_INFO 0x00000700
#define BF_JTX_CONV_SEL_2(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_2_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_2_INFO 0x00000107
#define BF_JTX_CONV_MASK_2(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_2_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV12_ADDR 0x0000060C
#define BF_JTX_CONV_SEL_3_INFO 0x00000700
#define BF_JTX_CONV_SEL_3(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_3_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_3_INFO 0x00000107
#define BF_JTX_CONV_MASK_3(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_3_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV11_ADDR 0x0000060B
#define BF_JTX_CONV_SEL_4_INFO 0x00000700
#define BF_JTX_CONV_SEL_4(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_4_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_4_INFO 0x00000107
#define BF_JTX_CONV_MASK_4(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_4_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV10_ADDR 0x0000060A
#define BF_JTX_CONV_SEL_5_INFO 0x00000700
#define BF_JTX_CONV_SEL_5(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_5_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_5_INFO 0x00000107
#define BF_JTX_CONV_MASK_5(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_5_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV9_ADDR 0x00000609
#define BF_JTX_CONV_SEL_6_INFO 0x00000700
#define BF_JTX_CONV_SEL_6(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_6_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_6_INFO 0x00000107
#define BF_JTX_CONV_MASK_6(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_6_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV8_ADDR 0x00000608
#define BF_JTX_CONV_SEL_7_INFO 0x00000700
#define BF_JTX_CONV_SEL_7(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_7_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_7_INFO 0x00000107
#define BF_JTX_CONV_MASK_7(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_7_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV7_ADDR 0x00000607
#define BF_JTX_CONV_SEL_8_INFO 0x00000700
#define BF_JTX_CONV_SEL_8(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_8_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_8_INFO 0x00000107
#define BF_JTX_CONV_MASK_8(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_8_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV6_ADDR 0x00000606
#define BF_JTX_CONV_SEL_9_INFO 0x00000700
#define BF_JTX_CONV_SEL_9(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_9_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_9_INFO 0x00000107
#define BF_JTX_CONV_MASK_9(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_9_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV5_ADDR 0x00000605
#define BF_JTX_CONV_SEL_10_INFO 0x00000700
#define BF_JTX_CONV_SEL_10(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_10_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_10_INFO 0x00000107
#define BF_JTX_CONV_MASK_10(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_10_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV4_ADDR 0x00000604
#define BF_JTX_CONV_SEL_11_INFO 0x00000700
#define BF_JTX_CONV_SEL_11(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_11_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_11_INFO 0x00000107
#define BF_JTX_CONV_MASK_11(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_11_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV3_ADDR 0x00000603
#define BF_JTX_CONV_SEL_12_INFO 0x00000700
#define BF_JTX_CONV_SEL_12(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_12_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_12_INFO 0x00000107
#define BF_JTX_CONV_MASK_12(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_12_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV2_ADDR 0x00000602
#define BF_JTX_CONV_SEL_13_INFO 0x00000700
#define BF_JTX_CONV_SEL_13(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_13_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_13_INFO 0x00000107
#define BF_JTX_CONV_MASK_13(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_13_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV1_ADDR 0x00000601
#define BF_JTX_CONV_SEL_14_INFO 0x00000700
#define BF_JTX_CONV_SEL_14(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_14_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_14_INFO 0x00000107
#define BF_JTX_CONV_MASK_14(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_14_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_0_CONV0_ADDR 0x00000600
#define BF_JTX_CONV_SEL_15_INFO 0x00000700
#define BF_JTX_CONV_SEL_15(val) (val & 0x0000007F)
#define BF_JTX_CONV_SEL_15_GET(val) (val & 0x0000007F)
#define BF_JTX_CONV_MASK_15_INFO 0x00000107
#define BF_JTX_CONV_MASK_15(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_CONV_MASK_15_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_1_ADDR 0x00000611
#define BF_JTX_CHKSUM_LSB_ALG_INFO 0x00000100
#define BF_JTX_CHKSUM_LSB_ALG(val) (val & 0x00000001)
#define BF_JTX_CHKSUM_LSB_ALG_GET(val) (val & 0x00000001)
#define BF_JTX_CHKSUM_DISABLE_INFO 0x00000101
#define BF_JTX_CHKSUM_DISABLE(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_CHKSUM_DISABLE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_LINK_204C_SEL_INFO 0x00000204
#define BF_JTX_LINK_204C_SEL(val) ((val & 0x00000003) << 0x00000004)
#define BF_JTX_LINK_204C_SEL_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_JTX_SYSREF_FOR_STARTUP_INFO 0x00000106
#define BF_JTX_SYSREF_FOR_STARTUP(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_SYSREF_FOR_STARTUP_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_SYSREF_FOR_RELINK_INFO 0x00000107
#define BF_JTX_SYSREF_FOR_RELINK(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_SYSREF_FOR_RELINK_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE7_ADDR 0x00000622
#define BF_JTX_LANE_ASSIGN_0_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_0(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_0_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_0_INFO 0x00000105
#define BF_JTX_LANE_INV_0(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_0_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_0_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_0(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_0_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_0_INFO 0x00000107
#define BF_JTX_LANE_PD_0(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_0_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE6_ADDR 0x00000621
#define BF_JTX_LANE_ASSIGN_1_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_1(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_1_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_1_INFO 0x00000105
#define BF_JTX_LANE_INV_1(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_1_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_1_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_1(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_1_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_1_INFO 0x00000107
#define BF_JTX_LANE_PD_1(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_1_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE5_ADDR 0x00000620
#define BF_JTX_LANE_ASSIGN_2_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_2(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_2_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_2_INFO 0x00000105
#define BF_JTX_LANE_INV_2(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_2_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_2_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_2(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_2_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_2_INFO 0x00000107
#define BF_JTX_LANE_PD_2(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_2_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE4_ADDR 0x0000061F
#define BF_JTX_LANE_ASSIGN_3_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_3(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_3_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_3_INFO 0x00000105
#define BF_JTX_LANE_INV_3(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_3_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_3_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_3(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_3_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_3_INFO 0x00000107
#define BF_JTX_LANE_PD_3(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_3_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE3_ADDR 0x0000061E
#define BF_JTX_LANE_ASSIGN_4_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_4(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_4_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_4_INFO 0x00000105
#define BF_JTX_LANE_INV_4(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_4_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_4_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_4(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_4_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_4_INFO 0x00000107
#define BF_JTX_LANE_PD_4(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_4_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE2_ADDR 0x0000061D
#define BF_JTX_LANE_ASSIGN_5_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_5(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_5_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_5_INFO 0x00000105
#define BF_JTX_LANE_INV_5(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_5_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_5_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_5(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_5_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_5_INFO 0x00000107
#define BF_JTX_LANE_PD_5(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_5_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE1_ADDR 0x0000061C
#define BF_JTX_LANE_ASSIGN_6_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_6(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_6_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_6_INFO 0x00000105
#define BF_JTX_LANE_INV_6(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_6_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_6_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_6(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_6_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_6_INFO 0x00000107
#define BF_JTX_LANE_PD_6(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_6_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_2_LANE0_ADDR 0x0000061B
#define BF_JTX_LANE_ASSIGN_7_INFO 0x00000500
#define BF_JTX_LANE_ASSIGN_7(val) (val & 0x0000001F)
#define BF_JTX_LANE_ASSIGN_7_GET(val) (val & 0x0000001F)
#define BF_JTX_LANE_INV_7_INFO 0x00000105
#define BF_JTX_LANE_INV_7(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_LANE_INV_7_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_FORCE_LANE_PD_7_INFO 0x00000106
#define BF_JTX_FORCE_LANE_PD_7(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_FORCE_LANE_PD_7_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_LANE_PD_7_INFO 0x00000107
#define BF_JTX_LANE_PD_7(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_LANE_PD_7_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_3_ADDR 0x00000624
#define BF_JTX_TEST_GEN_MODE_INFO 0x00000400
#define BF_JTX_TEST_GEN_MODE(val) (val & 0x0000000F)
#define BF_JTX_TEST_GEN_MODE_GET(val) (val & 0x0000000F)
#define BF_JTX_TEST_GEN_SEL_INFO 0x00000204
#define BF_JTX_TEST_GEN_SEL(val) ((val & 0x00000003) << 0x00000004)
#define BF_JTX_TEST_GEN_SEL_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_JTX_TEST_MIRROR_INFO 0x00000106
#define BF_JTX_TEST_MIRROR(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_TEST_MIRROR_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_TEST_USER_GO_INFO 0x00000107
#define BF_JTX_TEST_USER_GO(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_TEST_USER_GO_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_CORE_4_ADDR 0x00000625
#define REG_JTX_CORE_5_ADDR 0x00000626
#define REG_JTX_CORE_6_ADDR 0x00000627
#define REG_JTX_CORE_7_ADDR 0x00000628
#define REG_JTX_CORE_8_ADDR 0x00000629
#define REG_JTX_CORE_9_ADDR 0x0000062A
#define REG_JTX_CORE_10_ADDR 0x0000062B
#define REG_JTX_CORE_11_ADDR 0x0000062C
#define REG_JTX_CORE_12_ADDR 0x0000062D
#define BF_JTX_SYNC_N_SEL_INFO 0x00000305
#define BF_JTX_SYNC_N_SEL(val) ((val & 0x00000007) << 0x00000005)
#define BF_JTX_SYNC_N_SEL_GET(val) ((val >> 0x00000005) & 0x00000007)
#define REG_JTX_CORE_13_ADDR 0x0000062E
#define BF_JTX_LINK_EN_INFO 0x00000100
#define BF_JTX_LINK_EN(val) (val & 0x00000001)
#define BF_JTX_LINK_EN_GET(val) (val & 0x00000001)
#define REG_JTX_TPL_0_ADDR 0x00000630
#define BF_JTX_TPL_ADAPTIVE_LATENCY_INFO 0x00000100
#define BF_JTX_TPL_ADAPTIVE_LATENCY(val) (val & 0x00000001)
#define BF_JTX_TPL_ADAPTIVE_LATENCY_GET(val) (val & 0x00000001)
#define BF_JTX_TPL_TEST_ENABLE_INFO 0x00000101
#define BF_JTX_TPL_TEST_ENABLE(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_TPL_TEST_ENABLE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_CONV_ASYNCHRONOUS_INFO 0x00000102
#define BF_JTX_CONV_ASYNCHRONOUS(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_CONV_ASYNCHRONOUS_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_NS_CFG_INFO 0x00000503
#define BF_JTX_NS_CFG(val) ((val & 0x0000001F) << 0x00000003)
#define BF_JTX_NS_CFG_GET(val) ((val >> 0x00000003) & 0x0000001F)
#define REG_JTX_TPL_1_ADDR 0x00000631
#define BF_JTX_TPL_LATENCY_ADJUST_INFO 0x00000800
#define BF_JTX_TPL_LATENCY_ADJUST(val) (val & 0x000000FF)
#define BF_JTX_TPL_LATENCY_ADJUST_GET(val) (val & 0x000000FF)
#define REG_JTX_TPL_2_ADDR 0x00000632
#define BF_JTX_TPL_PHASE_ADJUST_INFO 0x00001000
#define BF_JTX_TPL_PHASE_ADJUST(val) (val & 0x0000FFFF)
#define BF_JTX_TPL_PHASE_ADJUST_GET(val) (val & 0x0000FFFF)
#define REG_JTX_TPL_3_ADDR 0x00000633
#define REG_JTX_TPL_4_ADDR 0x00000634
#define BF_JTX_TPL_TEST_NUM_FRAMES_M1_INFO 0x00001000
#define BF_JTX_TPL_TEST_NUM_FRAMES_M1(val) (val & 0x0000FFFF)
#define BF_JTX_TPL_TEST_NUM_FRAMES_M1_GET(val) (val & 0x0000FFFF)
#define REG_JTX_TPL_5_ADDR 0x00000635
#define REG_JTX_TPL_6_ADDR 0x00000636
#define BF_JTX_TPL_INVALID_CFG_INFO 0x00000100
#define BF_JTX_TPL_INVALID_CFG(val) (val & 0x00000001)
#define BF_JTX_TPL_INVALID_CFG_GET(val) (val & 0x00000001)
#define BF_JTX_TPL_SYSREF_RCVD_INFO 0x00000101
#define BF_JTX_TPL_SYSREF_RCVD(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_TPL_SYSREF_RCVD_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_TPL_SYSREF_PHASE_ERR_INFO 0x00000102
#define BF_JTX_TPL_SYSREF_PHASE_ERR(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_TPL_SYSREF_PHASE_ERR_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_TPL_SYSREF_MASK_INFO 0x00000105
#define BF_JTX_TPL_SYSREF_MASK(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_TPL_SYSREF_MASK_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_TPL_SYSREF_CLR_PHASE_ERR_INFO 0x00000106
#define BF_JTX_TPL_SYSREF_CLR_PHASE_ERR(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_TPL_SYSREF_CLR_PHASE_ERR_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_TPL_SYSREF_IGNORE_WHEN_LINKED_INFO 0x00000107
#define BF_JTX_TPL_SYSREF_IGNORE_WHEN_LINKED(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_TPL_SYSREF_IGNORE_WHEN_LINKED_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_TPL_7_ADDR 0x00000637
#define BF_JTX_TPL_SYSREF_N_SHOT_COUNT_INFO 0x00000400
#define BF_JTX_TPL_SYSREF_N_SHOT_COUNT(val) (val & 0x0000000F)
#define BF_JTX_TPL_SYSREF_N_SHOT_COUNT_GET(val) (val & 0x0000000F)
#define BF_JTX_TPL_SYSREF_N_SHOT_ENABLE_INFO 0x00000104
#define BF_JTX_TPL_SYSREF_N_SHOT_ENABLE(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_TPL_SYSREF_N_SHOT_ENABLE_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_TPL_8_ADDR 0x00000638
#define BF_JTX_TPL_LATENCY_ADDED_INFO 0x00000800
#define BF_JTX_TPL_LATENCY_ADDED(val) (val & 0x000000FF)
#define BF_JTX_TPL_LATENCY_ADDED_GET(val) (val & 0x000000FF)
#define REG_JTX_TPL_9_ADDR 0x00000639
#define BF_JTX_TPL_BUF_FRAMES_INFO 0x00000800
#define BF_JTX_TPL_BUF_FRAMES(val) (val & 0x000000FF)
#define BF_JTX_TPL_BUF_FRAMES_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_0_ADDR 0x0000063A
#define BF_JTX_DID_CFG_INFO 0x00000800
#define BF_JTX_DID_CFG(val) (val & 0x000000FF)
#define BF_JTX_DID_CFG_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_1_ADDR 0x0000063B
#define BF_JTX_BID_CFG_INFO 0x00000400
#define BF_JTX_BID_CFG(val) (val & 0x0000000F)
#define BF_JTX_BID_CFG_GET(val) (val & 0x0000000F)
#define BF_JTX_ADJCNT_CFG_INFO 0x00000404
#define BF_JTX_ADJCNT_CFG(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_ADJCNT_CFG_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_L0_2_ADDR 0x0000063C
#define BF_JTX_PHADJ_CFG_INFO 0x00000105
#define BF_JTX_PHADJ_CFG(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_PHADJ_CFG_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_ADJDIR_CFG_INFO 0x00000106
#define BF_JTX_ADJDIR_CFG(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_ADJDIR_CFG_GET(val) ((val >> 0x00000006) & 0x00000001)
#define REG_JTX_L0_3_ADDR 0x0000063D
#define BF_JTX_L_CFG_INFO 0x00000500
#define BF_JTX_L_CFG(val) (val & 0x0000001F)
#define BF_JTX_L_CFG_GET(val) (val & 0x0000001F)
#define BF_JTX_SCR_CFG_INFO 0x00000107
#define BF_JTX_SCR_CFG(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_SCR_CFG_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_L0_4_ADDR 0x0000063E
#define BF_JTX_F_CFG_INFO 0x00000800
#define BF_JTX_F_CFG(val) (val & 0x000000FF)
#define BF_JTX_F_CFG_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_5_ADDR 0x0000063F
#define BF_JTX_K_CFG_INFO 0x00000800
#define BF_JTX_K_CFG(val) (val & 0x000000FF)
#define BF_JTX_K_CFG_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_6_ADDR 0x00000640
#define BF_JTX_M_CFG_INFO 0x00000800
#define BF_JTX_M_CFG(val) (val & 0x000000FF)
#define BF_JTX_M_CFG_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_7_ADDR 0x00000641
#define BF_JTX_N_CFG_INFO 0x00000500
#define BF_JTX_N_CFG(val) (val & 0x0000001F)
#define BF_JTX_N_CFG_GET(val) (val & 0x0000001F)
#define BF_JTX_CS_CFG_INFO 0x00000206
#define BF_JTX_CS_CFG(val) ((val & 0x00000003) << 0x00000006)
#define BF_JTX_CS_CFG_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_JTX_L0_8_ADDR 0x00000642
#define BF_JTX_NP_CFG_INFO 0x00000500
#define BF_JTX_NP_CFG(val) (val & 0x0000001F)
#define BF_JTX_NP_CFG_GET(val) (val & 0x0000001F)
#define BF_JTX_SUBCLASSV_CFG_INFO 0x00000305
#define BF_JTX_SUBCLASSV_CFG(val) ((val & 0x00000007) << 0x00000005)
#define BF_JTX_SUBCLASSV_CFG_GET(val) ((val >> 0x00000005) & 0x00000007)
#define REG_JTX_L0_9_ADDR 0x00000643
#define BF_JTX_S_CFG_INFO 0x00000500
#define BF_JTX_S_CFG(val) (val & 0x0000001F)
#define BF_JTX_S_CFG_GET(val) (val & 0x0000001F)
#define BF_JTX_JESDV_CFG_INFO 0x00000305
#define BF_JTX_JESDV_CFG(val) ((val & 0x00000007) << 0x00000005)
#define BF_JTX_JESDV_CFG_GET(val) ((val >> 0x00000005) & 0x00000007)
#define REG_JTX_L0_10_ADDR 0x00000644
#define BF_JTX_HD_CFG_INFO 0x00000107
#define BF_JTX_HD_CFG(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_HD_CFG_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_L0_13_LANE7_ADDR 0x0000064E
#define BF_JTX_CHKSUM_CFG_0_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_0(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_0_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_13_LANE6_ADDR 0x0000064D
#define BF_JTX_CHKSUM_CFG_1_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_1(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_1_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_13_LANE5_ADDR 0x0000064C
#define BF_JTX_CHKSUM_CFG_2_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_2(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_2_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_13_LANE4_ADDR 0x0000064B
#define BF_JTX_CHKSUM_CFG_3_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_3(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_3_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_13_LANE3_ADDR 0x0000064A
#define BF_JTX_CHKSUM_CFG_4_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_4(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_4_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_13_LANE2_ADDR 0x00000649
#define BF_JTX_CHKSUM_CFG_5_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_5(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_5_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_13_LANE1_ADDR 0x00000648
#define BF_JTX_CHKSUM_CFG_6_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_6(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_6_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_13_LANE0_ADDR 0x00000647
#define BF_JTX_CHKSUM_CFG_7_INFO 0x00000800
#define BF_JTX_CHKSUM_CFG_7(val) (val & 0x000000FF)
#define BF_JTX_CHKSUM_CFG_7_GET(val) (val & 0x000000FF)
#define REG_JTX_L0_14_LANE7_ADDR 0x00000657
#define BF_JTX_LID_CFG_0_INFO 0x00000500
#define BF_JTX_LID_CFG_0(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_0_GET(val) (val & 0x0000001F)
#define REG_JTX_L0_14_LANE6_ADDR 0x00000656
#define BF_JTX_LID_CFG_1_INFO 0x00000500
#define BF_JTX_LID_CFG_1(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_1_GET(val) (val & 0x0000001F)
#define REG_JTX_L0_14_LANE5_ADDR 0x00000655
#define BF_JTX_LID_CFG_2_INFO 0x00000500
#define BF_JTX_LID_CFG_2(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_2_GET(val) (val & 0x0000001F)
#define REG_JTX_L0_14_LANE4_ADDR 0x00000654
#define BF_JTX_LID_CFG_3_INFO 0x00000500
#define BF_JTX_LID_CFG_3(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_3_GET(val) (val & 0x0000001F)
#define REG_JTX_L0_14_LANE3_ADDR 0x00000653
#define BF_JTX_LID_CFG_4_INFO 0x00000500
#define BF_JTX_LID_CFG_4(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_4_GET(val) (val & 0x0000001F)
#define REG_JTX_L0_14_LANE2_ADDR 0x00000652
#define BF_JTX_LID_CFG_5_INFO 0x00000500
#define BF_JTX_LID_CFG_5(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_5_GET(val) (val & 0x0000001F)
#define REG_JTX_L0_14_LANE1_ADDR 0x00000651
#define BF_JTX_LID_CFG_6_INFO 0x00000500
#define BF_JTX_LID_CFG_6(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_6_GET(val) (val & 0x0000001F)
#define REG_JTX_L0_14_LANE0_ADDR 0x00000650
#define BF_JTX_LID_CFG_7_INFO 0x00000500
#define BF_JTX_LID_CFG_7(val) (val & 0x0000001F)
#define BF_JTX_LID_CFG_7_GET(val) (val & 0x0000001F)
#define REG_JTX_DL_204B_0_ADDR 0x00000659
#define BF_JTX_DL_204B_BYP_ACG_CFG_INFO 0x00000100
#define BF_JTX_DL_204B_BYP_ACG_CFG(val) (val & 0x00000001)
#define BF_JTX_DL_204B_BYP_ACG_CFG_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_BYP_8B10B_CFG_INFO 0x00000101
#define BF_JTX_DL_204B_BYP_8B10B_CFG(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_DL_204B_BYP_8B10B_CFG_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_DL_204B_ILAS_TEST_EN_CFG_INFO 0x00000102
#define BF_JTX_DL_204B_ILAS_TEST_EN_CFG(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_ILAS_TEST_EN_CFG_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_BYP_ILAS_CFG_INFO 0x00000103
#define BF_JTX_DL_204B_BYP_ILAS_CFG(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_BYP_ILAS_CFG_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_ILAS_DELAY_CFG_INFO 0x00000404
#define BF_JTX_DL_204B_ILAS_DELAY_CFG(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_DL_204B_ILAS_DELAY_CFG_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_DL_204B_1_ADDR 0x0000065A
#define BF_JTX_DL_204B_10B_MIRROR_INFO 0x00000100
#define BF_JTX_DL_204B_10B_MIRROR(val) (val & 0x00000001)
#define BF_JTX_DL_204B_10B_MIRROR_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_DEL_SCR_CFG_INFO 0x00000101
#define BF_JTX_DL_204B_DEL_SCR_CFG(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_DL_204B_DEL_SCR_CFG_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_DL_204B_LSYNC_EN_CFG_INFO 0x00000102
#define BF_JTX_DL_204B_LSYNC_EN_CFG(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_LSYNC_EN_CFG_GET(val) ((val >> 0x00000002) & 0x00000001)
#define REG_JTX_DL_204B_2_ADDR 0x0000065B
#define BF_JTX_DL_204B_KF_ILAS_CFG_INFO 0x00000800
#define BF_JTX_DL_204B_KF_ILAS_CFG(val) (val & 0x000000FF)
#define BF_JTX_DL_204B_KF_ILAS_CFG_GET(val) (val & 0x000000FF)
#define REG_JTX_DL_204B_3_ADDR 0x0000065C
#define BF_JTX_DL_204B_RJSPAT_EN_CFG_INFO 0x00000100
#define BF_JTX_DL_204B_RJSPAT_EN_CFG(val) (val & 0x00000001)
#define BF_JTX_DL_204B_RJSPAT_EN_CFG_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_RJSPAT_SEL_CFG_INFO 0x00000201
#define BF_JTX_DL_204B_RJSPAT_SEL_CFG(val) ((val & 0x00000003) << 0x00000001)
#define BF_JTX_DL_204B_RJSPAT_SEL_CFG_GET(val) ((val >> 0x00000001) & 0x00000003)
#define BF_JTX_DL_204B_TPL_TEST_EN_CFG_INFO 0x00000104
#define BF_JTX_DL_204B_TPL_TEST_EN_CFG(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_TPL_TEST_EN_CFG_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_JTX_DL_204B_SYNC_N_INFO 0x00000105
#define BF_JTX_DL_204B_SYNC_N(val) ((val & 0x00000001) << 0x00000005)
#define BF_JTX_DL_204B_SYNC_N_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_JTX_DL_204B_TESTMODE_IGNORE_SYNCN_CFG_INFO 0x00000106
#define BF_JTX_DL_204B_TESTMODE_IGNORE_SYNCN_CFG(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_DL_204B_TESTMODE_IGNORE_SYNCN_CFG_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_DL_204B_CLEAR_SYNC_NE_COUNT_INFO 0x00000107
#define BF_JTX_DL_204B_CLEAR_SYNC_NE_COUNT(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_DL_204B_CLEAR_SYNC_NE_COUNT_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_DL_204B_4_ADDR 0x0000065D
#define BF_JTX_DL_204B_STATE_INFO 0x00000400
#define BF_JTX_DL_204B_STATE(val) (val & 0x0000000F)
#define BF_JTX_DL_204B_STATE_GET(val) (val & 0x0000000F)
#define BF_JTX_DL_204B_SYNC_N_FORCE_VAL_INFO 0x00000106
#define BF_JTX_DL_204B_SYNC_N_FORCE_VAL(val) ((val & 0x00000001) << 0x00000006)
#define BF_JTX_DL_204B_SYNC_N_FORCE_VAL_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_JTX_DL_204B_SYNC_N_FORCE_EN_INFO 0x00000107
#define BF_JTX_DL_204B_SYNC_N_FORCE_EN(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_DL_204B_SYNC_N_FORCE_EN_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_DL_204B_5_ADDR 0x0000065E
#define BF_JTX_DL_204B_SYNC_NE_COUNT_INFO 0x00000800
#define BF_JTX_DL_204B_SYNC_NE_COUNT(val) (val & 0x000000FF)
#define BF_JTX_DL_204B_SYNC_NE_COUNT_GET(val) (val & 0x000000FF)
#define REG_JTX_DL_204B_6_LANE7_ADDR 0x00000666
#define BF_JTX_DL_204B_L_EN_CFG_0_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_0(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_0_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_0_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_0(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_0_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_0_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_0(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_0_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_0_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_0(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_0_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204B_6_LANE6_ADDR 0x00000665
#define BF_JTX_DL_204B_L_EN_CFG_1_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_1(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_1_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_1_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_1(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_1_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_1_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_1(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_1_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_1_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_1(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_1_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204B_6_LANE5_ADDR 0x00000664
#define BF_JTX_DL_204B_L_EN_CFG_2_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_2(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_2_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_2_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_2(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_2_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_2_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_2(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_2_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_2_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_2(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_2_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204B_6_LANE4_ADDR 0x00000663
#define BF_JTX_DL_204B_L_EN_CFG_3_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_3(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_3_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_3_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_3(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_3_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_3_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_3(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_3_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_3_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_3(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_3_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204B_6_LANE3_ADDR 0x00000662
#define BF_JTX_DL_204B_L_EN_CFG_4_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_4(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_4_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_4_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_4(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_4_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_4_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_4(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_4_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_4_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_4(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_4_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204B_6_LANE2_ADDR 0x00000661
#define BF_JTX_DL_204B_L_EN_CFG_5_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_5(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_5_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_5_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_5(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_5_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_5_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_5(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_5_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_5_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_5(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_5_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204B_6_LANE1_ADDR 0x00000660
#define BF_JTX_DL_204B_L_EN_CFG_6_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_6(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_6_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_6_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_6(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_6_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_6_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_6(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_6_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_6_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_6(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_6_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204B_6_LANE0_ADDR 0x0000065F
#define BF_JTX_DL_204B_L_EN_CFG_7_INFO 0x00000100
#define BF_JTX_DL_204B_L_EN_CFG_7(val) (val & 0x00000001)
#define BF_JTX_DL_204B_L_EN_CFG_7_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_7_INFO 0x00000102
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_7(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_7_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_7_INFO 0x00000103
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_7(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_7_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_7_INFO 0x00000104
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_7(val) ((val & 0x00000001) << 0x00000004)
#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_7_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_JTX_DL_204C_0_ADDR 0x00000667
#define BF_JTX_CRC_FEC_REVERSE_CFG_INFO 0x00000100
#define BF_JTX_CRC_FEC_REVERSE_CFG(val) (val & 0x00000001)
#define BF_JTX_CRC_FEC_REVERSE_CFG_GET(val) (val & 0x00000001)
#define BF_JTX_LINK_FEC_ENABLE_INFO 0x00000101
#define BF_JTX_LINK_FEC_ENABLE(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_LINK_FEC_ENABLE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_FORCE_METABITS_INFO 0x00000102
#define BF_JTX_FORCE_METABITS(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_FORCE_METABITS_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204C_SYSREF_RCVD_INFO 0x00000103
#define BF_JTX_DL_204C_SYSREF_RCVD(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204C_SYSREF_RCVD_GET(val) ((val >> 0x00000003) & 0x00000001)
#define REG_JTX_DL_204C_1_ADDR 0x00000668
#define BF_JTX_E_CFG_INFO 0x00000800
#define BF_JTX_E_CFG(val) (val & 0x000000FF)
#define BF_JTX_E_CFG_GET(val) (val & 0x000000FF)
#define REG_JTX_DL_204C_2_ADDR 0x00000669
#define BF_JTX_BURST_ERROR_INJECT_INFO 0x00000100
#define BF_JTX_BURST_ERROR_INJECT(val) (val & 0x00000001)
#define BF_JTX_BURST_ERROR_INJECT_GET(val) (val & 0x00000001)
#define BF_JTX_BURST_ERROR_LENGTH_INFO 0x00000404
#define BF_JTX_BURST_ERROR_LENGTH(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_BURST_ERROR_LENGTH_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_DL_204C_3_ADDR 0x0000066A
#define BF_JTX_BURST_ERROR_LOCATION_INFO 0x00000B00
#define BF_JTX_BURST_ERROR_LOCATION(val) (val & 0x000007FF)
#define BF_JTX_BURST_ERROR_LOCATION_GET(val) (val & 0x000007FF)
#define REG_JTX_DL_204H_0_ADDR 0x0000066B
#define BF_JTX_DL_204H_ACG_BYP_INFO 0x00000100
#define BF_JTX_DL_204H_ACG_BYP(val) (val & 0x00000001)
#define BF_JTX_DL_204H_ACG_BYP_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204H_BYP_ILAS_CFG_INFO 0x00000101
#define BF_JTX_DL_204H_BYP_ILAS_CFG(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_DL_204H_BYP_ILAS_CFG_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_DL_204H_CLEAR_SYNC_NE_COUNT_INFO 0x00000102
#define BF_JTX_DL_204H_CLEAR_SYNC_NE_COUNT(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204H_CLEAR_SYNC_NE_COUNT_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204H_LANE_SYNC_2SIDES_INFO 0x00000103
#define BF_JTX_DL_204H_LANE_SYNC_2SIDES(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204H_LANE_SYNC_2SIDES_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204H_ILAS_DELAY_CFG_INFO 0x00000404
#define BF_JTX_DL_204H_ILAS_DELAY_CFG(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_DL_204H_ILAS_DELAY_CFG_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_DL_204H_1_ADDR 0x0000066C
#define BF_JTX_DL_204H_INTERLEAVE_MODE_INFO 0x00000200
#define BF_JTX_DL_204H_INTERLEAVE_MODE(val) (val & 0x00000003)
#define BF_JTX_DL_204H_INTERLEAVE_MODE_GET(val) (val & 0x00000003)
#define BF_JTX_DL_204H_PARITY_BYPASS_INFO 0x00000102
#define BF_JTX_DL_204H_PARITY_BYPASS(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204H_PARITY_BYPASS_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204H_PARITY_MODE_INFO 0x00000103
#define BF_JTX_DL_204H_PARITY_MODE(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204H_PARITY_MODE_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204H_STATE_INFO 0x00000404
#define BF_JTX_DL_204H_STATE(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_DL_204H_STATE_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_DL_204H_2_ADDR 0x0000066D
#define BF_JTX_DL_204H_KF_ILAS_CFG_INFO 0x00000800
#define BF_JTX_DL_204H_KF_ILAS_CFG(val) (val & 0x000000FF)
#define BF_JTX_DL_204H_KF_ILAS_CFG_GET(val) (val & 0x000000FF)
#define REG_JTX_DL_204H_3_ADDR 0x0000066E
#define BF_JTX_DL_204H_PARITY_ODD_ENABLE_INFO 0x00000100
#define BF_JTX_DL_204H_PARITY_ODD_ENABLE(val) (val & 0x00000001)
#define BF_JTX_DL_204H_PARITY_ODD_ENABLE_GET(val) (val & 0x00000001)
#define BF_JTX_DL_204H_SCR_CFG_INFO 0x00000101
#define BF_JTX_DL_204H_SCR_CFG(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_DL_204H_SCR_CFG_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_JTX_DL_204H_SYNC_N_FORCE_EN_INFO 0x00000102
#define BF_JTX_DL_204H_SYNC_N_FORCE_EN(val) ((val & 0x00000001) << 0x00000002)
#define BF_JTX_DL_204H_SYNC_N_FORCE_EN_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_JTX_DL_204H_SYNC_N_FORCE_VAL_INFO 0x00000103
#define BF_JTX_DL_204H_SYNC_N_FORCE_VAL(val) ((val & 0x00000001) << 0x00000003)
#define BF_JTX_DL_204H_SYNC_N_FORCE_VAL_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_JTX_DL_204H_TEST_MODE_INFO 0x00000204
#define BF_JTX_DL_204H_TEST_MODE(val) ((val & 0x00000003) << 0x00000004)
#define BF_JTX_DL_204H_TEST_MODE_GET(val) ((val >> 0x00000004) & 0x00000003)
#define REG_JTX_DL_204H_4_ADDR 0x0000066F
#define BF_JTX_DL_204H_SYNC_NE_COUNT_INFO 0x00000800
#define BF_JTX_DL_204H_SYNC_NE_COUNT(val) (val & 0x000000FF)
#define BF_JTX_DL_204H_SYNC_NE_COUNT_GET(val) (val & 0x000000FF)
#define REG_JTX_PHY_IFX_0_LANE7_ADDR 0x00000677
#define BF_JTX_BR_LOG2_RATIO_0_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_0(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_0_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_0_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_0(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_0_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_PHY_IFX_0_LANE6_ADDR 0x00000676
#define BF_JTX_BR_LOG2_RATIO_1_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_1(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_1_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_1_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_1(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_1_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_PHY_IFX_0_LANE5_ADDR 0x00000675
#define BF_JTX_BR_LOG2_RATIO_2_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_2(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_2_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_2_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_2(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_2_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_PHY_IFX_0_LANE4_ADDR 0x00000674
#define BF_JTX_BR_LOG2_RATIO_3_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_3(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_3_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_3_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_3(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_3_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_PHY_IFX_0_LANE3_ADDR 0x00000673
#define BF_JTX_BR_LOG2_RATIO_4_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_4(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_4_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_4_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_4(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_4_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_PHY_IFX_0_LANE2_ADDR 0x00000672
#define BF_JTX_BR_LOG2_RATIO_5_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_5(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_5_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_5_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_5(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_5_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_PHY_IFX_0_LANE1_ADDR 0x00000671
#define BF_JTX_BR_LOG2_RATIO_6_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_6(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_6_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_6_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_6(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_6_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_JTX_PHY_IFX_0_LANE0_ADDR 0x00000670
#define BF_JTX_BR_LOG2_RATIO_7_INFO 0x00000400
#define BF_JTX_BR_LOG2_RATIO_7(val) (val & 0x0000000F)
#define BF_JTX_BR_LOG2_RATIO_7_GET(val) (val & 0x0000000F)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_7_INFO 0x00000404
#define BF_JTX_LANE_FIFO_WR_ENTRIES_7(val) ((val & 0x0000000F) << 0x00000004)
#define BF_JTX_LANE_FIFO_WR_ENTRIES_7_GET(val) ((val >> 0x00000004) & 0x0000000F)
#endif /* __ADI_AD9081_BF_JTX_DUAL_LINK_H__ */
/*! @} */

109
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_jtx_qbf_ad9081.h Executable file
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/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:26 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_JTX_QBF_AD9081_H__
#define __ADI_AD9081_BF_JTX_QBF_AD9081_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_JTX_C2R_EN_ADDR 0x00000700
#define BF_JTX_MODE_C2R_EN_INFO 0x00000100
#define BF_JTX_MODE_C2R_EN(val) (val & 0x00000001)
#define BF_JTX_MODE_C2R_EN_GET(val) (val & 0x00000001)
#define REG_PLL_STATUS_ADDR 0x00000701
#define BF_JTX_PLL_LOCKED_INFO 0x00000107
#define BF_JTX_PLL_LOCKED(val) ((val & 0x00000001) << 0x00000007)
#define BF_JTX_PLL_LOCKED_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_QUICK_CFG_ADDR 0x00000702
#define BF_JTX_MODE_INFO 0x00000600
#define BF_JTX_MODE(val) (val & 0x0000003F)
#define BF_JTX_MODE_GET(val) (val & 0x0000003F)
#define BF_JTX_MODE_S_SEL_INFO 0x00000206
#define BF_JTX_MODE_S_SEL(val) ((val & 0x00000003) << 0x00000006)
#define BF_JTX_MODE_S_SEL_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_JTX_LINK_CTRL1_ADDR 0x00000703
#define BF_JTX_LINK_PD_INFO 0x00000100
#define BF_JTX_LINK_PD(val) (val & 0x00000001)
#define BF_JTX_LINK_PD_GET(val) (val & 0x00000001)
#define REG_JTX_SER_CLK_INVERT_ADDR 0x00000706
#define BF_JTX_SER_CLK_INVERT_INFO 0x00000100
#define BF_JTX_SER_CLK_INVERT(val) (val & 0x00000001)
#define BF_JTX_SER_CLK_INVERT_GET(val) (val & 0x00000001)
#define BF_LOOPBACK_JTX_LINK_CLK_INVERT_INFO 0x00000104
#define BF_LOOPBACK_JTX_LINK_CLK_INVERT(val) ((val & 0x00000001) << 0x00000004)
#define BF_LOOPBACK_JTX_LINK_CLK_INVERT_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_LOOPBACK_JTX_LANE_CLK_INVERT_INFO 0x00000105
#define BF_LOOPBACK_JTX_LANE_CLK_INVERT(val) ((val & 0x00000001) << 0x00000005)
#define BF_LOOPBACK_JTX_LANE_CLK_INVERT_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_LOOPBACK_JTX_CONV_CLK_INVERT_INFO 0x00000106
#define BF_LOOPBACK_JTX_CONV_CLK_INVERT(val) ((val & 0x00000001) << 0x00000006)
#define BF_LOOPBACK_JTX_CONV_CLK_INVERT_GET(val) ((val >> 0x00000006) & 0x00000001)
#define REG_JTX_PDWN_CTRL_ADDR 0x00000708
#define BF_STDBY_CHIP_INFO 0x00000101
#define BF_STDBY_CHIP(val) ((val & 0x00000001) << 0x00000001)
#define BF_STDBY_CHIP_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_RESET_CTRL_REG_ADDR 0x0000070A
#define BF_FORCE_JTX_DIGITAL_RESET_ON_RSTEN_FORCE_EN_INFO 0x00000100
#define BF_FORCE_JTX_DIGITAL_RESET_ON_RSTEN_FORCE_EN(val) (val & 0x00000001)
#define BF_FORCE_JTX_DIGITAL_RESET_ON_RSTEN_FORCE_EN_GET(val) (val & 0x00000001)
#define REG_SER_PARITY_RESET_EN1_ADDR 0x0000070B
#define BF_SER_PARITY_RESET_EN_INFO 0x00000800
#define BF_SER_PARITY_RESET_EN(val) (val & 0x000000FF)
#define BF_SER_PARITY_RESET_EN_GET(val) (val & 0x000000FF)
#define REG_FORCE_LINK_RESET_REG_ADDR 0x00000710
#define BF_FORCE_LINK_RESET_INFO 0x00000100
#define BF_FORCE_LINK_RESET(val) (val & 0x00000001)
#define BF_FORCE_LINK_RESET_GET(val) (val & 0x00000001)
#define BF_FORCE_LINK_DIGITAL_RESET_INFO 0x00000104
#define BF_FORCE_LINK_DIGITAL_RESET(val) ((val & 0x00000001) << 0x00000004)
#define BF_FORCE_LINK_DIGITAL_RESET_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_QC_MODE_STATUS_ADDR 0x00000711
#define BF_JTX_INVALID_MODE_INFO 0x00000100
#define BF_JTX_INVALID_MODE(val) (val & 0x00000001)
#define BF_JTX_INVALID_MODE_GET(val) (val & 0x00000001)
#define REG_K_EMB_QC_OVERRIDE_ADDR 0x00000712
#define BF_JTX_K_EMB_QC_OVERRIDE_INFO 0x00000100
#define BF_JTX_K_EMB_QC_OVERRIDE(val) (val & 0x00000001)
#define BF_JTX_K_EMB_QC_OVERRIDE_GET(val) (val & 0x00000001)
#define REG_PHASE_ESTABLISH_STATUS_ADDR 0x00000713
#define BF_JTX_PHASE_ESTABLISHED_INFO 0x00000100
#define BF_JTX_PHASE_ESTABLISHED(val) (val & 0x00000001)
#define BF_JTX_PHASE_ESTABLISHED_GET(val) (val & 0x00000001)
#define REG_PHASE_ESTABLISH_DATA_GATING_ADDR 0x00000716
#define BF_JTX_PHASE_ESTABLISHED_DATA_GATING_EN_INFO 0x00000100
#define BF_JTX_PHASE_ESTABLISHED_DATA_GATING_EN(val) (val & 0x00000001)
#define BF_JTX_PHASE_ESTABLISHED_DATA_GATING_EN_GET(val) (val & 0x00000001)
#define REG_PLL_REF_CLK_DIV1_REG_ADDR 0x00000717
#define BF_DIVM_LCPLL_RC_RX_INFO 0x00000200
#define BF_DIVM_LCPLL_RC_RX(val) (val & 0x00000003)
#define BF_DIVM_LCPLL_RC_RX_GET(val) (val & 0x00000003)
#endif /* __ADI_AD9081_BF_JTX_QBF_AD9081_H__ */
/*! @} */

336
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_lcpll_28nm.h Executable file
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@@ -0,0 +1,336 @@
/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:26 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_LCPLL_28NM_R1_H__
#define __ADI_AD9081_BF_LCPLL_28NM_R1_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_LCPLL_RST_ADDR 0x00000720
#define BF_RSTB_LCPLL_RC_INFO 0x00000100
#define BF_RSTB_LCPLL_RC(val) (val & 0x00000001)
#define BF_RSTB_LCPLL_RC_GET(val) (val & 0x00000001)
#define REG_PLL_ENABLE_CTRL_ADDR 0x00000721
#define BF_PWRUP_LCPLL_INFO 0x00000100
#define BF_PWRUP_LCPLL(val) (val & 0x00000001)
#define BF_PWRUP_LCPLL_GET(val) (val & 0x00000001)
#define BF_LDSYNTH_FORCE_LCPLL_ADC_INFO 0x00000101
#define BF_LDSYNTH_FORCE_LCPLL_ADC(val) ((val & 0x00000001) << 0x00000001)
#define BF_LDSYNTH_FORCE_LCPLL_ADC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_LOLSTICKYCLEAR_FORCE_LCPLL_RC_INFO 0x00000103
#define BF_LOLSTICKYCLEAR_FORCE_LCPLL_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_LOLSTICKYCLEAR_FORCE_LCPLL_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_LCPLL_JTX_PLL_BYPASS_LOCK_INFO 0x00000105
#define BF_LCPLL_JTX_PLL_BYPASS_LOCK(val) ((val & 0x00000001) << 0x00000005)
#define BF_LCPLL_JTX_PLL_BYPASS_LOCK_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_PLL_LOCKED_BYPASS_INFO 0x00000106
#define BF_PLL_LOCKED_BYPASS(val) ((val & 0x00000001) << 0x00000006)
#define BF_PLL_LOCKED_BYPASS_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_PLL_LOCKED_BYPASS_VAL_INFO 0x00000107
#define BF_PLL_LOCKED_BYPASS_VAL(val) ((val & 0x00000001) << 0x00000007)
#define BF_PLL_LOCKED_BYPASS_VAL_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_PLL_STATUS_LCPLL_ADDR 0x00000722
#define BF_LCPLLLOCK_LCPLL_RS_INFO 0x00000100
#define BF_LCPLLLOCK_LCPLL_RS(val) (val & 0x00000001)
#define BF_LCPLLLOCK_LCPLL_RS_GET(val) (val & 0x00000001)
#define BF_REGULATORRDY_LCPLL_RS_INFO 0x00000101
#define BF_REGULATORRDY_LCPLL_RS(val) ((val & 0x00000001) << 0x00000001)
#define BF_REGULATORRDY_LCPLL_RS_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_VCOCALINPROG_LCPLL_RS_INFO 0x00000102
#define BF_VCOCALINPROG_LCPLL_RS(val) ((val & 0x00000001) << 0x00000002)
#define BF_VCOCALINPROG_LCPLL_RS_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_RFPLLLOCK_LCPLL_RS_INFO 0x00000103
#define BF_RFPLLLOCK_LCPLL_RS(val) ((val & 0x00000001) << 0x00000003)
#define BF_RFPLLLOCK_LCPLL_RS_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_LOSSLOCK_LCPLL_RS_INFO 0x00000104
#define BF_LOSSLOCK_LCPLL_RS(val) ((val & 0x00000001) << 0x00000004)
#define BF_LOSSLOCK_LCPLL_RS_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_PLL_PWR_UP1_ADDR 0x00000723
#define BF_PWRUP_ADC_LCPLL_RC_INFO 0x00000101
#define BF_PWRUP_ADC_LCPLL_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_PWRUP_ADC_LCPLL_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_PWRUP_CP_LCPLL_RC_INFO 0x00000102
#define BF_PWRUP_CP_LCPLL_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_PWRUP_CP_LCPLL_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_PWRUP_DIV_LCPLL_RC_INFO 0x00000103
#define BF_PWRUP_DIV_LCPLL_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_PWRUP_DIV_LCPLL_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_PWRUP_PEAKDET_LCPLL_RC_INFO 0x00000104
#define BF_PWRUP_PEAKDET_LCPLL_RC(val) ((val & 0x00000001) << 0x00000004)
#define BF_PWRUP_PEAKDET_LCPLL_RC_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_PWRUP_PLLBIAS_LCPLL_RC_INFO 0x00000105
#define BF_PWRUP_PLLBIAS_LCPLL_RC(val) ((val & 0x00000001) << 0x00000005)
#define BF_PWRUP_PLLBIAS_LCPLL_RC_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_PWRUP_VCO_LCPLL_RC_INFO 0x00000106
#define BF_PWRUP_VCO_LCPLL_RC(val) ((val & 0x00000001) << 0x00000006)
#define BF_PWRUP_VCO_LCPLL_RC_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_PWRUP_REG_LCPLL_RC_INFO 0x00000107
#define BF_PWRUP_REG_LCPLL_RC(val) ((val & 0x00000001) << 0x00000007)
#define BF_PWRUP_REG_LCPLL_RC_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_PLL_PWR_UP2_ADDR 0x00000724
#define BF_PWRUP_REFCLK_LCPLL_RC_INFO 0x00000100
#define BF_PWRUP_REFCLK_LCPLL_RC(val) (val & 0x00000001)
#define BF_PWRUP_REFCLK_LCPLL_RC_GET(val) (val & 0x00000001)
#define BF_PWRUP_VCOVAR_LCPLL_RC_INFO 0x00000101
#define BF_PWRUP_VCOVAR_LCPLL_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_PWRUP_VCOVAR_LCPLL_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_PWRUP_VCOBUF_LCPLL_RC_INFO 0x00000102
#define BF_PWRUP_VCOBUF_LCPLL_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_PWRUP_VCOBUF_LCPLL_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_PWRUP_VCOVARBIAS_LCPLL_RC_INFO 0x00000103
#define BF_PWRUP_VCOVARBIAS_LCPLL_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_PWRUP_VCOVARBIAS_LCPLL_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_PWRUP_ADCAUX_LCPLL_RC_INFO 0x00000106
#define BF_PWRUP_ADCAUX_LCPLL_RC(val) ((val & 0x00000001) << 0x00000006)
#define BF_PWRUP_ADCAUX_LCPLL_RC_GET(val) ((val >> 0x00000006) & 0x00000001)
#define REG_PLL_PWR_UP3_ADDR 0x00000725
#define BF_PWRUP_VCOBIAS_LCPLL_RC_INFO 0x00000400
#define BF_PWRUP_VCOBIAS_LCPLL_RC(val) (val & 0x0000000F)
#define BF_PWRUP_VCOBIAS_LCPLL_RC_GET(val) (val & 0x0000000F)
#define REG_PLL_ENCAL_ADDR 0x00000726
#define BF_FIXED_SERDES_PLL_INFO 0x00000100
#define BF_FIXED_SERDES_PLL(val) (val & 0x00000001)
#define BF_FIXED_SERDES_PLL_GET(val) (val & 0x00000001)
#define BF_EN_TX_ONLY_LCPLL_RC_INFO 0x00000101
#define BF_EN_TX_ONLY_LCPLL_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_EN_TX_ONLY_LCPLL_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_PD_RXCLK_DIST_RC_INFO 0x00000103
#define BF_PD_RXCLK_DIST_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_PD_RXCLK_DIST_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_PD_TXCLK_DIST_RC_INFO 0x00000104
#define BF_PD_TXCLK_DIST_RC(val) ((val & 0x00000001) << 0x00000004)
#define BF_PD_TXCLK_DIST_RC_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_LCPLL_REF_CLK_DIV1_REG_ADDR 0x00000727
#define BF_SERDES_PLL_BF_0_INFO 0x00000300
#define BF_SERDES_PLL_BF_0(val) (val & 0x00000007)
#define BF_SERDES_PLL_BF_0_GET(val) (val & 0x00000007)
#define BF_DIVM_LCPLL_RC_INFO 0x00000204
#define BF_DIVM_LCPLL_RC(val) ((val & 0x00000003) << 0x00000004)
#define BF_DIVM_LCPLL_RC_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_SERDES_PLL_BF_1_INFO 0x00000106
#define BF_SERDES_PLL_BF_1(val) ((val & 0x00000001) << 0x00000006)
#define BF_SERDES_PLL_BF_1_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_REFCK_DIV40BDIV120_LCPLL_INFO 0x00000107
#define BF_REFCK_DIV40BDIV120_LCPLL(val) ((val & 0x00000001) << 0x00000007)
#define BF_REFCK_DIV40BDIV120_LCPLL_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_PLL_DIV2_ADDR 0x00000728
#define BF_SERDES_PLL_BF_9_INFO 0x00000800
#define BF_SERDES_PLL_BF_9(val) (val & 0x000000FF)
#define BF_SERDES_PLL_BF_9_GET(val) (val & 0x000000FF)
#define REG_PLL_RXDIVRATE_STATUS_ADDR 0x00000729
#define BF_RXDIVRATE_LCPLL_RS_INFO 0x00000400
#define BF_RXDIVRATE_LCPLL_RS(val) (val & 0x0000000F)
#define BF_RXDIVRATE_LCPLL_RS_GET(val) (val & 0x0000000F)
#define BF_DIVM_LCPLL_RS_INFO 0x00000204
#define BF_DIVM_LCPLL_RS(val) ((val & 0x00000003) << 0x00000004)
#define BF_DIVM_LCPLL_RS_GET(val) ((val >> 0x00000004) & 0x00000003)
#define REG_PLL_DIVOVD_ADDR 0x0000072A
#define BF_SERDES_PLL_BF_3_INFO 0x00000100
#define BF_SERDES_PLL_BF_3(val) (val & 0x00000001)
#define BF_SERDES_PLL_BF_3_GET(val) (val & 0x00000001)
#define BF_SERDES_PLL_BF_4_INFO 0x00000101
#define BF_SERDES_PLL_BF_4(val) ((val & 0x00000001) << 0x00000001)
#define BF_SERDES_PLL_BF_4_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_SERDES_PLL_BF_5_INFO 0x00000102
#define BF_SERDES_PLL_BF_5(val) ((val & 0x00000001) << 0x00000002)
#define BF_SERDES_PLL_BF_5_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_SERDES_PLL_BF_6_INFO 0x00000103
#define BF_SERDES_PLL_BF_6(val) ((val & 0x00000001) << 0x00000003)
#define BF_SERDES_PLL_BF_6_GET(val) ((val >> 0x00000003) & 0x00000001)
#define REG_PLL_RXDIVRATE_ADDR 0x0000072B
#define BF_SERDES_PLL_BF_7_INFO 0x00000400
#define BF_SERDES_PLL_BF_7(val) (val & 0x0000000F)
#define BF_SERDES_PLL_BF_7_GET(val) (val & 0x0000000F)
#define REG_PLL_VCO_TRIM_ADDR 0x0000072C
#define BF_VCORTRIM_LCPLL_RC_INFO 0x00000600
#define BF_VCORTRIM_LCPLL_RC(val) (val & 0x0000003F)
#define BF_VCORTRIM_LCPLL_RC_GET(val) (val & 0x0000003F)
#define REG_PLL_REFCLK_CPL_ADDR 0x0000072D
#define BF_SEL_REFCKDCACB_LCPLL_RC_INFO 0x00000100
#define BF_SEL_REFCKDCACB_LCPLL_RC(val) (val & 0x00000001)
#define BF_SEL_REFCKDCACB_LCPLL_RC_GET(val) (val & 0x00000001)
#define BF_SERDES_PLL_BF_8_INFO 0x00000101
#define BF_SERDES_PLL_BF_8(val) ((val & 0x00000001) << 0x00000001)
#define BF_SERDES_PLL_BF_8_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_DIGCLK_REFIN_DIV_RC_INFO 0x00000304
#define BF_DIGCLK_REFIN_DIV_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DIGCLK_REFIN_DIV_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_CBUS_REN_LCPLL_ADDR 0x0000072E
#define BF_LCPLL_CBUS_REN_LCPLL_RC_INFO 0x00000100
#define BF_LCPLL_CBUS_REN_LCPLL_RC(val) (val & 0x00000001)
#define BF_LCPLL_CBUS_REN_LCPLL_RC_GET(val) (val & 0x00000001)
#define REG_CBUS_WSTROBE_LCPLL_ADDR 0x0000072F
#define BF_LCPLL_CBUS_WSTROBE_LCPLL_RC_INFO 0x00000100
#define BF_LCPLL_CBUS_WSTROBE_LCPLL_RC(val) (val & 0x00000001)
#define BF_LCPLL_CBUS_WSTROBE_LCPLL_RC_GET(val) (val & 0x00000001)
#define REG_CKDIST_PD_ADDR 0x00000730
#define BF_PD_PPF_DES_RC_INFO 0x00000100
#define BF_PD_PPF_DES_RC(val) (val & 0x00000001)
#define BF_PD_PPF_DES_RC_GET(val) (val & 0x00000001)
#define BF_IDIST_PD_RC_INFO 0x00000101
#define BF_IDIST_PD_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_IDIST_PD_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_POLYPHASE_CTRL_ADDR 0x00000731
#define BF_TRIM_POLYPHASE_DES_RC_INFO 0x00000800
#define BF_TRIM_POLYPHASE_DES_RC(val) (val & 0x000000FF)
#define BF_TRIM_POLYPHASE_DES_RC_GET(val) (val & 0x000000FF)
#define REG_PLL_READ_FREQ4_ADDR 0x00000732
#define BF_VCOFREQBAND_LCPLL_RS_INFO 0x00000B00
#define BF_VCOFREQBAND_LCPLL_RS(val) (val & 0x000007FF)
#define BF_VCOFREQBAND_LCPLL_RS_GET(val) (val & 0x000007FF)
#define REG_PLL_READ_FREQ5_ADDR 0x00000733
#define REG_PLL_PTAT_STARTUP_ADDR 0x00000734
#define BF_PTAT_STARTUP_LCPLL_RC_INFO 0x00000800
#define BF_PTAT_STARTUP_LCPLL_RC(val) (val & 0x000000FF)
#define BF_PTAT_STARTUP_LCPLL_RC_GET(val) (val & 0x000000FF)
#define REG_PLL_PTAT_STARTUP_STATUS1_ADDR 0x00000735
#define BF_PTAT_STARTUP_STATUS_RS1_INFO 0x00000100
#define BF_PTAT_STARTUP_STATUS_RS1(val) (val & 0x00000001)
#define BF_PTAT_STARTUP_STATUS_RS1_GET(val) (val & 0x00000001)
#define REG_PLL_PTAT_STARTUP_STATUS2_ADDR 0x00000736
#define BF_PTAT_STARTUP_STATUS_RS2_INFO 0x00000100
#define BF_PTAT_STARTUP_STATUS_RS2(val) (val & 0x00000001)
#define BF_PTAT_STARTUP_STATUS_RS2_GET(val) (val & 0x00000001)
#define REG_PLL_TEMP_ADDR 0x00000737
#define BF_TDEGCINIT_LCPLL_RC_INFO 0x00000100
#define BF_TDEGCINIT_LCPLL_RC(val) (val & 0x00000001)
#define BF_TDEGCINIT_LCPLL_RC_GET(val) (val & 0x00000001)
#define REG_PLL_READ_TEMP1_ADDR 0x0000073A
#define BF_TDEGC_LCPLL_RS_INFO 0x00000C00
#define BF_TDEGC_LCPLL_RS(val) (val & 0x00000FFF)
#define BF_TDEGC_LCPLL_RS_GET(val) (val & 0x00000FFF)
#define REG_PLL_READ_TEMP2_ADDR 0x0000073B
#define REG_PLL_LDSYNTH_DELAY_ADDR 0x0000073D
#define BF_LDSYNTH_LCPLL_HIGH_INFO 0x00000400
#define BF_LDSYNTH_LCPLL_HIGH(val) (val & 0x0000000F)
#define BF_LDSYNTH_LCPLL_HIGH_GET(val) (val & 0x0000000F)
#define BF_LDSYNTH_LCPLL_WARMUP_INFO 0x00000404
#define BF_LDSYNTH_LCPLL_WARMUP(val) ((val & 0x0000000F) << 0x00000004)
#define BF_LDSYNTH_LCPLL_WARMUP_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_PLL_LOCK_CTL1_ADDR 0x0000073E
#define BF_LCPLL_LOCK_SEL_INFO 0x00000100
#define BF_LCPLL_LOCK_SEL(val) (val & 0x00000001)
#define BF_LCPLL_LOCK_SEL_GET(val) (val & 0x00000001)
#define BF_LCPLL_LOCK_DIVIDER_INFO 0x00000A04
#define BF_LCPLL_LOCK_DIVIDER(val) ((val & 0x000003FF) << 0x00000004)
#define BF_LCPLL_LOCK_DIVIDER_GET(val) ((val >> 0x00000004) & 0x000003FF)
#define REG_PLL_LOCK_CTL2_ADDR 0x0000073F
#define REG_CBUS_ADDR_LCPLL_ADDR 0x00000740
#define BF_LCPLL_CBUS_ADDR_LCPLL_RC_INFO 0x00000800
#define BF_LCPLL_CBUS_ADDR_LCPLL_RC(val) (val & 0x000000FF)
#define BF_LCPLL_CBUS_ADDR_LCPLL_RC_GET(val) (val & 0x000000FF)
#define REG_CBUS_WDATA_LCPLL_ADDR 0x00000741
#define BF_LCPLL_CBUS_WDATA_LCPLL_RC_INFO 0x00000800
#define BF_LCPLL_CBUS_WDATA_LCPLL_RC(val) (val & 0x000000FF)
#define BF_LCPLL_CBUS_WDATA_LCPLL_RC_GET(val) (val & 0x000000FF)
#define REG_CBUS_RDATA_LCPLL_ADDR 0x00000742
#define BF_LCPLL_CBUS_RDATA_LCPLL_RS_INFO 0x00000800
#define BF_LCPLL_CBUS_RDATA_LCPLL_RS(val) (val & 0x000000FF)
#define BF_LCPLL_CBUS_RDATA_LCPLL_RS_GET(val) (val & 0x000000FF)
#define REG_REFCLK_CTRL_ADDR 0x00000743
#define BF_EN_REFCLK_RCVR_RC_INFO 0x00000100
#define BF_EN_REFCLK_RCVR_RC(val) (val & 0x00000001)
#define BF_EN_REFCLK_RCVR_RC_GET(val) (val & 0x00000001)
#define BF_SEL_SYNCA_FOR_REFCLK_RC_INFO 0x00000101
#define BF_SEL_SYNCA_FOR_REFCLK_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_SEL_SYNCA_FOR_REFCLK_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_SEL_REFCLK_RCVR_LP_MODE_RC_INFO 0x00000102
#define BF_SEL_REFCLK_RCVR_LP_MODE_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_SEL_REFCLK_RCVR_LP_MODE_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_SEL_REFCLK_RCVR_CM_CTRL_INFO 0x00000403
#define BF_SEL_REFCLK_RCVR_CM_CTRL(val) ((val & 0x0000000F) << 0x00000003)
#define BF_SEL_REFCLK_RCVR_CM_CTRL_GET(val) ((val >> 0x00000003) & 0x0000000F)
#define REG_SERDES_REV_ID_RS_LCPLL_ADDR 0x00000744
#define BF_LCPLL_SERDES_REV_ID_RS_INFO 0x00000800
#define BF_LCPLL_SERDES_REV_ID_RS(val) (val & 0x000000FF)
#define BF_LCPLL_SERDES_REV_ID_RS_GET(val) (val & 0x000000FF)
#define REG_SPARE0_ADDR 0x00000745
#define BF_LCPLL_SPARE0_INFO 0x00000800
#define BF_LCPLL_SPARE0(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE0_GET(val) (val & 0x000000FF)
#define REG_SPARE1_ADDR 0x00000746
#define BF_LCPLL_SPARE1_INFO 0x00000800
#define BF_LCPLL_SPARE1(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE1_GET(val) (val & 0x000000FF)
#define REG_SPARE2_ADDR 0x00000747
#define BF_LCPLL_SPARE2_INFO 0x00000800
#define BF_LCPLL_SPARE2(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE2_GET(val) (val & 0x000000FF)
#define REG_SPARE3_ADDR 0x00000748
#define BF_LCPLL_SPARE3_INFO 0x00000800
#define BF_LCPLL_SPARE3(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE3_GET(val) (val & 0x000000FF)
#define REG_SPARE4_ADDR 0x00000749
#define BF_LCPLL_SPARE4_INFO 0x00000800
#define BF_LCPLL_SPARE4(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE4_GET(val) (val & 0x000000FF)
#define REG_SPARE5_ADDR 0x0000074A
#define BF_LCPLL_SPARE5_INFO 0x00000800
#define BF_LCPLL_SPARE5(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE5_GET(val) (val & 0x000000FF)
#define REG_SPARE6_ADDR 0x0000074B
#define BF_LCPLL_SPARE6_INFO 0x00000800
#define BF_LCPLL_SPARE6(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE6_GET(val) (val & 0x000000FF)
#define REG_SPARE7_ADDR 0x0000074C
#define BF_LCPLL_SPARE7_INFO 0x00000800
#define BF_LCPLL_SPARE7(val) (val & 0x000000FF)
#define BF_LCPLL_SPARE7_GET(val) (val & 0x000000FF)
#endif /* __ADI_AD9081_BF_LCPLL_28NM_R1_H__ */
/*! @} */

99
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_main.h Executable file
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@@ -0,0 +1,99 @@
/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:26 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_MAIN_H__
#define __ADI_AD9081_BF_MAIN_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_DEVICE_CONFIG_ADDR 0x00000002
#define BF_OP_MODE_INFO 0x00000200
#define BF_OP_MODE(val) (val & 0x00000003)
#define BF_OP_MODE_GET(val) (val & 0x00000003)
#define BF_CUST_OP_MODE_INFO 0x00000202
#define BF_CUST_OP_MODE(val) ((val & 0x00000003) << 0x00000002)
#define BF_CUST_OP_MODE_GET(val) ((val >> 0x00000002) & 0x00000003)
#define BF_DEVICE_STATUS_INFO 0x00000404
#define BF_DEVICE_STATUS(val) ((val & 0x0000000F) << 0x00000004)
#define BF_DEVICE_STATUS_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_CHIP_TYPE_ADDR 0x00000003
#define BF_CHIP_TYPE_INFO 0x00000800
#define BF_CHIP_TYPE(val) (val & 0x000000FF)
#define BF_CHIP_TYPE_GET(val) (val & 0x000000FF)
#define REG_PROD_ID_LSB_ADDR 0x00000004
#define BF_PROD_ID_INFO 0x00001000
#define BF_PROD_ID(val) (val & 0x0000FFFF)
#define BF_PROD_ID_GET(val) (val & 0x0000FFFF)
#define REG_PROD_ID_MSB_ADDR 0x00000005
#define REG_CHIP_GRADE_ADDR 0x00000006
#define BF_CHIP_GRADE_INFO 0x00000800
#define BF_CHIP_GRADE(val) (val & 0x000000FF)
#define BF_CHIP_GRADE_GET(val) (val & 0x000000FF)
#define REG_DEVICE_INDEX1_ADDR 0x00000008
#define BF_DEV_INDEX1_INFO 0x00000800
#define BF_DEV_INDEX1(val) (val & 0x000000FF)
#define BF_DEV_INDEX1_GET(val) (val & 0x000000FF)
#define REG_DEVICE_INDEX2_ADDR 0x00000009
#define BF_DEV_INDEX2_INFO 0x00000800
#define BF_DEV_INDEX2(val) (val & 0x000000FF)
#define BF_DEV_INDEX2_GET(val) (val & 0x000000FF)
#define REG_CHIP_SCRATCH_ADDR 0x0000000A
#define BF_CHIP_SCRATCH_INFO 0x00000800
#define BF_CHIP_SCRATCH(val) (val & 0x000000FF)
#define BF_CHIP_SCRATCH_GET(val) (val & 0x000000FF)
#define REG_SPI_REVISION_ADDR 0x0000000B
#define BF_SPI_REVISION_INFO 0x00000800
#define BF_SPI_REVISION(val) (val & 0x000000FF)
#define BF_SPI_REVISION_GET(val) (val & 0x000000FF)
#define REG_VENDOR_ID_LSB_ADDR 0x0000000C
#define BF_CHIP_VENDOR_ID_INFO 0x00001000
#define BF_CHIP_VENDOR_ID(val) (val & 0x0000FFFF)
#define BF_CHIP_VENDOR_ID_GET(val) (val & 0x0000FFFF)
#define REG_VENDOR_ID_MSB_ADDR 0x0000000D
#define REG_CHIP_ID_L_ADDR 0x00000010
#define BF_CHIP_ID_L_INFO 0x00000800
#define BF_CHIP_ID_L(val) (val & 0x000000FF)
#define BF_CHIP_ID_L_GET(val) (val & 0x000000FF)
#define REG_CHIP_ID_M1_ADDR 0x00000011
#define BF_CHIP_ID_M1_INFO 0x00000800
#define BF_CHIP_ID_M1(val) (val & 0x000000FF)
#define BF_CHIP_ID_M1_GET(val) (val & 0x000000FF)
#define REG_CHIP_ID_M2_ADDR 0x00000012
#define BF_CHIP_ID_M2_INFO 0x00000800
#define BF_CHIP_ID_M2(val) (val & 0x000000FF)
#define BF_CHIP_ID_M2_GET(val) (val & 0x000000FF)
#define REG_CHIP_ID_H_ADDR 0x00000013
#define BF_CHIP_ID_H_INFO 0x00000800
#define BF_CHIP_ID_H(val) (val & 0x000000FF)
#define BF_CHIP_ID_H_GET(val) (val & 0x000000FF)
#endif /* __ADI_AD9081_BF_MAIN_H__ */
/*! @} */

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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_nb_coarse_nco.h Executable file
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/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:26 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_NB_COARSE_NCO_H__
#define __ADI_AD9081_BF_NB_COARSE_NCO_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_COARSE_DDC_SYNC_CTRL_ADDR 0x00000A00
#define BF_COARSE_DDC_SYNC_EN_INFO 0x00000100
#define BF_COARSE_DDC_SYNC_EN(val) (val & 0x00000001)
#define BF_COARSE_DDC_SYNC_EN_GET(val) (val & 0x00000001)
#define BF_COARSE_DDC_SYNC_NEXT_INFO 0x00000101
#define BF_COARSE_DDC_SYNC_NEXT(val) ((val & 0x00000001) << 0x00000001)
#define BF_COARSE_DDC_SYNC_NEXT_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_COARSE_DDC_SOFT_RESET_INFO 0x00000104
#define BF_COARSE_DDC_SOFT_RESET(val) ((val & 0x00000001) << 0x00000004)
#define BF_COARSE_DDC_SOFT_RESET_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_COARSE_DDC_TRIG_NCO_RESET_EN_INFO 0x00000107
#define BF_COARSE_DDC_TRIG_NCO_RESET_EN(val) ((val & 0x00000001) << 0x00000007)
#define BF_COARSE_DDC_TRIG_NCO_RESET_EN_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_COARSE_DDC_SYNC_STATUS_ADDR 0x00000A01
#define BF_COARSE_DDC_SYNC_EN_CLEAR_INFO 0x00000100
#define BF_COARSE_DDC_SYNC_EN_CLEAR(val) (val & 0x00000001)
#define BF_COARSE_DDC_SYNC_EN_CLEAR_GET(val) (val & 0x00000001)
#define REG_COARSE_DDC_TRIG_CTRL_ADDR 0x00000A02
#define BF_COARSE_DDC_TRIG_HOP_EN_INFO 0x00000100
#define BF_COARSE_DDC_TRIG_HOP_EN(val) (val & 0x00000001)
#define BF_COARSE_DDC_TRIG_HOP_EN_GET(val) (val & 0x00000001)
#define REG_COARSE_DDC_NCO_CTRL_ADDR 0x00000A03
#define BF_COARSE_DDC0_NCO_REGMAP_CHAN_SEL_INFO 0x00000400
#define BF_COARSE_DDC0_NCO_REGMAP_CHAN_SEL(val) (val & 0x0000000F)
#define BF_COARSE_DDC0_NCO_REGMAP_CHAN_SEL_GET(val) (val & 0x0000000F)
#define BF_COARSE_DDC0_NCO_CHAN_SEL_MODE_INFO 0x00000404
#define BF_COARSE_DDC0_NCO_CHAN_SEL_MODE(val) ((val & 0x0000000F) << 0x00000004)
#define BF_COARSE_DDC0_NCO_CHAN_SEL_MODE_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_COARSE_DDC_PROFILE_CTRL_ADDR 0x00000A04
#define BF_COARSE_DDC0_PROFILE_UPDATE_INDEX_INFO 0x00000400
#define BF_COARSE_DDC0_PROFILE_UPDATE_INDEX(val) (val & 0x0000000F)
#define BF_COARSE_DDC0_PROFILE_UPDATE_INDEX_GET(val) (val & 0x0000000F)
#define BF_COARSE_DDC0_GPIO_CHIP_TRANSFER_MODE_INFO 0x00000106
#define BF_COARSE_DDC0_GPIO_CHIP_TRANSFER_MODE(val) ((val & 0x00000001) << 0x00000006)
#define BF_COARSE_DDC0_GPIO_CHIP_TRANSFER_MODE_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_COARSE_DDC0_PROFILE_UPDATE_MODE_INFO 0x00000107
#define BF_COARSE_DDC0_PROFILE_UPDATE_MODE(val) ((val & 0x00000001) << 0x00000007)
#define BF_COARSE_DDC0_PROFILE_UPDATE_MODE_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_COARSE_DDC_PHASE_INC0_ADDR 0x00000A05
#define BF_COARSE_DDC0_PHASE_INC0_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC0(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC0_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC1_ADDR 0x00000A06
#define BF_COARSE_DDC0_PHASE_INC1_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC1(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC1_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC2_ADDR 0x00000A07
#define BF_COARSE_DDC0_PHASE_INC2_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC2(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC2_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC3_ADDR 0x00000A08
#define BF_COARSE_DDC0_PHASE_INC3_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC3(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC3_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC4_ADDR 0x00000A09
#define BF_COARSE_DDC0_PHASE_INC4_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC4(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC4_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC5_ADDR 0x00000A0A
#define BF_COARSE_DDC0_PHASE_INC5_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC5(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC5_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_OFFSET0_ADDR 0x00000A0B
#define BF_COARSE_DDC0_PHASE_OFFSET0_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_OFFSET0(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_OFFSET0_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_OFFSET1_ADDR 0x00000A0C
#define BF_COARSE_DDC0_PHASE_OFFSET1_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_OFFSET1(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_OFFSET1_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_OFFSET2_ADDR 0x00000A0D
#define BF_COARSE_DDC0_PHASE_OFFSET2_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_OFFSET2(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_OFFSET2_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_OFFSET3_ADDR 0x00000A0E
#define BF_COARSE_DDC0_PHASE_OFFSET3_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_OFFSET3(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_OFFSET3_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_OFFSET4_ADDR 0x00000A0F
#define BF_COARSE_DDC0_PHASE_OFFSET4_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_OFFSET4(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_OFFSET4_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_OFFSET5_ADDR 0x00000A10
#define BF_COARSE_DDC0_PHASE_OFFSET5_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_OFFSET5(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_OFFSET5_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_A0_ADDR 0x00000A11
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A0_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A0(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A0_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_A1_ADDR 0x00000A12
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A1_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A1(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A1_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_A2_ADDR 0x00000A13
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A2_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A2(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A2_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_A3_ADDR 0x00000A14
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A3_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A3(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A3_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_A4_ADDR 0x00000A15
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A4_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A4(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A4_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_A5_ADDR 0x00000A16
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A5_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A5(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_A5_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_B0_ADDR 0x00000A17
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B0_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B0(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B0_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_B1_ADDR 0x00000A18
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B1_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B1(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B1_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_B2_ADDR 0x00000A19
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B2_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B2(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B2_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_B3_ADDR 0x00000A1A
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B3_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B3(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B3_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_B4_ADDR 0x00000A1B
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B4_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B4(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B4_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PHASE_INC_FRAC_B5_ADDR 0x00000A1C
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B5_INFO 0x00000800
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B5(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PHASE_INC_FRAC_B5_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_TRANSFER_STATUS_ADDR 0x00000A1D
#define BF_COARSE_DDC0_CHIP_TRANSFER_STATUS_INFO 0x00000100
#define BF_COARSE_DDC0_CHIP_TRANSFER_STATUS(val) (val & 0x00000001)
#define BF_COARSE_DDC0_CHIP_TRANSFER_STATUS_GET(val) (val & 0x00000001)
#define REG_COARSE_DDC_DITHER_ADDR 0x00000A1E
#define BF_COARSE_DDC0_AMP_DITHER_EN_INFO 0x00000100
#define BF_COARSE_DDC0_AMP_DITHER_EN(val) (val & 0x00000001)
#define BF_COARSE_DDC0_AMP_DITHER_EN_GET(val) (val & 0x00000001)
#define BF_COARSE_DDC0_PHASE_DITHER_EN_INFO 0x00000101
#define BF_COARSE_DDC0_PHASE_DITHER_EN(val) ((val & 0x00000001) << 0x00000001)
#define BF_COARSE_DDC0_PHASE_DITHER_EN_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_COARSE_DDC_TRANSFER_CTRL_ADDR 0x00000A1F
#define BF_COARSE_DDC0_CHIP_TRANSFER_INFO 0x00000100
#define BF_COARSE_DDC0_CHIP_TRANSFER(val) (val & 0x00000001)
#define BF_COARSE_DDC0_CHIP_TRANSFER_GET(val) (val & 0x00000001)
#define REG_COARSE_DDC_PSW_0_ADDR 0x00000A20
#define BF_COARSE_DDC0_PSW0_INFO 0x00000800
#define BF_COARSE_DDC0_PSW0(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PSW0_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PSW_1_ADDR 0x00000A21
#define BF_COARSE_DDC0_PSW1_INFO 0x00000800
#define BF_COARSE_DDC0_PSW1(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PSW1_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PSW_2_ADDR 0x00000A22
#define BF_COARSE_DDC0_PSW2_INFO 0x00000800
#define BF_COARSE_DDC0_PSW2(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PSW2_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PSW_3_ADDR 0x00000A23
#define BF_COARSE_DDC0_PSW3_INFO 0x00000800
#define BF_COARSE_DDC0_PSW3(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PSW3_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PSW_4_ADDR 0x00000A24
#define BF_COARSE_DDC0_PSW4_INFO 0x00000800
#define BF_COARSE_DDC0_PSW4(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PSW4_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_PSW_5_ADDR 0x00000A25
#define BF_COARSE_DDC0_PSW5_INFO 0x00000800
#define BF_COARSE_DDC0_PSW5(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_PSW5_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_INC0_ADDR 0x00000A26
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC0_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC0(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC0_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_INC1_ADDR 0x00000A27
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC1_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC1(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC1_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_INC2_ADDR 0x00000A28
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC2_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC2(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC2_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_INC3_ADDR 0x00000A29
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC3_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC3(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC3_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_INC4_ADDR 0x00000A2A
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC4_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC4(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC4_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_INC5_ADDR 0x00000A2B
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC5_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC5(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_INC5_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_OFFSET0_ADDR 0x00000A2C
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET0_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET0(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET0_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_OFFSET1_ADDR 0x00000A2D
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET1_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET1(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET1_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_OFFSET2_ADDR 0x00000A2E
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET2_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET2(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET2_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_OFFSET3_ADDR 0x00000A2F
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET3_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET3(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET3_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_OFFSET4_ADDR 0x00000A30
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET4_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET4(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET4_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_ACTIVE_PHASE_OFFSET5_ADDR 0x00000A31
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET5_INFO 0x00000800
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET5(val) (val & 0x000000FF)
#define BF_COARSE_DDC0_ACTIVE_PHASE_OFFSET5_GET(val) (val & 0x000000FF)
#define REG_COARSE_TIMESTAMP_COUNTER_REG0_ADDR 0x00000A32
#define BF_COARSE_TIMESTAMP_INFO 0x00003000
#define REG_COARSE_TIMESTAMP_COUNTER_REG1_ADDR 0x00000A33
#define REG_COARSE_TIMESTAMP_COUNTER_REG2_ADDR 0x00000A34
#define REG_COARSE_TIMESTAMP_COUNTER_REG3_ADDR 0x00000A35
#define REG_COARSE_TIMESTAMP_COUNTER_REG4_ADDR 0x00000A36
#define REG_COARSE_TIMESTAMP_COUNTER_REG5_ADDR 0x00000A37
#define REG_COARSE_TIMESTAMP_READ_CTRL_ADDR 0x00000A38
#define BF_COARSE_TIMESTAMP_READ_ENABLE_INFO 0x00000100
#define BF_COARSE_TIMESTAMP_READ_ENABLE(val) (val & 0x00000001)
#define BF_COARSE_TIMESTAMP_READ_ENABLE_GET(val) (val & 0x00000001)
#endif /* __ADI_AD9081_BF_NB_COARSE_NCO_H__ */
/*! @} */

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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_nb_ddc_dformat.h Executable file
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@@ -0,0 +1,607 @@
/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:26 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_NB_DDC_DFORMAT_H__
#define __ADI_AD9081_BF_NB_DDC_DFORMAT_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_ADC_COARSE_CB_ADDR 0x00000280
#define BF_ADC_COARSE_CB_INFO 0x00000400
#define BF_ADC_COARSE_CB(val) (val & 0x0000000F)
#define BF_ADC_COARSE_CB_GET(val) (val & 0x0000000F)
#define BF_C_MXR_IQ_SFL_INFO 0x00000404
#define BF_C_MXR_IQ_SFL(val) ((val & 0x0000000F) << 0x00000004)
#define BF_C_MXR_IQ_SFL_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_COARSE_FINE_CB_ADDR 0x00000281
#define BF_COARSE_FINE_CB_INFO 0x00000800
#define BF_COARSE_FINE_CB(val) (val & 0x000000FF)
#define BF_COARSE_FINE_CB_GET(val) (val & 0x000000FF)
#define REG_COARSE_DEC_CTRL_ADDR 0x00000282
#define BF_COARSE_DEC_SEL_INFO 0x00000400
#define BF_COARSE_DEC_SEL(val) (val & 0x0000000F)
#define BF_COARSE_DEC_SEL_GET(val) (val & 0x0000000F)
#define BF_COARSE_C2R_EN_INFO 0x00000104
#define BF_COARSE_C2R_EN(val) ((val & 0x00000001) << 0x00000004)
#define BF_COARSE_C2R_EN_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_COARSE_GAIN_INFO 0x00000105
#define BF_COARSE_GAIN(val) ((val & 0x00000001) << 0x00000005)
#define BF_COARSE_GAIN_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_COARSE_MXR_IF_INFO 0x00000206
#define BF_COARSE_MXR_IF(val) ((val & 0x00000003) << 0x00000006)
#define BF_COARSE_MXR_IF_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_FINE_DEC_CTRL_ADDR 0x00000283
#define BF_FINE_DEC_SEL_INFO 0x00000300
#define BF_FINE_DEC_SEL(val) (val & 0x00000007)
#define BF_FINE_DEC_SEL_GET(val) (val & 0x00000007)
#define BF_FINE_C2R_EN_INFO 0x00000104
#define BF_FINE_C2R_EN(val) ((val & 0x00000001) << 0x00000004)
#define BF_FINE_C2R_EN_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_FINE_GAIN_INFO 0x00000105
#define BF_FINE_GAIN(val) ((val & 0x00000001) << 0x00000005)
#define BF_FINE_GAIN_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_FINE_MXR_IF_INFO 0x00000206
#define BF_FINE_MXR_IF(val) ((val & 0x00000003) << 0x00000006)
#define BF_FINE_MXR_IF_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_DDC_OVERALL_DECIM_ADDR 0x00000284
#define BF_DDC_OVERALL_DECIM_INFO 0x00000800
#define BF_DDC_OVERALL_DECIM(val) (val & 0x000000FF)
#define BF_DDC_OVERALL_DECIM_GET(val) (val & 0x000000FF)
#define REG_COARSE_DDC_EN_ADDR 0x00000285
#define BF_COARSE_DDC_EN_INFO 0x00000400
#define BF_COARSE_DDC_EN(val) (val & 0x0000000F)
#define BF_COARSE_DDC_EN_GET(val) (val & 0x0000000F)
#define REG_FINE_DDC_EN_ADDR 0x00000286
#define BF_FINE_DDC_EN_INFO 0x00000800
#define BF_FINE_DDC_EN(val) (val & 0x000000FF)
#define BF_FINE_DDC_EN_GET(val) (val & 0x000000FF)
#define REG_FINE_BYPASS_ADDR 0x00000287
#define BF_FINE_BYPASS_INFO 0x00000800
#define BF_FINE_BYPASS(val) (val & 0x000000FF)
#define BF_FINE_BYPASS_GET(val) (val & 0x000000FF)
#define REG_CHIP_DECIMATION_RATIO_ADDR 0x00000289
#define BF_CHIP_DECIMATION_RATIO_INFO 0x00000800
#define BF_CHIP_DECIMATION_RATIO(val) (val & 0x000000FF)
#define BF_CHIP_DECIMATION_RATIO_GET(val) (val & 0x000000FF)
#define REG_COMMON_HOP_EN_ADDR 0x0000028A
#define BF_COMMON_HOP_EN_INFO 0x00000100
#define BF_COMMON_HOP_EN(val) (val & 0x00000001)
#define BF_COMMON_HOP_EN_GET(val) (val & 0x00000001)
#define REG_CTRL_0_1_SEL_ADDR 0x000002A1
#define BF_DFORMAT_CTRL_BIT_0_SEL_INFO 0x00000400
#define BF_DFORMAT_CTRL_BIT_0_SEL(val) (val & 0x0000000F)
#define BF_DFORMAT_CTRL_BIT_0_SEL_GET(val) (val & 0x0000000F)
#define BF_DFORMAT_CTRL_BIT_1_SEL_INFO 0x00000404
#define BF_DFORMAT_CTRL_BIT_1_SEL(val) ((val & 0x0000000F) << 0x00000004)
#define BF_DFORMAT_CTRL_BIT_1_SEL_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_CTRL_2_SEL_ADDR 0x000002A2
#define BF_DFORMAT_CTRL_BIT_2_SEL_INFO 0x00000400
#define BF_DFORMAT_CTRL_BIT_2_SEL(val) (val & 0x0000000F)
#define BF_DFORMAT_CTRL_BIT_2_SEL_GET(val) (val & 0x0000000F)
#define REG_OUT_FORMAT_SEL_ADDR 0x000002A3
#define BF_DFORMAT_SEL_INFO 0x00000200
#define BF_DFORMAT_SEL(val) (val & 0x00000003)
#define BF_DFORMAT_SEL_GET(val) (val & 0x00000003)
#define BF_DFORMAT_INV_INFO 0x00000102
#define BF_DFORMAT_INV(val) ((val & 0x00000001) << 0x00000002)
#define BF_DFORMAT_INV_GET(val) ((val >> 0x00000002) & 0x00000001)
#define REG_OVR_CLR_0_ADDR 0x000002A4
#define BF_DFORMAT_OVR_CLR_INFO 0x00001000
#define BF_DFORMAT_OVR_CLR(val) (val & 0x0000FFFF)
#define BF_DFORMAT_OVR_CLR_GET(val) (val & 0x0000FFFF)
#define REG_OVR_CLR_1_ADDR 0x000002A5
#define REG_OVR_STATUS_0_ADDR 0x000002A6
#define BF_DFORMAT_OVR_STATUS_INFO 0x00001000
#define BF_DFORMAT_OVR_STATUS(val) (val & 0x0000FFFF)
#define BF_DFORMAT_OVR_STATUS_GET(val) (val & 0x0000FFFF)
#define REG_OVR_STATUS_1_ADDR 0x000002A7
#define REG_OUT_RES_ADDR 0x000002A8
#define BF_DFORMAT_RES_INFO 0x00000400
#define BF_DFORMAT_RES(val) (val & 0x0000000F)
#define BF_DFORMAT_RES_GET(val) (val & 0x0000000F)
#define BF_DFORMAT_FBW_DITHER_EN_INFO 0x00000104
#define BF_DFORMAT_FBW_DITHER_EN(val) ((val & 0x00000001) << 0x00000004)
#define BF_DFORMAT_FBW_DITHER_EN_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_DFORMAT_DDC_DITHER_EN_INFO 0x00000105
#define BF_DFORMAT_DDC_DITHER_EN(val) ((val & 0x00000001) << 0x00000005)
#define BF_DFORMAT_DDC_DITHER_EN_GET(val) ((val >> 0x00000005) & 0x00000001)
#define REG_FD_SEL_0_ADDR 0x000002A9
#define BF_DFORMAT_FD_SEL_INFO 0x00001000
#define BF_DFORMAT_FD_SEL(val) (val & 0x0000FFFF)
#define BF_DFORMAT_FD_SEL_GET(val) (val & 0x0000FFFF)
#define REG_FD_SEL_1_ADDR 0x000002AA
#define REG_FBW_SEL_0_ADDR 0x000002AB
#define BF_DFORMAT_FBW_SEL_INFO 0x00001000
#define BF_DFORMAT_FBW_SEL(val) (val & 0x0000FFFF)
#define BF_DFORMAT_FBW_SEL_GET(val) (val & 0x0000FFFF)
#define REG_FBW_SEL_1_ADDR 0x000002AC
#define REG_TMODE_SEL_0_ADDR 0x000002AD
#define BF_DFORMAT_TMODE_SEL_INFO 0x00001000
#define BF_DFORMAT_TMODE_SEL(val) (val & 0x0000FFFF)
#define BF_DFORMAT_TMODE_SEL_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_SEL_1_ADDR 0x000002AE
#define REG_TMODE_I_CTRL1_ADDR 0x000002B0
#define BF_TMODE_I_PN_SEL_INFO 0x00000400
#define BF_TMODE_I_PN_SEL(val) (val & 0x0000000F)
#define BF_TMODE_I_PN_SEL_GET(val) (val & 0x0000000F)
#define BF_TMODE_I_TYPE_SEL_INFO 0x00000404
#define BF_TMODE_I_TYPE_SEL(val) ((val & 0x0000000F) << 0x00000004)
#define BF_TMODE_I_TYPE_SEL_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_TMODE_I_CTRL2_ADDR 0x000002B1
#define BF_TMODE_I_RES_INFO 0x00000400
#define BF_TMODE_I_RES(val) (val & 0x0000000F)
#define BF_TMODE_I_RES_GET(val) (val & 0x0000000F)
#define BF_TMODE_I_USR_PAT_SEL_INFO 0x00000104
#define BF_TMODE_I_USR_PAT_SEL(val) ((val & 0x00000001) << 0x00000004)
#define BF_TMODE_I_USR_PAT_SEL_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_TMODE_I_FORCE_RST_INFO 0x00000105
#define BF_TMODE_I_FORCE_RST(val) ((val & 0x00000001) << 0x00000005)
#define BF_TMODE_I_FORCE_RST_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_TMODE_I_PN_FORCE_RST_INFO 0x00000106
#define BF_TMODE_I_PN_FORCE_RST(val) ((val & 0x00000001) << 0x00000006)
#define BF_TMODE_I_PN_FORCE_RST_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_TMODE_I_FLUSH_INFO 0x00000107
#define BF_TMODE_I_FLUSH(val) ((val & 0x00000001) << 0x00000007)
#define BF_TMODE_I_FLUSH_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_TMODE_I_USR_PAT0_LSB_ADDR 0x000002B2
#define BF_TMODE_I_USR_PAT0_INFO 0x00001000
#define BF_TMODE_I_USR_PAT0(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT0_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT0_MSB_ADDR 0x000002B3
#define REG_TMODE_I_USR_PAT1_LSB_ADDR 0x000002B4
#define BF_TMODE_I_USR_PAT1_INFO 0x00001000
#define BF_TMODE_I_USR_PAT1(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT1_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT1_MSB_ADDR 0x000002B5
#define REG_TMODE_I_USR_PAT2_LSB_ADDR 0x000002B6
#define BF_TMODE_I_USR_PAT2_INFO 0x00001000
#define BF_TMODE_I_USR_PAT2(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT2_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT2_MSB_ADDR 0x000002B7
#define REG_TMODE_I_USR_PAT3_LSB_ADDR 0x000002B8
#define BF_TMODE_I_USR_PAT3_INFO 0x00001000
#define BF_TMODE_I_USR_PAT3(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT3_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT3_MSB_ADDR 0x000002B9
#define REG_SYNC_CTRL1_ADDR 0x000002BA
#define BF_DP_CLK_FORCEN_INFO 0x00000100
#define BF_DP_CLK_FORCEN(val) (val & 0x00000001)
#define BF_DP_CLK_FORCEN_GET(val) (val & 0x00000001)
#define BF_RISEDGE_SYSREF_INFO 0x00000101
#define BF_RISEDGE_SYSREF(val) ((val & 0x00000001) << 0x00000001)
#define BF_RISEDGE_SYSREF_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_SYSREF_RESYNC_MODE_INFO 0x00000102
#define BF_SYSREF_RESYNC_MODE(val) ((val & 0x00000001) << 0x00000002)
#define BF_SYSREF_RESYNC_MODE_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_NCORESET_ALL_SYSREF_INFO 0x00000103
#define BF_NCORESET_ALL_SYSREF(val) ((val & 0x00000001) << 0x00000003)
#define BF_NCORESET_ALL_SYSREF_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_ALLOW_SYSREFMASK_INFO 0x00000104
#define BF_ALLOW_SYSREFMASK(val) ((val & 0x00000001) << 0x00000004)
#define BF_ALLOW_SYSREFMASK_GET(val) ((val >> 0x00000004) & 0x00000001)
#define REG_TRIG_PROG_DELAY_ADDR 0x000002BB
#define BF_TRIG_PROG_DELAY_INFO 0x00000800
#define BF_TRIG_PROG_DELAY(val) (val & 0x000000FF)
#define BF_TRIG_PROG_DELAY_GET(val) (val & 0x000000FF)
#define REG_SYSREF_PROG_DELAY_ADDR 0x000002BC
#define BF_SYSREF_PROG_DELAY_INFO 0x00000800
#define BF_SYSREF_PROG_DELAY(val) (val & 0x000000FF)
#define BF_SYSREF_PROG_DELAY_GET(val) (val & 0x000000FF)
#define REG_TRIG_CTRL_ADDR 0x000002BD
#define BF_GPIO_TRIG_EN_INFO 0x00000100
#define BF_GPIO_TRIG_EN(val) (val & 0x00000001)
#define BF_GPIO_TRIG_EN_GET(val) (val & 0x00000001)
#define BF_MASTERTRIG_EN_INFO 0x00000101
#define BF_MASTERTRIG_EN(val) ((val & 0x00000001) << 0x00000001)
#define BF_MASTERTRIG_EN_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_LOOPBACK_MASTERTRIG_INFO 0x00000102
#define BF_LOOPBACK_MASTERTRIG(val) ((val & 0x00000001) << 0x00000002)
#define BF_LOOPBACK_MASTERTRIG_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_RESYNC_AFTER_TRIG_INFO 0x00000103
#define BF_RESYNC_AFTER_TRIG(val) ((val & 0x00000001) << 0x00000003)
#define BF_RESYNC_AFTER_TRIG_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_GPIOTRIG_SYNCEN_INFO 0x00000104
#define BF_GPIOTRIG_SYNCEN(val) ((val & 0x00000001) << 0x00000004)
#define BF_GPIOTRIG_SYNCEN_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_GPIOTRIG_DEGLITCH_INFO 0x00000105
#define BF_GPIOTRIG_DEGLITCH(val) ((val & 0x00000001) << 0x00000005)
#define BF_GPIOTRIG_DEGLITCH_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_RISEDGE_TRIG_INFO 0x00000106
#define BF_RISEDGE_TRIG(val) ((val & 0x00000001) << 0x00000006)
#define BF_RISEDGE_TRIG_GET(val) ((val >> 0x00000006) & 0x00000001)
#define REG_I_PHASEMAX_POSTSRC_STATUS_LSB_ADDR 0x000002C2
#define BF_I_PHASEMAX_POSTSRC_STATUS_INFO 0x00000C00
#define BF_I_PHASEMAX_POSTSRC_STATUS(val) (val & 0x00000FFF)
#define BF_I_PHASEMAX_POSTSRC_STATUS_GET(val) (val & 0x00000FFF)
#define REG_I_PHASEMAX_POSTSRC_STATUS_MSB_ADDR 0x000002C3
#define REG_I_PHASEMAX_PRESRC_STATUS_LSB_ADDR 0x000002C4
#define BF_I_PHASEMAX_PRESRC_STATUS_INFO 0x00000C00
#define BF_I_PHASEMAX_PRESRC_STATUS(val) (val & 0x00000FFF)
#define BF_I_PHASEMAX_PRESRC_STATUS_GET(val) (val & 0x00000FFF)
#define REG_I_PHASEMAX_PRESRC_STATUS_MSB_ADDR 0x000002C5
#define REG_RXEN0_SEL0_ADDR 0x000002C6
#define BF_RXEN0_FDDC_SEL_INFO 0x00000800
#define BF_RXEN0_FDDC_SEL(val) (val & 0x000000FF)
#define BF_RXEN0_FDDC_SEL_GET(val) (val & 0x000000FF)
#define REG_RXEN0_SEL1_ADDR 0x000002C7
#define BF_RXEN0_CDDC_SEL_INFO 0x00000400
#define BF_RXEN0_CDDC_SEL(val) (val & 0x0000000F)
#define BF_RXEN0_CDDC_SEL_GET(val) (val & 0x0000000F)
#define BF_RXEN0_JTXL_SEL_INFO 0x00000204
#define BF_RXEN0_JTXL_SEL(val) ((val & 0x00000003) << 0x00000004)
#define BF_RXEN0_JTXL_SEL_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_RXEN0_ADC_SEL_INFO 0x00000206
#define BF_RXEN0_ADC_SEL(val) ((val & 0x00000003) << 0x00000006)
#define BF_RXEN0_ADC_SEL_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_RXEN0_SEL2_ADDR 0x000002C8
#define BF_RXEN0_JTXPHY_SEL_INFO 0x00000800
#define BF_RXEN0_JTXPHY_SEL(val) (val & 0x000000FF)
#define BF_RXEN0_JTXPHY_SEL_GET(val) (val & 0x000000FF)
#define REG_RXEN1_SEL0_ADDR 0x000002C9
#define BF_RXEN1_FDDC_SEL_INFO 0x00000800
#define BF_RXEN1_FDDC_SEL(val) (val & 0x000000FF)
#define BF_RXEN1_FDDC_SEL_GET(val) (val & 0x000000FF)
#define REG_RXEN1_SEL1_ADDR 0x000002CA
#define BF_RXEN1_CDDC_SEL_INFO 0x00000400
#define BF_RXEN1_CDDC_SEL(val) (val & 0x0000000F)
#define BF_RXEN1_CDDC_SEL_GET(val) (val & 0x0000000F)
#define BF_RXEN1_JTXL_SEL_INFO 0x00000204
#define BF_RXEN1_JTXL_SEL(val) ((val & 0x00000003) << 0x00000004)
#define BF_RXEN1_JTXL_SEL_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_RXEN1_ADC_SEL_INFO 0x00000206
#define BF_RXEN1_ADC_SEL(val) ((val & 0x00000003) << 0x00000006)
#define BF_RXEN1_ADC_SEL_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_RXEN1_SEL2_ADDR 0x000002CB
#define BF_RXEN1_JTXPHY_SEL_INFO 0x00000800
#define BF_RXEN1_JTXPHY_SEL(val) (val & 0x000000FF)
#define BF_RXEN1_JTXPHY_SEL_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_STATUS_SEL_ADDR 0x000002CC
#define BF_FINE_DDC_I_STATUS_SEL_INFO 0x00000200
#define BF_FINE_DDC_I_STATUS_SEL(val) (val & 0x00000003)
#define BF_FINE_DDC_I_STATUS_SEL_GET(val) (val & 0x00000003)
#define BF_FINE_DDC_Q_STATUS_SEL_INFO 0x00000202
#define BF_FINE_DDC_Q_STATUS_SEL(val) ((val & 0x00000003) << 0x00000002)
#define BF_FINE_DDC_Q_STATUS_SEL_GET(val) ((val >> 0x00000002) & 0x00000003)
#define REG_FD_EQ_STATUS_SEL_ADDR 0x000002CD
#define BF_FD_EQ_I_STATUS_SEL_INFO 0x00000200
#define BF_FD_EQ_I_STATUS_SEL(val) (val & 0x00000003)
#define BF_FD_EQ_I_STATUS_SEL_GET(val) (val & 0x00000003)
#define BF_FD_EQ_Q_STATUS_SEL_INFO 0x00000202
#define BF_FD_EQ_Q_STATUS_SEL(val) ((val & 0x00000003) << 0x00000002)
#define BF_FD_EQ_Q_STATUS_SEL_GET(val) ((val >> 0x00000002) & 0x00000003)
#define REG_RXENGP0_SEL0_ADDR 0x000002CE
#define BF_RXENGP0_FDDC_SEL_INFO 0x00000800
#define BF_RXENGP0_FDDC_SEL(val) (val & 0x000000FF)
#define BF_RXENGP0_FDDC_SEL_GET(val) (val & 0x000000FF)
#define REG_RXENGP0_SEL1_ADDR 0x000002CF
#define BF_RXENGP0_CDDC_SEL_INFO 0x00000400
#define BF_RXENGP0_CDDC_SEL(val) (val & 0x0000000F)
#define BF_RXENGP0_CDDC_SEL_GET(val) (val & 0x0000000F)
#define BF_RXENGP0_JTXL_SEL_INFO 0x00000204
#define BF_RXENGP0_JTXL_SEL(val) ((val & 0x00000003) << 0x00000004)
#define BF_RXENGP0_JTXL_SEL_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_RXENGP0_ADC_SEL_INFO 0x00000206
#define BF_RXENGP0_ADC_SEL(val) ((val & 0x00000003) << 0x00000006)
#define BF_RXENGP0_ADC_SEL_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_RXENGP0_SEL2_ADDR 0x000002D0
#define BF_RXENGP0_JTXPHY_SEL_INFO 0x00000800
#define BF_RXENGP0_JTXPHY_SEL(val) (val & 0x000000FF)
#define BF_RXENGP0_JTXPHY_SEL_GET(val) (val & 0x000000FF)
#define REG_RXENGP1_SEL0_ADDR 0x000002D1
#define BF_RXENGP1_FDDC_SEL_INFO 0x00000800
#define BF_RXENGP1_FDDC_SEL(val) (val & 0x000000FF)
#define BF_RXENGP1_FDDC_SEL_GET(val) (val & 0x000000FF)
#define REG_RXENGP1_SEL1_ADDR 0x000002D2
#define BF_RXENGP1_CDDC_SEL_INFO 0x00000400
#define BF_RXENGP1_CDDC_SEL(val) (val & 0x0000000F)
#define BF_RXENGP1_CDDC_SEL_GET(val) (val & 0x0000000F)
#define BF_RXENGP1_JTXL_SEL_INFO 0x00000204
#define BF_RXENGP1_JTXL_SEL(val) ((val & 0x00000003) << 0x00000004)
#define BF_RXENGP1_JTXL_SEL_GET(val) ((val >> 0x00000004) & 0x00000003)
#define BF_RXENGP1_ADC_SEL_INFO 0x00000206
#define BF_RXENGP1_ADC_SEL(val) ((val & 0x00000003) << 0x00000006)
#define BF_RXENGP1_ADC_SEL_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_RXENGP1_SEL2_ADDR 0x000002D3
#define BF_RXENGP1_JTXPHY_SEL_INFO 0x00000800
#define BF_RXENGP1_JTXPHY_SEL(val) (val & 0x000000FF)
#define BF_RXENGP1_JTXPHY_SEL_GET(val) (val & 0x000000FF)
#define REG_TMODE_Q_CTRL1_ADDR 0x000002D4
#define BF_TMODE_Q_PN_SEL_INFO 0x00000400
#define BF_TMODE_Q_PN_SEL(val) (val & 0x0000000F)
#define BF_TMODE_Q_PN_SEL_GET(val) (val & 0x0000000F)
#define BF_TMODE_Q_TYPE_SEL_INFO 0x00000404
#define BF_TMODE_Q_TYPE_SEL(val) ((val & 0x0000000F) << 0x00000004)
#define BF_TMODE_Q_TYPE_SEL_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_TMODE_Q_CTRL2_ADDR 0x000002D5
#define BF_TMODE_Q_RES_INFO 0x00000400
#define BF_TMODE_Q_RES(val) (val & 0x0000000F)
#define BF_TMODE_Q_RES_GET(val) (val & 0x0000000F)
#define BF_TMODE_Q_USR_PAT_SEL_INFO 0x00000104
#define BF_TMODE_Q_USR_PAT_SEL(val) ((val & 0x00000001) << 0x00000004)
#define BF_TMODE_Q_USR_PAT_SEL_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_TMODE_Q_FORCE_RST_INFO 0x00000105
#define BF_TMODE_Q_FORCE_RST(val) ((val & 0x00000001) << 0x00000005)
#define BF_TMODE_Q_FORCE_RST_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_TMODE_Q_PN_FORCE_RST_INFO 0x00000106
#define BF_TMODE_Q_PN_FORCE_RST(val) ((val & 0x00000001) << 0x00000006)
#define BF_TMODE_Q_PN_FORCE_RST_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_TMODE_Q_FLUSH_INFO 0x00000107
#define BF_TMODE_Q_FLUSH(val) ((val & 0x00000001) << 0x00000007)
#define BF_TMODE_Q_FLUSH_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_TMODE_Q_USR_PAT0_LSB_ADDR 0x000002D6
#define BF_TMODE_Q_USR_PAT0_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT0(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT0_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT0_MSB_ADDR 0x000002D7
#define REG_TMODE_Q_USR_PAT1_LSB_ADDR 0x000002D8
#define BF_TMODE_Q_USR_PAT1_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT1(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT1_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT1_MSB_ADDR 0x000002D9
#define REG_TMODE_Q_USR_PAT2_LSB_ADDR 0x000002DA
#define BF_TMODE_Q_USR_PAT2_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT2(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT2_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT2_MSB_ADDR 0x000002DB
#define REG_TMODE_Q_USR_PAT3_LSB_ADDR 0x000002DC
#define BF_TMODE_Q_USR_PAT3_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT3(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT3_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT3_MSB_ADDR 0x000002DD
#define REG_ADC_MODES_ADDR 0x000002E4
#define BF_ADC0_ADC1_MODES_INFO 0x00000300
#define BF_ADC0_ADC1_MODES(val) (val & 0x00000007)
#define BF_ADC0_ADC1_MODES_GET(val) (val & 0x00000007)
#define BF_ADC2_ADC3_MODES_INFO 0x00000303
#define BF_ADC2_ADC3_MODES(val) ((val & 0x00000007) << 0x00000003)
#define BF_ADC2_ADC3_MODES_GET(val) ((val >> 0x00000003) & 0x00000007)
#define BF_QUAD_MODES_INFO 0x00000206
#define BF_QUAD_MODES(val) ((val & 0x00000003) << 0x00000006)
#define BF_QUAD_MODES_GET(val) ((val >> 0x00000006) & 0x00000003)
#define REG_HEAD_ROOM_GROWTH_ADDR 0x000002E8
#define BF_HEAD_ROOM_INFO 0x00000400
#define BF_HEAD_ROOM(val) (val & 0x0000000F)
#define BF_HEAD_ROOM_GET(val) (val & 0x0000000F)
#define REG_COARSE_FSRC_EN_ADDR 0x000002E9
#define BF_COARSE_FSRC_EN_INFO 0x00000400
#define BF_COARSE_FSRC_EN(val) (val & 0x0000000F)
#define BF_COARSE_FSRC_EN_GET(val) (val & 0x0000000F)
#define REG_TMODE_I_USR_PAT4_LSB_ADDR 0x000002EA
#define BF_TMODE_I_USR_PAT4_INFO 0x00001000
#define BF_TMODE_I_USR_PAT4(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT4_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT4_MSB_ADDR 0x000002EB
#define REG_TMODE_I_USR_PAT5_LSB_ADDR 0x000002EC
#define BF_TMODE_I_USR_PAT5_INFO 0x00001000
#define BF_TMODE_I_USR_PAT5(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT5_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT5_MSB_ADDR 0x000002ED
#define REG_TMODE_I_USR_PAT6_LSB_ADDR 0x000002EE
#define BF_TMODE_I_USR_PAT6_INFO 0x00001000
#define BF_TMODE_I_USR_PAT6(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT6_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT6_MSB_ADDR 0x000002EF
#define REG_TMODE_I_USR_PAT7_LSB_ADDR 0x000002F0
#define BF_TMODE_I_USR_PAT7_INFO 0x00001000
#define BF_TMODE_I_USR_PAT7(val) (val & 0x0000FFFF)
#define BF_TMODE_I_USR_PAT7_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_I_USR_PAT7_MSB_ADDR 0x000002F1
#define REG_TMODE_Q_USR_PAT4_LSB_ADDR 0x000002F2
#define BF_TMODE_Q_USR_PAT4_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT4(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT4_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT4_MSB_ADDR 0x000002F3
#define REG_TMODE_Q_USR_PAT5_LSB_ADDR 0x000002F4
#define BF_TMODE_Q_USR_PAT5_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT5(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT5_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT5_MSB_ADDR 0x000002F5
#define REG_TMODE_Q_USR_PAT6_LSB_ADDR 0x000002F6
#define BF_TMODE_Q_USR_PAT6_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT6(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT6_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT6_MSB_ADDR 0x000002F7
#define REG_TMODE_Q_USR_PAT7_LSB_ADDR 0x000002F8
#define BF_TMODE_Q_USR_PAT7_INFO 0x00001000
#define BF_TMODE_Q_USR_PAT7(val) (val & 0x0000FFFF)
#define BF_TMODE_Q_USR_PAT7_GET(val) (val & 0x0000FFFF)
#define REG_TMODE_Q_USR_PAT7_MSB_ADDR 0x000002F9
#define REG_RXEN_CTRL_ADDR 0x000002FA
#define BF_RXEN0_USETXEN_INFO 0x00000100
#define BF_RXEN0_USETXEN(val) (val & 0x00000001)
#define BF_RXEN0_USETXEN_GET(val) (val & 0x00000001)
#define BF_RXEN1_USETXEN_INFO 0x00000101
#define BF_RXEN1_USETXEN(val) ((val & 0x00000001) << 0x00000001)
#define BF_RXEN1_USETXEN_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_RXEN0_POL_INFO 0x00000102
#define BF_RXEN0_POL(val) ((val & 0x00000001) << 0x00000002)
#define BF_RXEN0_POL_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_RXEN1_POL_INFO 0x00000103
#define BF_RXEN1_POL(val) ((val & 0x00000001) << 0x00000003)
#define BF_RXEN1_POL_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_RXENGP0_POL_INFO 0x00000104
#define BF_RXENGP0_POL(val) ((val & 0x00000001) << 0x00000004)
#define BF_RXENGP0_POL_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_RXENGP1_POL_INFO 0x00000105
#define BF_RXENGP1_POL(val) ((val & 0x00000001) << 0x00000005)
#define BF_RXENGP1_POL_GET(val) ((val >> 0x00000005) & 0x00000001)
#define REG_RXEN_SPI_CTRL_ADDR 0x000002FB
#define BF_RXEN0_SPIEN_INFO 0x00000100
#define BF_RXEN0_SPIEN(val) (val & 0x00000001)
#define BF_RXEN0_SPIEN_GET(val) (val & 0x00000001)
#define BF_RXEN1_SPIEN_INFO 0x00000101
#define BF_RXEN1_SPIEN(val) ((val & 0x00000001) << 0x00000001)
#define BF_RXEN1_SPIEN_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_RXENGP0_SPIEN_INFO 0x00000102
#define BF_RXENGP0_SPIEN(val) ((val & 0x00000001) << 0x00000002)
#define BF_RXENGP0_SPIEN_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_RXENGP1_SPIEN_INFO 0x00000103
#define BF_RXENGP1_SPIEN(val) ((val & 0x00000001) << 0x00000003)
#define BF_RXENGP1_SPIEN_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_RXEN0_SPI_INFO 0x00000104
#define BF_RXEN0_SPI(val) ((val & 0x00000001) << 0x00000004)
#define BF_RXEN0_SPI_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_RXEN1_SPI_INFO 0x00000105
#define BF_RXEN1_SPI(val) ((val & 0x00000001) << 0x00000005)
#define BF_RXEN1_SPI_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_RXENGP0_SPI_INFO 0x00000106
#define BF_RXENGP0_SPI(val) ((val & 0x00000001) << 0x00000006)
#define BF_RXENGP0_SPI_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_RXENGP1_SPI_INFO 0x00000107
#define BF_RXENGP1_SPI(val) ((val & 0x00000001) << 0x00000007)
#define BF_RXENGP1_SPI_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_RXEN_NOVALP_CTRL1_ADDR 0x000002FC
#define BF_RXEN0_0S_CTRL_INFO 0x00000100
#define BF_RXEN0_0S_CTRL(val) (val & 0x00000001)
#define BF_RXEN0_0S_CTRL_GET(val) (val & 0x00000001)
#define BF_RXENGP0_0S_CTRL_INFO 0x00000101
#define BF_RXENGP0_0S_CTRL(val) ((val & 0x00000001) << 0x00000001)
#define BF_RXENGP0_0S_CTRL_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_RXEN1_1S_CTRL_INFO 0x00000102
#define BF_RXEN1_1S_CTRL(val) ((val & 0x00000001) << 0x00000002)
#define BF_RXEN1_1S_CTRL_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_RXENGP1_1S_CTRL_INFO 0x00000103
#define BF_RXENGP1_1S_CTRL(val) ((val & 0x00000001) << 0x00000003)
#define BF_RXENGP1_1S_CTRL_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_RXEN0_0F_CTRL_INFO 0x00000104
#define BF_RXEN0_0F_CTRL(val) ((val & 0x00000001) << 0x00000004)
#define BF_RXEN0_0F_CTRL_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_RXENGP0_0F_CTRL_INFO 0x00000105
#define BF_RXENGP0_0F_CTRL(val) ((val & 0x00000001) << 0x00000005)
#define BF_RXENGP0_0F_CTRL_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_RXEN1_1F_CTRL_INFO 0x00000106
#define BF_RXEN1_1F_CTRL(val) ((val & 0x00000001) << 0x00000006)
#define BF_RXEN1_1F_CTRL_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_RXENGP1_1F_CTRL_INFO 0x00000107
#define BF_RXENGP1_1F_CTRL(val) ((val & 0x00000001) << 0x00000007)
#define BF_RXENGP1_1F_CTRL_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_RXEN_NOVALP_CTRL2_ADDR 0x000002FD
#define BF_RXEN0_2S_CTRL_INFO 0x00000100
#define BF_RXEN0_2S_CTRL(val) (val & 0x00000001)
#define BF_RXEN0_2S_CTRL_GET(val) (val & 0x00000001)
#define BF_RXENGP0_2S_CTRL_INFO 0x00000101
#define BF_RXENGP0_2S_CTRL(val) ((val & 0x00000001) << 0x00000001)
#define BF_RXENGP0_2S_CTRL_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_RXEN1_3S_CTRL_INFO 0x00000102
#define BF_RXEN1_3S_CTRL(val) ((val & 0x00000001) << 0x00000002)
#define BF_RXEN1_3S_CTRL_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_RXENGP1_3S_CTRL_INFO 0x00000103
#define BF_RXENGP1_3S_CTRL(val) ((val & 0x00000001) << 0x00000003)
#define BF_RXENGP1_3S_CTRL_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_RXEN0_2F_CTRL_INFO 0x00000104
#define BF_RXEN0_2F_CTRL(val) ((val & 0x00000001) << 0x00000004)
#define BF_RXEN0_2F_CTRL_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_RXENGP0_2F_CTRL_INFO 0x00000105
#define BF_RXENGP0_2F_CTRL(val) ((val & 0x00000001) << 0x00000005)
#define BF_RXENGP0_2F_CTRL_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_RXEN1_3F_CTRL_INFO 0x00000106
#define BF_RXEN1_3F_CTRL(val) ((val & 0x00000001) << 0x00000006)
#define BF_RXEN1_3F_CTRL_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_RXENGP1_3F_CTRL_INFO 0x00000107
#define BF_RXENGP1_3F_CTRL(val) ((val & 0x00000001) << 0x00000007)
#define BF_RXENGP1_3F_CTRL_GET(val) ((val >> 0x00000007) & 0x00000001)
#endif /* __ADI_AD9081_BF_NB_DDC_DFORMAT_H__ */
/*! @} */

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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_nb_fine_nco.h Executable file
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/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:26 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_NB_FINE_NCO_H__
#define __ADI_AD9081_BF_NB_FINE_NCO_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_FINE_DDC_SYNC_CTRL_ADDR 0x00000A80
#define BF_FINE_DDC_SYNC_EN_INFO 0x00000100
#define BF_FINE_DDC_SYNC_EN(val) (val & 0x00000001)
#define BF_FINE_DDC_SYNC_EN_GET(val) (val & 0x00000001)
#define BF_FINE_DDC_SYNC_NEXT_INFO 0x00000101
#define BF_FINE_DDC_SYNC_NEXT(val) ((val & 0x00000001) << 0x00000001)
#define BF_FINE_DDC_SYNC_NEXT_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_FINE_DDC_SOFT_RESET_INFO 0x00000104
#define BF_FINE_DDC_SOFT_RESET(val) ((val & 0x00000001) << 0x00000004)
#define BF_FINE_DDC_SOFT_RESET_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_FINE_DDC_TRIG_NCO_RESET_EN_INFO 0x00000107
#define BF_FINE_DDC_TRIG_NCO_RESET_EN(val) ((val & 0x00000001) << 0x00000007)
#define BF_FINE_DDC_TRIG_NCO_RESET_EN_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_FINE_DDC_SYNC_STATUS_ADDR 0x00000A81
#define BF_FINE_DDC_SYNC_EN_CLEAR_INFO 0x00000100
#define BF_FINE_DDC_SYNC_EN_CLEAR(val) (val & 0x00000001)
#define BF_FINE_DDC_SYNC_EN_CLEAR_GET(val) (val & 0x00000001)
#define REG_FINE_DDC_TRIG_CTRL_ADDR 0x00000A82
#define BF_FINE_DDC_TRIG_HOP_EN_INFO 0x00000100
#define BF_FINE_DDC_TRIG_HOP_EN(val) (val & 0x00000001)
#define BF_FINE_DDC_TRIG_HOP_EN_GET(val) (val & 0x00000001)
#define REG_FINE_DDC_NCO_CTRL_ADDR 0x00000A83
#define BF_FINE_DDC0_NCO_REGMAP_CHAN_SEL_INFO 0x00000400
#define BF_FINE_DDC0_NCO_REGMAP_CHAN_SEL(val) (val & 0x0000000F)
#define BF_FINE_DDC0_NCO_REGMAP_CHAN_SEL_GET(val) (val & 0x0000000F)
#define BF_FINE_DDC0_NCO_CHAN_SEL_MODE_INFO 0x00000404
#define BF_FINE_DDC0_NCO_CHAN_SEL_MODE(val) ((val & 0x0000000F) << 0x00000004)
#define BF_FINE_DDC0_NCO_CHAN_SEL_MODE_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_FINE_DDC_PROFILE_CTRL_ADDR 0x00000A84
#define BF_FINE_DDC0_PROFILE_UPDATE_INDEX_INFO 0x00000400
#define BF_FINE_DDC0_PROFILE_UPDATE_INDEX(val) (val & 0x0000000F)
#define BF_FINE_DDC0_PROFILE_UPDATE_INDEX_GET(val) (val & 0x0000000F)
#define BF_FINE_DDC0_GPIO_CHIP_TRANSFER_MODE_INFO 0x00000106
#define BF_FINE_DDC0_GPIO_CHIP_TRANSFER_MODE(val) ((val & 0x00000001) << 0x00000006)
#define BF_FINE_DDC0_GPIO_CHIP_TRANSFER_MODE_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_FINE_DDC0_PROFILE_UPDATE_MODE_INFO 0x00000107
#define BF_FINE_DDC0_PROFILE_UPDATE_MODE(val) ((val & 0x00000001) << 0x00000007)
#define BF_FINE_DDC0_PROFILE_UPDATE_MODE_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_FINE_DDC_PHASE_INC0_ADDR 0x00000A85
#define BF_FINE_DDC0_PHASE_INC0_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC0(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC0_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC1_ADDR 0x00000A86
#define BF_FINE_DDC0_PHASE_INC1_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC1(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC1_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC2_ADDR 0x00000A87
#define BF_FINE_DDC0_PHASE_INC2_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC2(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC2_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC3_ADDR 0x00000A88
#define BF_FINE_DDC0_PHASE_INC3_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC3(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC3_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC4_ADDR 0x00000A89
#define BF_FINE_DDC0_PHASE_INC4_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC4(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC4_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC5_ADDR 0x00000A8A
#define BF_FINE_DDC0_PHASE_INC5_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC5(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC5_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_OFFSET0_ADDR 0x00000A8B
#define BF_FINE_DDC0_PHASE_OFFSET0_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_OFFSET0(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_OFFSET0_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_OFFSET1_ADDR 0x00000A8C
#define BF_FINE_DDC0_PHASE_OFFSET1_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_OFFSET1(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_OFFSET1_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_OFFSET2_ADDR 0x00000A8D
#define BF_FINE_DDC0_PHASE_OFFSET2_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_OFFSET2(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_OFFSET2_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_OFFSET3_ADDR 0x00000A8E
#define BF_FINE_DDC0_PHASE_OFFSET3_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_OFFSET3(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_OFFSET3_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_OFFSET4_ADDR 0x00000A8F
#define BF_FINE_DDC0_PHASE_OFFSET4_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_OFFSET4(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_OFFSET4_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_OFFSET5_ADDR 0x00000A90
#define BF_FINE_DDC0_PHASE_OFFSET5_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_OFFSET5(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_OFFSET5_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_A0_ADDR 0x00000A91
#define BF_FINE_DDC0_PHASE_INC_FRAC_A0_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_A0(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_A0_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_A1_ADDR 0x00000A92
#define BF_FINE_DDC0_PHASE_INC_FRAC_A1_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_A1(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_A1_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_A2_ADDR 0x00000A93
#define BF_FINE_DDC0_PHASE_INC_FRAC_A2_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_A2(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_A2_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_A3_ADDR 0x00000A94
#define BF_FINE_DDC0_PHASE_INC_FRAC_A3_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_A3(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_A3_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_A4_ADDR 0x00000A95
#define BF_FINE_DDC0_PHASE_INC_FRAC_A4_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_A4(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_A4_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_A5_ADDR 0x00000A96
#define BF_FINE_DDC0_PHASE_INC_FRAC_A5_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_A5(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_A5_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_B0_ADDR 0x00000A97
#define BF_FINE_DDC0_PHASE_INC_FRAC_B0_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_B0(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_B0_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_B1_ADDR 0x00000A98
#define BF_FINE_DDC0_PHASE_INC_FRAC_B1_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_B1(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_B1_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_B2_ADDR 0x00000A99
#define BF_FINE_DDC0_PHASE_INC_FRAC_B2_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_B2(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_B2_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_B3_ADDR 0x00000A9A
#define BF_FINE_DDC0_PHASE_INC_FRAC_B3_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_B3(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_B3_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_B4_ADDR 0x00000A9B
#define BF_FINE_DDC0_PHASE_INC_FRAC_B4_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_B4(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_B4_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PHASE_INC_FRAC_B5_ADDR 0x00000A9C
#define BF_FINE_DDC0_PHASE_INC_FRAC_B5_INFO 0x00000800
#define BF_FINE_DDC0_PHASE_INC_FRAC_B5(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PHASE_INC_FRAC_B5_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_TRANSFER_STATUS_ADDR 0x00000A9D
#define BF_FINE_DDC0_CHIP_TRANSFER_STATUS_INFO 0x00000100
#define BF_FINE_DDC0_CHIP_TRANSFER_STATUS(val) (val & 0x00000001)
#define BF_FINE_DDC0_CHIP_TRANSFER_STATUS_GET(val) (val & 0x00000001)
#define REG_FINE_DDC_DITHER_ADDR 0x00000A9E
#define BF_FINE_DDC0_AMP_DITHER_EN_INFO 0x00000100
#define BF_FINE_DDC0_AMP_DITHER_EN(val) (val & 0x00000001)
#define BF_FINE_DDC0_AMP_DITHER_EN_GET(val) (val & 0x00000001)
#define BF_FINE_DDC0_PHASE_DITHER_EN_INFO 0x00000101
#define BF_FINE_DDC0_PHASE_DITHER_EN(val) ((val & 0x00000001) << 0x00000001)
#define BF_FINE_DDC0_PHASE_DITHER_EN_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_FINE_DDC_TRANSFER_CTRL_ADDR 0x00000A9F
#define BF_FINE_DDC0_CHIP_TRANSFER_INFO 0x00000100
#define BF_FINE_DDC0_CHIP_TRANSFER(val) (val & 0x00000001)
#define BF_FINE_DDC0_CHIP_TRANSFER_GET(val) (val & 0x00000001)
#define REG_FINE_DDC_PSW_0_ADDR 0x00000AA0
#define BF_FINE_DDC0_PSW0_INFO 0x00000800
#define BF_FINE_DDC0_PSW0(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PSW0_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PSW_1_ADDR 0x00000AA1
#define BF_FINE_DDC0_PSW1_INFO 0x00000800
#define BF_FINE_DDC0_PSW1(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PSW1_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PSW_2_ADDR 0x00000AA2
#define BF_FINE_DDC0_PSW2_INFO 0x00000800
#define BF_FINE_DDC0_PSW2(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PSW2_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PSW_3_ADDR 0x00000AA3
#define BF_FINE_DDC0_PSW3_INFO 0x00000800
#define BF_FINE_DDC0_PSW3(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PSW3_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PSW_4_ADDR 0x00000AA4
#define BF_FINE_DDC0_PSW4_INFO 0x00000800
#define BF_FINE_DDC0_PSW4(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PSW4_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_PSW_5_ADDR 0x00000AA5
#define BF_FINE_DDC0_PSW5_INFO 0x00000800
#define BF_FINE_DDC0_PSW5(val) (val & 0x000000FF)
#define BF_FINE_DDC0_PSW5_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_INC0_ADDR 0x00000AA6
#define BF_FINE_DDC0_ACTIVE_PHASE_INC0_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_INC0(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_INC0_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_INC1_ADDR 0x00000AA7
#define BF_FINE_DDC0_ACTIVE_PHASE_INC1_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_INC1(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_INC1_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_INC2_ADDR 0x00000AA8
#define BF_FINE_DDC0_ACTIVE_PHASE_INC2_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_INC2(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_INC2_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_INC3_ADDR 0x00000AA9
#define BF_FINE_DDC0_ACTIVE_PHASE_INC3_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_INC3(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_INC3_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_INC4_ADDR 0x00000AAA
#define BF_FINE_DDC0_ACTIVE_PHASE_INC4_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_INC4(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_INC4_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_INC5_ADDR 0x00000AAB
#define BF_FINE_DDC0_ACTIVE_PHASE_INC5_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_INC5(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_INC5_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_OFFSET0_ADDR 0x00000AAC
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET0_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET0(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET0_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_OFFSET1_ADDR 0x00000AAD
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET1_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET1(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET1_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_OFFSET2_ADDR 0x00000AAE
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET2_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET2(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET2_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_OFFSET3_ADDR 0x00000AAF
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET3_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET3(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET3_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_OFFSET4_ADDR 0x00000AB0
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET4_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET4(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET4_GET(val) (val & 0x000000FF)
#define REG_FINE_DDC_ACTIVE_PHASE_OFFSET5_ADDR 0x00000AB1
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET5_INFO 0x00000800
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET5(val) (val & 0x000000FF)
#define BF_FINE_DDC0_ACTIVE_PHASE_OFFSET5_GET(val) (val & 0x000000FF)
#define REG_FINE_TIMESTAMP_COUNTER_REG0_ADDR 0x00000AB2
#define BF_FINE_TIMESTAMP_INFO 0x00003000
#define REG_FINE_TIMESTAMP_COUNTER_REG1_ADDR 0x00000AB3
#define REG_FINE_TIMESTAMP_COUNTER_REG2_ADDR 0x00000AB4
#define REG_FINE_TIMESTAMP_COUNTER_REG3_ADDR 0x00000AB5
#define REG_FINE_TIMESTAMP_COUNTER_REG4_ADDR 0x00000AB6
#define REG_FINE_TIMESTAMP_COUNTER_REG5_ADDR 0x00000AB7
#define REG_FINE_TIMESTAMP_READ_CTRL_ADDR 0x00000AB8
#define BF_FINE_TIMESTAMP_READ_ENABLE_INFO 0x00000100
#define BF_FINE_TIMESTAMP_READ_ENABLE(val) (val & 0x00000001)
#define BF_FINE_TIMESTAMP_READ_ENABLE_GET(val) (val & 0x00000001)
#endif /* __ADI_AD9081_BF_NB_FINE_NCO_H__ */
/*! @} */

106
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_rx_paging.h Executable file
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/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:30 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_RX_PAGING_H__
#define __ADI_AD9081_BF_RX_PAGING_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_ADC_COARSE_PAGE_ADDR 0x00000018
#define BF_ADC0_PAGE_INFO 0x00000100
#define BF_ADC0_PAGE(val) (val & 0x00000001)
#define BF_ADC0_PAGE_GET(val) (val & 0x00000001)
#define BF_ADC1_PAGE_INFO 0x00000101
#define BF_ADC1_PAGE(val) ((val & 0x00000001) << 0x00000001)
#define BF_ADC1_PAGE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_ADC2_PAGE_INFO 0x00000102
#define BF_ADC2_PAGE(val) ((val & 0x00000001) << 0x00000002)
#define BF_ADC2_PAGE_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_ADC3_PAGE_INFO 0x00000103
#define BF_ADC3_PAGE(val) ((val & 0x00000001) << 0x00000003)
#define BF_ADC3_PAGE_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_COARSE_DDC0_PAGE_INFO 0x00000104
#define BF_COARSE_DDC0_PAGE(val) ((val & 0x00000001) << 0x00000004)
#define BF_COARSE_DDC0_PAGE_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_COARSE_DDC1_PAGE_INFO 0x00000105
#define BF_COARSE_DDC1_PAGE(val) ((val & 0x00000001) << 0x00000005)
#define BF_COARSE_DDC1_PAGE_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_COARSE_DDC2_PAGE_INFO 0x00000106
#define BF_COARSE_DDC2_PAGE(val) ((val & 0x00000001) << 0x00000006)
#define BF_COARSE_DDC2_PAGE_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_COARSE_DDC3_PAGE_INFO 0x00000107
#define BF_COARSE_DDC3_PAGE(val) ((val & 0x00000001) << 0x00000007)
#define BF_COARSE_DDC3_PAGE_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_FINE_DDC_PAGE_ADDR 0x00000019
#define BF_FINE_DDC0_PAGE_INFO 0x00000100
#define BF_FINE_DDC0_PAGE(val) (val & 0x00000001)
#define BF_FINE_DDC0_PAGE_GET(val) (val & 0x00000001)
#define BF_FINE_DDC1_PAGE_INFO 0x00000101
#define BF_FINE_DDC1_PAGE(val) ((val & 0x00000001) << 0x00000001)
#define BF_FINE_DDC1_PAGE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_FINE_DDC2_PAGE_INFO 0x00000102
#define BF_FINE_DDC2_PAGE(val) ((val & 0x00000001) << 0x00000002)
#define BF_FINE_DDC2_PAGE_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_FINE_DDC3_PAGE_INFO 0x00000103
#define BF_FINE_DDC3_PAGE(val) ((val & 0x00000001) << 0x00000003)
#define BF_FINE_DDC3_PAGE_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_FINE_DDC4_PAGE_INFO 0x00000104
#define BF_FINE_DDC4_PAGE(val) ((val & 0x00000001) << 0x00000004)
#define BF_FINE_DDC4_PAGE_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_FINE_DDC5_PAGE_INFO 0x00000105
#define BF_FINE_DDC5_PAGE(val) ((val & 0x00000001) << 0x00000005)
#define BF_FINE_DDC5_PAGE_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_FINE_DDC6_PAGE_INFO 0x00000106
#define BF_FINE_DDC6_PAGE(val) ((val & 0x00000001) << 0x00000006)
#define BF_FINE_DDC6_PAGE_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_FINE_DDC7_PAGE_INFO 0x00000107
#define BF_FINE_DDC7_PAGE(val) ((val & 0x00000001) << 0x00000007)
#define BF_FINE_DDC7_PAGE_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_JTX_PAGE_ADDR 0x0000001A
#define BF_JTX_LINK0_PAGE_INFO 0x00000100
#define BF_JTX_LINK0_PAGE(val) (val & 0x00000001)
#define BF_JTX_LINK0_PAGE_GET(val) (val & 0x00000001)
#define BF_JTX_LINK1_PAGE_INFO 0x00000101
#define BF_JTX_LINK1_PAGE(val) ((val & 0x00000001) << 0x00000001)
#define BF_JTX_LINK1_PAGE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_PFILT_CTL_PAGE_ADDR 0x0000001E
#define BF_PFILT_ADC_PAIR0_PAGE_INFO 0x00000100
#define BF_PFILT_ADC_PAIR0_PAGE(val) (val & 0x00000001)
#define BF_PFILT_ADC_PAIR0_PAGE_GET(val) (val & 0x00000001)
#define BF_PFILT_ADC_PAIR1_PAGE_INFO 0x00000101
#define BF_PFILT_ADC_PAIR1_PAGE(val) ((val & 0x00000001) << 0x00000001)
#define BF_PFILT_ADC_PAIR1_PAGE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_PFILT_COEFF_PAGE_ADDR 0x0000001F
#define BF_PFILT_COEFF_PAGE0_INFO 0x00000100
#define BF_PFILT_COEFF_PAGE0(val) (val & 0x00000001)
#define BF_PFILT_COEFF_PAGE0_GET(val) (val & 0x00000001)
#define BF_PFILT_COEFF_PAGE1_INFO 0x00000101
#define BF_PFILT_COEFF_PAGE1(val) ((val & 0x00000001) << 0x00000001)
#define BF_PFILT_COEFF_PAGE1_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_PFILT_COEFF_PAGE2_INFO 0x00000102
#define BF_PFILT_COEFF_PAGE2(val) ((val & 0x00000001) << 0x00000002)
#define BF_PFILT_COEFF_PAGE2_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_PFILT_COEFF_PAGE3_INFO 0x00000103
#define BF_PFILT_COEFF_PAGE3(val) ((val & 0x00000001) << 0x00000003)
#define BF_PFILT_COEFF_PAGE3_GET(val) ((val >> 0x00000003) & 0x00000001)
#endif /* __ADI_AD9081_BF_RX_PAGING_H__ */
/*! @} */

332
vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_ser_phy.h Executable file
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/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:30 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_SER_PHY_H__
#define __ADI_AD9081_BF_SER_PHY_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_PWR_DN_ADDR 0x00000750
#define BF_PD_SER_INFO 0x00001000
#define BF_PD_SER(val) (val & 0x0000FFFF)
#define BF_PD_SER_GET(val) (val & 0x0000FFFF)
#define REG_PWR_DN2_ADDR 0x00000751
#define REG_JTX_SWING_ADDR 0x00000752
#define BF_DRVSWING_CH0_SER_RC_INFO 0x00000300
#define BF_DRVSWING_CH0_SER_RC(val) (val & 0x00000007)
#define BF_DRVSWING_CH0_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVSWING_CH1_SER_RC_INFO 0x00000304
#define BF_DRVSWING_CH1_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVSWING_CH1_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_JTX_SWING2_ADDR 0x00000753
#define BF_DRVSWING_CH2_SER_RC_INFO 0x00000300
#define BF_DRVSWING_CH2_SER_RC(val) (val & 0x00000007)
#define BF_DRVSWING_CH2_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVSWING_CH3_SER_RC_INFO 0x00000304
#define BF_DRVSWING_CH3_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVSWING_CH3_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_JTX_SWING3_ADDR 0x00000754
#define BF_DRVSWING_CH4_SER_RC_INFO 0x00000300
#define BF_DRVSWING_CH4_SER_RC(val) (val & 0x00000007)
#define BF_DRVSWING_CH4_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVSWING_CH5_SER_RC_INFO 0x00000304
#define BF_DRVSWING_CH5_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVSWING_CH5_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_JTX_SWING4_ADDR 0x00000755
#define BF_DRVSWING_CH6_SER_RC_INFO 0x00000300
#define BF_DRVSWING_CH6_SER_RC(val) (val & 0x00000007)
#define BF_DRVSWING_CH6_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVSWING_CH7_SER_RC_INFO 0x00000304
#define BF_DRVSWING_CH7_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVSWING_CH7_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_POST_TAP_LEVEL1_ADDR 0x0000075A
#define BF_DRVPOSTEM_CH0_SER_RC_INFO 0x00000300
#define BF_DRVPOSTEM_CH0_SER_RC(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH0_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH1_SER_RC_INFO 0x00000304
#define BF_DRVPOSTEM_CH1_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVPOSTEM_CH1_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_POST_TAP_LEVEL2_ADDR 0x0000075B
#define BF_DRVPOSTEM_CH2_SER_RC_INFO 0x00000300
#define BF_DRVPOSTEM_CH2_SER_RC(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH2_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH3_SER_RC_INFO 0x00000304
#define BF_DRVPOSTEM_CH3_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVPOSTEM_CH3_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_POST_TAP_LEVEL3_ADDR 0x0000075C
#define BF_DRVPOSTEM_CH4_SER_RC_INFO 0x00000300
#define BF_DRVPOSTEM_CH4_SER_RC(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH4_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH5_SER_RC_INFO 0x00000304
#define BF_DRVPOSTEM_CH5_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVPOSTEM_CH5_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_POST_TAP_LEVEL4_ADDR 0x0000075D
#define BF_DRVPOSTEM_CH6_SER_RC_INFO 0x00000300
#define BF_DRVPOSTEM_CH6_SER_RC(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH6_SER_RC_GET(val) (val & 0x00000007)
#define BF_DRVPOSTEM_CH7_SER_RC_INFO 0x00000304
#define BF_DRVPOSTEM_CH7_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_DRVPOSTEM_CH7_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_PARDATAMODE_SER_ADDR 0x00000762
#define BF_PARDATAMODE_SER_RC_INFO 0x00000200
#define BF_PARDATAMODE_SER_RC(val) (val & 0x00000003)
#define BF_PARDATAMODE_SER_RC_GET(val) (val & 0x00000003)
#define BF_C2C_EN_SER_RC_INFO 0x00000102
#define BF_C2C_EN_SER_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_C2C_EN_SER_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define REG_PRE_TAP_LEVEL_CH0_ADDR 0x00000763
#define BF_DRVPREEM_CH0_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH0_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH0_SER_RC_GET(val) (val & 0x000000FF)
#define REG_PRE_TAP_LEVEL_CH1_ADDR 0x00000764
#define BF_DRVPREEM_CH1_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH1_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH1_SER_RC_GET(val) (val & 0x000000FF)
#define REG_PRE_TAP_LEVEL_CH2_ADDR 0x00000765
#define BF_DRVPREEM_CH2_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH2_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH2_SER_RC_GET(val) (val & 0x000000FF)
#define REG_PRE_TAP_LEVEL_CH3_ADDR 0x00000766
#define BF_DRVPREEM_CH3_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH3_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH3_SER_RC_GET(val) (val & 0x000000FF)
#define REG_PRE_TAP_LEVEL_CH4_ADDR 0x00000767
#define BF_DRVPREEM_CH4_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH4_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH4_SER_RC_GET(val) (val & 0x000000FF)
#define REG_PRE_TAP_LEVEL_CH5_ADDR 0x00000768
#define BF_DRVPREEM_CH5_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH5_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH5_SER_RC_GET(val) (val & 0x000000FF)
#define REG_PRE_TAP_LEVEL_CH6_ADDR 0x00000769
#define BF_DRVPREEM_CH6_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH6_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH6_SER_RC_GET(val) (val & 0x000000FF)
#define REG_PRE_TAP_LEVEL_CH7_ADDR 0x0000076A
#define BF_DRVPREEM_CH7_SER_RC_INFO 0x00000800
#define BF_DRVPREEM_CH7_SER_RC(val) (val & 0x000000FF)
#define BF_DRVPREEM_CH7_SER_RC_GET(val) (val & 0x000000FF)
#define REG_RSTB_ADDR 0x00000773
#define BF_RSTB_SER_INFO 0x00001000
#define BF_RSTB_SER(val) (val & 0x0000FFFF)
#define BF_RSTB_SER_GET(val) (val & 0x0000FFFF)
#define REG_RSTB2_ADDR 0x00000774
#define REG_PARITY_ERROR_ADDR 0x00000775
#define BF_PARITY_ERROR_SER_INFO 0x00001000
#define BF_PARITY_ERROR_SER(val) (val & 0x0000FFFF)
#define BF_PARITY_ERROR_SER_GET(val) (val & 0x0000FFFF)
#define REG_PARITY_ERROR2_ADDR 0x00000776
#define REG_PARITY_RST_N_ADDR 0x00000777
#define BF_SER_PARITY_RST_N_INFO 0x00001000
#define BF_SER_PARITY_RST_N(val) (val & 0x0000FFFF)
#define BF_SER_PARITY_RST_N_GET(val) (val & 0x0000FFFF)
#define REG_PARITY_RST_N2_ADDR 0x00000778
#define REG_CLK_OFFSET1_ADDR 0x00000779
#define BF_CLKOFFSET_CH0_SER_RC_INFO 0x00000300
#define BF_CLKOFFSET_CH0_SER_RC(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH0_SER_RC_GET(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH1_SER_RC_INFO 0x00000304
#define BF_CLKOFFSET_CH1_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_CLKOFFSET_CH1_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_CLK_OFFSET2_ADDR 0x0000077A
#define BF_CLKOFFSET_CH2_SER_RC_INFO 0x00000300
#define BF_CLKOFFSET_CH2_SER_RC(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH2_SER_RC_GET(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH3_SER_RC_INFO 0x00000304
#define BF_CLKOFFSET_CH3_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_CLKOFFSET_CH3_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_CLK_OFFSET3_ADDR 0x0000077B
#define BF_CLKOFFSET_CH4_SER_RC_INFO 0x00000300
#define BF_CLKOFFSET_CH4_SER_RC(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH4_SER_RC_GET(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH5_SER_RC_INFO 0x00000304
#define BF_CLKOFFSET_CH5_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_CLKOFFSET_CH5_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_CLK_OFFSET4_ADDR 0x0000077C
#define BF_CLKOFFSET_CH6_SER_RC_INFO 0x00000300
#define BF_CLKOFFSET_CH6_SER_RC(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH6_SER_RC_GET(val) (val & 0x00000007)
#define BF_CLKOFFSET_CH7_SER_RC_INFO 0x00000304
#define BF_CLKOFFSET_CH7_SER_RC(val) ((val & 0x00000007) << 0x00000004)
#define BF_CLKOFFSET_CH7_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_OTHER_ADDR 0x00000781
#define BF_EN_FBCK_SER_RC_INFO 0x00000104
#define BF_EN_FBCK_SER_RC(val) ((val & 0x00000001) << 0x00000004)
#define BF_EN_FBCK_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_FBCKINV_SER_RC_INFO 0x00000105
#define BF_FBCKINV_SER_RC(val) ((val & 0x00000001) << 0x00000005)
#define BF_FBCKINV_SER_RC_GET(val) ((val >> 0x00000005) & 0x00000001)
#define REG_EN_DRVSLICEOFFSET_ADDR 0x00000782
#define BF_EN_DRVSLICEOFFSET_CH01_SER_RC_INFO 0x00000100
#define BF_EN_DRVSLICEOFFSET_CH01_SER_RC(val) (val & 0x00000001)
#define BF_EN_DRVSLICEOFFSET_CH01_SER_RC_GET(val) (val & 0x00000001)
#define BF_EN_DRVSLICEOFFSET_CH23_SER_RC_INFO 0x00000101
#define BF_EN_DRVSLICEOFFSET_CH23_SER_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_EN_DRVSLICEOFFSET_CH23_SER_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_EN_DRVSLICEOFFSET_CH45_SER_RC_INFO 0x00000102
#define BF_EN_DRVSLICEOFFSET_CH45_SER_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_EN_DRVSLICEOFFSET_CH45_SER_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_EN_DRVSLICEOFFSET_CH67_SER_RC_INFO 0x00000103
#define BF_EN_DRVSLICEOFFSET_CH67_SER_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_EN_DRVSLICEOFFSET_CH67_SER_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define REG_PN_SWAP_ADDR 0x00000783
#define BF_DATA_PN_SWAP_CORR_INFO 0x00001000
#define BF_DATA_PN_SWAP_CORR(val) (val & 0x0000FFFF)
#define BF_DATA_PN_SWAP_CORR_GET(val) (val & 0x0000FFFF)
#define REG_PN_SWAP2_ADDR 0x00000784
#define REG_MAIN_DATA_INV_ADDR 0x00000789
#define BF_OUTPUTDATAINVERT_CH0_SER_RC_INFO 0x00000100
#define BF_OUTPUTDATAINVERT_CH0_SER_RC(val) (val & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH0_SER_RC_GET(val) (val & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH1_SER_RC_INFO 0x00000101
#define BF_OUTPUTDATAINVERT_CH1_SER_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_OUTPUTDATAINVERT_CH1_SER_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH2_SER_RC_INFO 0x00000102
#define BF_OUTPUTDATAINVERT_CH2_SER_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_OUTPUTDATAINVERT_CH2_SER_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH3_SER_RC_INFO 0x00000103
#define BF_OUTPUTDATAINVERT_CH3_SER_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_OUTPUTDATAINVERT_CH3_SER_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH4_SER_RC_INFO 0x00000104
#define BF_OUTPUTDATAINVERT_CH4_SER_RC(val) ((val & 0x00000001) << 0x00000004)
#define BF_OUTPUTDATAINVERT_CH4_SER_RC_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH5_SER_RC_INFO 0x00000105
#define BF_OUTPUTDATAINVERT_CH5_SER_RC(val) ((val & 0x00000001) << 0x00000005)
#define BF_OUTPUTDATAINVERT_CH5_SER_RC_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH6_SER_RC_INFO 0x00000106
#define BF_OUTPUTDATAINVERT_CH6_SER_RC(val) ((val & 0x00000001) << 0x00000006)
#define BF_OUTPUTDATAINVERT_CH6_SER_RC_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_OUTPUTDATAINVERT_CH7_SER_RC_INFO 0x00000107
#define BF_OUTPUTDATAINVERT_CH7_SER_RC(val) ((val & 0x00000001) << 0x00000007)
#define BF_OUTPUTDATAINVERT_CH7_SER_RC_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_POST_TAP_POL_ADDR 0x0000078B
#define BF_POSTTAPPOL_SER_RC_INFO 0x00001000
#define BF_POSTTAPPOL_SER_RC(val) (val & 0x0000FFFF)
#define BF_POSTTAPPOL_SER_RC_GET(val) (val & 0x0000FFFF)
#define REG_POST_TAP_POL2_ADDR 0x0000078C
#define REG_PRE_TAP_POL_ADDR 0x0000078D
#define BF_PRETAPPOL_SER_RC_INFO 0x00001000
#define BF_PRETAPPOL_SER_RC(val) (val & 0x0000FFFF)
#define BF_PRETAPPOL_SER_RC_GET(val) (val & 0x0000FFFF)
#define REG_PRE_TAP_POL2_ADDR 0x0000078E
#define REG_POLY_CODE_ADDR 0x0000078F
#define BF_DRVPOLYCODE_SER_RC_INFO 0x00000600
#define BF_DRVPOLYCODE_SER_RC(val) (val & 0x0000003F)
#define BF_DRVPOLYCODE_SER_RC_GET(val) (val & 0x0000003F)
#define REG_CBUS_ADDR_JTX_ADDR 0x00000790
#define BF_CBUS_ADDR_SER_INFO 0x00000800
#define BF_CBUS_ADDR_SER(val) (val & 0x000000FF)
#define BF_CBUS_ADDR_SER_GET(val) (val & 0x000000FF)
#define REG_CBUS_WSTROBE_ADDR 0x00000791
#define BF_CBUS_WSTROBE_SER_INFO 0x00001000
#define BF_CBUS_WSTROBE_SER(val) (val & 0x0000FFFF)
#define BF_CBUS_WSTROBE_SER_GET(val) (val & 0x0000FFFF)
#define REG_CBUS_WSTROBE2_ADDR 0x00000792
#define REG_CBUS_WDATA_JTX_ADDR 0x00000793
#define BF_CBUS_WDATA_SER_INFO 0x00000800
#define BF_CBUS_WDATA_SER(val) (val & 0x000000FF)
#define BF_CBUS_WDATA_SER_GET(val) (val & 0x000000FF)
#define REG_CBUS_REN_ADDR 0x00000794
#define BF_CBUS_REN_SER_INFO 0x00001000
#define BF_CBUS_REN_SER(val) (val & 0x0000FFFF)
#define BF_CBUS_REN_SER_GET(val) (val & 0x0000FFFF)
#define REG_CBUS_REN2_ADDR 0x00000795
#define REG_CBUS_RDATA_JTX_ADDR 0x00000796
#define BF_CBUS_RDATA_SER_INFO 0x00000800
#define BF_CBUS_RDATA_SER(val) (val & 0x000000FF)
#define BF_CBUS_RDATA_SER_GET(val) (val & 0x000000FF)
#define REG_SYNCA_CTRL_ADDR 0x00000797
#define BF_SYNCA_RX_MODE_RC_INFO 0x00000100
#define BF_SYNCA_RX_MODE_RC(val) (val & 0x00000001)
#define BF_SYNCA_RX_MODE_RC_GET(val) (val & 0x00000001)
#define BF_SYNCA_RX_ONCHIP_TERM_RC_INFO 0x00000101
#define BF_SYNCA_RX_ONCHIP_TERM_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_SYNCA_RX_ONCHIP_TERM_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_SYNCA_RX_PN_INV_RC_INFO 0x00000102
#define BF_SYNCA_RX_PN_INV_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_SYNCA_RX_PN_INV_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_PD_SYNCA_RX_RC_INFO 0x00000103
#define BF_PD_SYNCA_RX_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_PD_SYNCA_RX_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define REG_SYNCB_CTRL_ADDR 0x00000798
#define BF_SYNCB_RX_MODE_RC_INFO 0x00000100
#define BF_SYNCB_RX_MODE_RC(val) (val & 0x00000001)
#define BF_SYNCB_RX_MODE_RC_GET(val) (val & 0x00000001)
#define BF_SYNCB_RX_ONCHIP_TERM_RC_INFO 0x00000101
#define BF_SYNCB_RX_ONCHIP_TERM_RC(val) ((val & 0x00000001) << 0x00000001)
#define BF_SYNCB_RX_ONCHIP_TERM_RC_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_SYNCB_RX_PN_INV_RC_INFO 0x00000102
#define BF_SYNCB_RX_PN_INV_RC(val) ((val & 0x00000001) << 0x00000002)
#define BF_SYNCB_RX_PN_INV_RC_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_PD_SYNCB_RX_RC_INFO 0x00000103
#define BF_PD_SYNCB_RX_RC(val) ((val & 0x00000001) << 0x00000003)
#define BF_PD_SYNCB_RX_RC_GET(val) ((val >> 0x00000003) & 0x00000001)
#define REG_JTX_CTRL_ADDR 0x00000799
#define BF_JTAG_EN_SER_TESTMODE_RC_INFO 0x00000100
#define BF_JTAG_EN_SER_TESTMODE_RC(val) (val & 0x00000001)
#define BF_JTAG_EN_SER_TESTMODE_RC_GET(val) (val & 0x00000001)
#endif /* __ADI_AD9081_BF_SER_PHY_H__ */
/*! @} */

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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_bf_spi_only_up.h Executable file
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/*!
* @brief SPI Register Definition Header File, automatically generated file at 1/20/2020 6:24:30 AM.
*
* @copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_BF
* @{
*/
#ifndef __ADI_AD9081_BF_SPI_ONLY_UP_H__
#define __ADI_AD9081_BF_SPI_ONLY_UP_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
/*============= D E F I N E S ==============*/
#define REG_CRP_CDIVH_OVRRD_ADDR 0x00003D12
#define BF_CDIVH_OVRD_SPI_INFO 0x00000500
#define BF_CDIVH_OVRD_SPI(val) (val & 0x0000001F)
#define BF_CDIVH_OVRD_SPI_GET(val) (val & 0x0000001F)
#define REG_CRP_SDIVPDIV_OVRRD_ADDR 0x00003D13
#define BF_PDIV_OVRD_SPI_INFO 0x00000300
#define BF_PDIV_OVRD_SPI(val) (val & 0x00000007)
#define BF_PDIV_OVRD_SPI_GET(val) (val & 0x00000007)
#define BF_SDIV_OVRD_SPI_INFO 0x00000304
#define BF_SDIV_OVRD_SPI(val) ((val & 0x00000007) << 0x00000004)
#define BF_SDIV_OVRD_SPI_GET(val) ((val >> 0x00000004) & 0x00000007)
#define REG_CRP_CDIVL_OVRRD_ADDR 0x00003D14
#define BF_CDIVL_OVRD_SPI_INFO 0x00000500
#define BF_CDIVL_OVRD_SPI(val) (val & 0x0000001F)
#define BF_CDIVL_OVRD_SPI_GET(val) (val & 0x0000001F)
#define REG_SPI_BASE_ADDR3_ADDR 0x00003D23
#define BF_SPI_BASE_ADDR_0_INFO 0x00000800
#define BF_SPI_BASE_ADDR_0(val) (val & 0x000000FF)
#define BF_SPI_BASE_ADDR_0_GET(val) (val & 0x000000FF)
#define REG_SPI_BASE_ADDR2_ADDR 0x00003D22
#define BF_SPI_BASE_ADDR_1_INFO 0x00000800
#define BF_SPI_BASE_ADDR_1(val) (val & 0x000000FF)
#define BF_SPI_BASE_ADDR_1_GET(val) (val & 0x000000FF)
#define REG_SPI_BASE_ADDR1_ADDR 0x00003D21
#define BF_SPI_BASE_ADDR_2_INFO 0x00000800
#define BF_SPI_BASE_ADDR_2(val) (val & 0x000000FF)
#define BF_SPI_BASE_ADDR_2_GET(val) (val & 0x000000FF)
#define REG_SPI_BASE_ADDR0_ADDR 0x00003D20
#define BF_SPI_BASE_ADDR_3_INFO 0x00000800
#define BF_SPI_BASE_ADDR_3(val) (val & 0x000000FF)
#define BF_SPI_BASE_ADDR_3_GET(val) (val & 0x000000FF)
#define REG_OTP_DIV_ADDR 0x00003D24
#define BF_MCLKDIV_SPI_INFO 0x00000800
#define BF_MCLKDIV_SPI(val) (val & 0x000000FF)
#define BF_MCLKDIV_SPI_GET(val) (val & 0x000000FF)
#define REG_UP_STALL_ADDR 0x00003D25
#define BF_UP_STALL_INFO 0x00000100
#define BF_UP_STALL(val) (val & 0x00000001)
#define BF_UP_STALL_GET(val) (val & 0x00000001)
#define REG_UP_CTRL_ADDR 0x00003D26
#define BF_UP_BRESET_INFO 0x00000100
#define BF_UP_BRESET(val) (val & 0x00000001)
#define BF_UP_BRESET_GET(val) (val & 0x00000001)
#define BF_UP_STATVECTORSEL_INFO 0x00000101
#define BF_UP_STATVECTORSEL(val) ((val & 0x00000001) << 0x00000001)
#define BF_UP_STATVECTORSEL_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_UP_SPI_EDGE_INTERRUPT_INFO 0x00000103
#define BF_UP_SPI_EDGE_INTERRUPT(val) ((val & 0x00000001) << 0x00000003)
#define BF_UP_SPI_EDGE_INTERRUPT_GET(val) ((val >> 0x00000003) & 0x00000001)
#define REG_UP_STATUS_ADDR 0x00003D27
#define BF_UP_STATUS_INFO 0x00000100
#define BF_UP_STATUS(val) (val & 0x00000001)
#define BF_UP_STATUS_GET(val) (val & 0x00000001)
#define BF_UP_PWAITMODE_INFO 0x00000101
#define BF_UP_PWAITMODE(val) ((val & 0x00000001) << 0x00000001)
#define BF_UP_PWAITMODE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define REG_BLOCKOUT_UP_ADDR 0x00003D28
#define BF_BLOCKOUT_UP_EN_INFO 0x00000100
#define BF_BLOCKOUT_UP_EN(val) (val & 0x00000001)
#define BF_BLOCKOUT_UP_EN_GET(val) (val & 0x00000001)
#define BF_BLOCKOUT_WINDOW_INFO 0x00000301
#define BF_BLOCKOUT_WINDOW(val) ((val & 0x00000007) << 0x00000001)
#define BF_BLOCKOUT_WINDOW_GET(val) ((val >> 0x00000001) & 0x00000007)
#define REG_REG8_BYP_ADDR 0x00003D29
#define BF_REG8_ACC_MOD_INFO 0x00000103
#define BF_REG8_ACC_MOD(val) ((val & 0x00000001) << 0x00000003)
#define BF_REG8_ACC_MOD_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_SPI2_SELECT_INFO 0x00000104
#define BF_SPI2_SELECT(val) ((val & 0x00000001) << 0x00000004)
#define BF_SPI2_SELECT_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_SPI3_SELECT_INFO 0x00000105
#define BF_SPI3_SELECT(val) ((val & 0x00000001) << 0x00000005)
#define BF_SPI3_SELECT_GET(val) ((val >> 0x00000005) & 0x00000001)
#define REG_REG8_SCRATCH3_ADDR 0x00003D2D
#define BF_REG8_SCRATCH_0_INFO 0x00000800
#define BF_REG8_SCRATCH_0(val) (val & 0x000000FF)
#define BF_REG8_SCRATCH_0_GET(val) (val & 0x000000FF)
#define REG_REG8_SCRATCH2_ADDR 0x00003D2C
#define BF_REG8_SCRATCH_1_INFO 0x00000800
#define BF_REG8_SCRATCH_1(val) (val & 0x000000FF)
#define BF_REG8_SCRATCH_1_GET(val) (val & 0x000000FF)
#define REG_REG8_SCRATCH1_ADDR 0x00003D2B
#define BF_REG8_SCRATCH_2_INFO 0x00000800
#define BF_REG8_SCRATCH_2(val) (val & 0x000000FF)
#define BF_REG8_SCRATCH_2_GET(val) (val & 0x000000FF)
#define REG_REG8_SCRATCH0_ADDR 0x00003D2A
#define BF_REG8_SCRATCH_3_INFO 0x00000800
#define BF_REG8_SCRATCH_3(val) (val & 0x000000FF)
#define BF_REG8_SCRATCH_3_GET(val) (val & 0x000000FF)
#define REG_SCAN_CTL_ADDR 0x00003D30
#define BF_SCAN_MODE_INFO 0x00000100
#define BF_SCAN_MODE(val) (val & 0x00000001)
#define BF_SCAN_MODE_GET(val) (val & 0x00000001)
#define BF_COMPRESSION_INFO 0x00000101
#define BF_COMPRESSION(val) ((val & 0x00000001) << 0x00000001)
#define BF_COMPRESSION_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_OPCGENABLE_CCLK_INFO 0x00000102
#define BF_OPCGENABLE_CCLK(val) ((val & 0x00000001) << 0x00000002)
#define BF_OPCGENABLE_CCLK_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_OPCGENABLE_SYSCLK_INFO 0x00000103
#define BF_OPCGENABLE_SYSCLK(val) ((val & 0x00000001) << 0x00000003)
#define BF_OPCGENABLE_SYSCLK_GET(val) ((val >> 0x00000003) & 0x00000001)
#define BF_OPCGENABLE_NVMCLK_INFO 0x00000104
#define BF_OPCGENABLE_NVMCLK(val) ((val & 0x00000001) << 0x00000004)
#define BF_OPCGENABLE_NVMCLK_GET(val) ((val >> 0x00000004) & 0x00000001)
#define BF_SCAN_SPREADEN_INFO 0x00000105
#define BF_SCAN_SPREADEN(val) ((val & 0x00000001) << 0x00000005)
#define BF_SCAN_SPREADEN_GET(val) ((val >> 0x00000005) & 0x00000001)
#define BF_SCAN_MEM_NOBYPASS_INFO 0x00000106
#define BF_SCAN_MEM_NOBYPASS(val) ((val & 0x00000001) << 0x00000006)
#define BF_SCAN_MEM_NOBYPASS_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_RST_MODE_INFO 0x00000107
#define BF_RST_MODE(val) ((val & 0x00000001) << 0x00000007)
#define BF_RST_MODE_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_OSC_TRIM_ADDR 0x00003D31
#define BF_TRIM_COARSE_INFO 0x00000400
#define BF_TRIM_COARSE(val) (val & 0x0000000F)
#define BF_TRIM_COARSE_GET(val) (val & 0x0000000F)
#define BF_TRIM_FINE_INFO 0x00000404
#define BF_TRIM_FINE(val) ((val & 0x0000000F) << 0x00000004)
#define BF_TRIM_FINE_GET(val) ((val >> 0x00000004) & 0x0000000F)
#define REG_OSC_CLKSEL_ADDR 0x00003D32
#define BF_ADC_CLK_AVAIL_INFO 0x00000100
#define BF_ADC_CLK_AVAIL(val) (val & 0x00000001)
#define BF_ADC_CLK_AVAIL_GET(val) (val & 0x00000001)
#define BF_OSCCLK_DBG_FORCE_SEL_INFO 0x00000106
#define BF_OSCCLK_DBG_FORCE_SEL(val) ((val & 0x00000001) << 0x00000006)
#define BF_OSCCLK_DBG_FORCE_SEL_GET(val) ((val >> 0x00000006) & 0x00000001)
#define BF_OSCCLK_DBG_SEL_INFO 0x00000107
#define BF_OSCCLK_DBG_SEL(val) ((val & 0x00000001) << 0x00000007)
#define BF_OSCCLK_DBG_SEL_GET(val) ((val >> 0x00000007) & 0x00000001)
#define REG_OSC_CLKDIV_ADDR 0x00003D33
#define BF_ADC_CLK_AVAIL_OVERRIDE_INFO 0x00000100
#define BF_ADC_CLK_AVAIL_OVERRIDE(val) (val & 0x00000001)
#define BF_ADC_CLK_AVAIL_OVERRIDE_GET(val) (val & 0x00000001)
#define BF_CRP_CLKDIV_OVERRIDE_INFO 0x00000101
#define BF_CRP_CLKDIV_OVERRIDE(val) ((val & 0x00000001) << 0x00000001)
#define BF_CRP_CLKDIV_OVERRIDE_GET(val) ((val >> 0x00000001) & 0x00000001)
#define BF_OSC_MONITOR_EN_INFO 0x00000102
#define BF_OSC_MONITOR_EN(val) ((val & 0x00000001) << 0x00000002)
#define BF_OSC_MONITOR_EN_GET(val) ((val >> 0x00000002) & 0x00000001)
#define BF_MC_OSC_CLKDIV_RATIO_INFO 0x00000204
#define BF_MC_OSC_CLKDIV_RATIO(val) ((val & 0x00000003) << 0x00000004)
#define BF_MC_OSC_CLKDIV_RATIO_GET(val) ((val >> 0x00000004) & 0x00000003)
#define REG_UP_MSGREG_STATUS3_ADDR 0x00003D37
#define BF_UP_MSGBIT_STAT_0_INFO 0x00000800
#define BF_UP_MSGBIT_STAT_0(val) (val & 0x000000FF)
#define BF_UP_MSGBIT_STAT_0_GET(val) (val & 0x000000FF)
#define REG_UP_MSGREG_STATUS2_ADDR 0x00003D36
#define BF_UP_MSGBIT_STAT_1_INFO 0x00000800
#define BF_UP_MSGBIT_STAT_1(val) (val & 0x000000FF)
#define BF_UP_MSGBIT_STAT_1_GET(val) (val & 0x000000FF)
#define REG_UP_MSGREG_STATUS1_ADDR 0x00003D35
#define BF_UP_MSGBIT_STAT_2_INFO 0x00000800
#define BF_UP_MSGBIT_STAT_2(val) (val & 0x000000FF)
#define BF_UP_MSGBIT_STAT_2_GET(val) (val & 0x000000FF)
#define REG_UP_MSGREG_STATUS0_ADDR 0x00003D34
#define BF_UP_MSGBIT_STAT_3_INFO 0x00000800
#define BF_UP_MSGBIT_STAT_3(val) (val & 0x000000FF)
#define BF_UP_MSGBIT_STAT_3_GET(val) (val & 0x000000FF)
#define REG_MBIST_MODE_REG_ADDR 0x00003D39
#define BF_MBIST_MODE_INFO 0x00000100
#define BF_MBIST_MODE(val) (val & 0x00000001)
#define BF_MBIST_MODE_GET(val) (val & 0x00000001)
#define REG_UP_CLOCKS_OFF_ADDR 0x00003D3A
#define BF_UP_CLOCKS_OFF_INFO 0x00000100
#define BF_UP_CLOCKS_OFF(val) (val & 0x00000001)
#define BF_UP_CLOCKS_OFF_GET(val) (val & 0x00000001)
#define REG_ENH_REG_ADDR 0x00003D3B
#define BF_SPI_ENHANCEMENT_EN_INFO 0x00000100
#define BF_SPI_ENHANCEMENT_EN(val) (val & 0x00000001)
#define BF_SPI_ENHANCEMENT_EN_GET(val) (val & 0x00000001)
#define REG_SYNC_REG_ADDR 0x00003D3C
#define BF_SYNC_EN_INFO 0x00000100
#define BF_SYNC_EN(val) (val & 0x00000001)
#define BF_SYNC_EN_GET(val) (val & 0x00000001)
#endif /* __ADI_AD9081_BF_SPI_ONLY_UP_H__ */
/*! @} */

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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_config.h Executable file
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vitis/radar/src/ad9081_api/ad9081/inc/adi_ad9081_hal.h Executable file
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/*!
* @brief APIs to call HAL functions
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_HAL_API
* @{
*/
#ifndef __AD9081_HAL_H__
#define __AD9081_HAL_H__
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
#ifdef __KERNEL__
#include <linux/math64.h>
#endif
/*============= E X P O R T S ==============*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Open and initialize resources and peripherals required for the TxFE device.
*
* \param[in] device Pointer to device handler structure.
*
* \returns API_CMS_ERROR_OK is returned upon success. Otherwise, API_CMS_ERROR_HW_OPEN failure code.
*/
int32_t adi_ad9081_hal_hw_open(adi_ad9081_device_t *device);
/**
* \brief Shutdown and close any resources opened by adi_aegir_hal_hw_open.
*
* \param[in] device Pointer to device handler structure.
*
* \returns API_CMS_ERROR_OK is returned upon success. Otherwise, API_CMS_ERROR_HW_CLOSE failure code.
*/
int32_t adi_ad9081_hal_hw_close(adi_ad9081_device_t *device);
/**
* \brief Perform a wait/thread sleep in units of microseconds.
*
* \param[in] device Pointer to device handler structure.
* \param[in] us Delay duration in microseconds.
*
* \returns API_CMS_ERROR_OK is returned upon success. Otherwise, API_CMS_ERROR_DELAY_US failure code.
*/
int32_t adi_ad9081_hal_delay_us(adi_ad9081_device_t *device, uint32_t us);
/**
* \brief Set ADI device RESETB pin high or low.
*
* \param[in] device Pointer to device handler structure.
* \param[in] enable 0: set RESETB pin low, 1: set RESETB pin high.
*
* \returns API_CMS_ERROR_OK is returned upon success. Otherwise, API_CMS_ERROR_RESET_PIN_CTRL failure code.
*/
int32_t adi_ad9081_hal_reset_pin_ctrl(adi_ad9081_device_t *device, uint8_t enable);
int32_t adi_ad9081_hal_log_write(adi_ad9081_device_t *device, adi_cms_log_type_e type, const char* comment, ...);
int32_t adi_ad9081_hal_bf_get(adi_ad9081_device_t *device, uint32_t reg, uint32_t info, uint8_t *value, uint8_t value_size_bytes);
int32_t adi_ad9081_hal_bf_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t info, uint64_t value);
int32_t adi_ad9081_hal_2bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1,
uint8_t value_size_bytes);
int32_t adi_ad9081_hal_3bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2,
uint8_t value_size_bytes);
int32_t adi_ad9081_hal_4bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint8_t value_size_bytes);
int32_t adi_ad9081_hal_5bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4,
uint8_t value_size_bytes);
int32_t adi_ad9081_hal_6bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4, uint32_t info5, uint8_t *value5,
uint8_t value_size_bytes);
int32_t adi_ad9081_hal_7bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4, uint32_t info5, uint8_t *value5, uint32_t info6, uint8_t *value6,
uint8_t value_size_bytes);
int32_t adi_ad9081_hal_8bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4, uint32_t info5, uint8_t *value5, uint32_t info6, uint8_t *value6, uint32_t info7, uint8_t *value7,
uint8_t value_size_bytes);
int32_t adi_ad9081_hal_2bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1);
int32_t adi_ad9081_hal_3bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2);
int32_t adi_ad9081_hal_4bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3);
int32_t adi_ad9081_hal_5bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4);
int32_t adi_ad9081_hal_6bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4, uint32_t info5, uint64_t value5);
int32_t adi_ad9081_hal_7bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4, uint32_t info5, uint64_t value5, uint32_t info6, uint64_t value6);
int32_t adi_ad9081_hal_8bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4, uint32_t info5, uint64_t value5, uint32_t info6, uint64_t value6, uint32_t info7, uint64_t value7);
int32_t adi_ad9081_hal_multi_bf_get(adi_ad9081_device_t *device, uint32_t reg, uint32_t *info, uint8_t **value, uint8_t value_size_bytes, uint8_t num_bfs);
int32_t adi_ad9081_hal_multi_bf_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t *info, uint64_t *value, uint8_t num_bfs);
int32_t adi_ad9081_hal_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t *data);
int32_t adi_ad9081_hal_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t data);
int32_t adi_ad9081_hal_cbusjrx_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t* data, uint8_t lane);
int32_t adi_ad9081_hal_cbusjrx_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint8_t data, uint8_t lane);
int32_t adi_ad9081_hal_cbusjtx_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t* data, uint8_t lane);
int32_t adi_ad9081_hal_cbusjtx_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint8_t data, uint8_t lane);
int32_t adi_ad9081_hal_cbuspll_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t* data);
int32_t adi_ad9081_hal_cbuspll_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint8_t data);
int32_t adi_ad9081_hal_bf_wait_to_clear(adi_ad9081_device_t *device, uint32_t reg, uint32_t info);
int32_t adi_ad9081_hal_bf_wait_to_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t info);
int32_t adi_ad9081_hal_error_report(adi_ad9081_device_t* device, adi_cms_log_type_e log_type,
int32_t error, const char* file_name, const char* func_name, uint32_t line_num,
const char* var_name, const char* comment);
int32_t adi_ad9081_hal_calc_nco_ftw(adi_ad9081_device_t* device, uint64_t freq, int64_t nco_shift, uint64_t *ftw, uint64_t *a, uint64_t *b);
#if AD9081_USE_FLOATING_TYPE > 0
int32_t adi_ad9081_hal_calc_nco_ftw_f(adi_ad9081_device_t* device, double freq, double nco_shift, uint64_t *ftw, uint64_t *a, uint64_t *b);
#endif
int32_t adi_ad9081_hal_calc_rx_nco_ftw(adi_ad9081_device_t* device, uint64_t adc_freq, int64_t nco_shift, uint64_t *ftw);
int32_t adi_ad9081_hal_calc_tx_nco_ftw(adi_ad9081_device_t* device, uint64_t dac_freq, int64_t nco_shift, uint64_t *ftw);
int32_t adi_ad9081_hal_calc_rx_nco_ftw32(adi_ad9081_device_t *device, uint64_t adc_freq, int64_t nco_shift, uint64_t *ftw);
int32_t adi_ad9081_hal_calc_tx_nco_ftw32(adi_ad9081_device_t *device, uint64_t dac_freq, int64_t nco_shift, uint64_t *ftw);
#ifdef __cplusplus
}
#endif
#endif /* __AD9081_REG_H__ */
/*! @} */

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vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_adc.c Executable file
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vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_dac.c Executable file
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vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_device.c Executable file
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vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_hal.c Executable file
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/*!
* @brief APIs to call HAL functions
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_HAL_API
* @{
*/
/*============= I N C L U D E S ============*/
#include "adi_ad9081_hal.h"
/*============= C O D E ====================*/
int32_t adi_ad9081_hal_hw_open(adi_ad9081_device_t *device)
{
AD9081_NULL_POINTER_RETURN(device);
if (device->hal_info.hw_open != NULL) {
if (API_CMS_ERROR_OK != device->hal_info.hw_open(device->hal_info.user_data))
return API_CMS_ERROR_HW_OPEN;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_hw_close(adi_ad9081_device_t *device)
{
AD9081_NULL_POINTER_RETURN(device);
if (device->hal_info.hw_close != NULL) {
if (API_CMS_ERROR_OK != device->hal_info.hw_close(device->hal_info.user_data))
return API_CMS_ERROR_HW_CLOSE;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_delay_us(adi_ad9081_device_t *device, uint32_t us)
{
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(device->hal_info.delay_us);
if (API_CMS_ERROR_OK != device->hal_info.delay_us(device->hal_info.user_data, us)) {
return API_CMS_ERROR_DELAY_US;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_reset_pin_ctrl(adi_ad9081_device_t *device, uint8_t enable)
{
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(device->hal_info.reset_pin_ctrl);
if (API_CMS_ERROR_OK != device->hal_info.reset_pin_ctrl(device->hal_info.user_data, enable)){
return API_CMS_ERROR_RESET_PIN_CTRL;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_log_write(adi_ad9081_device_t *device, adi_cms_log_type_e log_type, const char* comment, ...)
{
va_list argp;
AD9081_NULL_POINTER_RETURN(device);
if (((log_type & ADI_REPORT_VERBOSE) > 0) && (device->hal_info.log_write != NULL)) {
va_start(argp, comment);
if (API_CMS_ERROR_OK != device->hal_info.log_write(device->hal_info.user_data, log_type, comment, argp))
return API_CMS_ERROR_LOG_WRITE;
va_end(argp);
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_bf_get(adi_ad9081_device_t *device, uint32_t reg, uint32_t info, uint8_t *value, uint8_t value_size_bytes)
{
int32_t err;
uint8_t reg_offset = 0, data8 = 0;
uint8_t offset = (uint8_t)(info >> 0), width = (uint8_t)(info >> 8);
uint32_t data32 = 0, mask = 0, endian_test_val = 0x11223344;
uint64_t bf_val = 0;
uint8_t reg_bytes = ((width + offset) >> 3) + (((width + offset) & 7) == 0 ? 0 : 1);
uint8_t i = 0, j = 0, filled_bits = 0;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(value);
AD9081_INVALID_PARAM_RETURN(width > 64);
AD9081_INVALID_PARAM_RETURN(width < 1);
AD9081_INVALID_PARAM_RETURN(value_size_bytes > 8);
if (reg < 0x4000) {
for (reg_offset = 0; reg_offset < reg_bytes; reg_offset ++) {
err = adi_ad9081_hal_reg_get(device, reg + reg_offset, &data8);
AD9081_ERROR_RETURN(err);
if ((offset + width) <= 8) { /* last 8bits */
mask = (1 << width) - 1;
data8 = (data8 >> offset) & mask;
bf_val = bf_val + ((uint64_t)data8 << filled_bits);
filled_bits = filled_bits + width;
}
else {
mask = (1 << (8 - offset)) - 1;
data8 = (data8 >> offset) & mask;
bf_val = bf_val + ((uint64_t)data8 << filled_bits);
width = offset + width - 8;
filled_bits = filled_bits + (8 - offset);
offset = 0;
}
}
} else { /* access extended space */
for (reg_offset = 0; reg_offset < reg_bytes; reg_offset +=4) {
err = adi_ad9081_hal_reg_get(device, reg + reg_offset, (uint8_t*)&data32);
AD9081_ERROR_RETURN(err);
if ((offset + width) <= 32) { /* last 32bits */
mask = ((uint64_t)1 << width) - 1;
data32 = (data32 >> offset) & mask;
bf_val = bf_val + ((uint64_t)data32 << filled_bits);
filled_bits = filled_bits + width;
}
else {
mask = ((uint64_t)1 << (32 - offset)) - 1;
data32 = (data32 >> offset) & mask;
bf_val = bf_val + ((uint64_t)data32 << filled_bits);
width = offset + width - 32;
filled_bits = filled_bits + (32 - offset);
offset = 0;
}
}
}
/* save bitfield value to buffer */
for(i = 0; i < value_size_bytes; i++) {
j = (*(uint8_t *)&endian_test_val == 0x44) ? (i) : (value_size_bytes - 1 - i);
value[j] = (uint8_t)(bf_val >> (i << 3));
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_bf_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t info, uint64_t value)
{
int32_t err;
uint8_t reg_offset = 0, data8 = 0;
uint8_t offset = (uint8_t)(info >> 0), width = (uint8_t)(info >> 8);
uint32_t data32 = 0, mask = 0;
uint8_t reg_bytes = ((width + offset) >> 3) + (((width + offset) & 7) == 0 ? 0 : 1);
AD9081_NULL_POINTER_RETURN(device);
AD9081_INVALID_PARAM_RETURN(width > 64);
AD9081_INVALID_PARAM_RETURN(width < 1);
if (reg < 0x4000) {
for (reg_offset = 0; reg_offset < reg_bytes; reg_offset ++) {
if ((offset + width) <= 8) { /* last 8bits */
if ((offset > 0) || ((offset + width) < 8)) {
err = adi_ad9081_hal_reg_get(device, reg + reg_offset, &data8);
AD9081_ERROR_RETURN(err);
}
mask = (1 << width) - 1;
data8 = data8 & (~(mask << offset));
data8 = data8 | ((value & mask) << offset);
}
else {
if (offset > 0) {
err = adi_ad9081_hal_reg_get(device, reg + reg_offset, &data8);
AD9081_ERROR_RETURN(err);
}
mask = (1 << (8 - offset)) - 1;
data8 = data8 & (~(mask << offset));
data8 = data8 | ((value & mask) << offset);
value = value >> (8 - offset);
width = offset + width - 8;
offset = 0;
}
err = adi_ad9081_hal_reg_set(device, reg + reg_offset, data8);
AD9081_ERROR_RETURN(err);
}
} else { /* access extended space */
for (reg_offset = 0; reg_offset < reg_bytes; reg_offset += 4) {
if ((offset + width) <= 32) { /* last 32bits */
if ((offset > 0) || ((offset + width) < 32)) {
err = adi_ad9081_hal_reg_get(device, reg + reg_offset, (uint8_t *)&data32);
AD9081_ERROR_RETURN(err);
}
mask = ((uint64_t)1 << width) - 1;
data32 = data32 & (~(mask << offset));
data32 = data32 | ((value & mask) << offset);
}
else {
if (offset > 0) {
err = adi_ad9081_hal_reg_get(device, reg + reg_offset, &data8);
AD9081_ERROR_RETURN(err);
}
mask = ((uint64_t)1 << (32 - offset)) - 1;
data32 = data32 & (~(mask << offset));
data32 = data32 | ((value & mask) << offset);
value = value >> (32 - offset);
width = offset + width - 32;
offset = 0;
}
err = adi_ad9081_hal_reg_set(device, reg + reg_offset, data32);
AD9081_ERROR_RETURN(err);
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t *data)
{
uint8_t in_data[6] = {0}, out_data[6] = {0};
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(device->hal_info.spi_xfer);
AD9081_NULL_POINTER_RETURN(data);
if (reg < 0x4000) {
in_data[0] = ((reg >> 8) & 0x3F) | 0x80;
in_data[1] = ((reg >> 0) & 0xFF);
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
*data = out_data[2];
if (API_CMS_ERROR_OK != AD9081_LOG_SPIR((in_data[0]<<8) + in_data[1], out_data[2]))
return API_CMS_ERROR_LOG_WRITE;
} else { /* access extended 32-bit data space */
in_data[0] = 0x3D;
in_data[1] = 0x21;
in_data[2] = (reg >> 8) & 0xC0;
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW(0x3d21, in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
in_data[0] = 0x3D;
in_data[1] = 0x22;
in_data[2] = (reg >> 16) & 0xFF;
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW(0x3d22, in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
in_data[0] = 0x3D;
in_data[1] = 0x23;
in_data[2] = (reg >> 24) & 0xFF;
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW(0x3d23, in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
if (((reg >= 0x4F00000) && (reg <= 0x4FFFFFF)) || ((reg >= 0x6001000) && (reg <= 0x60010FF))) {
/* 32-bit address, 8-bit data */
in_data[0] = ((reg >> 8) & 0x3F) | 0xC0;
in_data[1] = ((reg >> 0) & 0xFF);
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
*data = out_data[2];
if (API_CMS_ERROR_OK != AD9081_LOG_SPIR((in_data[0]<<8) + in_data[1], out_data[2]))
return API_CMS_ERROR_LOG_WRITE;
} else {
/* 32-bit address, 32-bit data */
reg += (device->hal_info.addr_inc == SPI_ADDR_INC_AUTO) ? 0 : 3;
in_data[0] = ((reg >> 8) & 0x3F) | 0xC0;
in_data[1] = ((reg >> 0) & 0xFF);
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x20000006))
return API_CMS_ERROR_SPI_XFER;
if (device->hal_info.addr_inc == SPI_ADDR_INC_AUTO) {
*(uint32_t *)data = (out_data[2]) + (out_data[3] << 8) + (out_data[4] << 16) + (out_data[5] << 24);
} else { /* streaming addresses are decremented */
*(uint32_t *)data = (out_data[5]) + (out_data[4] << 8) + (out_data[3] << 16) + (out_data[2] << 24);
}
if (API_CMS_ERROR_OK != AD9081_LOG_SPIR32((in_data[0]<<8) + in_data[1], *(uint32_t *)data))
return API_CMS_ERROR_LOG_WRITE;
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t data)
{
uint8_t in_data[6] = {0}, out_data[6] = {0};
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(device->hal_info.spi_xfer);
if (reg < 0x4000) {
in_data[0] = (reg >> 8) & 0x3F;
in_data[1] = (reg >> 0) & 0xFF;
in_data[2] = (uint8_t)(data & 0xFF);
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW(reg & 0x3fff, in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
} else { /* access extended 32-bit data space */
in_data[0] = 0x3D;
in_data[1] = 0x21;
in_data[2] = (reg >> 8) & 0xC0;
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW(0x3d21, in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
in_data[0] = 0x3D;
in_data[1] = 0x22;
in_data[2] = (reg >> 16) & 0xFF;
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW(0x3d22, in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
in_data[0] = 0x3D;
in_data[1] = 0x23;
in_data[2] = (reg >> 24) & 0xFF;
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW(0x3d23, in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
if (((reg >= 0x4F00000) && (reg <= 0x4FFFFFF)) || ((reg >= 0x6001000) && (reg <= 0x60010FF))) {
/* 32-bit address, 8-bit data */
in_data[0] = ((reg >> 8) & 0x3F) | 0x40;
in_data[1] = ((reg >> 0) & 0xFF);
in_data[2] = (uint8_t)(data & 0xFF);
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x3))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW((in_data[0]<<8) + in_data[1], in_data[2]))
return API_CMS_ERROR_LOG_WRITE;
} else {
/* 32-bit address, 32-bit data */
if (device->hal_info.addr_inc == SPI_ADDR_INC_AUTO) {
in_data[0] = ((reg >> 8) & 0x3F) | 0x40;
in_data[1] = ((reg >> 0) & 0xFF);
in_data[2] = (uint8_t)((data >> 0) & 0xFF);
in_data[3] = (uint8_t)((data >> 8) & 0xFF);
in_data[4] = (uint8_t)((data >> 16) & 0xFF);
in_data[5] = (uint8_t)((data >> 24) & 0xFF);
} else { /* streaming addresses are decremented */
in_data[0] = (((reg + 3) >> 8) & 0x3F) | 0x40;
in_data[1] = (((reg + 3) >> 0) & 0xFF);
in_data[2] = (uint8_t)((data >> 24) & 0xFF);
in_data[3] = (uint8_t)((data >> 16) & 0xFF);
in_data[4] = (uint8_t)((data >> 8) & 0xFF);
in_data[5] = (uint8_t)((data >> 0) & 0xFF);
}
if (API_CMS_ERROR_OK != device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, 0x20000006))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != AD9081_LOG_SPIW32((in_data[0]<<8) + in_data[1], data))
return API_CMS_ERROR_LOG_WRITE;
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_cbusjrx_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t* data, uint8_t lane)
{
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(data);
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x406, reg))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x409, 0x00))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x409, 1 << lane))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_get(device, 0x40a, data))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x409, 0x00))
return API_CMS_ERROR_SPI_XFER;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_cbusjrx_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint8_t data, uint8_t lane)
{
AD9081_NULL_POINTER_RETURN(device);
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x406, reg))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x408, data))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x407, 0x00))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x407, lane))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x407, 0x00))
return API_CMS_ERROR_SPI_XFER;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_cbusjtx_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t* data, uint8_t lane)
{
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(data);
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x790, reg))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x794, 0x00))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x794, 1 << lane))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_get(device, 0x796, data))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x794, 0x00))
return API_CMS_ERROR_SPI_XFER;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_cbusjtx_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint8_t data, uint8_t lane)
{
AD9081_NULL_POINTER_RETURN(device);
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x790, reg))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x793, data))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x791, 0x00))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x791, lane))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x791, 0x00))
return API_CMS_ERROR_SPI_XFER;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_cbuspll_reg_get(adi_ad9081_device_t *device, uint32_t reg, uint8_t* data)
{
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(data);
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x740, reg))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x72E, 0x01))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_get(device, 0x742, data))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x72E, 0x00))
return API_CMS_ERROR_SPI_XFER;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_cbuspll_reg_set(adi_ad9081_device_t *device, uint32_t reg, uint8_t data)
{
AD9081_NULL_POINTER_RETURN(device);
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x740, reg))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x741, data))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_delay_us(device, 500))
return API_CMS_ERROR_DELAY_US;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x72F, 0x00))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x72F, 0x01))
return API_CMS_ERROR_SPI_XFER;
if (API_CMS_ERROR_OK != adi_ad9081_hal_reg_set(device, 0x72F, 0x00))
return API_CMS_ERROR_SPI_XFER;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_bf_wait_to_clear(adi_ad9081_device_t *device, uint32_t reg, uint32_t info)
{
int32_t err;
uint8_t i = 0, bf_value = 0;
AD9081_NULL_POINTER_RETURN(device);
for (i = 0; i < 200; i++) {
err = adi_ad9081_hal_delay_us(device, 20);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_get(device, reg, info, &bf_value, 1);
AD9081_ERROR_RETURN(err);
if (bf_value == 0) {
break;
}
if (i == 199) {
return API_CMS_ERROR_ERROR;
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_bf_wait_to_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t info)
{
int32_t err;
uint8_t i = 0, bf_value = 0;
AD9081_NULL_POINTER_RETURN(device);
for (i = 0; i < 200; i++) {
err = adi_ad9081_hal_delay_us(device, 20);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_get(device, reg, info, &bf_value, 1);
AD9081_ERROR_RETURN(err);
if (bf_value == 1) {
break;
}
if (i == 199) {
return API_CMS_ERROR_ERROR;
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_error_report(adi_ad9081_device_t* device, adi_cms_log_type_e log_type,
int32_t error, const char* file_name, const char* func_name, uint32_t line_num,
const char* var_name, const char* comment)
{
if (device == NULL)
return API_CMS_ERROR_NULL_PARAM;
if (API_CMS_ERROR_OK != adi_ad9081_hal_log_write(device, log_type, "%s, \"%s\" in %s(...), line%d in %s",
comment, var_name, func_name, line_num, file_name))
return API_CMS_ERROR_LOG_WRITE;
return API_CMS_ERROR_OK;
}
void adi_ad9081_hal_add_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl, uint64_t *hi, uint64_t *lo)
{
uint64_t rl = al + bl, rh = ah + bh;
if (rl < al)
rh++;
*lo = rl;
*hi = rh;
}
void adi_ad9081_hal_sub_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl, uint64_t *hi, uint64_t *lo)
{
uint64_t rl, rh;
if (bl <= al) {
rl = al - bl;
rh = ah - bh;
} else {
rl = bl - al - 1;
rl = 0xffffffffffffffffull - rl;
ah--;
rh = ah - bh;
}
*lo = rl;
*hi = rh;
}
void adi_ad9081_hal_mult_128(uint64_t a, uint64_t b, uint64_t *hi, uint64_t *lo)
{
uint64_t ah = a >> 32, al = a & 0xffffffff, bh = b >> 32, bl = b & 0xffffffff,
rh = ah * bh, rl = al * bl, rm1 = ah * bl, rm2 = al * bh,
rm1h = rm1 >> 32, rm2h = rm2 >> 32, rm1l = rm1 & 0xffffffff, rm2l = rm2 & 0xffffffff,
rmh = rm1h + rm2h, rml = rm1l + rm2l,
c = ((rl >> 32) + rml) >> 32;
rl = rl + (rml << 32);
rh = rh + rmh + c;
*lo = rl;
*hi = rh;
}
void adi_ad9081_hal_lshift_128(uint64_t *hi, uint64_t *lo)
{
*hi <<= 1;
if (*lo & 0x8000000000000000ull)
*hi |= 1ull;
*lo <<= 1;
}
void adi_ad9081_hal_rshift_128(uint64_t *hi, uint64_t *lo)
{
*lo >>= 1;
if (*hi & 1ull)
*lo |= 0x8000000000000000ull;
*hi >>= 1;
}
void adi_ad9081_hal_div_128(uint64_t a_hi, uint64_t a_lo, uint64_t b_hi, uint64_t b_lo, uint64_t *hi, uint64_t *lo)
{
uint64_t remain_lo = a_lo, remain_hi = a_hi, part1_lo = b_lo, part1_hi = b_hi;
uint64_t result_lo = 0, result_hi = 0, mask_lo = 1, mask_hi = 0;
while (!(part1_hi & 0x8000000000000000ull)) {
adi_ad9081_hal_lshift_128(&part1_hi, &part1_lo);
adi_ad9081_hal_lshift_128(&mask_hi, &mask_lo);
}
do {
if ((remain_hi > part1_hi) || ((remain_hi == part1_hi) && (remain_lo >= part1_lo))) {
adi_ad9081_hal_sub_128(remain_hi, remain_lo, part1_hi, part1_lo, &remain_hi, &remain_lo);
adi_ad9081_hal_add_128(result_hi, result_lo, mask_hi, mask_lo, &result_hi, &result_lo);
}
adi_ad9081_hal_rshift_128(&part1_hi, &part1_lo);
adi_ad9081_hal_rshift_128(&mask_hi, &mask_lo);
} while ((mask_hi != 0) || (mask_lo != 0));
*lo = result_lo;
*hi = result_hi;
}
int32_t adi_ad9081_hal_calc_nco_ftw(adi_ad9081_device_t* device, uint64_t freq, int64_t nco_shift, uint64_t *ftw, uint64_t *a, uint64_t *b)
{
uint64_t hi, lo, hi1, hi2, lo2, hi3, lo3, hi4, lo4;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
AD9081_INVALID_PARAM_RETURN(freq == 0);
/* ftw + a/b nco_shift */
/* --------- = --------- */
/* 2^48 freq */
if (nco_shift >= 0) {
adi_ad9081_hal_mult_128(281474976710656ull, nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, freq, &hi1, ftw);
adi_ad9081_hal_mult_128(*ftw, freq, &hi2, &lo2);
adi_ad9081_hal_sub_128(hi, lo, hi2, lo2, &hi3, &lo3);
adi_ad9081_hal_mult_128(lo3, 281474976710655ull, &hi4, &lo4);
adi_ad9081_hal_div_128(hi4, lo4, 0, freq, &hi1, a);
*b = 281474976710655ull;
} else {
adi_ad9081_hal_mult_128(281474976710656ull, -nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, freq, &hi, ftw);
adi_ad9081_hal_mult_128(*ftw, freq, &hi2, &lo2);
adi_ad9081_hal_sub_128(hi, lo, hi2, lo2, &hi3, &lo3);
adi_ad9081_hal_mult_128(lo3, 281474976710655ull, &hi4, &lo4);
adi_ad9081_hal_div_128(hi4, lo4, 0, freq, &hi1, a);
*b = 281474976710655ull;
*a = (*a > 0) ? (281474976710656ull - *a) : *a; /* assume register a/b is unsigned 48bit value */
*ftw = 281474976710656ull - *ftw - (*a > 0 ? 1 : 0);
}
return API_CMS_ERROR_OK;
}
#if AD9081_USE_FLOATING_TYPE > 0
int32_t adi_ad9081_hal_calc_nco_ftw_f(adi_ad9081_device_t* device, double freq, double nco_shift, uint64_t *ftw, uint64_t *a, uint64_t *b)
{
double set_shift, rem_shift;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
AD9081_INVALID_PARAM_RETURN(freq == 0);
/* ftw + a/b nco_shift */
/* --------- = --------- */
/* 2^48 freq */
if (nco_shift >= 0) {
*ftw = (uint64_t)(281474976710656ull * nco_shift / freq);
set_shift = (*ftw) * freq / 281474976710656ull;
rem_shift = nco_shift - set_shift;
*b = 281474976710655ull;
*a = (uint64_t)((rem_shift * 281474976710656ull / freq) * (*b));
} else {
*ftw = (uint64_t)(281474976710656ull * (-nco_shift) / freq);
set_shift = (*ftw) * freq / 281474976710656ull;
rem_shift = -nco_shift - set_shift;
*b = 281474976710655ull;
*a = (uint64_t)((rem_shift * 281474976710656ull / freq) * (*b));
*a = (*a > 0) ? (281474976710656ull - *a) : *a; /* assume register a/b is unsigned 48bit value */
*ftw = 281474976710656ull - *ftw - (*a > 0 ? 1 : 0);
}
return API_CMS_ERROR_OK;
}
#endif
int32_t adi_ad9081_hal_calc_rx_nco_ftw(adi_ad9081_device_t* device, uint64_t adc_freq, int64_t nco_shift, uint64_t *ftw)
{
uint64_t hi, lo;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
AD9081_INVALID_PARAM_RETURN(adc_freq == 0);
if (nco_shift >= 0) {
adi_ad9081_hal_mult_128(281474976710656ull, nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, adc_freq, &hi, ftw);
} else {
adi_ad9081_hal_mult_128(281474976710656ull, -nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, adc_freq, &hi, ftw);
*ftw = 281474976710656ull - *ftw;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_calc_rx_nco_ftw32(adi_ad9081_device_t *device, uint64_t adc_freq, int64_t nco_shift, uint64_t *ftw)
{
uint64_t hi, lo;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
AD9081_INVALID_PARAM_RETURN(adc_freq == 0);
if (nco_shift >= 0) {
adi_ad9081_hal_mult_128(4294967296ull, nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, adc_freq, &hi, ftw);
} else {
adi_ad9081_hal_mult_128(4294967296ull, -nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, adc_freq, &hi, ftw);
*ftw = 4294967296ull - *ftw;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_calc_tx_nco_ftw(adi_ad9081_device_t* device, uint64_t dac_freq, int64_t nco_shift, uint64_t *ftw)
{
uint64_t hi, lo;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
AD9081_INVALID_PARAM_RETURN(dac_freq == 0);
if (nco_shift >= 0) {
adi_ad9081_hal_mult_128(281474976710656ull, nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, dac_freq, &hi, ftw);
} else {
adi_ad9081_hal_mult_128(281474976710656ull, -nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, dac_freq, &hi, ftw);
*ftw = 281474976710656ull - *ftw;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_calc_tx_nco_ftw32(adi_ad9081_device_t *device, uint64_t dac_freq, int64_t nco_shift, uint64_t *ftw)
{
uint64_t hi, lo;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
AD9081_INVALID_PARAM_RETURN(dac_freq == 0);
if (nco_shift >= 0) {
adi_ad9081_hal_mult_128(4294967296ull, nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, dac_freq, &hi, ftw);
} else {
adi_ad9081_hal_mult_128(4294967296ull, -nco_shift, &hi, &lo);
adi_ad9081_hal_div_128(hi, lo, 0, dac_freq, &hi, ftw);
*ftw = 4294967296ull - *ftw;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_2bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1,
uint8_t value_size_bytes)
{
uint32_t info[2] = {info0, info1};
uint8_t *value[2] = {value0, value1};
return adi_ad9081_hal_multi_bf_get(device, reg, info, value, value_size_bytes, 2);
}
int32_t adi_ad9081_hal_3bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2,
uint8_t value_size_bytes)
{
uint32_t info[3] = {info0, info1, info2};
uint8_t *value[3] = {value0, value1, value2};
return adi_ad9081_hal_multi_bf_get(device, reg, info, value, value_size_bytes, 3);
}
int32_t adi_ad9081_hal_4bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint8_t value_size_bytes)
{
uint32_t info[4] = {info0, info1, info2, info3};
uint8_t *value[4] = {value0, value1, value2, value3};
return adi_ad9081_hal_multi_bf_get(device, reg, info, value, value_size_bytes, 4);
}
int32_t adi_ad9081_hal_5bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4,
uint8_t value_size_bytes)
{
uint32_t info[5] = {info0, info1, info2, info3, info4};
uint8_t *value[5] = {value0, value1, value2, value3, value4};
return adi_ad9081_hal_multi_bf_get(device, reg, info, value, value_size_bytes, 5);
}
int32_t adi_ad9081_hal_6bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4, uint32_t info5, uint8_t *value5,
uint8_t value_size_bytes)
{
uint32_t info[6] = {info0, info1, info2, info3, info4, info5};
uint8_t *value[6] = {value0, value1, value2, value3, value4, value5};
return adi_ad9081_hal_multi_bf_get(device, reg, info, value, value_size_bytes, 6);
}
int32_t adi_ad9081_hal_7bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4, uint32_t info5, uint8_t *value5, uint32_t info6, uint8_t *value6,
uint8_t value_size_bytes)
{
uint32_t info[7] = {info0, info1, info2, info3, info4, info5, info6};
uint8_t *value[7] = {value0, value1, value2, value3, value4, value5, value6};
return adi_ad9081_hal_multi_bf_get(device, reg, info, value, value_size_bytes, 7);
}
int32_t adi_ad9081_hal_8bf_get(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint8_t *value0, uint32_t info1, uint8_t *value1, uint32_t info2, uint8_t *value2, uint32_t info3, uint8_t *value3,
uint32_t info4, uint8_t *value4, uint32_t info5, uint8_t *value5, uint32_t info6, uint8_t *value6, uint32_t info7, uint8_t *value7,
uint8_t value_size_bytes)
{
uint32_t info[8] = {info0, info1, info2, info3, info4, info5, info6, info7};
uint8_t *value[8] = {value0, value1, value2, value3, value4, value5, value6, value7};
return adi_ad9081_hal_multi_bf_get(device, reg, info, value, value_size_bytes, 8);
}
int32_t adi_ad9081_hal_2bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1)
{
uint32_t info[2] = {info0, info1};
uint64_t value[2] = {value0, value1};
return adi_ad9081_hal_multi_bf_set(device, reg, info, value, 2);
}
int32_t adi_ad9081_hal_3bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2)
{
uint32_t info[3] = {info0, info1, info2};
uint64_t value[3] = {value0, value1, value2};
return adi_ad9081_hal_multi_bf_set(device, reg, info, value, 3);
}
int32_t adi_ad9081_hal_4bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3)
{
uint32_t info[4] = {info0, info1, info2, info3};
uint64_t value[4] = {value0, value1, value2, value3};
return adi_ad9081_hal_multi_bf_set(device, reg, info, value, 4);
}
int32_t adi_ad9081_hal_5bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4)
{
uint32_t info[5] = {info0, info1, info2, info3, info4};
uint64_t value[5] = {value0, value1, value2, value3, value4};
return adi_ad9081_hal_multi_bf_set(device, reg, info, value, 5);
}
int32_t adi_ad9081_hal_6bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4, uint32_t info5, uint64_t value5)
{
uint32_t info[6] = {info0, info1, info2, info3, info4, info5};
uint64_t value[6] = {value0, value1, value2, value3, value4, value5};
return adi_ad9081_hal_multi_bf_set(device, reg, info, value, 6);
}
int32_t adi_ad9081_hal_7bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4, uint32_t info5, uint64_t value5, uint32_t info6, uint64_t value6)
{
uint32_t info[7] = {info0, info1, info2, info3, info4, info5, info6};
uint64_t value[7] = {value0, value1, value2, value3, value4, value5, value6};
return adi_ad9081_hal_multi_bf_set(device, reg, info, value, 7);
}
int32_t adi_ad9081_hal_8bf_set(adi_ad9081_device_t *device, uint32_t reg,
uint32_t info0, uint64_t value0, uint32_t info1, uint64_t value1, uint32_t info2, uint64_t value2, uint32_t info3, uint64_t value3,
uint32_t info4, uint64_t value4, uint32_t info5, uint64_t value5, uint32_t info6, uint64_t value6, uint32_t info7, uint64_t value7)
{
uint32_t info[8] = {info0, info1, info2, info3, info4, info5, info6, info7};
uint64_t value[8] = {value0, value1, value2, value3, value4, value5, value6, value7};
return adi_ad9081_hal_multi_bf_set(device, reg, info, value, 8);
}
int32_t adi_ad9081_hal_multi_bf_get(adi_ad9081_device_t *device, uint32_t reg, uint32_t *info, uint8_t **value, uint8_t value_size_bytes, uint8_t num_bfs)
{
int32_t err;
uint32_t mask = 0;
uint8_t data8 = 0, offset = 0, width = 0;
uint8_t i = 0, reg_bytes = 0, reg_read_reqd = 1;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(info);
AD9081_NULL_POINTER_RETURN(value);
AD9081_INVALID_PARAM_RETURN(reg >= 0x4000);
if (num_bfs == 1) {
/* Use the standard non multi bit field */
return adi_ad9081_hal_bf_get(device, reg, *info, *value, value_size_bytes);
}
/* Extract the mulit bit-fields from a single reg, or use standard method for more complex situations. */
for (i = 0; i < num_bfs; i++) {
offset = (uint8_t)(*(info + i) >> 0);
width = (uint8_t)(*(info + i) >> 8);
reg_bytes = ((width + offset) >> 3) + (((width + offset) & 7) == 0 ? 0 : 1);
if ( (reg_bytes == 1) && (value_size_bytes == 1) ) {
if (reg_read_reqd == 1) {
reg_read_reqd = 0;
err = adi_ad9081_hal_reg_get(device, reg, &data8);
AD9081_ERROR_RETURN(err);
}
mask = (1 << width) - 1;
**(value + i) = (data8 >> offset) & mask;
} else {
/* Use non-multi bf get */
AD9081_LOG_WARN("Multi bit-field get doesn't support cross register access. Will use standard, but incurs extra SPI reads.");
err = adi_ad9081_hal_bf_get(device, reg, *(info + i), *(value + i), value_size_bytes);
AD9081_ERROR_RETURN(err);
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_hal_multi_bf_set(adi_ad9081_device_t *device, uint32_t reg, uint32_t *info, uint64_t *value, uint8_t num_bfs)
{
int32_t err;
uint32_t mask = 0;
uint8_t data8 = 0, offset = 0, width = 0;
uint8_t i = 0, reg_bytes = 0, reg_read_reqd = 1;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(info);
AD9081_NULL_POINTER_RETURN(value);
AD9081_INVALID_PARAM_RETURN(reg >= 0x4000);
if (num_bfs == 1) {
/* Use the standard non multi bit field */
return adi_ad9081_hal_bf_set(device, reg, *info, *value);
}
/* Write the bit fields */
for (i = 0; i < num_bfs; i++) {
offset = (uint8_t)(*(info + i) >> 0);
width = (uint8_t)(*(info + i) >> 8);
reg_bytes = ((width + offset) >> 3) + (((width + offset) & 7) == 0 ? 0 : 1);
if (reg_bytes == 1) {
if ((reg_read_reqd == 1) && ((offset > 0) || ((offset + width) < 8))) {
reg_read_reqd = 0;
err = adi_ad9081_hal_reg_get(device, reg, &data8);
AD9081_ERROR_RETURN(err);
}
mask = (1 << width) - 1;
data8 = data8 & (~(mask << offset));
data8 = data8 | ((*(value + i) & mask) << offset);
} else {
/* Use non-multi bf set */
AD9081_LOG_WARN("multi bit-field set doesn't support cross register bit-fields.Will use standard, but incurs extra SPI reads.");
err = adi_ad9081_hal_bf_set(device, reg, *(info + i), *(value + i));
AD9081_ERROR_RETURN(err);
}
}
if (reg_read_reqd == 0) {
err = adi_ad9081_hal_reg_set(device, reg, data8);
AD9081_ERROR_RETURN(err);
}
return API_CMS_ERROR_OK;
}
/*! @} */

3698
vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_jesd.c Executable file
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vitis/radar/src/ad9081_api/ad9081/src/adi_ad9081_sync.c Executable file
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/*!
* @brief APIs for SYSREF configuration and control
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup AD9081_SYSREF_API
* @{
*/
/*============= I N C L U D E S ============*/
#include "adi_ad9081_config.h"
#include "adi_ad9081_hal.h"
#include "adi_utils.h"
/*============= C O D E ====================*/
int32_t adi_ad9081_jesd_sysref_enable_set(adi_ad9081_device_t *device, uint8_t enable)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
/* Power down the sysref receiver and sync circuitry. */
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_CTRL_ADDR, BF_SYSREF_PD_INFO, !enable); /* not paged */
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_d2acenter_enable_set(adi_ad9081_device_t *device, uint8_t enable)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
err = adi_ad9081_hal_bf_set(device, REG_SPI_ENABLE_DAC_ADDR, BF_SPI_EN_D2ACENTER_INFO, enable);
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_input_mode_set(adi_ad9081_device_t *device, uint8_t enable_receiver, uint8_t enable_capture, adi_cms_signal_coupling_e input_mode)
{
int32_t err;
AD9081_LOG_FUNC();
AD9081_NULL_POINTER_RETURN(device);
if ((input_mode >= COUPLING_UNKNOWN) || (input_mode < 0)) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_ad9081_jesd_sysref_d2acenter_enable_set(device, 1);
AD9081_ERROR_RETURN(err);
/* 1: AC couple, 0: DC couple */
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_CTRL_ADDR, BF_SYSREF_INPUTMODE_INFO, ((input_mode== COUPLING_AC) ? 1:0)); /* not paged */
AD9081_ERROR_RETURN(err);
/* Power down the sysref receiver and sync circuitry. */
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_CTRL_ADDR, BF_SYSREF_PD_INFO, !enable_receiver); /* not paged */
AD9081_ERROR_RETURN(err);
/* enables sysref capture */
err = adi_ad9081_hal_bf_set(device, 0x0fb0, 0x0103, enable_capture); /* not paged, spi_sysref_en@sysref_control */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_jesd_sysref_d2acenter_enable_set(device, 0);
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_sync_sysref_input_config_set(adi_ad9081_device_t *device, adi_cms_signal_coupling_e coupling_mode, adi_cms_signal_type_e signal_type, uint8_t sysref_single_end_p, uint8_t sysref_single_end_n)
{
int32_t err;
AD9081_LOG_FUNC();
AD9081_NULL_POINTER_RETURN(device);
AD9081_INVALID_PARAM_RETURN(sysref_single_end_n > 15 || sysref_single_end_n < 0);
AD9081_INVALID_PARAM_RETURN(sysref_single_end_p > 15 || sysref_single_end_p < 0);
AD9081_INVALID_PARAM_RETURN(coupling_mode != COUPLING_AC && coupling_mode != COUPLING_DC);
AD9081_INVALID_PARAM_RETURN(signal_type == SIGNAL_UNKNOWN);
if ((coupling_mode == COUPLING_AC && (signal_type == SIGNAL_LVDS || signal_type == SIGNAL_CML || signal_type == SIGNAL_LVPECL)) || coupling_mode == COUPLING_DC) {
err = adi_ad9081_jesd_sysref_input_mode_set(device, 1, 1, (signal_type == SIGNAL_LVDS || signal_type == SIGNAL_CML || signal_type == SIGNAL_LVPECL) ? 0:1);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_jesd_sysref_d2acenter_enable_set(device, 1);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, 0x0fb9, 0x100, (coupling_mode == COUPLING_AC) ? 0:1); /* not paged, sysref_dc_mode_sel */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, 0x0fb9, 0x104, (signal_type == SIGNAL_CMOS) ? 1:0); /* not paged, sysref_single_end_mode_sel */
AD9081_ERROR_RETURN(err);
/* for 1.8V CMOS or higher, set ground ref resistor to 6.3 kohm. For 1.5V CMOS, set to 7.9 kohm.*/
if (signal_type == SIGNAL_CMOS) {
err = adi_ad9081_hal_bf_set(device, 0x0fba, 0x400, sysref_single_end_p); /* not paged, sysref_single_end_p */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, 0x0fba, 0x404, sysref_single_end_n); /* not paged, sysref_single_end_n */
AD9081_ERROR_RETURN(err);
}
err = adi_ad9081_jesd_sysref_d2acenter_enable_set(device, 0);
AD9081_ERROR_RETURN(err);
}
else {
AD9081_LOG_ERR("The SYSREF receiver input buffer cannot be configured in the mode specified.");
return API_CMS_ERROR_INVALID_PARAM;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_sync_sysref_ctrl(adi_ad9081_device_t *device)
{
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(device->clk_info.sysref_clk);
AD9081_NULL_POINTER_RETURN(device->clk_info.sysref_ctrl);
if (API_CMS_ERROR_OK != device->clk_info.sysref_ctrl(device->clk_info.sysref_clk)) {
return API_CMS_ERROR_SYSREF_CTRL;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_oneshot_sync(adi_ad9081_device_t *device, adi_cms_jesd_subclass_e subclass)
{
int32_t err;
uint8_t pd_fdacby4, sync_done;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
err = adi_ad9081_hal_bf_get(device, REG_CLK_CTRL1_ADDR, 0x00000102, &pd_fdacby4, 1); /* not paged */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_CLK_CTRL1_ADDR, 0x00000102, 0); /* not paged */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_ROTATION_MODE_ADDR, BF_ROTATION_MODE_INFO, 1); /* not paged */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_SPI_ENABLE_DAC_ADDR, BF_SPI_EN_D2A0_INFO, 1);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_SPI_ENABLE_DAC_ADDR, BF_SPI_EN_D2A1_INFO, 1);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_SPI_ENABLE_DAC_ADDR, BF_SPI_EN_ANACENTER_INFO, 1);
AD9081_ERROR_RETURN(err);
if (device->dev_info.dev_rev == 3) { /* r2 */
err = adi_ad9081_hal_bf_set(device, REG_ACLK_CTRL_ADDR, BF_PD_TXDIGCLK_INFO, 1); /* not paged */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_ADC_DIVIDER_CTRL_ADDR, 0x00000107, 0); /* not paged */
AD9081_ERROR_RETURN(err);
}
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_MODE_ADDR, BF_SYSREF_MODE_ONESHOT_INFO, 0); /* not paged */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_MODE_ADDR, BF_SYSREF_MODE_ONESHOT_INFO, 1); /* not paged */
AD9081_ERROR_RETURN(err);
if (device->clk_info.sysref_mode == SYSREF_ONESHOT) {
err = adi_ad9081_sync_sysref_ctrl(device);
AD9081_ERROR_RETURN(err);
}
if (err = adi_ad9081_hal_bf_wait_to_clear(device, REG_SYSREF_MODE_ADDR, BF_SYSREF_MODE_ONESHOT_INFO), /* not paged */
err != API_CMS_ERROR_OK) {
AD9081_LOG_WARN("sysref_mode_oneshot bit never cleared.");
}
err = adi_ad9081_hal_bf_get(device, REG_SYSREF_MODE_ADDR, BF_ONESHOT_SYNC_DONE_INFO, &sync_done, 1); /* not paged */
AD9081_ERROR_RETURN(err);
if (sync_done != 1) {
AD9081_LOG_WARN("oneshot sync not finished.");
}
if (device->dev_info.dev_rev == 3) { /* r2 */
err = adi_ad9081_hal_bf_set(device, REG_ADC_DIVIDER_CTRL_ADDR, 0x00000107, 1); /* not paged */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_set(device, REG_ACLK_CTRL_ADDR, BF_PD_TXDIGCLK_INFO, 0); /* not paged */
AD9081_ERROR_RETURN(err);
}
err = adi_ad9081_hal_bf_set(device, REG_CLK_CTRL1_ADDR, 0x00000102, pd_fdacby4); /* not paged */
AD9081_ERROR_RETURN(err);
if (sync_done != 1) {
return API_CMS_ERROR_JESD_SYNC_NOT_DONE;
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_setup_hold_get(adi_ad9081_device_t *device, uint8_t *setup_risk_violation, uint8_t *hold_risk_violation)
{
int32_t err;
uint8_t i=0;
uint8_t scount=0, snum, hcount=0, hnum;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(setup_risk_violation);
AD9081_NULL_POINTER_RETURN(hold_risk_violation);
AD9081_LOG_FUNC();
err = adi_ad9081_hal_bf_get(device, 0x0fb7, 0x800, setup_risk_violation, sizeof(uint8_t)); /* SYSREF_SETUP */
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_get(device, 0x0fb8, 0x800, hold_risk_violation, sizeof(uint8_t)); /* SYSREF_HOLD */
AD9081_ERROR_RETURN(err);
/* Number of 1s in setup time register */
snum = *setup_risk_violation;
for (i = 0; i < 8; i++) {
if (1 & snum){
scount++;
snum = snum >> 1;
}
}
*setup_risk_violation = scount;
/* Number of 1s in hold time register */
hnum = *hold_risk_violation;
for (i = 0; i < 8; i++) {
if (1 & hnum) {
hcount++;
hnum = hnum >> 1;
}
}
*hold_risk_violation = hcount;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_fine_superfine_delay_set(adi_ad9081_device_t *device, uint8_t enable, uint8_t fine_delay, uint8_t superfine_delay) {
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
if (enable > 3) {
return API_CMS_ERROR_INVALID_PARAM;
}
/*Enable Fine and Super fine delay on the SYSREF input
00: SYSREF delay disabled
01: Fine delay
10: Super fine delay
11: both Fine and Superfine Delay*/
err = adi_ad9081_hal_bf_set(device, 0x0fb1, 0x200, enable);
AD9081_ERROR_RETURN(err);
if (enable == 1 || enable == 3) {
err = adi_ad9081_hal_bf_set(device, 0x0fb2, 0x800, fine_delay); /* maximum effective setting is 0x2F */
AD9081_ERROR_RETURN(err);
}
if (enable == 2 || enable == 3) {
err = adi_ad9081_hal_bf_set(device, 0xfb3, 0x800, superfine_delay); /* maximum is approx. 4ps (255 x 16 fs) */
AD9081_ERROR_RETURN(err);
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_count_set(adi_ad9081_device_t *device, uint8_t edges)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_COUNT_ADDR, BF_SYSREF_COUNT_INFO, edges);
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_average_set(adi_ad9081_device_t *device, uint8_t pulses)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
if (pulses > 0x7) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_AVERAGE_ADDR, BF_SYSREF_AVERAGE_INFO, pulses);
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_monitor_phase_get(adi_ad9081_device_t *device, uint16_t *sysref_phase)
{
int32_t err;
uint8_t phase0_val;
uint8_t phase1_val;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(sysref_phase);
AD9081_LOG_FUNC();
/* Write strobe to trigger a value update */
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_PHASE0_ADDR, 0x800, 0x00);
err = adi_ad9081_hal_bf_get(device, REG_SYSREF_PHASE0_ADDR, 0x800, &phase0_val, sizeof(uint8_t));
err = adi_ad9081_hal_bf_get(device, REG_SYSREF_PHASE1_ADDR, 0x400, &phase1_val, sizeof(uint8_t));
*sysref_phase = (phase1_val << 8) + phase0_val;
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_monitor_lmfc_align_error_get(adi_ad9081_device_t *device, uint8_t *lmfc_align_err)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(lmfc_align_err);
AD9081_LOG_FUNC();
err = adi_ad9081_hal_bf_get(device, REG_SYSREF_ERR_WINDOW_ADDR, BF_SYSREF_WITHIN_LMFC_ERRWINDOW_INFO, lmfc_align_err, sizeof(uint8_t));
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_monitor_lmfc_align_threshold_set(adi_ad9081_device_t *device, uint8_t sysref_error_window)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
if (sysref_error_window > 0x7F) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_ad9081_hal_bf_set(device, REG_SYSREF_ERR_WINDOW_ADDR, BF_SYSREF_ERR_WINDOW_INFO, sysref_error_window);
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_irq_enable_set(adi_ad9081_device_t *device, uint8_t enable)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
err = adi_ad9081_hal_bf_set(device, REG_IRQ_ENABLE_0_ADDR, BF_EN_SYSREF_IRQ_INFO, enable);
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_irq_jitter_mux_set(adi_ad9081_device_t *device, uint8_t pin)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_LOG_FUNC();
if (pin != 0 && pin != 1) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_ad9081_hal_bf_set(device, REG_IRQ_OUTPUT_MUX_0_ADDR, BF_MUX_SYSREF_JITTER_INFO, pin);
AD9081_ERROR_RETURN(err);
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_jesd_sysref_oneshot_sync_done_get(adi_ad9081_device_t *device, uint8_t *sync_done)
{
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(sync_done);
AD9081_LOG_FUNC();
err = adi_ad9081_hal_bf_get(device, REG_SYSREF_MODE_ADDR, BF_ONESHOT_SYNC_DONE_INFO, sync_done, 1); /* not paged */
AD9081_ERROR_RETURN(err);
if (*sync_done != 1) {
AD9081_LOG_ERR("oneshot sync not finished.");
}
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_sync_calc_jrx_lmfc_lemc(uint64_t dac_clk, uint8_t main_interp, uint8_t ch_interp, adi_cms_jesd_param_t *jesd_param, uint64_t *lmfc_freq) {
if (lmfc_freq == NULL){
return API_CMS_ERROR_NULL_PARAM;
}
#ifdef __KERNEL__
*lmfc_freq = div64_u64(dac_clk, jesd_param->jesd_s * jesd_param->jesd_k * main_interp * ch_interp);
#else
*lmfc_freq = (dac_clk)/(jesd_param->jesd_s * jesd_param->jesd_k * main_interp * ch_interp);
#endif
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_sync_calc_jtx_lmfc_lemc(uint64_t adc_clk, uint8_t cddc_dcm[4], uint8_t fddc_dcm[8], adi_ad9081_jesd_link_select_e links, adi_cms_jesd_param_t jesd_param[2], uint64_t *lmfc_freq) {
uint64_t lmfc_link0, lmfc_link1, gcd, min_link, max_link, lmfc_gcd;
uint8_t cdcm, fdcm;
if (lmfc_freq == NULL){
return API_CMS_ERROR_NULL_PARAM;
}
cdcm = adi_ad9081_adc_ddc_coarse_dcm_decode(cddc_dcm[0]);
fdcm = adi_ad9081_adc_ddc_fine_dcm_decode(fddc_dcm[0]);
if (jesd_param->jesd_duallink > 0) {
#ifdef __KERNEL__
/* link 0 */
lmfc_link0 = div64_u64(adc_clk, jesd_param[0].jesd_s * jesd_param[0].jesd_k * cdcm * fdcm);
/* link 1 */
lmfc_link1 = div64_u64(adc_clk, jesd_param[1].jesd_s * jesd_param[1].jesd_k * cdcm * fdcm);
#else
/* link 0 */
lmfc_link0 = (adc_clk)/(jesd_param[0].jesd_s * jesd_param[0].jesd_k * cdcm * fdcm);
/* link 1 */
lmfc_link1 = (adc_clk)/(jesd_param[1].jesd_s * jesd_param[1].jesd_k * cdcm * fdcm);
#endif
/* gcd between links */
max_link = (lmfc_link0 >= lmfc_link1) ? lmfc_link0 : lmfc_link1;
min_link = (lmfc_link0 >= lmfc_link1) ? lmfc_link1 : lmfc_link0;
gcd = adi_api_utils_gcd(min_link, max_link);
lmfc_gcd = gcd;
}
else {
/* link 0 */
#ifdef __KERNEL__
lmfc_link0 = div64_u64(adc_clk, jesd_param[0].jesd_s*jesd_param[0].jesd_k*cdcm*fdcm);
#else
lmfc_link0 = (adc_clk)/(jesd_param[0].jesd_s*jesd_param[0].jesd_k*cdcm*fdcm);
#endif
lmfc_gcd = lmfc_link0;
}
*lmfc_freq = lmfc_gcd;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_sync_sysref_frequency_set(adi_ad9081_device_t *device, uint64_t *sysref_freq, uint64_t dev_ref, uint64_t dac_clk, uint64_t adc_clk, uint8_t main_interp, uint8_t ch_interp, uint8_t cddc_dcm[4], uint8_t fddc_dcm[8], adi_ad9081_jesd_link_select_e jtx_links, adi_cms_jesd_param_t *jrx_param, adi_cms_jesd_param_t jtx_param[2]) {
uint64_t jrx_lmfc=0, jtx_lmfc=0, max_lmfc=0, min_lmfc=0, gcd=0;
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(sysref_freq);
AD9081_NULL_POINTER_RETURN(jrx_param);
AD9081_LOG_FUNC();
/* jrx */
if (jrx_param->jesd_l > 0) {
AD9081_INVALID_PARAM_RETURN(jrx_param->jesd_s==0 || jrx_param->jesd_k==0 || main_interp==0 || ch_interp==0);
err = adi_ad9081_sync_calc_jrx_lmfc_lemc(dac_clk, main_interp, ch_interp, jrx_param, &jrx_lmfc);
AD9081_ERROR_RETURN(err);
if (jrx_lmfc == 0) {AD9081_LOG_ERR("LMFC/LEMC = 0, missing input params");}
/* Internal PLL requires LMFC and dev_ref to be integer multiples*/
printf("Dev Ref: %f, JRX_LMFC: %f, Dac Clk: %f\r\n", dev_ref/1e6, jrx_lmfc/1e6, dac_clk/1e6);
if (dev_ref != dac_clk && dev_ref % jrx_lmfc != 0 && jrx_lmfc % dev_ref != 0) {
AD9081_LOG_WARN("JRx LMFC/LEMC and dev_ref clock are not integer multiples. DL will not be achieved.");
}
}
/* jtx */
if (jtx_param[0].jesd_l > 0) {
AD9081_INVALID_PARAM_RETURN(jtx_param[0].jesd_s==0 || jtx_param[0].jesd_k==0);
if (jtx_param[0].jesd_duallink==1) {AD9081_INVALID_PARAM_RETURN(jtx_param[1].jesd_s==0 || jtx_param[1].jesd_k==0); }
err = adi_ad9081_sync_calc_jtx_lmfc_lemc(adc_clk, cddc_dcm, fddc_dcm, jtx_links, jtx_param, &jtx_lmfc);
AD9081_ERROR_RETURN(err);
if (jtx_lmfc == 0) {AD9081_LOG_ERR("LMFC/LEMC = 0, missing input params");}
/* Internal PLL requires LMFC and dev_ref to be integer multiples*/
printf("Dev Ref: %f, JRX_LMFC: %f, Dac Clk: %f\r\n", dev_ref/1e6, jtx_lmfc/1e6, dac_clk/1e6);
if (dev_ref != dac_clk && dev_ref % jtx_lmfc != 0 && jtx_lmfc % dev_ref != 0) {
AD9081_LOG_WARN("JTx LMFC/LEMC and dev_ref clock are not integer multiples. DL will not be achieved.");
}
}
/* gcd */
max_lmfc = (jrx_lmfc >= jtx_lmfc) ? jrx_lmfc : jtx_lmfc;
min_lmfc = (jrx_lmfc >= jtx_lmfc) ? jtx_lmfc : jrx_lmfc;
gcd = adi_api_utils_gcd(min_lmfc, max_lmfc);
*sysref_freq = gcd;
return API_CMS_ERROR_OK;
}
int32_t adi_ad9081_sync_jrx_tpl_phase_diff_get(adi_ad9081_device_t *device, adi_ad9081_jesd_link_select_e links, uint8_t *jrx_phase_diff) {
int32_t err;
AD9081_NULL_POINTER_RETURN(device);
AD9081_NULL_POINTER_RETURN(jrx_phase_diff);
AD9081_LOG_FUNC();
if ((links & AD9081_LINK_0) > 0) {
err = adi_ad9081_jesd_rx_link_select_set(device, AD9081_LINK_0);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_get(device, REG_JRX_TPL_5_ADDR, BF_JRX_TPL_PHASE_DIFF_INFO, jrx_phase_diff, 1);
AD9081_ERROR_RETURN(err);
}
if ((links & AD9081_LINK_1) > 0) {
err = adi_ad9081_jesd_rx_link_select_set(device, AD9081_LINK_1);
AD9081_ERROR_RETURN(err);
err = adi_ad9081_hal_bf_get(device, REG_JRX_TPL_5_ADDR, BF_JRX_TPL_PHASE_DIFF_INFO, jrx_phase_diff, 1);
AD9081_ERROR_RETURN(err);
}
return API_CMS_ERROR_OK;
}

332
vitis/radar/src/ad9081_api/adi_inc/adi_ad7175.h Executable file
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@@ -0,0 +1,332 @@
/*!
* @brief API header file
* This file contains all the publicly exposed methods and data
* structures to interface with API.
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup ADI_AD7175
* @{
*/
#ifndef __ADI_AD7175_H__
#define __ADI_AD7175_H__
/*============= I N C L U D E S ============*/
#include "adi_cms_api_common.h"
/*============= D E F I N E S ==============*/
typedef enum {
AD7175_MODE_CONT_CONV = 0x0000, /* Continous conversion mode */
AD7175_MODE_SINGLE_CONV = 0x0001, /* Single conversion mode*/
AD7175_MODE_STANDBY = 0x0002, /* Standby mode */
AD7175_MODE_PD = 0x0003, /* Power-down mode */
AD7175_MODE_INT_OFFSET_CAL = 0x0004, /* Internal offset calibration */
AD7175_MODE_SYS_OFFSET_CAL = 0x0006, /* System offset calibration */
AD7175_MODE_SYS_GAIN_CAL = 0x0007, /* System gain calibration */
}adi_ad7175_adc_mode_e;
typedef enum {
AD7175_INTF_WL16 = 0x01, /* Changes ADC data register to 16 bits */
AD7175_INTF_CRC_EN = 0x0D, /* Enables CRC protection of register r/w */
AD7175_INTF_REG_CHECK = 0x20, /* Enables register integrity checker */
AD7175_INTF_DATA_STAT = 0x40, /* Enables status register appending to data register */
AD7175_INTF_CONTREAD = 0x80, /* Enables continuous read mode of ADC data*/
AD7175_INTF_DOUT_RESET = 0x100, /* Resets DOUT pin */
AD7175_INTF_IOSTRENGTH = 0x200, /* Enables drive strength of DOUT pin */
AD7175_INTF_ALT_SYNC = 0x400, /* Enables SYNC pin as conversion control */
}adi_ad7175_interface_mode_e;
typedef enum {
AD7175_INT_OSC = 0x0, /* Internal oscillator */
AD7175_INT_OSC_XTAL2 = 0x1, /* Internal oscillator output on XTAL2/CLKIO pin */
AD7175_EXT_CLKIO = 0x2, /* External clock input on XTAL2/CLKIO pin */
AD7175_XTAL2 = 0x3, /* External crystal on XTAL1 and XTAL2/CLKIO pins */
}adi_ad7175_clk_sel_e;
typedef enum {
AD7175_DELAY_0_US = 0x0,
AD7175_DELAY_4_US = 0x1,
AD7175_DELAY_16_US = 0x2,
AD7175_DELAY_40_US = 0x3,
AD7175_DELAY_100_US = 0x4,
AD7175_DELAY_200_US = 0x5,
AD7175_DELAY_500_US = 0x6,
AD7175_DELAY_1000_US = 0x7,
}adi_ad7175_prog_delay_e;
typedef enum {
AD7175_DISABLE = 0x0000, /* Disabled */
AD7175_XOR_R_CHECKSUM = 0x0001, /* XOR checksum for read, CRC for write */
AD7175_CRC_WR_CHECKSUM = 0x0002, /* CRC checksum for r/w */
}adi_ad7175_crc_en_e;
typedef enum {
AD7175_SETUP0 = 0x0000,
AD7175_SETUP1 = 0x0001,
AD7175_SETUP2 = 0x0002,
AD7175_SETUP3 = 0x0003,
AD7175_SETUP4 = 0x0004,
AD7175_SETUP5 = 0x0005,
AD7175_SETUP6 = 0x0006,
AD7175_SETUP7 = 0x0007,
}adi_ad7175_setup_sel_e;
typedef enum {
AD7175_SETUP_REF_EXT = 0x00, /* External reference */
AD7175_SETUP_REF_EXT2 = 0x01, /* External reference 2 supplied to AIN1/REF2+ AND AIN0/REF2- pins */
AD7175_SETUP_REF_INT = 0x02, /* Internal 2.5V reference */
AD7175_SETUP_REF_AVDD1_AVSS = 0x03, /* AVDDS1 - AVSS Diagonstic to validate other refs */
}adi_ad7175_setup_ref_sel_e;
typedef enum {
AD7175_SETUP_BURNOUT_EN = 0x80, /* Enables burnout currents */
AD7175_SETUP_AINBUF_N = 0x100, /* Enables AIN- input buffer */
AD7175_SETUP_AINBUF_P = 0x200, /* Enables AIN+ input buffer */
AD7175_SETUP_REFBUF_N = 0x400, /* Enables REF- input buffer */
AD7175_SETUP_REFBUF_P = 0x800, /* Enables REF+ input buffer */
AD7175_SETUP_BI_UNIPOLAR = 0x1000, /* Output coding */
}adi_ad7175_setup_config_e;
typedef enum {
AD7175_AIN0 = 0x0000,
AD7175_AIN1 = 0x0001,
AD7175_AIN2 = 0x0002,
AD7175_AIN3 = 0x0003,
AD7175_AIN4 = 0x0004,
AD7175_AIN5 = 0x0005,
AD7175_AIN6 = 0x0006,
AD7175_AIN7 = 0x0007,
AD7175_AIN8 = 0x0008,
AD7175_AIN9 = 0x0009,
AD7175_AIN10 = 0x000A,
AD7175_AIN11 = 0x000B,
AD7175_AIN12 = 0x000C,
AD7175_AIN13 = 0x000D,
AD7175_AIN14 = 0x000E,
AD7175_AIN15 = 0x000F,
AD7175_AIN16 = 0x0010,
}adi_ad7175_ain_e;
typedef struct {
void * user_data;
adi_spi_xfer_t spi_xfer; /*!< Function Pointer to HAL SPI access function */
adi_delay_us_t delay_us; /*!< Function Pointer to HAL delay function */
adi_hw_open_t hw_open; /*!< OPTIONAL Function Pointer to HAL initialization function */
adi_hw_close_t hw_close; /*!< OPTIONAL Function Pointer to HAL De-initialization function */
}adi_ad7175_hal_t;
typedef struct {
uint8_t dev_prod_id; /*!< Product ID */
}adi_ad7175_info_t;
typedef struct {
adi_ad7175_hal_t hal_info; /*!< HAL information */
adi_ad7175_info_t dev_info; /*!< DEV information */
}adi_ad7175_device_t;
/*============= E X P O R T S ==============*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Open device
*
* @param device Pointer to the device structure
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return API_CMS_ERROR_INVALID_HANDLE_PARAM Invalid Device Handle
* @return API_CMS_ERROR_INVALID_SPI_XFER_PTR Invalid HAL SPI XFER FUNCTION
* @return API_CMS_ERROR_INVALID_DELAYUS_PTR Invalid HAL SPI XFER FUNCTION
* @return API_CMS_ERROR_DELAY_US Invalid HAL SPI XFER FUNCTION
*/
int32_t adi_ad7175_device_hw_open(adi_ad7175_device_t *device);
/**
* @brief Close device
*
* @param device Pointer to the device structure
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return API_CMS_ERROR_INVALID_HANDLE_PARAM Invalid Device Handle
* @return API_CMS_ERROR_INVALID_DELAYUS_PTR Invalid HAL SPI XFER FUNCTION
* @return API_CMS_ERROR_DELAY_US Invalid HAL SPI XFER FUNCTION
*/
int32_t adi_ad7175_device_hw_close(adi_ad7175_device_t *device);
/**
* @brief Perform SPI register write access to device
*
* @param device Pointer to the device structure
* @param addr SPI address to which the value of data parameter shall be written
* @param val 8-bit value to be written to SPI register defined
* by the address parameter.
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return API_CMS_ERROR_INVALID_HANDLE_PARAM Invalid Device Handle
* @return API_CMS_ERROR_SPI_XFER SPI Access Failed
* @return API_CMS_ERROR_INVALID_PARAM Invalid Parameter
*/
int32_t adi_ad7175_device_spi_register_set(adi_ad7175_device_t *device, uint16_t addr, uint32_t val);
/**
* @brief Perform SPI register read access to device.
*
*
* @param device Pointer to the device structure
* @param addr SPI address from which the value of val parameter shall be read,
* @param val Pointer to an 8-bit variable to which the value of the
* SPI register at the address defined by address parameter
* shall be stored.
* @param size_bytes Number of bytes being read
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return API_CMS_ERROR_INVALID_HANDLE_PARAM Invalid Device Handle
* @return API_CMS_ERROR_SPI_XFER SPI Access Failed
* @return API_CMS_ERROR_INVALID_PARAM Invalid Parameter
*/
int32_t adi_ad7175_device_spi_register_get(adi_ad7175_device_t *device, uint16_t addr, uint32_t *val, uint32_t size_bytes);
/**
* @brief Get API Revision Data
*
* @param device Pointer to the device structure.
* @param rev_major Pointer to variable to store the Major Revision Number
* @param rev_minor Pointer to variable to store the Minor Revision Number
* @param rev_rc Pointer to variable to store the RC Revision Number
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return API_CMS_ERROR_INVALID_HANDLE_PARAM Invalid Device Handle
* @return API_CMS_ERROR_INVALID_PARAM Invalid Parameter
*/
int32_t adi_ad7175_device_api_revision_get(adi_ad7175_device_t *device, uint8_t *rev_major, uint8_t *rev_minor, uint8_t *rev_rc);
/**
* @brief Get chip identification data
*
* @param device Pointer to the device structure
* @param id Pointer to chip id
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_id_get(adi_ad7175_device_t *device, uint32_t *id);
/**
* @brief Configure channel
*
* @param device Pointer to the device structure
* @param chan Channel Index
* @param ch_enable Enable: 1, Disable: 0
* @param setup Selected configuration for channel
* @param ainpos Positive analog input to channel
* @param ainneg Negative analog input to channel
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_channel_config_set(adi_ad7175_device_t *device, uint8_t chan, uint8_t ch_enable, adi_ad7175_setup_sel_e setup,
adi_ad7175_ain_e ainpos, adi_ad7175_ain_e ainneg);
/**
* @brief Run selected channel
*
* @param device Pointer to the device structure
* @param chan Channel Index
* @param ref_en Enable internal reference and output to REFOUT pin
* Enable:1, Disable:0
* @param clk_sel Select ADC clock source @see adi_ad7175_clk_sel_e for details
* @param adc_mode Desired conversion mode of the adc, @see adi_ad7175_adc_mode_e for details
* @param delay Desired programmable delay after channel switch @see adi_ad7175_prog_delay_e for details
* @param hide_delay Hides delay by absorbing it into conversion time for selected data rates
* Enable:0, Disable:1
* @param sing_cyc Set ADC to only output at settled filter data rate when using single channel only
* Enable:1, Disable:0
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_channel_run(adi_ad7175_device_t *device, uint8_t chan, uint8_t ref_en, adi_ad7175_clk_sel_e clk_sel,
adi_ad7175_adc_mode_e adc_mode, adi_ad7175_prog_delay_e delay, uint8_t hide_delay, uint8_t sing_cyc);
/**
* @brief Configures the reference selection, input buffers, and output coding
*
* @param device Pointer to the device structure
* @param setup Selected configuration for channel, @see adi_ad7175_setup_sel_e for options
* @param ref_sel Select reference source for ADC conversion, @see adi_ad7175_setup_ref_sel_e for details
* @param setup_config Selection configuration of input buffers and output coding, @see adi_ad7175_setup_config_e for details
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_setup_config_set(adi_ad7175_device_t *device, adi_ad7175_setup_sel_e setup, adi_ad7175_setup_ref_sel_e ref_sel, uint32_t setup_config);
/**
* @brief Set conversion mode of ADC to continuous or single
*
* @param device Pointer to the device structure
* @param ref_en Enable internal reference and output to REFOUT pin
* Enable:1, Disable:0
* @param clk_sel Select ADC clock source @see adi_ad7175_clk_sel_e for details
* @param adc_mode Desired conversion mode of the adc, @see adi_ad7175_adc_mode_e for details
* @param delay Desired programmable delay after channel switch @see adi_ad7175_prog_delay_e for details
* @param hide_delay Hides delay by absorbing it into conversion time for selected data rates
* Enable:0, Disable:1
* @param sing_cyc Set ADC to only output at settled filter data rate when using single channel only
* Enable:1, Disable:0
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_adc_mode_config_set(adi_ad7175_device_t *device, uint8_t ref_en, adi_ad7175_clk_sel_e clk_sel,
adi_ad7175_adc_mode_e adc_mode, adi_ad7175_prog_delay_e delay, uint8_t hide_delay, uint8_t sing_cyc);
/**
* @brief Configure serial interface options
*
* @param device Pointer to the device structure
* @param intf_mode Desired digital interface operation, @see adi_ad7175_interface_mode_e for details
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_intf_config_set(adi_ad7175_device_t *device, uint32_t intf_mode);
/**
* @brief Get ADC conversion result
*
* @param device Pointer to the device structure
* @param data_status Pointer to ADC conversion result
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_data_get(adi_ad7175_device_t *device, uint32_t *data_status);
/**
* @brief Checks status bit and triggers data conversion
*
* @param device Pointer to the device structure
* @param data_status Pointer to status and data register data
* @param channel Active channel index
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t adi_ad7175_device_run_data_conv_get(adi_ad7175_device_t *device, uint32_t *data_status, uint8_t channel);
#ifdef __cplusplus
}
#endif
#endif /* __ADI_AD7175_H__ */
/*! @} */

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/*!
* @brief Common API definitions header file.
* This file contains all common API definitions.
*
* @copyright copyright(c) 2020 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup ADI_API_COMMON
* @{
*/
#ifndef __ADI_CMS_API_COMMON_H__
#define __ADI_CMS_API_COMMON_H__
/*============= I N C L U D E S ============*/
#include <stdio.h>
#include <stdint.h>
#include <stddef.h>
#include <stdarg.h>
#include "adi_cms_api_config.h"
/*============= D E F I N E S ==============*/
/*!
* @brief Enumerate error code
*/
typedef enum {
API_CMS_ERROR_OK = 0, /*!< No Error */
API_CMS_ERROR_ERROR = -1, /*!< General Error */
API_CMS_ERROR_NULL_PARAM = -2, /*!< Null parameter */
API_CMS_ERROR_SPI_SDO = -10, /*!< Wrong value assigned to the SDO in device structure */
API_CMS_ERROR_INVALID_HANDLE_PTR = -11, /*!< Device handler pointer is invalid */
API_CMS_ERROR_INVALID_XFER_PTR = -12, /*!< Invalid pointer to the SPI xfer function assigned */
API_CMS_ERROR_INVALID_DELAYUS_PTR = -13, /*!< Invalid pointer to the delay_us function assigned */
API_CMS_ERROR_INVALID_PARAM = -14, /*!< Invalid parameter passed */
API_CMS_ERROR_INVALID_RESET_CTRL_PTR = -15, /*!< Invalid pointer to the reset control function assigned */
API_CMS_ERROR_NOT_SUPPORTED = -16, /*!< Not supported */
API_CMS_ERROR_VCO_OUT_OF_RANGE = -20, /*!< The VCO is out of range */
API_CMS_ERROR_PLL_NOT_LOCKED = -21, /*!< PLL is not locked */
API_CMS_ERROR_DLL_NOT_LOCKED = -22, /*!< DLL is not locked */
API_CMS_ERROR_MODE_NOT_IN_TABLE = -23, /*!< JESD Mode not in table */
API_CMS_ERROR_JESD_PLL_NOT_LOCKED = -24, /*!< PD STBY function error */
API_CMS_ERROR_JESD_SYNC_NOT_DONE = -25, /*!< JESD_SYNC_NOT_DONE */
API_CMS_ERROR_FTW_LOAD_ACK = -30, /*!< FTW acknowledge not received */
API_CMS_ERROR_NCO_NOT_ENABLED = -31, /*!< The NCO is not enabled */
API_CMS_ERROR_INIT_SEQ_FAIL = -40, /*!< Initialization sequence failed */
API_CMS_ERROR_TEST_FAILED = -50, /*!< Test failed */
API_CMS_ERROR_SPI_XFER = -60, /*!< SPI transfer error */
API_CMS_ERROR_TX_EN_PIN_CTRL = -62, /*!< TX enable function error */
API_CMS_ERROR_RESET_PIN_CTRL = -63, /*!< HW reset function error */
API_CMS_ERROR_EVENT_HNDL = -64, /*!< Event handling error */
API_CMS_ERROR_HW_OPEN = -65, /*!< HW open function error */
API_CMS_ERROR_HW_CLOSE = -66, /*!< HW close function error */
API_CMS_ERROR_LOG_OPEN = -67, /*!< Log open error */
API_CMS_ERROR_LOG_WRITE = -68, /*!< Log write error */
API_CMS_ERROR_LOG_CLOSE = -69, /*!< Log close error */
API_CMS_ERROR_DELAY_US = -70, /*!< Delay error */
API_CMS_ERROR_PD_STBY_PIN_CTRL = -71, /*!< PD STBY function error */
API_CMS_ERROR_SYSREF_CTRL = -72 /*!< SYSREF enable function error */
} adi_cms_error_e;
/*!
* @brief Enumerate log source type
*/
typedef enum {
ADI_CMS_LOG_NONE = 0x0000, /*!< all not selected */
ADI_CMS_LOG_ERR = 0x0001, /*!< error message */
ADI_CMS_LOG_WARN = 0x0002, /*!< warning message */
ADI_CMS_LOG_MSG = 0x0004, /*!< tips info message */
ADI_CMS_LOG_SPI = 0x0010, /*!< spi r/w info message */
ADI_CMS_LOG_API = 0x0020, /*!< api info message */
ADI_CMS_LOG_ALL = 0xFFFF /*!< all selected */
} adi_cms_log_type_e;
/*!
* @brief ADI Device Identification Data
*/
typedef struct {
uint8_t chip_type; /*!< Chip Type Code */
uint16_t prod_id; /*!< Product ID Code */
uint8_t prod_grade; /*!< Product Grade Code */
uint8_t dev_revision; /*!< Device Revision */
}adi_cms_chip_id_t;
/*!
* @brief API register access structure
*/
typedef struct {
uint16_t reg; /*!< Register address */
uint8_t val; /*!< Register value */
}adi_cms_reg_data_t;
/*!
* @brief SPI mode settings
*/
typedef enum {
SPI_NONE = 0, /*!< Keep this for test */
SPI_SDO = 1, /*!< SDO active, 4-wire only */
SPI_SDIO = 2, /*!< SDIO active, 3-wire only */
SPI_CONFIG_MAX = 3 /*!< Keep it last */
}adi_cms_spi_sdo_config_e;
/*!
* @brief SPI bit order settings
*/
typedef enum {
SPI_MSB_LAST = 0, /*!< LSB first */
SPI_MSB_FIRST = 1 /*!< MSB first */
}adi_cms_spi_msb_config_e;
/*!
* @brief SPI address increment settings
*/
typedef enum {
SPI_ADDR_DEC_AUTO = 0, /*!< auto decremented */
SPI_ADDR_INC_AUTO = 1 /*!< auto incremented */
}adi_cms_spi_addr_inc_e;
/*!
*@brief driver operation mode
*/
typedef enum
{
OPEN_DRAIN_MODE = 0,
CMOS_MODE = 1
}adi_cms_driver_mode_config_e;
/*!
* @brief Enumerate Impedance Types
*/
typedef enum {
ADI_CMS_NO_INTERNAL_RESISTOR = 0, /*!< disable internal resistor */
ADI_CMS_INTERNAL_RESISTOR_100_OHM = 1, /*!< internal 100ohm resistor */
ADI_CMS_INTERNAL_RESISTOR_50_OHM = 2, /*!< internal 50ohm resistor */
ADI_CMS_INTERNAL_RESISTOR_UNKNOWN =3 /*!< unknown type */
}adi_cms_signal_impedance_type_e;
/*!
* @brief Enumerate Signal Types
*/
typedef enum {
SIGNAL_CMOS = 0, /*!< CMOS signal */
SIGNAL_LVDS = 1, /*!< LVDS signal */
SIGNAL_CML = 2, /*!< CML signal */
SIGNAL_LVPECL = 3, /*!< LVPECL signal */
SIGNAL_UNKNOWN = 4 /*!< UNKNOW signal */
}adi_cms_signal_type_e;
/*!
* @brief Enumerate coupling mode
*/
typedef enum {
COUPLING_AC = 0, /*!< AC coupled signal */
COUPLING_DC = 1, /*!< DC signal */
COUPLING_UNKNOWN = 2 /*!< UNKNOWN coupling */
}adi_cms_signal_coupling_e;
/*!
* @brief Enumerates JESD LINK Signals
*/
typedef enum {
JESD_LINK_NONE = 0, /*!< JESD link none */
JESD_LINK_0 = 1, /*!< JESD link 0 */
JESD_LINK_1 = 2, /*!< JESD link 1 */
JESD_LINK_ALL = 3 /*!< All JESD links */
}adi_cms_jesd_link_e;
/*!
* @brief Enumerates SYNCOUTB Output Signals
*/
typedef enum {
SYNCOUTB_0 = 0x0, /*!< SYNCOUTB 0 */
SYNCOUTB_1 = 0x1, /*!< SYNCOUTB 1 */
SYNCOUTB_ALL = 0xFF /*!< ALL SYNCOUTB SIGNALS */
}adi_cms_jesd_syncoutb_e;
/*!
* @brief Enumerates SYSREF Synchronization Mode
*/
typedef enum {
SYSREF_NONE = 0, /*!< No SYSREF Support */
SYSREF_ONESHOT = 1, /*!< ONE-SHOT SYSREF */
SYSREF_CONT = 2, /*!< Continuous SysRef sync. */
SYSREF_MON = 3, /*!< SYSREF monitor mode */
SYSREF_MODE_INVALID = 4
}adi_cms_jesd_sysref_mode_e;
/*!
* @brief Enumerates PRBS pattern type
*/
typedef enum {
PRBS_NONE = 0, /*!< PRBS off */
PRBS7 = 1, /*!< PRBS7 pattern */
PRBS9 = 2, /*!< PRBS9 pattern */
PRBS15 = 3, /*!< PRBS15 pattern */
PRBS23 = 4, /*!< PRBS23 pattern */
PRBS31 = 5, /*!< PRBS31 pattern */
PRBS_MAX = 6 /*!< Number of member */
}adi_cms_jesd_prbs_pattern_e;
/*!
* @brief Enumerates all available Jesd Subclass Modes
*/
typedef enum {
JESD_SUBCLASS_0 = 0, /*!< JESD SUBCLASS 0 */
JESD_SUBCLASS_1 = 1, /*!< JESD SUBCLASS 1 */
JESD_SUBCLASS_INVALID = 2
}adi_cms_jesd_subclass_e;
/*!
* @brief Defines JESD Parameters
*/
typedef struct {
uint8_t jesd_l; /*!< No of lanes */
uint8_t jesd_f; /*!< No of octets in a frame */
uint8_t jesd_m; /*!< No of converters */
uint8_t jesd_s; /*!< No of samples */
uint8_t jesd_hd; /*!< High Density */
uint16_t jesd_k; /*!< No of frames for a multi-frame */
uint8_t jesd_n; /*!< Converter resolution */
uint8_t jesd_np; /*!< Bit packing sample */
uint8_t jesd_cf; /*!< Parameter CF */
uint8_t jesd_cs; /*!< Parameter CS */
uint8_t jesd_did; /*!< Device ID DID */
uint8_t jesd_bid; /*!< Bank ID. BID */
uint8_t jesd_lid0; /*!< Lane ID for lane0 */
uint8_t jesd_subclass; /*!< Subclass */
uint8_t jesd_scr; /*!< Scramble enable */
uint8_t jesd_duallink; /*!< Link mode (single/dual) */
uint8_t jesd_jesdv; /*!< Version (0:204A, 1:204B, 2:204C) */
uint8_t jesd_mode_id; /*!< JESD mode ID */
uint8_t jesd_mode_c2r_en; /*!< JESD mode C2R enable */
uint8_t jesd_mode_s_sel; /*!< JESD mode S value */
}adi_cms_jesd_param_t;
/*!
* @brief Enumerate ADI Device Operating Mode
*/
typedef enum {
TX_ONLY = 1, /*!< Chip using Tx path only */
RX_ONLY = 2, /*!< Chip using Rx path only */
TX_RX_ONLY = 3 /*!< Chip using Tx + Rx both paths */
}adi_cms_chip_op_mode_t;
/**
* @brief Platform dependent SPI access functions.
*
* @param in_data Pointer to array with the data to be sent on the SPI
* @param out_data Pointer to array where the data to which the SPI will be written
* @param size_bytes The size in bytes allocated for each of the in_data and out_data arrays.
* bit[31:28]: 0000-8bit reg data, 0001-16bit reg data, 0010-32bit reg data
*
* @return 0 for success
* @return Any non-zero value indicates an error
*
* @note in_data and out_data arrays are of same size.
*/
typedef int32_t(*adi_spi_xfer_t)(void *user_data, uint8_t *in_data, uint8_t *out_data, uint32_t size_bytes);
/**
* @brief Delay for specified number of microseconds. Platform Dependant.
* Performs a blocking or sleep delay for the specified time in microseconds
* The implementation of this function is platform dependent and
* is required for correct operation of the API.
*
* @param us time to delay/sleep in microseconds.
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_delay_us_t)(void *user_data, uint32_t us);
/**
* @brief Write log message. Platform Dependant.
*
* @param user_data A void pointer to a client defined structure containing any
* parameters/settings that may be required by the function
* to write log messages for the ADI Device.
* @param log_type @see adi_cms_log_type_e
* @param message Format string
* @param argp Variable message
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_log_write_t)(void *user_data, int32_t log_type, const char *message, va_list argp);
/**
* @brief Write log message. Platform Dependant.
*
* @param user_data A void pointer to a client defined structure containing any
* parameters/settings that may be required by the function
* to write log messages for the ADI Device.
* @param log_type @see adi_cms_log_type_e
* @param message Message string
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_log_write_s_t)(void *user_data, int32_t log_type, char *message);
/**
* @brief Platform hardware initialization for the ADL5580 Device
* This function shall initialize all external hardware resources required by
* the ADI Device and API for correct functionality as per the
* target platform.
* For example initialization of SPI, GPIO resources, clocks etc.
*
* @param user_data A void pointer to a client defined structure containing any
* parameters/settings that may be required by the function
* to initialize the hardware for the ADI Device.
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_hw_open_t)(void *user_data);
/**
* @brief Closes any platform hardware resources for device.
* This function shall close or shutdown all external hardware resources
* required by the ADL5580 Device and API for correct functionality
* as per the target platform.
* For example initialization of SPI, GPIO resources, clocks etc.
* It should close and free any resources assigned in the hw_open_t function.
*
* @param user_data A void pointer to a client defined structure containing any
* parameters/settings that may be required by the function
* to close/shutdown the hardware for the ADI Device.
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_hw_close_t)(void *user_data);
/**
* @brief Client Event Handler
*
* @param event A uint16_t value representing the event that occurred.
* @param ref A uint8_t value indicating the reference for that event if any.
* For example 0 if even occurred on lane 0.
* @param data A void pointer to any user data that may pertain to that event.
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_event_handler_t)(uint16_t event, uint8_t ref, void* data);
/**
* @brief tx_enable pin control function
*
* @param user_data A void pointer to a client defined structure containing
* any parameters/settings that may be required by the function
* to control the hardware for the ADI Device TX_ENABLE PIN.
* @param enable A uint8_t value indicating the desired enable/disable
* setting for the tx_enable pin.
* A value of 1 indicates TX_ENABLE pin is set HIGH
* A value of 0 indicates TX_ENABLE pin is set LOW
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_tx_en_pin_ctrl_t)(void *user_data, uint8_t enable);
/**
* @brief pd_stby pin control function
*
* @param user_data A void pointer to a client defined structure containing
* any parameters/settings that may be required by the function
* to control the hardware for the ADI Device PD_STBY PIN.
* @param enable A uint8_t value indicating the desired enable/disable
* setting for the pd_stby pin.
* A value of 1 indicates pd_stby pin is set HIGH
* A value of 0 indicates pd_stby pin is set LOW
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_pd_stby_pin_ctrl_t)(void *user_data, uint8_t enable);
/**
* @brief reset pin control function
*
* @param user_data A void pointer to a client defined structure containing
* any parameters/settings that may be required by the function
* to control the hardware for the ADI Device RESETB PIN.
* @param enable A uint8_t value indicating the desired enable/disable
* reset via the ADI device RESETB pin.
* A value of 1 indicates RESETB pin is set LOW
* A value of 0 indicates RESETB pin is set HIGH
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_reset_pin_ctrl_t)(void *user_data, uint8_t enable);
/**
* @brief sysref control function
*
* @param sysref_clk A void pointer to a structure containing the clock source
* required by the function to control the hardware sysref control.
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t (*adi_sysref_ctrl_t)(void *sysref_clk);
/**
* @brief Control function for GPIO write.
*
* @param user_data A void pointer to a client defined structure containing
* any parameters/settings that may be required by the function
* to control the hardware for the ADI Device RESETB PIN.
* @param gpio A uint32_t GPIO index used for identification. See enum "adi_adl5580_gpio_e".
* @param value A uint32_t value indicating the desired high/low state for GPIO.
* A value of 1 indicates GPIO pin is set HIGH
* A value of 0 indicates GPIO pin is set LOW
*
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_gpio_write_t) (void *user_data, uint32_t gpio, uint32_t value);
/**
* @brief Control function for GPIO write.
*
* @param user_data A void pointer to a client defined structure containing
* any parameters/settings that may be required by the function
* to control the hardware for the ADI Device RESETB PIN.
* @param gpio A uint32_t GPIO index used for identification. See enum "adi_adl5580_gpio_e".
* @param value A uint32_t integer pointer indicating the readback state of GPIO.
* A value of 1 indicates GPIO pin is set HIGH
* A value of 0 indicates GPIO pin is set LOW
* @Note Depending on the platform, reading a GPIO which is set as an OUTPUT may result in changing the GPIO state.
* @return 0 for success
* @return Any non-zero value indicates an error
*/
typedef int32_t(*adi_gpio_read_t)(void *user_data, uint32_t gpio, uint32_t *value);
#endif /* __ADI_API_COMMON_H__ */
/*! @} */

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/*!
* @brief API configuration header file.
* This file contains API configuration parameters.
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup ADI_API_CONFIG
* @{
*/
#ifndef __ADI_CMS_API_CONFIG_H__
#define __ADI_CMS_API_CONFIG_H__
/*============= D E F I N E S ==============*/
#define ADI_REPORT_VERBOSE ADI_CMS_LOG_ALL /*!< verbose log report control */
#define ADI_INVALID_POINTER 0 /*!< invalid pointer address */
#endif /* __ADI_API_CONFIG_H__ */
/*! @} */

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/*!
* @brief ADI utility functions header file.
*
* @version 0.1.x
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __ADI_UTILS__
* @{
*/
#ifndef __ADI_UTILS_H__
#define __ADI_UTILS_H__
/*============= I N C L U D E S ============*/
#include "adi_cms_api_common.h"
/*============= D E F I N E S ==============*/
#define ADI_UTILS_POW2_32 ((uint64_t)1 << 32)
#define ADI_UTILS_POW2_48 ((uint64_t)1 << 48)
#define ADI_UTILS_MAXUINT24 (0xffffff)
#define ADI_UTILS_MAXUINT32 (ADI_UTILS_POW2_32 - 1)
#define ADI_UTILS_MAXUINT48 (ADI_UTILS_POW2_48 - 1)
#define ADI_UTILS_GET_BYTE(w, p) (uint8_t)(((w) >> (p)) & 0xff)
#define ADI_UTILS_DIV_U64(x, y) ((x) / (y))
#define ADI_UTILS_BIT(x) ((1) << (x))
#define ADI_UTILS_ALL (-1)
#define ADI_UTILS_ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
/*============= E X P O R T S ==============*/
#ifdef __cplusplus
extern "C" {
#endif
int32_t adi_api_utils_gcd(int32_t u, int32_t v);
int32_t adi_api_utils_is_power_of_two(uint64_t x);
void adi_api_utils_mult_64(uint32_t a, uint32_t b, uint32_t *hi, uint32_t *lo);
void adi_api_utils_lshift_128(uint64_t *hi, uint64_t *lo);
void adi_api_utils_rshift_128(uint64_t *hi, uint64_t *lo);
void adi_api_utils_mult_128(uint64_t a, uint64_t b, uint64_t *hi, uint64_t *lo);
void adi_api_utils_div_128(uint64_t a_hi, uint64_t a_lo, uint64_t b_hi,
uint64_t b_lo, uint64_t *hi, uint64_t *lo);
void adi_api_utils_mod_128(uint64_t ah, uint64_t al, uint64_t div, uint64_t *mod);
void adi_api_utils_add_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl,
uint64_t *hi, uint64_t *lo);
void adi_api_utils_subt_128(uint64_t ah, uint64_t al, uint64_t bh,uint64_t bl,
uint64_t *hi,uint64_t *lo);
uint32_t adi_api_utils_log2(uint32_t a);
#ifdef __cplusplus
}
#endif
#endif /*__ADI_UTILS_H__*/
/*! @} */

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/*!
* @brief API utility helper functions
*
* @version 0.1.x
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __ADI_UTILS__
* @{
*/
/*============= I N C L U D E S ============*/
#include "adi_utils.h"
/*============= D E F I N E S ==============*/
#define LOWER_16(A) (((A) & 0xffff))
#define UPPER_16(A) (((A) >> 16) & 0xffff)
#define LOWER_32(A) (((A) & (uint32_t) 0xffffffff))
#define U64MSB (0x8000000000000000ull)
/*============= C O D E ====================*/
int32_t adi_api_utils_gcd(int32_t u, int32_t v)
{
int32_t t;
while (v != 0) {
t = u;
u = v;
v = t % v;
}
return u < 0 ? -u : u; /* abs(u) */
}
int32_t adi_api_utils_is_power_of_two(uint64_t x)
{
return ((x != 0) && !(x & (x - 1)));
}
void adi_api_utils_mult_64(uint32_t a, uint32_t b, uint32_t *hi, uint32_t *lo)
{
uint32_t ah = a >> 16,
al = a & 0xffff,
bh = b >> 16,
bl = b & 0xffff,
rh = ah * bh,
rl = al * bl,
rm1 = ah * bl,
rm2 = al * bh,
rm1h = rm1 >> 16,
rm2h = rm2 >> 16,
rm1l = rm1 & 0xffff,
rm2l = rm2 & 0xffff,
rmh = rm1h + rm2h,
rml = rm1l + rm2l,
c = ((rl >> 16) + rml) >> 16;
rl = rl + (rml << 16);
rh = rh + rmh + c;
*lo = rl;
*hi = rh;
}
void adi_api_utils_lshift_128(uint64_t *hi, uint64_t *lo)
{
*hi <<= 1;
if (*lo & U64MSB)
{
*hi |= 1ul;
}
*lo <<= 1;
}
void adi_api_utils_rshift_128(uint64_t *hi, uint64_t *lo)
{
*lo >>= 1;
if (*hi & 1u) {
*lo |= U64MSB;
}
*hi >>= 1;
}
void adi_api_utils_mult_128(uint64_t a, uint64_t b, uint64_t *hi, uint64_t *lo)
{
uint64_t ah = a >> 32,
al = a & 0xffffffff,
bh = b >> 32,
bl = b & 0xffffffff,
rh = ah * bh,
rl = al * bl,
rm1 = ah * bl,
rm2 = al * bh,
rm1h = rm1 >> 32,
rm2h = rm2 >> 32,
rm1l = rm1 & 0xffffffff,
rm2l = rm2 & 0xffffffff,
rmh = rm1h + rm2h,
rml = rm1l + rm2l,
c = ((rl >> 32) + rml) >> 32;
rl = rl + (rml << 32);
rh = rh + rmh + c;
*lo = rl;
*hi = rh;
}
void adi_api_utils_div_128(uint64_t a_hi, uint64_t a_lo, uint64_t b_hi, uint64_t b_lo,
uint64_t *hi, uint64_t *lo)
{
uint64_t remain_lo = a_lo; /* The left-hand side of division, i.e. what is being divided */
uint64_t remain_hi = a_hi; /* The left-hand side of division, i.e. what is being divided */
uint64_t part1_lo = b_lo; /* The right-hand side of division */
uint64_t part1_hi = b_hi; /* The right-hand side of division */
uint64_t result_lo = 0;
uint64_t result_hi = 0;
uint64_t mask_lo = 1;
uint64_t mask_hi = 0;
if ((part1_lo == 0) && (part1_hi == 0)) {
/* Do whatever should happen when dividing by zero. */
return;
}
/* while(part1_lo < remain_lo)
* Alternative: while(!(part1 & 0x8000)) - For 16-bit, test highest order bit.
* Alternative: while(not_signed(part1)) - Same as above: As long as sign bit is not set in part1.
*/
while (!(part1_hi & U64MSB)) {
adi_api_utils_lshift_128(&part1_hi, &part1_lo);
adi_api_utils_lshift_128(&mask_hi, &mask_lo);
}
do {
if ((remain_hi > part1_hi) || ((remain_hi == part1_hi) && (remain_lo >= part1_lo))) {
/* remain_lo = remain_lo - part1_lo */
adi_api_utils_subt_128(remain_hi, remain_lo, part1_hi, part1_lo, &remain_hi, &remain_lo);
/* result = result + mask */
adi_api_utils_add_128(result_hi, result_lo, mask_hi, mask_lo, &result_hi, &result_lo);
}
adi_api_utils_rshift_128(&part1_hi, &part1_lo); /* part1 = part1 >> 1 */
adi_api_utils_rshift_128(&mask_hi, &mask_lo); /* mask = mask >> 1 */
} while ((mask_hi != 0) || (mask_lo != 0));
/* result = division result (quotient) */
/* remain_lo = division remain_loder (modulo) */
*lo = result_lo;
*hi = result_hi;
}
void adi_api_utils_mod_128(uint64_t ah, uint64_t al, uint64_t div, uint64_t *mod)
{
uint64_t result = 0;
uint64_t a = ((~0 % div) +1);
ah %= div;
/*modular multiplication of (2^64*upper) % div*/
while (ah != 0) {
if ( (ah & 1) == 1) {
result += a;
if(result >= div) {
result -= div;
}
}
a <<= 1;
if(a >= div) {
a -= div;
}
ah >>= 1;
}
/* add up the 2 results and return the modulus*/
if (al > div) {
al -= div;
}
*mod = (al + result) % div;
}
void adi_api_utils_add_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl,
uint64_t *hi, uint64_t *lo)
{
/* r = a + b */
uint64_t rl, rh;
rl = al + bl;
rh = ah + bh;
if (rl < al)
{
rh++;
}
*lo = rl;
*hi = rh;
}
void adi_api_utils_subt_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl,
uint64_t *hi, uint64_t *lo)
{
/* r = a - b */
uint64_t rl, rh;
if (bl <= al) {
rl = al - bl;
rh = ah - bh;
} else {
rl = bl - al - 1;
rl = 0xFFFFFFFFFFFFFFFFll - rl;
ah--;
rh = ah - bh;
}
*lo = rl;
*hi = rh;
}
uint32_t adi_api_utils_log2(uint32_t a)
{
uint8_t b = 0;
while (a >>= 1)
b++;
return b; /* log2(a) , only for power of 2 numbers */
}
/*! @} */

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# AD9081 API
## 1. INTRODUCTION
### 1.1 PURPOSE
This document serves as a programmer's reference for using and utilizing various aspects of the Application Program Interface (API) library targeting the AD9081 family of ADI Direct RF Transmitter and Receiver Devices. It describes the general structure of the AD9081 API library, provides a detail list of the API functions and its associated data structures, macros, and definitions.
### 1.2 SCOPE
This document targets API libraries the devices listed in following table, a source code package is available for each devices.
|Target Device Name | Device Description | Device Release Status|
|-------------------|----------------------------------------------------------------------|----------------------|
|AD9081 | 4x 16-bit 12GSPS RF DAC cores and 4x 12- bit 4GSPS rate RF ADC cores | Unreleased |
|AD9082 | 4x 16-bit 12GSPS RF DAC cores and 2x 12- bit 6GSPS rate RF ADC cores | Unreleased |
|AD9986 | 4x 16-bit 12GSPS RF DAC cores and 2x 12- bit 6GSPS rate RF ADC cores | Unreleased |
|AD9988 | 4x 16-bit 12GSPS RF DAC cores and 4x 12- bit 4GSPS rate RF ADC cores | Unreleased |
### 1.3 DISCLAIMER
This is a preliminary pre-release version of API and documentation. All information is subject to change.
The software and any related information and/or advice is provided on and "AS IS" basis, without representations, guarantees or warranties of any kind, express or implied, oral or written, including without limitation warranties of merchantability fitness for a particular purpose, title and non-infringement. Please refer to the Software License Agreement applied to the source code for full details.
## 2. ARCHITECTURE
![Linux Server Based Arch](https://confluence.analog.com/download/attachments/21520831/Evaluation%20System%E2%80%99s%20Software%20Architecture7.PNG?version=1&modificationDate=1516009214932&api=v2)

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/*!
* @brief Standalone Linux Application Helper Functions
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __ADI_AD9081_APP__
* @{
*/
/*============= I N C L U D E S ============*/
#include "ad9081_app_helper.h"
/*============= M A C R O S====================*/
/*============= D A T A ====================*/
/*Eval Application Usecase Datapath Configuration*/
/*Refer to uc_settings.c for list of uc definitions*/
/*Clock Scheme Sources and Frequencies*/
extern uint64_t clk_hz[][4];
/* Transmit Datapath Configuration*/
extern uint8_t tx_dac_chan_xbar[][4]; /*Transmit Channel and Main DAC Datapaths*/
extern int8_t tx_chan_gain[][8]; /*Transmit Channel Gain DAC Datapaths*/
extern int64_t tx_main_shift[][4]; /*Transmit Main/Coarse DUC NCO Frequency Setting*/
extern int64_t tx_chan_shift[][8]; /*Transmit Channel/Fine DUC NCO Frequency Setting*/
extern uint8_t tx_interp[][2]; /*Trnacmit Data Interpolation for Coarse/Fine DUCs */
extern uint8_t rx_cddc_select[];
extern uint8_t rx_fddc_select[];
extern int64_t rx_cddc_shift[][4];
extern int64_t rx_fddc_shift[][8];
extern uint8_t rx_cddc_dcm[][4];
extern uint8_t rx_fddc_dcm[][8];
extern uint8_t rx_cddc_c2r[][4];
extern uint8_t rx_fddc_c2r[8];
extern uint8_t jtx_logiclane_mapping_pe_brd[2][8];
extern uint8_t jtx_logiclane_mapping_ce_brd[2][8];
extern adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2];
extern adi_cms_jesd_param_t jrx_param[];
extern adi_cms_jesd_param_t jtx_param[][2];
extern uint8_t jtx_chip_dcm[][2];
/*============= C O D E ====================*/
//
//static int32_t app_show_jrx_204b_lane_status(uint16_t ad9081_jrx_link_status, uint16_t num_lanes);
//static int32_t app_show_jrx_204c_state_machine_status(uint16_t ad9081_jrx_link_status);
//
//
//int32_t app_show_jrx_204b_lane_status(uint16_t ad9081_jrx_link_status, uint16_t num_lanes)
//{
// int8_t i;
// uint16_t lanes_status;
//
// lanes_status = (ad9081_jrx_link_status & 0x0ff) ^ ((1 << num_lanes) - 1);
// for (i = 0; i < 8; i++) {
// if (lanes_status & (1 << i)) {
// printf(" Lane %d has cgs/ils/fs errors.\n", i);
// }
// }
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_show_jrx_204c_state_machine_status(uint16_t ad9081_jrx_link_status)
//{
// uint8_t jrx_state_status;
// jrx_state_status = (ad9081_jrx_link_status & 0xf00) >> 8;
//
// if (jrx_state_status == 0x0) {
// printf(" AD9081 JESD204C RX state machine in reset.\n");
// } else if (jrx_state_status == 0x1) {
// printf(" AD9081 JESD204C RX state machine is unlocked.\n");
// } else if (jrx_state_status == 0x2) {
// printf(" AD9081 JESD204C RX state machine is block aligned.\n");
// } else if (jrx_state_status == 0x3) {
// printf(" AD9081 JESD204C RX state machine is lane aligned.\n");
// } else if (jrx_state_status == 0x4) {
// printf(" AD9081 JESD204C RX state machine is extended multiblock aligned.\n");
// } else if (jrx_state_status == 0x6) {
// printf(" AD9081 JESD204C RX state machine is locked.\n");
// }
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_show_link_status(adi_ad9081_device_t *device)
//{
// int32_t err;
// uint32_t fpga_use_204c;
// uint32_t fpga_jrx_np, fpga_jtx_np;
//
// /* get link configuration */
// if (err = adi_ads9_reg_get(0x943, &fpga_use_204c), err != API_CMS_ERROR_OK)
// return err;
// printf("APP: Checking JESD link status: %s Mode \n", (fpga_use_204c ? "204C" : "204B"));
//
// if (err = adi_ads9_reg_get(0x121, &fpga_jrx_np), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_reg_get(0x521, &fpga_jtx_np), err != API_CMS_ERROR_OK)
// return err;
//
//
//#if !defined(AD9207_ID) && !defined(AD9209_ID)
// /* get link status of tx */
// uint16_t ad9081_jrx_link_status[2];
// uint32_t fpga_jesd204b_tx_status;
// uint8_t ad9081_jrx_tpl_link_status[2];
// uint32_t fpga_jtx_lscrparam;
// uint8_t linkup = 0;
// uint16_t jrx_dl_204c_state_link_up = 0x600;
//
// if (err = adi_ads9_reg_get(0x54e, &fpga_jesd204b_tx_status), err != API_CMS_ERROR_OK)
// return err;
// if ((fpga_jtx_np & 0x00ff) > 0) { /* link0 */
// if (err = adi_ad9081_jesd_rx_link_status_get(device, AD9081_LINK_0, &ad9081_jrx_link_status[0]), err != API_CMS_ERROR_OK)
// return err;
// }
// if ((fpga_jtx_np & 0xff00) > 0) { /* link1 */
// if (err = adi_ad9081_jesd_rx_link_status_get(device, AD9081_LINK_1, &ad9081_jrx_link_status[1]), err != API_CMS_ERROR_OK)
// return err;
// }
// err = adi_ad9081_jesd_rx_link_select_set(device, AD9081_LINK_0);
// err = adi_ad9081_device_spi_register_get(device, 0x04a0, &ad9081_jrx_tpl_link_status[0]);
// err = adi_ad9081_jesd_rx_link_select_set(device, AD9081_LINK_1);
// err = adi_ad9081_device_spi_register_get(device, 0x04a0, &ad9081_jrx_tpl_link_status[1]);
//
// if (err = adi_ads9_reg_get(0x520, &fpga_jtx_lscrparam), err != API_CMS_ERROR_OK)
// return err;
// fpga_jtx_lscrparam = (fpga_jtx_lscrparam & 0x1f) + 1;
//
// if (fpga_use_204c == 0) {
// if ((fpga_jtx_np & 0x00ff) > 0) { /* link0 */
// linkup = ((ad9081_jrx_link_status[0] & 0x0ff) == ((1 << fpga_jtx_lscrparam) - 1)) ? 1 : 0;
// if (linkup) {
// printf(" AD9081 JRX link0 is up.\n");
// } else {
// printf(" AD9081 JRX link0 isn't up.\n");
// app_show_jrx_204b_lane_status(ad9081_jrx_link_status[0], fpga_jtx_lscrparam);
// }
// printf(" AD9081 JRX Status = 0x%.4x, AD9081 JRX TPL Status =0x%.2x FPGA JTX Status = 0x%.2x\n", ad9081_jrx_link_status[0], ad9081_jrx_tpl_link_status[0], fpga_jesd204b_tx_status);
// }
// if ((fpga_jtx_np & 0xff00) > 0) { /* link1 */
// linkup = ((ad9081_jrx_link_status[1] & 0x0ff) == ((1 << fpga_jtx_lscrparam) - 1)) ? 1 : 0;
// if (linkup) {
// printf(" AD9081 JRX link1 is up.\n");
// } else {
// printf(" AD9081 JRX link1 isn't up.\n");
// app_show_jrx_204b_lane_status(ad9081_jrx_link_status[1], fpga_jtx_lscrparam);
// }
// printf(" AD9081 JRX Status = 0x%.4x, AD9081 TPL Status =0x%.2x, FPGA JTX Status = 0x%.2x\n", ad9081_jrx_link_status[1], ad9081_jrx_tpl_link_status[1],fpga_jesd204b_tx_status);
// }
// } else { /* 204C */
// if ((fpga_jtx_np & 0x00ff) > 0) { /* link0 */
// linkup = ((ad9081_jrx_link_status[0] & 0xf00) == jrx_dl_204c_state_link_up) ? 1 : 0;
// if (linkup) {
// printf(" AD9081 JRX link0 is up.\n");
// } else {
// printf(" AD9081 JRX link0 isn't up.\n");
// app_show_jrx_204c_state_machine_status(ad9081_jrx_link_status[0]);
// }
// printf(" AD9081 JRX Status = 0x%.4x, AD9081 TPL Status =0x%.2x, FPGA JTX Status = 0x%.2x\n", ad9081_jrx_link_status[0], ad9081_jrx_tpl_link_status[0], fpga_jesd204b_tx_status);
// }
// if ((fpga_jtx_np & 0xff00) > 0) { /* link1 */
// linkup = ((ad9081_jrx_link_status[1] & 0xf00) == jrx_dl_204c_state_link_up) ? 1 : 0;
// if (linkup) {
// printf(" AD9081 JRX link1 is up.\n");
// } else {
// printf(" AD9081 JRX link1 isn't up.\n");
// app_show_jrx_204c_state_machine_status(ad9081_jrx_link_status[1]);
// }
// printf(" AD9081 JRX Status = 0x%.4x, AD9081 TPL Status =0x%.2x, FPGA JTX Status = 0x%.2x\n", ad9081_jrx_link_status[1], ad9081_jrx_tpl_link_status[1], fpga_jesd204b_tx_status);
// }
// }
//#endif
//
//#if !defined(AD9177_ID)
// /* get link status of rx */
// uint16_t ad9081_jtx_link_status[2];
// uint32_t fpga_jesd204b_rx_status, fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt, fpga_rx_err_total_cnt;
// if (err = adi_ads9_reg_get(0x14e, &fpga_jesd204b_rx_status), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_reg_get(0x205, &fpga_jesd240c_rx_status), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_reg_get(0x160, &fpga_rx_err_total_cnt), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_reg_get(0x220, &fpga_jesd204c_link_err_cnt), err != API_CMS_ERROR_OK)
// return err;
// if ((fpga_jrx_np & 0x00ff) > 0) { /* link0 */
// if (err = adi_ad9081_jesd_tx_link_status_get(device, AD9081_LINK_0, &ad9081_jtx_link_status[0]), err != API_CMS_ERROR_OK)
// return err;
// }
// if ((fpga_jrx_np & 0xff00) > 0) { /* link1 */
// if (err = adi_ad9081_jesd_tx_link_status_get(device, AD9081_LINK_1, &ad9081_jtx_link_status[1]), err != API_CMS_ERROR_OK)
// return err;
// }
// if (fpga_use_204c == 0) {
// if ((fpga_jrx_np & 0x00ff) > 0) { /* link0 */
// printf((((ad9081_jtx_link_status[0] & 0xff) == 0x7d) && ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ? " AD9081 JTX link0 is up.\n" : " AD9081 JTX link0 isn't up.\n");
// printf(" AD9081 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\n",
// ad9081_jtx_link_status[0], fpga_jesd204b_rx_status, fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16, fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
// }
// if ((fpga_jrx_np & 0xff00) > 0) { /* link1 */
// printf((((ad9081_jtx_link_status[1] & 0xff) == 0x7d) && ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ? " AD9081 JTX link1 is up.\n" : " AD9081 JTX link1 isn't up.\n");
// printf(" AD9081 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\n",
// ad9081_jtx_link_status[1], fpga_jesd204b_rx_status, fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16, fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
// }
// } else { /* 204C */
// if ((fpga_jrx_np & 0x00ff) > 0) { /* link0 */
// printf((((ad9081_jtx_link_status[0] & 0x60) == 0x60) && ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ? " AD9081 JTX link0 is up.\n" : " AD9081 JTX link0 isn't up.\n");
// printf(" AD9081 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\n",
// ad9081_jtx_link_status[0], fpga_jesd204b_rx_status, fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16, fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
// }
// if ((fpga_jrx_np & 0xff00) > 0) { /* link1 */
// printf((((ad9081_jtx_link_status[1] & 0x60) == 0x60) && ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ? " AD9081 JTX link1 is up.\n" : " AD9081 JTX link1 isn't up.\n");
// printf(" AD9081 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\n",
// ad9081_jtx_link_status[1], fpga_jesd204b_rx_status, fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16, fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
// }
// }
//#endif
//
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_test_phy_prbs(adi_ad9081_device_t *device, adi_cms_jesd_prbs_pattern_e prbs)
//{
//#if !defined(AD9207_ID) && !defined(AD9209_ID)
// /* Make sure clock to fpga is lane_rate/64 for 204C, and lane_rate/20 for 204B */
// int32_t err, i;
// adi_ad9081_prbs_test_t result;
//
// printf("APP: Starting AD9081 JRX PHY PRBS Test: \n");
// if (err = adi_ads9_stop_transmit(), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_config_jtx_prbs(prbs), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_start_transmit(), err != API_CMS_ERROR_OK)
// return err;
// /* Configure link and enable prior to running PRBS */
// /* Available APIs for link operation: adi_ad9081_jesd_rx_link_config_set, adi_ad9081_jesd_rx_link_enable_set */
// if (err = adi_ad9081_jesd_rx_phy_prbs_test(device, prbs, 1), err != API_CMS_ERROR_OK)
// return err;
// for(i = 0; i < 8; i ++) {
// if (err = adi_ad9081_jesd_rx_phy_prbs_test_result_get(device, i, &result), err != API_CMS_ERROR_OK)
// return err;
// printf("APP: PRBS Error Count on Lane %d: %d \n", i, result.phy_prbs_err_cnt);
// }
//#endif
//
// return API_CMS_ERROR_OK;
//}
int32_t app_sysref_clk_src_sel(void *sysref_clk) {
adi_hmc7044_device_t *hmc7044_device = (adi_hmc7044_device_t*) sysref_clk;
if (hmc7044_device == NULL)
return API_CMS_ERROR_ERROR;
return adi_hmc7044_pulse_gen_set(hmc7044_device);
}
void app_calc_tx_lane_rate(uint64_t clock_hz[4], adi_cms_jesd_param_t *jesd_rx_param, uint8_t transmit_interp[2], uint64_t *calc_app_jrx_lane_rate)
{
uint8_t k;
*calc_app_jrx_lane_rate = 0;
for (k = 0; k < (jesd_rx_param->jesd_duallink + 1) ; k++) {
if (jesd_rx_param->jesd_l) {
*calc_app_jrx_lane_rate = (jesd_rx_param->jesd_m * jesd_rx_param->jesd_np * ((jesd_rx_param->jesd_jesdv == 1) ? 10 : 66) * clock_hz[2]);
*calc_app_jrx_lane_rate = *calc_app_jrx_lane_rate / (jesd_rx_param->jesd_l * ((jesd_rx_param->jesd_jesdv == 1) ? 8 : 64) * transmit_interp[0] * transmit_interp[1]);
}
}
}
void app_calc_rx_lane_rate(uint64_t clock_hz[4], adi_cms_jesd_param_t jesd_tx_param[2], uint8_t jesd_tx_chip_dcm_ratio[2], uint64_t calc_app_jtx_lane_rate[2])
{
uint8_t k;
calc_app_jtx_lane_rate[0] = 0;
calc_app_jtx_lane_rate[1] = 0;
for (k = 0; k < (jesd_tx_param[0].jesd_duallink + 1) ; k++) {
if (jesd_tx_param[k].jesd_l) {
calc_app_jtx_lane_rate[k] = jesd_tx_param[k].jesd_np * jesd_tx_param[k].jesd_m * clock_hz[3] * ((jesd_tx_param[k].jesd_jesdv == 1) ? 10 : 66);
calc_app_jtx_lane_rate[k] = calc_app_jtx_lane_rate[k] / (jesd_tx_param[k].jesd_l * jesd_tx_chip_dcm_ratio[k] * ((jesd_tx_param[k].jesd_jesdv == 1) ? 8 : 64));
}
}
}
//
//int32_t app_cal_ctle_manual_config_load(adi_ad9081_device_t *device, char filename[])
//{
// int32_t err;
// int8_t i;
// FILE *fp;
// char lane_data[20];
// printf("APP: Loading CTLE Coefficient values from file\n");
//
// /* load ctle coeffs values from file to array */
// strcat(filename, ".txt");
// fp = fopen(filename, "r");
// if (fp == NULL) {
// printf("APP: fopen failed to open the file\n");
// return API_CMS_ERROR_NULL_PARAM;
// }
// for (i = 0; i < 8; i++) {
// if (fgets(lane_data, 20, fp) != NULL) {
// sscanf(lane_data, "%u,%u,%u,%u\n", (unsigned int*)&(device->serdes_info.des_settings.ctle_coeffs[i][0]), (unsigned int*)&(device->serdes_info.des_settings.ctle_coeffs[i][1]),
// (unsigned int*)&(device->serdes_info.des_settings.ctle_coeffs[i][2]), (unsigned int*)&(device->serdes_info.des_settings.ctle_coeffs[i][3]));
// }
// }
// fclose(fp);
//
// /*set array ctle coeffs to regs*/
// for (int i = 0; i < 8; i++) {
// if (err = adi_ad9081_jesd_rx_ctle_manual_config_set(device, i), err != API_CMS_ERROR_OK)
// return err;
// }
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_cal_ctle_manual_config_save(adi_ad9081_device_t *device, char filename[])
//{
// int32_t err;
// int8_t i;
// FILE *fp;
//
// printf("APP: Saving CTLE Coefficient values to file\n");
//
// /* get ctle coeffs values from regs */
// for (i = 0; i < 8; i++) {
// if (err = adi_ad9081_jesd_rx_ctle_manual_config_get(device, i), err != API_CMS_ERROR_OK)
// return err;
// }
//
// /* save values to file */
// strcat(filename, ".txt");
// fp = fopen(filename, "w+");
// if (fp == NULL) {
// printf("APP: fopen failed to open the file\n");
// return API_CMS_ERROR_NULL_PARAM;
// }
// for (i = 0; i < 8; i++) {
// char * lane_data = malloc(sizeof(char)*20);
// snprintf(lane_data, 20, "%u,%u,%u,%u\n", (uint8_t)device->serdes_info.des_settings.ctle_coeffs[i][0], (uint8_t)device->serdes_info.des_settings.ctle_coeffs[i][1],
// (uint8_t)device->serdes_info.des_settings.ctle_coeffs[i][2], (uint8_t)device->serdes_info.des_settings.ctle_coeffs[i][3]);
// fputs(lane_data, fp);
// free(lane_data);
// }
// fclose(fp);
//
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_calc_nco_freq_get(uint64_t freq, uint64_t ftw, double *nco_shift)
//{
// double sign = 1.0;
// double freq_mhz = freq/1e6;
// double nco_freq = 0.00;
//
// if (ftw > (140737488355328ull)) {
// ftw = (1ull << 48) - ftw;
// sign = -1.0;
// }
// nco_freq = (freq_mhz * ftw)/(1ull << 48);
// *nco_shift = sign * nco_freq;
//
// printf("APP: NCO freq: %.2f MHz\n", *nco_shift);
//
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_test_eye_scan_write_to_file(adi_ad9081_device_t *device, adi_ad9081_deser_mode_e mode, uint8_t lane, uint8_t spo_size, int16_t eye_scan_data[])
//{
// uint8_t i;
// FILE *fp;
// char filename[50] = "eye_scan_lane_";
// char lane_save[50];
// snprintf(lane_save, 50, "%d", lane);
// strcat(filename, lane_save);
// strcat(filename, ".txt");
// fp = fopen(filename, "w+");
// if (fp == NULL) {
// printf("APP: fopen failed to open the file\n");
// return API_CMS_ERROR_NULL_PARAM;
// }
// for (i = 0; i < spo_size; i++) {
// char * spo = malloc(sizeof(char)*20);
// snprintf(spo, 20, "%d,%d,%d\n", (int16_t)eye_scan_data[i*3], (int16_t)eye_scan_data[(i*3)+1], (int16_t)eye_scan_data[(i*3)+2]);
// fputs(spo, fp);
// free(spo);
// }
// fclose(fp);
// printf("APP: Scan Complete \n");
//
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_test_eye_scan(adi_ad9081_device_t *device, adi_cms_jesd_param_t *jesd_rx_param, int32_t uc, adi_ad9081_deser_mode_e mode, adi_cms_jesd_prbs_pattern_e prbs, uint8_t lane)
//{
//#if !defined(AD9207_ID) && !defined(AD9209_ID)
// int32_t err;
// uint8_t spo_size=(mode == (AD9081_QUART_RATE) ? 32:64) +1;
// int16_t *eye_scan_data = (int16_t*) calloc((spo_size*3), sizeof(int16_t));
//
// printf("APP: Starting Eye Scan.... Text file output is saved to device when completed.\n");
// printf("APP: WARNING Run all eye scan use cases with direct clock only \n");
//
// if ((jesd_rx_param->jesd_jesdv == 2 && device->dev_info.jesd_rx_lane_rate/64 != clk_hz[uc][1]) || (jesd_rx_param->jesd_jesdv == 1 && device->dev_info.jesd_rx_lane_rate/20 != clk_hz[uc][1])) {
// printf("APP: WARNING Set FPGA input clock to lane_rate/64 for 204C or lane_rate/20 for 204B to run PRBS test modes.\n");
// }
//
// /* Setup FPGA to send PRBS test pattern */
// if (err = adi_ads9_stop_transmit(), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_config_jtx_prbs(prbs), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ads9_start_transmit(), err != API_CMS_ERROR_OK)
// return err;
//
// /* Run Eye Scan */
// if (mode == AD9081_QUART_RATE) {
// printf("APP: Running Quarter Rate Eye Scan...\n");
// if (err = adi_ad9081_jesd_cal_bg_cal_pause(device), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ad9081_jesd_rx_qr_two_dim_eye_scan(device, lane, eye_scan_data), err != API_CMS_ERROR_OK)
// return err;
// if (err = adi_ad9081_jesd_cal_bg_cal_start(device), err != API_CMS_ERROR_OK)
// return err;
// }
// else if (mode == AD9081_HALF_RATE) {
// printf("APP: Running Half Rate Eye Scan...\n");
// if (err = adi_ad9081_jesd_rx_hr_two_dim_eye_scan(device, lane, prbs, 500, eye_scan_data), err != API_CMS_ERROR_OK)
// return err;
// }
// else {
// printf("APP: Lane rate is not within eye scan capabilities (8 Gbps and above).\n");
// return API_CMS_ERROR_INVALID_PARAM;
// }
// if (err = app_test_eye_scan_write_to_file(device, mode, lane, spo_size, eye_scan_data), err != API_CMS_ERROR_OK)
// return err;
//
// free(eye_scan_data);
//#endif
//
// return API_CMS_ERROR_OK;
//}
//
//int32_t app_collect_power_measurements(adi_ad7175_device_t *ad7175_dev)
//{
// int32_t err;
// uint32_t data_status[8] = {0};
// float data_only[8] = {0};
// float conversion[8] = {0};
// float power[4] = {0};
// float total_power = 0;
// adi_ad7175_adc_mode_e adc_mode = AD7175_MODE_SINGLE_CONV;
//
// for (int i = 0; i < 8; i++){
// /* Trigger conversion */
// if (err = adi_ad7175_device_channel_run(ad7175_dev, i, 1, AD7175_INT_OSC, adc_mode, AD7175_DELAY_0_US, 0, 0), err != API_CMS_ERROR_OK)
// return err;
// /* Collect Data */
// if (err = adi_ad7175_device_run_data_conv_get(ad7175_dev, &data_status[i], i), err != API_CMS_ERROR_OK) {
// if (err == API_CMS_ERROR_DELAY_US) {
// printf("APP: ERROR timed out before AD7175 data conversion.\n");
// return API_CMS_ERROR_DELAY_US;
// }
// if (err == API_CMS_ERROR_ERROR) {
// printf("APP: ERROR 7175 reported error in conversion, check STATUS register in log.\n");
// return API_CMS_ERROR_ERROR;
// }
// }
// data_only[i] = (float) (data_status[i]>>8);
// conversion[i] = (data_only[i]/65535)*2.5*1.058;
// }
// /* Resistors being measured across */
// float r1m = 0.05;
// float r1xa = 0.05;
// float r1 = 0.05;
// float r18 = 1;
//
// /* Power Calculations */
// power[0] = (conversion[0]/r1m)-0.012; //1V digital domain
// power[1] = (conversion[2]/r1xa)-0.014; //1V mixed domain
// power[2] = (conversion[4]/r1)-0.014; //1V analog domain
// power[3] = 2*((conversion[6]/r18)-0.006); //2V analog domain
// total_power = power[0] + power[1] + power[2] + power[3];
// printf("APP: Power consumption Measurements:\n \
// 1V digital domain: %.3fW\n \
// 1V mixed domain: %.3fW\n \
// 1V analog domain: %.3fW\n \
// 2V analog domain: %.3fW\n \
// Total power: %.3fW\n", power[0], power[1], power[2], power[3], total_power);
//
// return API_CMS_ERROR_OK;
//}

174
vitis/radar/src/ad9081_app_helper.h Executable file
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/*!
* @brief Standalone Linux Application Helper Header file
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __ADI_AD9081_APP__
* @{
*/
/*============= I N C L U D E S ============*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include "adi_cms_api_common.h"
#include "adi_ad9081.h"
//#include "adi_ads9.h"
#include "adi_hmc7044.h"
#include "adi_ad7175.h"
//#include "ads9.h"
/*============= M A C R O S====================*/
/*============= C O D E ====================*/
/*===== A P P J E S D S T A T U S & C O N F I G =====*/
///**
// * @ingroup APP JESD STATUS & CONFIG
// * @brief App Level API. \n Show JESD link status after configuration
// *
// * @param device Pointer to the device structure
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_show_link_status(adi_ad9081_device_t *device);
//
///**
// * @ingroup APP JESD STATUS & CONFIG
// * @brief App Level API. \n Run JRX PRBS PHY test
// * Configure links and enable prior to running this test
// *
// * @param device Pointer to the device structure
// * @param prbs PRBS pattern @see adi_cms_jesd_prbs_pattern_e for options
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_test_phy_prbs(adi_ad9081_device_t *device, adi_cms_jesd_prbs_pattern_e prbs);
/**
* @ingroup APP JESD STATUS & CONFIG
* @brief App Level API. \n Calculate tx lane rate using uc settings
*
* @param clock_hz Clock settings for selected use case
* @param jesd_rx_param Jesd Rx parameters for selected use case
* @param transmit_interp Main and channelizer DUC interpolation for selected use case
* @param calc_app_jrx_lane_rate Pointer to variable to store calculated lane rate value
*
*/
void app_calc_tx_lane_rate(uint64_t clock_hz[4], adi_cms_jesd_param_t *jesd_rx_param, uint8_t transmit_interp[2], uint64_t *calc_app_jrx_lane_rate);
/**
* @ingroup APP JESD STATUS & CONFIG
* @brief App Level API. \n Calculate rx lane rate using uc settings
*
* @param clock_hz Clock settings for selected use case
* @param jesd_tx_param Jesd Tx parameters for selected use case
* @param jesd_tx_chip_dcm_ratio Coarse and fine DDC decimation for selected use case
* @param calc_app_jtx_lane_rate Pointer to variable to store calculated lane rate value
*
*/
void app_calc_rx_lane_rate(uint64_t clock_hz[4], adi_cms_jesd_param_t jesd_tx_param[2], uint8_t jesd_tx_chip_dcm_ratio[2], uint64_t calc_app_jtx_lane_rate[2]);
//
///**
// * @ingroup APP JESD STATUS & CONFIG
// * @brief App Level API. \n Load pre-saved CTLE coefficients from file to bypass JESD RX 204C calibration
// *
// * @param device Pointer to the device structure
// * @param filename Name of txt file to load coefficients
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_cal_ctle_manual_config_load(adi_ad9081_device_t *device, char filename[]);
//
///**
// * @ingroup APP JESD STATUS & CONFIG
// * @brief App Level API. \n Save CTLE coefficients to file
// *
// * @param device Pointer to the device structure
// * @param filename Name of txt file to save coefficients
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_cal_ctle_manual_config_save(adi_ad9081_device_t *device, char filename[]);
//
///**
// * @ingroup APP JESD STATUS & CONFIG
// * @brief App Level API. \n Calculate nco frequency in Hz from frequency tuning word
// *
// * @param freq ADC or DAC clock frequency in Hz
// * @param ftw Frequency tuning word of NCO
// * @param nco_shift Pointer to variable to store calculated nco shift value
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_calc_nco_freq_get(uint64_t freq, uint64_t ftw, double *nco_shift);
//
///**
// * @ingroup APP JESD STATUS & CONFIG
// * @brief App Level API. \n Write eye scan data points to file
// *
// * @param device Pointer to the device structure
// * @param mode Lane rate mode @see adi_ad9081_deser_mode_e for options
// * @param lane Lane that data is collected on
// * @param spo_size SPO size of collected data
// * Quarter rate: 32, Half rate: 64
// * @param eye_scan_data Collected eye scan data to save to file
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_test_eye_scan_write_to_file(adi_ad9081_device_t *device, adi_ad9081_deser_mode_e mode, uint8_t lane, uint8_t spo_size, int16_t eye_scan_data[]);
//
///**
// * @ingroup APP JESD STATUS & CONFIG
// * @brief App Level API. \n Run JRX eye scan for quarter rate and half rate modes
// *
// * @param device Pointer to the device structure
// * @param jesd_rx_param JESD Rx parameters for selected use case
// * @param uc Selected use case
// * @param mode Lane rate mode @see adi_ad9081_deser_mode_e for options
// * @param prbs PRBS test mode pattern @see adi_cms_jesd_prbs_pattern_e for options
// * @param lane Lane that data is collected on
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_test_eye_scan(adi_ad9081_device_t *device, adi_cms_jesd_param_t *jesd_rx_param, int32_t uc, adi_ad9081_deser_mode_e mode, adi_cms_jesd_prbs_pattern_e prbs, uint8_t lane);
/*===== A P P C L O C K I N G =====*/
/**
* @ingroup APP CLOCKING
* @brief App Level API. \n Select clock source for sysref signal
*
* @param sysref_clk Pointer to clock source for SYSREF signal
*
* @return API_CMS_ERROR_OK API Completed Successfully
* @return <0 Failed. @see adi_cms_error_e for details.
*/
int32_t app_sysref_clk_src_sel(void *sysref_clk);
///*===== A P P P O W E R =====*/
///**
// * @ingroup APP POWER
// * @brief App Level API. \n Collect power measurements from AD7175 ADC
// *
// * @param ad7175_dev Pointer to the ad7175 device structure
// *
// * @return API_CMS_ERROR_OK API Completed Successfully
// * @return <0 Failed. @see adi_cms_error_e for details.
// */
//int32_t app_collect_power_measurements(adi_ad7175_device_t *ad7175_dev);

125
vitis/radar/src/ad9081_hal_functions.c Executable file
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#include <stdarg.h>
#include <stdio.h>
#include "FreeRTOS.h"
#include "task.h"
#include "xspi.h" /* SPI device driver */
#include "xspi_l.h"
#include "xstatus.h"
#include "xil_printf.h"
#include "project.h"
#include "ad9081_api/adi_inc/adi_cms_api_common.h"
#define MAX_LOG_LINE_LENGTH 1000
#define RESET_PIN_REG_ADDR 0x40050008
#define RESET_PIN_BIT_MASK 0x20
static XSpi SpiInstance;
int32_t ad9081_hal_init() {
int Status;
XSpi_Config *ConfigPtr; /* Pointer to Configuration data */
/*
* Initialize the SPI driver so that it is ready to use.
*/
ConfigPtr = XSpi_LookupConfig(XPAR_SPI_0_DEVICE_ID);
if (ConfigPtr == NULL) {
return XST_DEVICE_NOT_FOUND;
}
Status = XSpi_CfgInitialize(&SpiInstance, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (SpiInstance.SpiMode != XSP_STANDARD_MODE) {
return XST_SUCCESS;
}
/*
* Set the Spi device as a master and in loopback mode.
*/
Status = XSpi_SetOptions(&SpiInstance, XSP_MASTER_OPTION);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Start the SPI driver so that the device is enabled.
*/
XSpi_Start(&SpiInstance);
/*
* Disable Global interrupt to use polled mode operation
*/
XSpi_IntrGlobalDisable(&SpiInstance);
XSpi_SetSlaveSelect(&SpiInstance, 1);
return XST_SUCCESS;
}
int32_t ad9081_hal_log_write(void *user_data, int32_t log_type, const char *comment, va_list argp) {
int32_t err;
char log_msg[MAX_LOG_LINE_LENGTH] = {0};
const char *log_type_str;
log_type_str = "MESSAGE:";
if ((log_type & ADI_CMS_LOG_WARN) > 0)
log_type_str = "WARNING:";
if ((log_type & ADI_CMS_LOG_ERR) > 0)
log_type_str = "ERROR :";
err = snprintf(log_msg + strlen(log_msg), MAX_LOG_LINE_LENGTH, "%s ", log_type_str);
if (err < 0)
return API_CMS_ERROR_LOG_WRITE;
if (vsprintf(log_msg + strlen(log_msg), comment, argp) < 0)
return API_CMS_ERROR_LOG_WRITE;
xil_printf("%s\r\n", log_msg);
// if (fprintf(g_log_fd, "%s\n", log_msg) < 0)
// return API_CMS_ERROR_LOG_WRITE;
return API_CMS_ERROR_OK;
}
int32_t ad9081_hal_wait_us(void *user_data, uint32_t time_us) {
u32 num_ticks = time_us / TICK_PERIOD_US;
if (num_ticks == 0) {
num_ticks = 1;
}
vTaskDelay(num_ticks);
return API_CMS_ERROR_OK;
}
int32_t ad9081_hal_spi_xfer_ad9081(void *user_data, uint8_t *in_data, uint8_t *out_data, uint32_t size_bytes) {
int ret = XSpi_Transfer(&SpiInstance, in_data, out_data, size_bytes);
if (ret == XST_SUCCESS) {
return API_CMS_ERROR_OK;
} else {
printf("SPI Error %d\n", ret);
return API_CMS_ERROR_ERROR;
}
}
int32_t ad9081_hal_hw_rst_pin_ctrl_ad9081(void *user_data, uint8_t pin_level) {
uint32_t tmp_val;
tmp_val = Xil_In32(RESET_PIN_REG_ADDR);
if (pin_level) {
tmp_val |= RESET_PIN_BIT_MASK;
} else {
tmp_val &= (~RESET_PIN_BIT_MASK);
}
xil_printf("bla 0x%x\r\n", tmp_val);
Xil_Out32(RESET_PIN_REG_ADDR, tmp_val);
return API_CMS_ERROR_OK;
}

13
vitis/radar/src/ad9081_hal_functions.h Executable file
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@@ -0,0 +1,13 @@
#ifndef HAL_H /* prevent circular inclusions */
#define HAL_H /* by using protection macros */
#define uint32_t u32
#define int32_t s32
int32_t ad9081_hal_init();
int32_t ad9081_hal_wait_us(void *user_data, uint32_t time_us);
int32_t ad9081_hal_log_write(void *user_data, int32_t log_type, const char *comment, va_list argp);
int32_t ad9081_hal_hw_rst_pin_ctrl_ad9081(void *user_data, uint8_t pin_level);
int32_t ad9081_hal_spi_xfer_ad9081(void *user_data, uint8_t *in_data, uint8_t *out_data, uint32_t size_bytes);
#endif /* end of protection macro */

644
vitis/radar/src/data_converter_setup.c Executable file
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@@ -0,0 +1,644 @@
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#include "xsysmon.h"
#include "xspi.h"
#include "project.h"
#include "hmc7044.h"
#include "ad9081_hal_functions.h"
#include "ad9081_app_helper.h"
#include "adi_ad9081.h"
#include "adi_hmc7044.h"
/*============= UC DATA ====================*/
/*Eval Application Usecase Datapath Configuration*/
/*Refer to uc_settings.c for list of uc definitions*/
/*Clock Scheme Sources and Frequencies*/
extern uint64_t clk_hz[][4];
/* Transmit Datapath Configuration*/
extern uint8_t tx_dac_chan_xbar[][4]; /*Transmit Channel and Main DAC Datapaths*/
extern int8_t tx_chan_gain[][8]; /*Transmit Channel Gain DAC Datapaths*/
extern int64_t tx_main_shift[][4]; /*Transmit Main/Coarse DUC NCO Frequency Setting*/
extern int64_t tx_chan_shift[][8]; /*Transmit Channel/Fine DUC NCO Frequency Setting*/
extern uint8_t tx_interp[][2]; /*Trnacmit Data Interpolation for Coarse/Fine DUCs */
extern uint8_t rx_cddc_select[];
extern uint8_t rx_fddc_select[];
extern int64_t rx_cddc_shift[][4];
extern int64_t rx_fddc_shift[][8];
extern uint8_t rx_cddc_dcm[][4];
extern uint8_t rx_fddc_dcm[][8];
extern uint8_t rx_cddc_c2r[][4];
extern uint8_t rx_fddc_c2r[8];
extern uint8_t jtx_logiclane_mapping_pe_brd[2][8];
extern uint8_t jtx_logiclane_mapping_ce_brd[2][8];
extern adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2];
extern adi_cms_jesd_param_t jrx_param[];
extern adi_cms_jesd_param_t jtx_param[][2];
extern uint8_t jtx_chip_dcm[][2];
/*============= END DATA ====================*/
void set_lane_cal(int lane, int pre, int post) {
// Select Lane
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x24, lane);
// Update Precursor 0 - 20 Valid (~0.22dB steps)
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x418, pre);
// Update Postcursor 0 - 32 Valid (~0.22dB steps)
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x414, post);
// Update RX Equalizer Setting 0 = DFE 1 = LPM
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x608, 0);
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x60C, 1);
Xil_Out32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x60C, 0);
uint32_t val0 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x418);
uint32_t val1 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x414);
uint32_t val2 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x608);
xil_printf("Lane %d, Pre %d, Post %d, RX %d\r\n", lane, val0, val1, val2);
}
adi_ad9081_device_t * ad9081_dev_ptr;
void setup_data_converter() {
// Reset Ethernet
setBit(0x40050008, 15);
vTaskDelay(1);
clearBit(0x40050008, 15);
ad9081_hal_init();
hmc7044_init();
// select use case
int uc = 0;
uint64_t app_jrx_lane_rate = 0;
uint64_t app_jtx_lane_rate[2] = {0};
int err;
// FPGA AD9081
// M2C ADC
// 7 1
// 6 7
// 5 0
// 4 6
// 3 5
// 2 4
// 1 3
// 0 2
// 5 7 0 1 2 3 4 6
// FPGA AD9081
// C2M DAC
// 7 0
// 6 4
// 5 1
// 4 7
// 3 6
// 2 5
// 1 3
// 0 2
// 7 5 0 1 6 2 3 4
/* connect to platform */
adi_ad9081_device_t ad9081_dev = {
.hal_info = {
.sdo = SPI_SDO,
.msb = SPI_MSB_FIRST,
.addr_inc = SPI_ADDR_INC_AUTO,
.log_write = ad9081_hal_log_write,
.delay_us = ad9081_hal_wait_us,
.spi_xfer = ad9081_hal_spi_xfer_ad9081,
.reset_pin_ctrl = ad9081_hal_hw_rst_pin_ctrl_ad9081,
},
.serdes_info = {
.ser_settings = { /* ad9081 jtx */
// .lane_settings = {
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// {.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_0DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
// },
.lane_settings = {
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
{.swing_setting = AD9081_SER_SWING_850,.pre_emp_setting = AD9081_SER_PRE_EMP_3DB,.post_emp_setting = AD9081_SER_POST_EMP_0DB},
},
.invert_mask = 0x00,
.lane_mapping = { { 5, 7, 0, 1, 2, 3, 4, 6 }, { 2, 0, 7, 7, 7, 7, 3, 1 } }, /* link0, link1 */
},
.des_settings = { /* ad9081 jrx */
.boost_mask = 0xff,
.invert_mask = 0x00,
.ctle_filter = { 2, 2, 2, 2, 2, 2, 2, 2 },
.cal_mode = AD9081_CAL_MODE_RUN,
.ctle_coeffs = {{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}}, /* CTLE 1-4 for lanes 0-7 */
.lane_mapping = { { 7, 5, 0, 1, 6, 2, 3, 4 }, { 4, 5, 6, 7, 0, 1, 2, 3 } }, /* link0, link1 */
}
},
.clk_info = {
.sysref_mode = SYSREF_NONE,
}
};
adi_hmc7044_device_t hmc7044_dev = {
.hal_info = {
.spi_xfer = hal_spi_xfer_hmc7044,
.delay_us = ad9081_hal_wait_us
}
};
ad9081_dev_ptr = &ad9081_dev;
uint8_t ad9081_rev[3];
adi_ad9081_device_api_revision_get(&ad9081_dev, &ad9081_rev[0], &ad9081_rev[1], &ad9081_rev[2]);
printf("AD9081 API v%d.%d.%d\n", ad9081_rev[0], ad9081_rev[1], ad9081_rev[2]);
printf("APP: Configure Usecase:%d, Tx Path: DAC Clk: %lld, JESD Rx Mode: %d & Rx Path: ADC CLK: %lld, Jesdmode Tx Mode: %d \r\n",
uc, clk_hz[uc][2], jrx_param[uc].jesd_mode_id, clk_hz[uc][3], jtx_param[uc][0].jesd_mode_id);
adi_ad9081_device_reset(&ad9081_dev, AD9081_HARD_RESET);
app_calc_tx_lane_rate(clk_hz[uc], &jrx_param[uc], tx_interp[uc], &app_jrx_lane_rate);
app_calc_rx_lane_rate(clk_hz[uc], jtx_param[uc], jtx_chip_dcm[uc], app_jtx_lane_rate);
printf("APP: Tx Lane Rate : %llu Rx0 Lane Rate : %llu Rx1 Lane Rate : %llu \r\n", app_jrx_lane_rate, app_jtx_lane_rate[0], app_jtx_lane_rate[1]);
//--------------------------------------------------------------------------------------------------------------------
printf("APP: Configure Platform Reference Clocks\n");
//--------------------------------------------------------------------------------------------------------------------
// configure 7044 to generate clock
uint64_t ad9081_clk = clk_hz[uc][0];
uint64_t fpga_clk = clk_hz[uc][1];
uint64_t sysref_clk_204c = fpga_clk/32;
uint64_t hmc7044_crystal_input = 100e6;
// uint64_t jesd_core_clk = 125e6;
// uint64_t jesd_core_clk = 237.5e6;
uint64_t jesd_core_clk = fpga_clk;
/* Configure HMC7044 SYSREF frequency output channels for SC1 Use Case */
ad9081_dev.clk_info.sysref_clk = &hmc7044_dev;
ad9081_dev.clk_info.sysref_ctrl = app_sysref_clk_src_sel;
/* Calculate SYSREF Freq for SC1 Use cases*/
ad9081_dev.clk_info.sysref_mode = SYSREF_CONT;
if (err = adi_ad9081_sync_sysref_frequency_set(&ad9081_dev, &sysref_clk_204c, ad9081_clk, clk_hz[uc][2], clk_hz[uc][3], tx_interp[uc][0], tx_interp[uc][1], rx_cddc_dcm[uc], rx_fddc_dcm[uc], jtx_param[uc][0].jesd_duallink, &jrx_param[uc], jtx_param[uc]), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
printf("APP: SYSREF Clk: %lld\n", sysref_clk_204c);
/*Configure HMC7044 to Provide Clocks For Txfe & FPGA*/
uint8_t hmc_priority[] = { 1, 0, 2, 3 };
uint16_t hmc_out_ch = HMC7044_OP_CH_0 | HMC7044_OP_CH_2 | HMC7044_OP_CH_3 | HMC7044_OP_CH_6 | HMC7044_OP_CH_8 | HMC7044_OP_CH_10 | HMC7044_OP_CH_12 | HMC7044_OP_CH_13;
uint64_t hmc_out_204c[14] = { fpga_clk, 0, ad9081_clk, sysref_clk_204c, 0, 0, jesd_core_clk, 0, fpga_clk, 0, jesd_core_clk, 0, fpga_clk, sysref_clk_204c };
/* Disable SYSREF signal channels for Subclass 0 */
if (((jrx_param[uc].jesd_subclass == 0) && (jtx_param[uc][0].jesd_subclass == 0))) {
hmc_out_ch &= ~(HMC7044_OP_CH_3 | HMC7044_OP_CH_13);
hmc_out_204c[3] = 0;
hmc_out_204c[13] = 0;
}
if (err = adi_hmc7044_device_init(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_device_reset(&hmc7044_dev, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/*Disable Configure but Output Drivers Prior to Clocking Scheme Configuration*/
for (int i = 0; i< HMC7044_NOF_OP_CH; i++) {
if (err = adi_hmc7044_output_config_set(&hmc7044_dev, i, HMC7044_OP_SIG_CH_DIV, 0, 0, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
}
if (err = adi_hmc7044_input_reference_set(&hmc7044_dev, 0, IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_input_reference_set(&hmc7044_dev, 1, IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_input_reference_los_config_set(&hmc7044_dev, 7, 0, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_vco_sel_set(&hmc7044_dev, HMC7044_VCO_INTERNAL_3GHZ, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_output_sync_config_set(&hmc7044_dev, 3, ((ad9081_dev.clk_info.sysref_mode == SYSREF_ONESHOT) ? 1 : 0), 1, 1), err != API_CMS_ERROR_OK) /* clkout3 as async mode or pulse gen mode*/
error_print(__LINE__, err);
if (err = adi_hmc7044_output_sync_config_set(&hmc7044_dev, 13, ((ad9081_dev.clk_info.sysref_mode == SYSREF_ONESHOT) ? 1 : 0), 1, 1), err != API_CMS_ERROR_OK) /* clkout13 as async mode or pulse gen mode*/
error_print(__LINE__, err);
if (err = adi_hmc7044_output_multi_slip_config_set(&hmc7044_dev, 3, 0, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_output_multi_slip_config_set(&hmc7044_dev, 13, 0, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Configure number of pulses generated from HMC7044 SYSREF - default set to continuous pulses */
if (err = adi_hmc7044_sysref_config_set(&hmc7044_dev, HMC7044_SYSREF_CONTINUOUS_MODE), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_clk_config(&hmc7044_dev, HMC7044_CLK_IN_0, hmc_priority, hmc7044_crystal_input, hmc7044_crystal_input, hmc_out_ch, hmc_out_204c), err != API_CMS_ERROR_OK) {
if (err == API_CMS_ERROR_INVALID_PARAM)
printf("APP: HMC7044: Invalid param passed.\n");
error_print(__LINE__, err);
}
if (err = adi_hmc7044_device_sysref_enable_control_set(&hmc7044_dev, 1, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_high_performance_set(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_reg_update(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_hmc7044_reseed_request_set(&hmc7044_dev), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = ad9081_hal_wait_us(NULL, 100000), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
uint8_t hmc_pll_locked = 0;
if (err = adi_hmc7044_device_pll_lock_status_get(&hmc7044_dev, &hmc_pll_locked), err != API_CMS_ERROR_OK) {
printf("APP: HMC7044: PLL is not locked.\n");
error_print(__LINE__, err);
}
printf("APP: Reference Clocks Configured\n");
//--------------------------------------------------------------------------------------------------------------------
/* AD9081 Device Data Path Configuration Sequenece
* Do AD9081 Device RESET, adi_ad9081_device_reset
* Do AD9081 Device Initialization: adi_ad9081_device_init
* Do AD9081 Device Clocks Config (REF CLK, DAC CLK, ADC Clock):adi_ad9081_device_clk_config_set
* Do AD9081 Device TX Datapath (JESD RX to DAC) Primary Configuration: adi_ad9081_device_startup_tx
* Do AD9081 Device Tx Datapath Secondary Configuration as per specific UC requirements
* eg TX Gain APIs
* - adi_ad9081_dac_duc_nco_gains_set
* TX Datapath Customization API:
* -adi_ad9081_dac_modulation_mux_mode_set
* -adi_ad9081_dac_xbar_set
* TX Test Modes APIs:
* -adi_ad9081_device_startup_nco_test_mode
* Do AD9081 Device RX Datapath (ADC to JESD TX) Primary Configuration: adi_ad9081_device_startup_rx
* Do AD9081 Device Rx Datapath Secondary Configuration as per specific UC requirements
* eg: RX Gain APIs:
* - adi_ad9081_adc_ddc_fine_gain_set
* RX Datapath Customization APIs:
* - adi_ad9081_adc_nyquist_zone_set
* - adi_ad9081_adc_xbar_set
* RX Test Mode APIs:
* - adi_ad9081_jesd_loopback_mode_set
* - adi_ad9081_adc_ddc_coarse_nco_mode_set
*
*/
//--------------------------------------------------------------------------------------------------------------------
uint8_t adc_cddc_xbar, cddc_fddc_xbar;
uint16_t phase = 0;
printf("APP: Configure ad9081 Device\n");
/* reset ad9081 */
if (err = adi_ad9081_device_reset(&ad9081_dev, AD9081_SOFT_RESET), err != API_CMS_ERROR_OK) {
printf("APP: ad9081 Initialisation Error\n");
error_print(__LINE__, err);
}
/* init ad9081 */
if (err = adi_ad9081_device_init(&ad9081_dev), err != API_CMS_ERROR_OK) {
printf("APP: ad9081 Initialisation Error\n");
error_print(__LINE__, err);
}
/* setup ad9081 clock */
err = adi_ad9081_device_clk_config_set(&ad9081_dev, clk_hz[uc][2], clk_hz[uc][3], clk_hz[uc][0]);
uint8_t ad9081_pll_locked = 0;
adi_ad9081_device_clk_pll_lock_status_get(&ad9081_dev, &ad9081_pll_locked);
if (ad9081_pll_locked == 0x3) {
printf("APP: ad9081 PLL LOCKED\n");
}
if (err != API_CMS_ERROR_OK) {
printf("APP: Clock Configuration error\n");
error_print(__LINE__, err);
}
// // DAC NCO TEST MODE!!!!!!
// xil_printf("!!!!!!!!!!! DAC NCO TEST MODE !!!!!!!!!!!!!!!!!!!!!!!\r\n");
// if (err = adi_ad9081_device_startup_nco_test_mode(&ad9081_dev, tx_interp[uc][0], tx_interp[uc][1], tx_dac_chan_xbar[uc],
// tx_main_shift[uc], tx_chan_shift[uc], &jrx_param[uc], (uint16_t)pow(10, ((0 + 20 * log10(0x5a82)) / 20))), err != API_CMS_ERROR_OK)
// return err;
/* start ad9081 tx */
if (err = adi_ad9081_device_startup_tx(&ad9081_dev, tx_interp[uc][0], tx_interp[uc][1], tx_dac_chan_xbar[uc],
tx_main_shift[uc], tx_chan_shift[uc], &jrx_param[uc]), err != API_CMS_ERROR_OK) {
printf("APP: ad9081 Tx Path Configuration Error \n");
if (err == API_CMS_ERROR_JESD_PLL_NOT_LOCKED) {
printf("APP: ad9081 Tx Path Configuration JESD PLL Not Locked \n");
}
error_print(__LINE__, err);
}
/* Setup ad9081 tx channel gain */
uint16_t tx_chan_gains[8];
for (int i = 0; i < 8; i++)
tx_chan_gains[i] = (uint16_t)(pow(2, 11) * pow(10, (tx_chan_gain[uc][i]) / 20.0));
if (err = adi_ad9081_dac_duc_nco_gains_set(&ad9081_dev, tx_chan_gains), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/*Configure Primary Rx Datapath Settings*/
if (err = adi_ad9081_device_startup_rx(&ad9081_dev, rx_cddc_select[uc], rx_fddc_select[uc], rx_cddc_shift[uc], rx_fddc_shift[uc],
rx_cddc_dcm[uc], rx_fddc_dcm[uc], rx_cddc_c2r[uc], rx_fddc_c2r, jtx_param[uc], jtx_conv_sel[uc]), err != API_CMS_ERROR_OK) {
printf("APP: ad9081 Rx Path Configuration Error \n");
error_print(__LINE__, err);
}
/* Configure Synchronization Options as per Application Use-case*/
/* By Default Application uses Subclass 0 and Internal Sysref Synchronization*/
/* Note 21/26/27 Are examples of Subclass 1*/
printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
/* Configure Sysref Receiver and Input mode */
if (err = adi_ad9081_sync_sysref_input_config_set(&ad9081_dev, COUPLING_AC, SIGNAL_CML, 0, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Configure cddc nco sync */
if (err = adi_ad9081_adc_ddc_coarse_sync_enable_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_adc_ddc_coarse_sync_next_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_adc_ddc_coarse_trig_nco_reset_enable_set(&ad9081_dev, AD9081_ADC_CDDC_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* Perform oneshot sync */
if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 1), err != API_CMS_ERROR_OK){
if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
printf("APP: JESD Oneshot Synchronization Not Completed\n");
}
error_print(__LINE__, err);
}
if (err = adi_ad9081_jesd_sysref_monitor_phase_get(&ad9081_dev, &phase), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
printf("APP: Phase offset between incoming SYSREF and internal LMFC/LEMC: %d DAC clock units\n", phase);
// printf("APP: JESD RX Synchronization Mode: %s\n", ((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ? "JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
// /* Power down Sysref Receiver circuitry*/
// if (err = adi_ad9081_jesd_sysref_input_mode_set(&ad9081_dev, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, jrx_param[uc].jesd_subclass > 0 ? 1 : 0, COUPLING_AC), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// /* Perform oneshot sync */
// if (err = adi_ad9081_jesd_oneshot_sync(&ad9081_dev, 0), err != API_CMS_ERROR_OK){
// if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE) {
// printf("APP: JESD Oneshot Synchronization Not Completed");
// }
// error_print(__LINE__, err);
// }
/* SYSTEM Link Bring Up Sequenece
* Check AD9081 JESD PLL Lock Status
* Enable AD9081 JESD Rx/ JESD TX Links
* Ensure FPGA JESD RX/ JESD TX Links are configured
* Ensure FPGA is transmitting Data
* Toggle AD9081 JESD RX Links Enable
* Run AD9081 JESD RX 204C Calibration if Lane Rate is above Threshold AD9081_JESDRX_204C_CAL_THRESH
* Toggle AD9081 JESD RX Links Enable
* Check Link Status after short period time
*/
/* Check JESD PLL LOCK Status */
uint8_t uc_jesd_pll_status = 0x00;
err = adi_ad9081_jesd_pll_lock_status_get(&ad9081_dev, &uc_jesd_pll_status);
printf("APP: ad9081 JESD PLL lock Status: %s : %s\n", (uc_jesd_pll_status ? "LOCKED" : "NOT LOCKED"), (uc_jesd_pll_status ? "Enabling Links" : "Exiting"));
if (err != API_CMS_ERROR_OK) {
error_print(__LINE__, err);
}
if (err = adi_ad9081_jesd_tx_link_enable_set(&ad9081_dev, (jtx_param[uc][0].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
//
// /* calibrate jrx when lane rate is high for 204c */
// printf("APP: Run JESD RX 204C Calibration & Enable TX Path Links\n");
// if ((jrx_param[uc].jesd_l > 0) && (jrx_param[uc].jesd_jesdv == 2) && ((clk_hz[uc][1] * 66) > AD9081_JESDRX_204C_CAL_THRESH)) {
// if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0x00, (ad9081_dev.serdes_info.des_settings.cal_mode == AD9081_CAL_MODE_RUN_AND_SAVE) ? 0 : 1), err != API_CMS_ERROR_OK) {
// printf("APP: ad9081 JESD RX Calibration Error\n");
// error_print(__LINE__, err);
// }
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
// error_print(__LINE__, err);
// }
#ifdef IBERT_TESTING
adi_ad9081_jesd_tx_phy_prbs_test(&ad9081_dev, AD9081_LINK_ALL, PRBS31);
#endif
#ifndef IBERT_TESTING
// Update FPGA TX Transceiver settings
set_lane_cal(0, 0, 0);
set_lane_cal(1, 10, 5);
set_lane_cal(2, 5, 0);
set_lane_cal(3, 0, 0);
set_lane_cal(4, 0, 0);
set_lane_cal(5, 0, 0);
set_lane_cal(6, 12, 0);
set_lane_cal(7, 0, 0);
vTaskDelay(100);
int subclass = jtx_param[uc][0].jesd_subclass;
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
xil_printf("Reset FPGA JESD Cores\r\n");
Xil_Out32(0x40050000 + 0x008, 0x31 | 0x300 | 0xC0);
vTaskDelay(100);
Xil_Out32(0x40050000 + 0x008, 0x31);
// Wait for reset to complete
xil_printf("Wait for RX to complete reset\r\n");
int val = 1;
while (val) {
val = Xil_In32(JESD_RX + RESET_REG);
xil_printf("rx reset state: 0x%x\r\n", val);
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
vTaskDelay(10);
}
xil_printf("Wait for TX to complete reset\r\n");
val = 1;
while (val) {
val = Xil_In32(JESD_TX + RESET_REG);
xil_printf("tx reset state: 0x%x\r\n", val);
vTaskDelay(10);
}
// for (int i = 0; i < 8; i++){
// uint32_t val0 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x418);
// uint32_t val1 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x414);
// uint32_t val2 = Xil_In32(XPAR_JESD_JESD204_PHY_0_BASEADDR + 0x608);
// xil_printf("Lane %d, Pre %d, Post %d, RX %d\r\n", i, val0, val1, val2);
// }
xil_printf("Changing MB in EMB\r\n");
Xil_Out32(JESD_TX + CTRL_MB_IN_EMB, 1);
Xil_Out32(JESD_RX + CTRL_MB_IN_EMB, 1);
xil_printf("Changing Subclass\r\n");
Xil_Out32(JESD_TX + 0x34, subclass);
Xil_Out32(JESD_RX + 0x34, subclass);
xil_printf("Changing Meta\r\n");
Xil_Out32(JESD_TX + 0x34, 0);
Xil_Out32(JESD_RX + 0x34, 0);
xil_printf("Changing Ctrl Sysref\r\n");
Xil_Out32(JESD_TX + 0x50, 2);
Xil_Out32(JESD_RX + 0x50, 2);
Xil_Out32(JESD_RX + CTRL_RX_BUF_ADV, 0);
val = Xil_In32(JESD_RX + CTRL_RX_BUF_ADV);
if (val != 0) {
xil_printf("ERROR. Buffer Advance (RX) not updated.\r\n");
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("* STATUS_REG = 0x%x\r\n", val);
}
xil_printf("Reset both modules to update configuration\r\n");
Xil_Out32(0x40050000 + 0x008, 0x31 | 0x300 | 0xC0);
vTaskDelay(100);
Xil_Out32(0x40050000 + 0x008, 0x31);
// Wait for reset to complete
xil_printf("Wait for RX to complete reset\r\n");
val = 1;
while (val) {
val = Xil_In32(JESD_RX + RESET_REG);
xil_printf("rx reset state: 0x%x\r\n", val);
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
vTaskDelay(10);
}
xil_printf("Wait for TX to complete reset\r\n");
val = 1;
while (val) {
val = Xil_In32(JESD_TX + RESET_REG);
xil_printf("tx reset state: 0x%x\r\n", val);
vTaskDelay(10);
}
xil_printf("Wait for Block Sync\r\n");
val = 0;
while ((val & STATUS_SH_LOCK_BIT) != STATUS_SH_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
vTaskDelay(100);
}
xil_printf("* Block sync achieved\r\n");
xil_printf("Wait for Extended Multiblock lock\r\n");
val = 0;
while ((val & STATUS_EMB_LOCK_BIT) != STATUS_EMB_LOCK_BIT) {
val = Xil_In32(JESD_RX + STAT_STATUS_REG);
xil_printf("STAT_STATUS_REG 0x%x\r\n", val);
vTaskDelay(100);
}
xil_printf("* Extended Multiblock lock achieved\r\n");
xil_printf("Enable TX data and command stream\r\n");
Xil_Out32(JESD_TX + CTRL_ENABLE_REG, ENABLE_DATA_CMD);
xil_printf("Enable RX data and command stream\r\n");
Xil_Out32(JESD_RX + CTRL_ENABLE_REG, ENABLE_DATA_CMD);
vTaskDelay(100);
xil_printf("GPI: 0x%x\r\n", Xil_In32(0x40050000 + 0x00C));
xil_printf("RX Version: 0x%x\r\n", Xil_In32(JESD_RX + 0x000));
xil_printf("RX Config: 0x%x\r\n", Xil_In32(JESD_RX + 0x004));
xil_printf("RX Stat Lock Debug: 0x%x\r\n", Xil_In32(JESD_RX + 0x054));
xil_printf("RX Stat Status: 0x%x\r\n", Xil_In32(JESD_RX + 0x060));
// TX Core
xil_printf("TX Version: 0x%x\r\n", Xil_In32(JESD_TX + 0x000));
xil_printf("TX Config: 0x%x\r\n", Xil_In32(JESD_TX + 0x004));
xil_printf("TX Stat Status: 0x%x\r\n", Xil_In32(JESD_TX + 0x060));
// RX Core
xil_printf("RX Version: 0x%x\r\n", Xil_In32(XPAR_JESD_JESD204C_0_BASEADDR + 0x000));
xil_printf("RX Config: 0x%x\r\n", Xil_In32(XPAR_JESD_JESD204C_0_BASEADDR + 0x004));
xil_printf("RX Stat Lock Debug: 0x%x\r\n", Xil_In32(XPAR_JESD_JESD204C_0_BASEADDR + 0x054));
xil_printf("RX Stat Status: 0x%x\r\n", Xil_In32(XPAR_JESD_JESD204C_0_BASEADDR + 0x060));
xil_printf("RX MB IN EBD: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_MB_IN_EMB));
xil_printf("RX SUBCLASS MODE: 0x%x\r\n", Xil_In32(JESD_RX + 0x34));
xil_printf("RX CTRL_META_MODE: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_META_MODE));
xil_printf("RX CTRL_ENABLE_REG: 0x%x\r\n", Xil_In32(JESD_RX + CTRL_ENABLE_REG));
xil_printf("RX CTRL_LANE_ENA: 0x%x\r\n", Xil_In32(JESD_RX + 0x40));
xil_printf("RX CTRL_SYSREF: 0x%x\r\n", Xil_In32(JESD_RX + 0x50));
xil_printf("RX STAT_LOCK_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x54));
xil_printf("RX STAT_RX_ERR: 0x%x\r\n", Xil_In32(JESD_RX + 0x58));
xil_printf("RX STAT_RX_DEBUG: 0x%x\r\n", Xil_In32(JESD_RX + 0x5C));
#endif
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
/* calibrate jrx when lane rate is high for 204c */
printf("APP: Run JESD RX 204C Calibration & Enable TX Path Links\n");
if ((jrx_param[uc].jesd_l > 0) && (jrx_param[uc].jesd_jesdv == 2) && ((clk_hz[uc][1] * 66) > AD9081_JESDRX_204C_CAL_THRESH)) {
if (err = adi_ad9081_jesd_rx_calibrate_204c(&ad9081_dev, 1, 0x00, (ad9081_dev.serdes_info.des_settings.cal_mode == AD9081_CAL_MODE_RUN_AND_SAVE) ? 0 : 1), err != API_CMS_ERROR_OK) {
printf("APP: ad9081 JESD RX Calibration Error\n");
error_print(__LINE__, err);
}
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, AD9081_LINK_ALL, 0), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
if (err = adi_ad9081_jesd_rx_link_enable_set(&ad9081_dev, (jrx_param[uc].jesd_duallink > 0) ? AD9081_LINK_ALL : AD9081_LINK_0, 1), err != API_CMS_ERROR_OK)
error_print(__LINE__, err);
}
for (int i = 0; i < 8; i++) {
// Clear Error Counts
Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10);
}
vTaskDelay(100);
for (int i = 0; i < 8; i++) {
xil_printf("Lane %d Buf Level: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x0));
xil_printf("Lane %d Stat 0: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x10));
xil_printf("Lane %d Stat 1: 0x%x\r\n", i, Xil_In32(JESD_RX + 0x400 + i * 0x100 + 0x14));
}
#ifdef IBERT_TESTING
while (1) {
adi_ad9081_jesd_rx_phy_prbs_test(&ad9081_dev, PRBS31, 100);
xil_printf("Check PRBS Errors\r\n");
for (int i = 0; i < 8; i++) {
adi_ad9081_prbs_test_t prbs_res;
adi_ad9081_jesd_rx_phy_prbs_test_result_get(&ad9081_dev, i, &prbs_res);
xil_printf(" Lane %d, Errors %d\r\n", i, prbs_res.phy_prbs_err_cnt);
}
}
#endif
}

257
vitis/radar/src/ethernet.c Executable file
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@@ -0,0 +1,257 @@
#include "netif/xadapter.h"
#include "lwipopts.h"
#include "lwip/init.h"
#include "lwip/inet.h"
#include "lwip/tcp.h"
#include "lwip/ip_addr.h"
#include "lwip/sockets.h"
#include "lwip/sys.h"
#include "project.h"
#include "radar_manager_icd.h"
#include "novatel.h"
#define DEFAULT_IP_ADDRESS "192.168.1.200"
#define DEFAULT_GW_ADDRESS "192.168.1.1"
#define DEFAULT_IP_MASK "255.255.255.0"
#define TCP_CONN_PORT 5001
static struct netif server_netif;
int curr_sd;
int new_sd;
static SemaphoreHandle_t xMutex;
static QueueHandle_t valid_client;
static unsigned char msgBuffer[MAX_MSG_LENGTH];
#define RECV_BUF_SIZE 1024
unsigned char recv_buf[RECV_BUF_SIZE+2];
void print_ip(char *msg, ip_addr_t *ip)
{
DEBUG_PRINT(msg);
DEBUG_PRINT("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
ip4_addr3(ip), ip4_addr4(ip));
}
void print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw, u16 port)
{
print_ip("Board IP: ", ip);
print_ip("Netmask : ", mask);
print_ip("Gateway : ", gw);
DEBUG_PRINT("Port : %d\n\r", htons(port));
}
static void assign_default_ip(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
{
int err;
DEBUG_PRINT("Configuring default IP %s \r\n", DEFAULT_IP_ADDRESS);
err = inet_aton(DEFAULT_IP_ADDRESS, ip);
if(!err)
DEBUG_PRINT("Invalid default IP address: %d\r\n", err);
err = inet_aton(DEFAULT_IP_MASK, mask);
if(!err)
DEBUG_PRINT("Invalid default IP MASK: %d\r\n", err);
err = inet_aton(DEFAULT_GW_ADDRESS, gw);
if(!err)
DEBUG_PRINT("Invalid default gateway address: %d\r\n", err);
}
void eth_sendMessage(u8 * data, int num_bytes)
{
// Need a mutex to make this safe to call from any task, currently this is
// setup to block forever until the mutex is available
if( xSemaphoreTake( xMutex, portMAX_DELAY ) )
{
int sent_count = 0;
while (sent_count < num_bytes)
{
sent_count += send(curr_sd, data, num_bytes, 0);
}
// Release the mutex
xSemaphoreGive( xMutex );
}
else
{
// Could not get mutex
}
}
void eth_rx_task()
{
int n;
int header_found = 0;
int msg_ind = 0;
while (1)
{
// Need to wait until we have a valid socket to interact with
DEBUG_PRINT("RX Thread - Waiting for client\r\n");
xQueueReceive( valid_client, &curr_sd, portMAX_DELAY);
DEBUG_PRINT("RX Thread - Got Client %d\r\n", curr_sd);
while (1)
{
struct pollfd poll_fd;
poll_fd.fd = curr_sd;
poll_fd.events = POLLIN;
int poll_ret = lwip_poll(&poll_fd, 1, 1000);
if (poll_ret == 0)
{
// This was a timeout, see if there is a new client available
int temp_sd;
if (xQueueReceive( valid_client, &temp_sd, 0) == pdTRUE)
{
// Close the old socket
close(curr_sd);
header_found = 0;
msg_ind = 0;
// Get the new socket
curr_sd = temp_sd;
DEBUG_PRINT("RX Thread - Got Client Poll %d\r\n", curr_sd);
}
}
else if (poll_ret > 0)
{
// Socket is ready
n = read(curr_sd, recv_buf, RECV_BUF_SIZE);
/* break if client closed connection or error */
if (n == 0)
{
DEBUG_PRINT("RX Thread - Client Closed Socket, closing socket %d\r\n", curr_sd);
close(curr_sd);
header_found = 0;
msg_ind = 0;
break;
}
else if (n < 0)
{
// Some other error
DEBUG_PRINT("RX Thread - Socket Error %d, closing socket %d\r\n", n, curr_sd);
close(curr_sd);
break;
}
// Send data to radar manager (radar_manager_get_message)
radar_manager_get_message(recv_buf, n, msgBuffer, &msg_ind, &header_found);
}
}
}
}
void tcp_server_task()
{
valid_client = xQueueCreate( 1, 4 );
// Mutex for thread saftey for send task
xMutex = xSemaphoreCreateMutex();
/* initialize lwIP before calling sys_thread_new */
lwip_init();
/* the mac address of the board. this should be unique per board */
u16 ip_port = htons(TCP_CONN_PORT);
u8_t mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 };
DEBUG_PRINT("\n\r\n\r");
DEBUG_PRINT("-----lwIP Socket Mode TCP Server Application------\r\n");
DEBUG_PRINT("Ethernet MAC: %02X:%02X:%02X:%02X:%02X:%02X\n\r",
mac_ethernet_address[0],
mac_ethernet_address[1],
mac_ethernet_address[2],
mac_ethernet_address[3],
mac_ethernet_address[4],
mac_ethernet_address[5]);
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(&server_netif, NULL, NULL, NULL, mac_ethernet_address,
XPAR_AXI_ETHERNET_0_BASEADDR)) {
DEBUG_PRINT("Error adding N/W interface\r\n");
return;
}
netif_set_default(&server_netif);
/* specify that the network if is up */
netif_set_up(&server_netif);
/* start packet receive thread - required for lwIP operation */
sys_thread_new("xemacif_input_thread",
(void(*)(void*))xemacif_input_thread, &server_netif,
1024, DEFAULT_THREAD_PRIO);
assign_default_ip(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw));
print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw), ip_port);
int sock;
int size;
struct sockaddr_in address, remote;
memset(&address, 0, sizeof(address));
if ((sock = lwip_socket(AF_INET, SOCK_STREAM, 0)) < 0) {
DEBUG_PRINT("TCP server: Error creating Socket\r\n");
return;
}
address.sin_family = AF_INET;
address.sin_port = ip_port;
address.sin_addr.s_addr = INADDR_ANY;
if (bind(sock, (struct sockaddr *)&address, sizeof (address)) < 0) {
DEBUG_PRINT("TCP server: Unable to bind to port %d\r\n",
htons(ip_port));
close(sock);
return;
}
if (listen(sock, 1) < 0) {
DEBUG_PRINT("TCP server: tcp_listen failed\r\n");
close(sock);
return;
}
size = sizeof(remote);
sys_thread_new("eth_rx", eth_rx_task,
NULL,
4096,
TASK_PRIORITY_ETH_RX);
sys_thread_new("novatel", novatel_task,
NULL,
4096,
TASK_PRIORITY_ETH_RX);
while (1)
{
// Wait for a client to connect, currently only support a single connected client. When a new client connects
// the old connection is dropped
DEBUG_PRINT("Server Listening\r\n");
new_sd = lwip_accept(sock, (struct sockaddr *)&remote, (socklen_t *)&size);
DEBUG_PRINT("Server Accept %d from %s:%d\r\n", new_sd, inet_ntoa(remote.sin_addr), htons(remote.sin_port));
if (new_sd > 0)
{
// Set socket options
int flags = 1;
int ret = setsockopt(new_sd, IPPROTO_TCP, TCP_NODELAY, (void *)&flags, sizeof(flags));
// Notify the RX task a new connection is available
xQueueSend( valid_client, &new_sd, 0 );
DEBUG_PRINT("Client Connected! %d, %d\r\n", new_sd, ret);
}
}
}

8
vitis/radar/src/ethernet.h Executable file
View File

@@ -0,0 +1,8 @@
#ifndef ETHERNET_H /* prevent circular inclusions */
#define ETHERNET_H /* by using protection macros */
void eth_sendMessage(u8 * data, int num_bytes);
void tcp_server_task();
#endif /* end of protection macro */

101
vitis/radar/src/hmc7044.c Executable file
View File

@@ -0,0 +1,101 @@
#include "xstatus.h"
#include "xspi_l.h"
#include "xil_printf.h"
#include "ad9081_hal_functions.h"
#include "ad9081_api/adi_inc/adi_cms_api_common.h"
#define uint32_t u32
#define int32_t s32
#define SPI_BASEADDR XPAR_SPI_1_BASEADDR
u32 send_byte(u8 data) {
XSpi_WriteReg(SPI_BASEADDR, XSP_DTR_OFFSET, data);
while (!(XSpi_ReadReg(SPI_BASEADDR, XSP_SR_OFFSET) & XSP_SR_TX_EMPTY_MASK));
u32 recv_byte = XSpi_ReadReg(SPI_BASEADDR, XSP_DRR_OFFSET);
return recv_byte;
}
u32 read_reg(u32 addr) {
u32 rw = 1;
u32 w = 0;
u32 reg_addr = addr;
XSpi_WriteReg(SPI_BASEADDR, XSP_SSR_OFFSET, 0x1);
XSpi_WriteReg(SPI_BASEADDR, XSP_SSR_OFFSET, 0x0);
send_byte((rw << 7) | (w << 5) | (reg_addr >> 8));
send_byte(reg_addr & 0xFF);
XSpi_WriteReg(SPI_BASEADDR, XSP_SSR_OFFSET, 0x2);
u32 read_data = send_byte(0);
XSpi_WriteReg(SPI_BASEADDR, XSP_SSR_OFFSET, 0x1);
// xil_printf("Read Data 0x%x\r\n", read_data);
return read_data;
}
u32 write_reg(u32 addr, u8 data) {
u32 rw = 0;
u32 w = 0;
u32 reg_addr = addr;
XSpi_WriteReg(SPI_BASEADDR, XSP_SSR_OFFSET, 0x1);
XSpi_WriteReg(SPI_BASEADDR, XSP_SSR_OFFSET, 0x0);
send_byte((rw << 7) | (w << 5) | (reg_addr >> 8));
send_byte(reg_addr & 0xFF);
send_byte(data);
XSpi_WriteReg(SPI_BASEADDR, XSP_SSR_OFFSET, 0x1);
}
void hmc7044_init() {
u32 Control;
/*
* Set up the device in loopback mode and enable master mode.
*/
Control = XSpi_ReadReg(SPI_BASEADDR, XSP_CR_OFFSET);
Control |= (XSP_CR_MASTER_MODE_MASK);
XSpi_WriteReg(SPI_BASEADDR, XSP_CR_OFFSET, Control);
/*
* Enable the device.
*/
Control = XSpi_ReadReg(SPI_BASEADDR, XSP_CR_OFFSET);
Control |= XSP_CR_ENABLE_MASK;
Control &= ~XSP_CR_TRANS_INHIBIT_MASK;
XSpi_WriteReg(SPI_BASEADDR, XSP_CR_OFFSET, Control);
}
int32_t hal_spi_xfer_hmc7044(void *user_data, uint8_t *in_data, uint8_t *out_data, uint32_t size_bytes)
{
uint32_t value;
char msg[100];
va_list argp = {0};
// if (user_data == NULL || in_data == NULL || out_data == NULL) {
if (in_data == NULL || out_data == NULL) {
return API_CMS_ERROR_NULL_PARAM;
}
uint32_t addr = (in_data[0] << 8) | in_data[1];
if (in_data[0] & 0x80) {
// ads9_spi_read(addr, &value, 8);
value = read_reg(addr);
out_data[2] = (uint8_t)value;
sprintf(msg, " 7044: r@%.4x = %.2x", addr, out_data[2]);
ad9081_hal_log_write(user_data, ADI_CMS_LOG_MSG, msg, argp);
}
else {
// ads9_spi_write(addr, in_data[2], 8);
write_reg(addr, in_data[2]);
sprintf(msg, " 7044: w@%.4x = %.2x", addr, in_data[2]);
ad9081_hal_log_write(user_data, ADI_CMS_LOG_MSG, msg, argp);
}
return API_CMS_ERROR_OK;
}
void hmc7044_configure() {
read_reg(0x78);
read_reg(0x79);
read_reg(0x7A);
}

9
vitis/radar/src/hmc7044.h Executable file
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#ifndef HMC_H /* prevent circular inclusions */
#define HMC_H /* by using protection macros */
void hmc7044_init();
void hmc7044_configure();
int32_t hal_spi_xfer_hmc7044(void *user_data, uint8_t *in_data, uint8_t *out_data, uint32_t size_bytes);
#endif /* end of protection macro */

55
vitis/radar/src/hmc7044/inc/hmc7044_hal.h Executable file
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@@ -0,0 +1,55 @@
/*!
* @brief Helper HAL functions
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __HMC7044_HAL_
* @{
*/
#ifndef __HMC7044_HAL_H__
#define __HMC7044_HAL_H__
/*============= I N C L U D E S ============*/
#include "adi_cms_api_common.h"
/*============= D E F I N E S ==============*/
#define SPI_IN_OUT_BUFF_SZ 0x3
uint64_t gcd(uint64_t value1, uint64_t value2);
uint64_t lcm(uint64_t value1, uint64_t value2);
/*============= E X P O R T S ==============*/
#ifdef _cplusplus
extern "C" {
#endif
int32_t hmc7044_hw_open(adi_hmc7044_device_t *device);
int32_t hmc7044_hw_close(adi_hmc7044_device_t *device);
int32_t hmc7044_sw_delay_us(adi_hmc7044_device_t *device, uint32_t us);
int32_t hmc7044_hw_reset(adi_hmc7044_device_t *device);
int32_t hmc7044_spi_reg_get(adi_hmc7044_device_t *device,
uint32_t reg, uint8_t *data);
int32_t hmc7044_spi_reg_set(adi_hmc7044_device_t *device,
uint32_t reg, uint8_t data);
int32_t hmc7044_spi_reg_tbl_set(adi_hmc7044_device_t *device,
adi_cms_reg_data_t *tbl, uint32_t count);
int32_t hmc7044_spi_reg_block_get(adi_hmc7044_device_t *device,
const uint16_t address, uint8_t *data, uint32_t count);
#ifdef __cplusplus
}
#endif
#endif /*__HMC7044_HAL_H__*/
/*! @} */

127
vitis/radar/src/hmc7044/inc/hmc7044_reg.h Executable file
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/*!
* @brief HMC7044 register and bit fields
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __HMC7044_REG_
* @{
*/
#ifndef __HMC7044_REG_H__
#define __HMC7044_REG_H__
/*============= I N C L U D E S ============*/
#include "adi_utils.h"
/*============= D E F I N E S ==============*/
#define HMC7044_
#define HMC7044_GLOBAL_SW_RESET_CTRL_REG 0x00
#define HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG 0x01
#define HMC7044_GLOBAL_ENABLE_CTRL_REG 0x03
#define HMC7044_GLOBAL_CH_ENABLE_CTRL_REG 0x04
#define HMC7044_GLOBAL_MODE_ENABLE_CTRL_REG 0x05
#define HMC7044_SOFT_RESET ADI_UTILS_BIT(0)
#define HMC7044_RESET_DIV_FSM ADI_UTILS_BIT(1)
#define HMC7044_MUTE_OP_DRIVERS_EN ADI_UTILS_BIT(2)
#define HMC7044_CLK_IP_BUFF_BASE_REG 0x000A
#define HMC7044_CLK_IP_BUFF_OFFSET 0x1
#define HMC7044_CLK_IP_PRIORITY_REG 0x014
#define HMC7044_PLL1_LOS_TIMER_CTRL_REG 0x0015
#define HMC7044_PLL1_HOLDOVER_EXIT_CTRL_REG 0x0016
#define HMC7044_PLL1_HOLDOVER_DAC_CTRL_REG 0x0017
#define HMC7044_PLL1_HOLDOVER_ADC_CTRL_REG 0x0018
#define HMC7044_PLL1_CHARGE_PUMP_CRTL_REG 0x001A
#define HMC7044_PLL1_LOS_VALID_TIMER(x) ((x & 0x7)<<0)
#define HMC7044_PLL1_LOS_MODE_REG 0x0019
#define HMC7044_LOS_INPUT_PRESCALER_BYPASS ADI_UTILS_BIT(1)
#define HMC7044_LOS_VCXO_PRESCALER_EN ADI_UTILS_BIT(0)
#define HMC7044_CHIP_ID_0_REG 0x078
#define HMC7044_CHIP_ID_1_REG 0x079
#define HMC7044_CHIP_ID_2_REG 0x07A
#define HMC7044_CLKINX_PRESCALER_BASE_REG 0x001C
#define HMC7044_CLKINX_PRESCALER_OFFSET 0x1
#define HMC7044_OSCIN_PRESCALER_REG 0x0020
#define HMC7044_PLL1_R_DIV_LSB_REG 0x0021
#define HMC7044_PLL1_R_DIV_MSB_REG 0x0022
#define HMC7044_PLL1_N_DIV_LSB_REG 0x0026
#define HMC7044_PLL1_N_DIV_MSB_REG 0x0027
#define HMC7044_PLL1_LOCK_DETECT_CTRL_REG 0x0028
#define HMC7044_PLL1_REF_SWITCH_CTRL_REG 0x0029
#define HMC7044_PLL1_HOLDOFF_TIME_CRTL_REG 0x002A
#define HMC7044_PLL2_FREQ_DOUBLER_REG 0x0032
#define HMC7044_PLL2_FREQ_DOUBLER_EN ADI_UTILS_BIT(0)
#define HMC7044_PLL2_R_DIV_LSB_REG 0x0033
#define HMC7044_PLL2_R_DIV_MSB_REG 0x0034
#define HMC7044_PLL2_N_DIV_LSB_REG 0x0035
#define HMC7044_PLL2_N_DIV_MSB_REG 0x0036
#define HMC7044_PLL2_CHARGE_PUMP_CRTL_REG 0x0037
#define HMC7044_PLL2_OSCOUT_PATH_CTRL_REG 0x0039
#define HMC7044_OSCOUT1_CTRL_REG 0x003A
#define HMC7044_OSC_OP_DRIVER_MODE(x) ((x & 0x3)<<4)
#define HMC7044_OSC_OP_DRIVER_IMPEDANCE(x) ((x & 0x3)<<1)
#define HMC7044_SYSREF_SYNC_CTRL_REG 0x005A
#define HMC7044_SYNC_CTRL_REG 0x005B
#define HMC7044_SYNC_TIMER_LSB_CTRL_REG 0x005C
#define HMC7044_SYNC_TIMER_MSB_CTRL_REG 0x005D
#define HMC7044_ALARM_MASK_CTRL_1_REG 0x0070
#define HMC7044_ALARM_MASK_CTRL_2_REG 0x0071
#define HMC7044_GPI_CTRL_1_REG 0x0046
#define HMC7044_GPI_CTRL_2_REG 0x0047
#define HMC7044_GPI_CTRL_3_REG 0x0048
#define HMC7044_GPI_CTRL_4_REG 0x0049
#define HMC7044_GPO_CTRL_1_REG 0x0050
#define HMC7044_GPO_CTRL_2_REG 0x0051
#define HMC7044_GPO_CTRL_3_REG 0x0052
#define HMC7044_GPO_CTRL_4_REG 0x0053
#define HMC7044_SDATA_CTRL_REG 0x0054
#define HMC7044_CLK_EXT_VCO_CTRL 0x0064
#define HMC7044_CLK_OP_CTRL_0_REG 0x00C8
#define HMC7044_CLK_OP_HIGH_PERFORM_EN ADI_UTILS_BIT(7)
#define HMC7044_CLK_OP_SYNC_EN ADI_UTILS_BIT(6)
#define HMC7044_CLK_OP_SLIP_EN ADI_UTILS_BIT(5)
#define HMC7044_CLK_OP_STARTUP_MODE(x) ((x & 0x3)<<2)
#define HMC7044_CLK_OP_MULTI_SLIP_EN ADI_UTILS_BIT(1)
#define HMC7044_CLK_OP_EN ADI_UTILS_BIT(0)
#define HMC7044_CLK_OP_CTRL_1_REG 0x00C9
#define HMC7044_CLK_OP_CTRL_2_REG 0x00CA
#define HMC7044_CLK_OP_CTRL_3_REG 0x00CB
#define HMC7044_CLK_OP_FINE_DELAY(x) ((x & 0xF)<<0)
#define HMC7044_CLK_OP_CTRL_4_REG 0x00CC
#define HMC7044_CLK_OP_COURSE_DELAY(x) ((x & 0x1F)<<0)
#define HMC7044_CLK_OP_CTRL_5_REG 0x00CD
#define HMC7044_CLK_OP_CTRL_6_REG 0x00CE
#define HMC7044_CLK_OP_CTRL_7_REG 0x00CF
#define HMC7044_CLK_OP_MUX_SEL(x) ((x & 0x3)<<0)
#define HMC7044_CLK_OP_CTRL_8_REG 0x00D0
#define HMC7044_CLK_OP_FORCE_MUTE(x) ((x & 0x3)<<6)
#define HMC7044_CLK_OP_DYNAMIC_DR_EN ADI_UTILS_BIT(5)
#define HMC7044_CLK_OP_DRIVER_MODE(x) ((x & 0x3)<<3)
#define HMC7044_CLK_OP_DRIVER_IMPEDANCE(x) ((x & 0x3)<<0)
#define HMC7044_CLK_OP_CTRL_9_REG 0x00D1
#define HMC7044_CLK_OP_CTRL_OFFSET 0x0A
#define HMC7044_OSC_OP_CTRL_OFFSET 0x01
#endif /*__HMC7044_REG_H__*/
/*! @} */

756
vitis/radar/src/hmc7044/src/adi_hmc7044_device.c Executable file
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@@ -0,0 +1,756 @@
/*!
* @brief Device level API implementation
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __HMC7044_DEVICE_API__
* @{
*/
/*============= I N C L U D E S ============*/
#include "adi_utils.h"
#include "adi_hmc7044.h"
#include "hmc7044_hal.h"
#include "hmc7044_reg.h"
/*============= D E F I N E S ==============*/
/*============= D A T A ====================*/
static uint8_t hmc7044_api_revision[3] = {0,3,3};
static adi_cms_reg_data_t ADI_RECOMMENDED_INIT_TBL[] = {
{0x09F,0x4D},
{0x0A0,0xDF},
{0x0A5,0x06},
{0x0A8,0x06},
{0x0B0,0x04},
};
/*============= C O D E ====================*/
int32_t adi_hmc7044_device_hw_open(adi_hmc7044_device_t *device)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (device->hal_info.spi_xfer == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_XFER_PTR;
}
if (device->hal_info.delay_us == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_DELAYUS_PTR;
}
err = hmc7044_hw_open(device);
if (err != API_CMS_ERROR_OK) {
return err;
}
#if 0 /*TODO: Finalise:Data sheet says its recommended but may be not required*/
err = hmc7044_hw_reset(device);
if (err != API_CMS_ERROR_OK) {
return err;
}
#endif
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_hw_close(adi_hmc7044_device_t *device)
{
int32_t err;
#if 0 /*TODO: Finalise:Data sheet says its recommended but may be not required*/
err = hmc7044_hw_reset(device);
if (err != API_CMS_ERROR_OK) {
return err;
}
#endif
err = hmc7044_hw_close(device);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_sleep_set(adi_hmc7044_device_t *device, uint8_t sleepmode)
{
int32_t err;
uint8_t reg_val;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
err = hmc7044_spi_reg_get(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val &= (sleepmode);
err = hmc7044_spi_reg_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_init(adi_hmc7044_device_t *device)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
err = hmc7044_spi_reg_tbl_set(device, &ADI_RECOMMENDED_INIT_TBL[0],
ADI_UTILS_ARRAY_SIZE(ADI_RECOMMENDED_INIT_TBL));
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_reset(adi_hmc7044_device_t *device, uint8_t hw_reset)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (hw_reset > 1) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (hw_reset) {
err = hmc7044_hw_reset(device);
if (err != API_CMS_ERROR_OK) {
return err;
}
} else {
err = hmc7044_spi_reg_set(device,
HMC7044_GLOBAL_SW_RESET_CTRL_REG, HMC7044_SOFT_RESET);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_sw_delay_us(device, HMC7044_SPI_RESET_PERIOD_US);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_spi_reg_set(device, HMC7044_GLOBAL_SW_RESET_CTRL_REG, 0x0);
if (err != API_CMS_ERROR_OK) {
return err;
}
}
err = hmc7044_sw_delay_us(device, HMC7044_SPI_RESET_PERIOD_US);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_spi_reg_tbl_set(device, &ADI_RECOMMENDED_INIT_TBL[0],
ADI_UTILS_ARRAY_SIZE(ADI_RECOMMENDED_INIT_TBL));
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_deinit(adi_hmc7044_device_t *device)
{
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_chip_id_get(adi_hmc7044_device_t *device, adi_cms_chip_id_t *chip_id)
{
int err;
uint8_t tmp_reg[3];
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (chip_id == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = hmc7044_spi_reg_get(device, HMC7044_CHIP_ID_0_REG, &tmp_reg[0]);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_spi_reg_get(device, HMC7044_CHIP_ID_1_REG, &tmp_reg[1]);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_spi_reg_get(device, HMC7044_CHIP_ID_2_REG, &tmp_reg[2]);
if (err != API_CMS_ERROR_OK) {
return err;
}
/*TODO: Get details on this*/
chip_id->dev_revision = tmp_reg[0];
chip_id->prod_id = (((uint16_t) tmp_reg[2]) << 8);
chip_id->prod_id |= (tmp_reg[1]);
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_spi_register_set(adi_hmc7044_device_t *device, uint16_t addr, uint8_t val)
{
return hmc7044_spi_reg_set(device, addr, val);
}
int32_t adi_hmc7044_device_spi_register_get(adi_hmc7044_device_t *device, uint16_t addr, uint8_t *val)
{
return hmc7044_spi_reg_get(device, addr, val);
}
int32_t adi_hmc7044_device_api_revision_get(adi_hmc7044_device_t *device, uint8_t *rev_major,
uint8_t *rev_minor, uint8_t *rev_rc)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
err = API_CMS_ERROR_OK;
if (rev_major != ADI_INVALID_POINTER) {
*rev_major = hmc7044_api_revision[0];
} else {
err = API_CMS_ERROR_INVALID_PARAM;
}
if (rev_minor != ADI_INVALID_POINTER) {
*rev_minor = hmc7044_api_revision[1];
} else {
err = API_CMS_ERROR_INVALID_PARAM;
}
if(rev_rc != ADI_INVALID_POINTER) {
*rev_rc = hmc7044_api_revision[2];
} else {
err = API_CMS_ERROR_INVALID_PARAM;
}
return err;
}
int32_t adi_hmc7044_device_trigger_restart(adi_hmc7044_device_t *device)
{
uint8_t reg_val;
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
err = hmc7044_spi_reg_get(device, HMC7044_GLOBAL_SW_RESET_CTRL_REG, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val |= HMC7044_RESET_DIV_FSM;
err = hmc7044_spi_reg_set(device, HMC7044_GLOBAL_SW_RESET_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_sw_delay_us(device, HMC7044_DIV_RESET_PERIOD_US);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val &= (~HMC7044_RESET_DIV_FSM);
err = hmc7044_spi_reg_set(device, HMC7044_GLOBAL_SW_RESET_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_gpi_config_set(adi_hmc7044_device_t *device, uint8_t gpi_index, uint8_t gpi_config, uint8_t enable)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((gpi_index >= HMC7044_NOF_GPIO_MAX)) {
return API_CMS_ERROR_INVALID_PARAM;
}
gpi_config = (gpi_config << 1) | enable;
err = adi_hmc7044_device_spi_register_set(device, (HMC7044_GPI_CTRL_1_REG + gpi_index), gpi_config);
return err;
}
int32_t adi_hmc7044_gpo_config_set(adi_hmc7044_device_t *device, uint8_t gpo_index, uint8_t gpo_config, uint8_t mode, uint8_t enable)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((gpo_index >= HMC7044_NOF_GPIO_MAX)) {
return API_CMS_ERROR_INVALID_PARAM;
}
gpo_config = (gpo_config << 2) | (mode << 1) | enable;
err = adi_hmc7044_device_spi_register_set(device, (HMC7044_GPO_CTRL_1_REG + gpo_index), gpo_config );
return err;
}
int32_t adi_hmc7044_sdata_config_set(adi_hmc7044_device_t *device, uint8_t mode, uint8_t enable)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_SDATA_CTRL_REG, (mode << 1) | enable);
return err;
}
int32_t adi_hmc7044_clk_config(adi_hmc7044_device_t *device, adi_hmc7044_clk_in_e ref_ch, uint8_t ref_priority[4], uint64_t ref_clk_freq_hz, uint64_t fvcxo_clk_freq_hz, uint16_t output_ch, uint64_t output_clk_freq_hz[14])
{
uint8_t pll_lock_st =0x0;
int32_t err;
uint64_t flcm_clk_hz, pfd1_clk_hz, pfd2_clk_hz, clkin_prescaler, vcxo_prescaler, pll2ref_clk_hz, pfd2_lcm_hz, pfd2_gcd_hz, fvco_clk_hz = 0;
uint64_t R1, N1, N2, R2, output_chan_divider;
uint64_t i = 0, M1 = 1, M2 = 1;
uint64_t sysref_timer = 0;
/*range check*/
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (ref_ch > HMC7044_CLK_IN_ALL) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((ref_clk_freq_hz > HMC7044_REF_CLK_FREQ_HZ_MAX || ref_clk_freq_hz < HMC7044_REF_CLK_FREQ_HZ_MIN)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (fvcxo_clk_freq_hz < HMC7044_VCXO_CLK_FREQ_HZ_MIN || fvcxo_clk_freq_hz > HMC7044_VCXO_CLK_FREQ_HZ_MAX) {
return API_CMS_ERROR_INVALID_PARAM;
}
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if (output_clk_freq_hz[i]) {
uint16_t opchan = 1 << i;
if ((output_ch & opchan) != opchan) {
return API_CMS_ERROR_INVALID_PARAM;
}
}
}
/*enable clkin*/
if (err = adi_hmc7044_enable_input_reference_set(device, 0, (ref_ch & HMC7044_CLK_IN_0)), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_enable_input_reference_set(device, 1, (ref_ch & HMC7044_CLK_IN_1) >> 1), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_enable_input_reference_set(device, 2, (ref_ch & HMC7044_CLK_IN_2) >> 2), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_enable_input_reference_set(device, 3, (ref_ch & HMC7044_CLK_IN_3) >> 3), err != API_CMS_ERROR_OK)
return err;
/*enable oscin*/
if (err = adi_hmc7044_enable_input_reference_set(device, 4, 1), err != API_CMS_ERROR_OK)
return err;
/*set clkin priority*/
if (err = adi_hmc7044_input_reference_priority_set(device, ref_priority, 4), err != API_CMS_ERROR_OK)
return err;
/*calculate fPFD1*/
pfd1_clk_hz = gcd(ref_clk_freq_hz, fvcxo_clk_freq_hz);
while (pfd1_clk_hz / M1 > 50e6) {
M1++;
}
pfd1_clk_hz = pfd1_clk_hz / M1;
if (fvcxo_clk_freq_hz / 65535 > pfd1_clk_hz) {
return API_CMS_ERROR_ERROR;
}
uint64_t ref_div = ref_clk_freq_hz / pfd1_clk_hz;
flcm_clk_hz = ref_clk_freq_hz;
while (flcm_clk_hz / M2 > 123.00e6 || ref_div % M2 !=0) {
M2++;
}
clkin_prescaler = M2;
flcm_clk_hz = ref_clk_freq_hz / M2;
vcxo_prescaler = (fvcxo_clk_freq_hz / pfd1_clk_hz)/(ref_div / clkin_prescaler);
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 0, clkin_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 1, clkin_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 2, clkin_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 3, clkin_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_oscin_prescaler_config_set(device, vcxo_prescaler), err != API_CMS_ERROR_OK)
return err;
/* calculate pll2ref*/
pll2ref_clk_hz = fvcxo_clk_freq_hz <= HMC7044_PLL2REF_CLK_DB_FREQ_HZ_MAX ? 2 * fvcxo_clk_freq_hz : fvcxo_clk_freq_hz;
/*calculate fvco*/
pfd2_gcd_hz = pll2ref_clk_hz;
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if (output_clk_freq_hz[i]) {
pfd2_gcd_hz = gcd(pfd2_gcd_hz, output_clk_freq_hz[i]);
}
}
pfd2_lcm_hz = pfd2_gcd_hz;
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if (output_clk_freq_hz[i]) {
pfd2_lcm_hz = lcm(pfd2_lcm_hz, output_clk_freq_hz[i]);
}
}
uint64_t fdist;
for (uint64_t k = 0; k < HMC7044_PLL2_R_DIV_MAX; k++) {
fdist = k * pfd2_lcm_hz;
if (fdist > HMC7044_VCO_CLK_FREQ_HZ_MIN && fdist < HMC7044_VCO_CLK_FREQ_HZ_MAX) {
/*check output divider, should be 1,3,5 or even numbers*/
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if (output_clk_freq_hz[i]) {
output_chan_divider = fdist / output_clk_freq_hz[i];
if (output_chan_divider % 2 != 0) {
if (output_chan_divider != 1 && output_chan_divider != 3 && output_chan_divider != 5) {
break;
}
}
}
}
if (i == HMC7044_NOF_OP_CH) {
fvco_clk_hz = fdist;
break;
}
}
}
/*calculate fpfd2*/
pfd2_clk_hz = gcd(fvco_clk_hz, pll2ref_clk_hz);
if (pfd2_clk_hz < HMC7044_PD2_CLK_FREQ_HZ_MIN || pfd2_clk_hz > HMC7044_PD2_CLK_FREQ_HZ_MAX) {
return API_CMS_ERROR_ERROR;
}
/*calculate R1, N1, R2, N2*/
R1 = flcm_clk_hz / pfd1_clk_hz;
N1 = fvcxo_clk_freq_hz / pfd1_clk_hz;
R2 = pll2ref_clk_hz / pfd2_clk_hz;
N2 = fvco_clk_hz / pfd2_clk_hz;
/*pll config*/
if (err = adi_hmc7044_pll1_config_set(device, R1, N1), err != API_CMS_ERROR_OK)
return err;
if (err = hmc7044_sw_delay_us(device, 10000), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_device_pll_lock_status_get(device, &pll_lock_st), err != API_CMS_ERROR_OK)
return err;
if (!(pll_lock_st & HMC7044_PLL1_LOCK_ST))
return API_CMS_ERROR_PLL_NOT_LOCKED;
if (fvcxo_clk_freq_hz <= HMC7044_PLL2REF_CLK_DB_FREQ_HZ_MAX)
{
if (err = adi_hmc7044_pll2_config_set(device, 0x0, R2, N2), err != API_CMS_ERROR_OK)
return err;
}
else
{
if (err = adi_hmc7044_pll2_config_set(device, 0x1, R2, N2), err != API_CMS_ERROR_OK)
return err;
}
if (err = hmc7044_sw_delay_us(device, 100000), err != API_CMS_ERROR_OK)
return err;
/*output config*/
if (err = adi_hmc7044_output_performance_set(device, 1), err != API_CMS_ERROR_OK)
return err;
/*output config*/
adi_hmc7044_op_driver_config_t hmc_driver_config;
hmc_driver_config.mode = SIGNAL_CML;
hmc_driver_config.impedance = ADI_CMS_INTERNAL_RESISTOR_50_OHM;
hmc_driver_config.force_mute_en = 0;
hmc_driver_config.dynamic_driver_en = 0;
uint8_t startup_mode = 0;
/*Configure SYSREF Timer*/
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if ((output_ch >> i & 0x1)) {
if (sysref_timer < (fvco_clk_hz / output_clk_freq_hz[i])) {
sysref_timer = fvco_clk_hz / output_clk_freq_hz[i];
}
}
}
while (fvco_clk_hz/sysref_timer >= 4000000) {
sysref_timer <<= 1;
}
if (err = adi_hmc7044_sysref_timer_config_set(device, sysref_timer), err != API_CMS_ERROR_OK)
return err;
/*Configure Clockout Frequencies*/
for (i = 0; i < HMC7044_NOF_OP_CH; i++) {
if (i == 10) {
hmc_driver_config.mode = SIGNAL_LVDS;
} else {
hmc_driver_config.mode = SIGNAL_CML;
}
if ((output_ch >> i & 0x1)) {
if (err = adi_hmc7044_channel_startup_mode_get(device, i, &startup_mode), startup_mode == 1){
hmc_driver_config.force_mute_en = 1;
if (adi_hmc7044_output_driver_config_set(device, i, &hmc_driver_config), err != API_CMS_ERROR_OK)
return err;
hmc_driver_config.force_mute_en = 0;
if (err = adi_hmc7044_output_config_set(device, i, HMC7044_OP_SIG_CH_DIV, sysref_timer, 0, 1), err != API_CMS_ERROR_OK)
return err;
}
else {
if (adi_hmc7044_output_driver_config_set(device, i, &hmc_driver_config), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_output_config_set(device, i, HMC7044_OP_SIG_CH_DIV, fvco_clk_hz / output_clk_freq_hz[i], 0, 1), err != API_CMS_ERROR_OK)
return err;
}
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_reg_update(adi_hmc7044_device_t *device)
{
int32_t err;
uint8_t reg_val;
err = adi_hmc7044_device_spi_register_get(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, (reg_val | 0x02));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, (reg_val & ~(0x02)));
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_reseed_request_set(adi_hmc7044_device_t *device)
{
int32_t err;
uint8_t reg_val;
err = adi_hmc7044_device_spi_register_get(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, (reg_val | 0x80));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, (reg_val & ~(0x80)));
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_high_performance_set(adi_hmc7044_device_t *device)
{
int32_t err;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, 0x40);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_vco_sel_set(adi_hmc7044_device_t *device, uint8_t vco_sel, uint8_t ext_vco_div_en)
{
int32_t err;
uint8_t reg_val = 0x00;
if (vco_sel >= HMC7044_VCO_SEL_INVALID || ext_vco_div_en > 1) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (err = adi_hmc7044_device_spi_register_get(device, HMC7044_GLOBAL_ENABLE_CTRL_REG, &reg_val), err != API_CMS_ERROR_OK) {
return err;
}
reg_val &= ~(0x18);
if (vco_sel != HMC7044_VCO_EXTERNAL) {
reg_val |= (vco_sel << 3);
}
else {
if (err = adi_hmc7044_device_spi_register_set(device, HMC7044_CLK_EXT_VCO_CTRL, (ext_vco_div_en << 1)), err != API_CMS_ERROR_OK) {
return err;
}
}
if (err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_ENABLE_CTRL_REG, reg_val), err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_channel_out_en(adi_hmc7044_device_t *device, uint8_t ch_en)
{
int32_t err;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_CH_ENABLE_CTRL_REG, ch_en);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_input_reference_path_en(adi_hmc7044_device_t *device, uint8_t sync_mode, uint8_t vco_input_mode, uint8_t sync_input_mode, uint8_t clk_in)
{
int32_t err;
uint8_t reg_val = 0x00;
if (err = adi_hmc7044_device_spi_register_get(device, HMC7044_GLOBAL_MODE_ENABLE_CTRL_REG, &reg_val), err != API_CMS_ERROR_OK) {
return err;
}
reg_val &= ~((0x1 << 6) | (0x1<< 5) | (0x1 << 4) | (0x1));
reg_val |= ((sync_mode << 6) | (vco_input_mode << 5) | (sync_input_mode << 4) | clk_in);
err = adi_hmc7044_device_spi_register_set(device, HMC7044_GLOBAL_MODE_ENABLE_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_sysref_enable_control_set(adi_hmc7044_device_t *device, uint8_t reseed_en, uint8_t sysref_timer_en)
{
int32_t err;
uint8_t reg_val;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
err = hmc7044_spi_reg_get(device, HMC7044_GLOBAL_ENABLE_CTRL_REG, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val |= (reseed_en << 5) | (sysref_timer_en << 2);
err = hmc7044_spi_reg_set(device, HMC7044_GLOBAL_ENABLE_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_sysref_config_set(adi_hmc7044_device_t *device, uint8_t pulse_gen_mode)
{
int32_t err;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_SYSREF_SYNC_CTRL_REG, pulse_gen_mode);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_sync_config_set(adi_hmc7044_device_t *device, uint8_t sync_retime, uint8_t sync_pll2, uint8_t sync_polarity)
{
int32_t err;
uint8_t reg_val = (sync_retime << 2) | (sync_pll2 << 1) | sync_polarity;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_SYNC_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_sysref_timer_config_set(adi_hmc7044_device_t *device, uint16_t sysref_timer)
{
int32_t err;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_SYNC_TIMER_LSB_CTRL_REG, sysref_timer & 0xFF);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_SYNC_TIMER_MSB_CTRL_REG, (sysref_timer >> 8) & 0xFF);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pulse_gen_set(adi_hmc7044_device_t *device) {
int32_t err;
uint8_t reg_val;
err = hmc7044_spi_reg_get(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_spi_reg_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, (reg_val | 0x04));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = hmc7044_spi_reg_set(device, HMC7044_GLOBAL_REQUEST_MODE_CTRL_REG, (reg_val & ~(0x04)));
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_alarm_mask_config_set(adi_hmc7044_device_t *device, adi_hmc7044_alarm_mask_config_t *config)
{
int32_t err;
uint8_t reg_val = (config->pll1_lock << 7) | (config->pll1_lock_aquisition << 6) | (config->pll1_lock_detect << 5) | (config->pll1_holdover_status << 4) | config->pll1_clkInx_status;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_ALARM_MASK_CTRL_1_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val = (config->sync_request << 4) | (config->pll1_pll2_lock_detect << 3) | (config->clkoutputs_phase_status << 2) | (config->sysref_sync_status << 1) | config->pll2_lock_detect;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_ALARM_MASK_CTRL_2_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_channel_startup_mode_get(adi_hmc7044_device_t *device, uint8_t ch, uint8_t *startup_mode) {
int32_t err;
uint8_t reg_val;
uint16_t reg_addr;
reg_addr = (HMC7044_CLK_OP_CTRL_0_REG + (ch * HMC7044_CLK_OP_CTRL_OFFSET));
err = adi_hmc7044_device_spi_register_get(device, reg_addr, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
*startup_mode = ((reg_val & 0x0C) > 0) ? 1 : 0;
return API_CMS_ERROR_OK;
}
/*! @! */

308
vitis/radar/src/hmc7044/src/adi_hmc7044_output_ch.c Executable file
View File

@@ -0,0 +1,308 @@
/*!
* @brief Output Clock Distributor Support API implementation
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __HMC7044_OUTPUT_CH_API__
* @{
*/
/*============= I N C L U D E S ============*/
#include "adi_utils.h"
#include "adi_hmc7044.h"
#include "hmc7044_hal.h"
#include "hmc7044_reg.h"
/*============= D E F I N E S ==============*/
/*============= C O D E ====================*/
int32_t adi_hmc7044_output_config_set(adi_hmc7044_device_t *device, uint8_t output_ch,
adi_hmc7044_op_source_e output_sel, uint16_t ch_div, uint8_t mode, uint8_t enable)
{
int32_t err;
uint16_t reg_addr;
uint8_t reg_val;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((output_ch >= HMC7044_NOF_OP_CH) || (ch_div > HMC7044_CH_DIV_MAX)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((output_sel >= HMC7044_OP_SIG_INVALID) || (mode > 1 ) || (enable > 1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (HMC7044_CLK_OP_CTRL_0_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
err = adi_hmc7044_device_spi_register_get(device, reg_addr, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
if (!enable) {
reg_val &= 0xFE;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
return API_CMS_ERROR_OK;
}
reg_val &= ~HMC7044_CLK_OP_HIGH_PERFORM_EN;
reg_val |= mode ? HMC7044_CLK_OP_HIGH_PERFORM_EN : 0;
reg_val |= enable;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_addr = (HMC7044_CLK_OP_CTRL_1_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
reg_val = (uint8_t) (ch_div & 0xFF);
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_addr = (HMC7044_CLK_OP_CTRL_2_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
reg_val = (uint8_t) ((ch_div >> 8) & 0xFF);
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_addr = (HMC7044_CLK_OP_CTRL_7_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
reg_val = 0x0;
reg_val |= HMC7044_CLK_OP_MUX_SEL(output_sel);
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_output_driver_config_set(adi_hmc7044_device_t *device,
uint8_t output_ch, adi_hmc7044_op_driver_config_t *config)
{
int32_t err;
uint16_t reg_addr;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (output_ch >= HMC7044_NOF_OP_CH) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((config->mode != SIGNAL_CML) &&
(config->mode != SIGNAL_LVPECL) &&
(config->mode != SIGNAL_LVDS) &&
(config->mode != SIGNAL_CMOS)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((config->impedance != ADI_CMS_NO_INTERNAL_RESISTOR) &&
(config->impedance != ADI_CMS_INTERNAL_RESISTOR_100_OHM) &&
(config->impedance != ADI_CMS_INTERNAL_RESISTOR_50_OHM) ) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((config->dynamic_driver_en > 1 ) ||
(config->force_mute_en > 1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (HMC7044_CLK_OP_CTRL_8_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
if (config->impedance == ADI_CMS_INTERNAL_RESISTOR_100_OHM) {
reg_val |= HMC7044_CLK_OP_DRIVER_IMPEDANCE(0x1);
} else if (config->impedance == ADI_CMS_INTERNAL_RESISTOR_50_OHM) {
reg_val |= HMC7044_CLK_OP_DRIVER_IMPEDANCE(0x3);
}
reg_val |= config->dynamic_driver_en ? HMC7044_CLK_OP_DYNAMIC_DR_EN : 0x0;
reg_val |= config->force_mute_en ? HMC7044_CLK_OP_FORCE_MUTE(0x2) : 0x0;
switch (config->mode) {
case SIGNAL_CML:
reg_val |= HMC7044_CLK_OP_DRIVER_MODE(0x0);
break;
case SIGNAL_LVPECL:
reg_val |= HMC7044_CLK_OP_DRIVER_MODE(0x1);
break;
case SIGNAL_LVDS:
reg_val |= HMC7044_CLK_OP_DRIVER_MODE(0x2);
break;
case SIGNAL_CMOS:
default:
reg_val |= HMC7044_CLK_OP_DRIVER_MODE(0x3);
break;
}
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_output_enable_set(adi_hmc7044_device_t *device, uint8_t output_ch, uint8_t en)
{
int32_t err;
uint16_t reg_addr;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((output_ch >= HMC7044_NOF_OP_CH) || (en >1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (HMC7044_CLK_OP_CTRL_0_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
err = adi_hmc7044_device_spi_register_get(device, reg_addr, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val &= !HMC7044_CLK_OP_EN;
reg_val |= en? HMC7044_CLK_OP_EN : 0x0;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_output_delay_set(adi_hmc7044_device_t *device,
uint8_t output_ch, uint8_t coarse_adj, uint8_t fine_adj)
{
int32_t err;
uint16_t reg_addr;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (output_ch >= HMC7044_NOF_OP_CH) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((coarse_adj >= HMC7044_CLK_OP_COURSE_DELAY(ADI_UTILS_ALL)) ||
(fine_adj >= HMC7044_CLK_OP_FINE_DELAY(ADI_UTILS_ALL))) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (HMC7044_CLK_OP_CTRL_4_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
reg_val = coarse_adj;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_addr = (HMC7044_CLK_OP_CTRL_3_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
reg_val = fine_adj;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_output_sync_config_set(adi_hmc7044_device_t *device, uint8_t output_ch,
uint8_t startup_mode, uint8_t slip_mode_en, uint8_t sync_mode_en)
{
int32_t err;
uint16_t reg_addr;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (output_ch >= HMC7044_NOF_OP_CH) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((startup_mode > 1) ||
(slip_mode_en > 1) ||
(sync_mode_en >1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (HMC7044_CLK_OP_CTRL_0_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
err = adi_hmc7044_device_spi_register_get(device, reg_addr, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val &= ~(HMC7044_CLK_OP_SYNC_EN |
HMC7044_CLK_OP_SLIP_EN |
HMC7044_CLK_OP_STARTUP_MODE(ADI_UTILS_ALL));
reg_val |= startup_mode ? HMC7044_CLK_OP_STARTUP_MODE(0x3) : HMC7044_CLK_OP_STARTUP_MODE(0x0);
reg_val |= slip_mode_en ? HMC7044_CLK_OP_SLIP_EN : 0;
reg_val |= sync_mode_en ? HMC7044_CLK_OP_SYNC_EN : 0;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_output_multi_slip_config_set(adi_hmc7044_device_t *device,
uint8_t output_ch, uint8_t multi_slip_en, uint16_t slip_delay)
{
int32_t err;
uint16_t reg_addr;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (output_ch >= HMC7044_NOF_OP_CH) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((multi_slip_en > 1) || (slip_delay > HMC7044_SLIP_DELAY_MAX)) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (HMC7044_CLK_OP_CTRL_0_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
err = adi_hmc7044_device_spi_register_get(device, reg_addr, &reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val &= ~(HMC7044_CLK_OP_MULTI_SLIP_EN);
reg_val |= multi_slip_en ? HMC7044_CLK_OP_MULTI_SLIP_EN : 0;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
if (multi_slip_en) {
reg_val = (uint8_t) (slip_delay & 0xFF);
reg_addr = (HMC7044_CLK_OP_CTRL_5_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val = (uint8_t) ((slip_delay >> 8) &0xF);
reg_addr = (HMC7044_CLK_OP_CTRL_6_REG + (output_ch * HMC7044_CLK_OP_CTRL_OFFSET));
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_output_performance_set(adi_hmc7044_device_t *device, uint8_t enable)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (!enable)
return API_CMS_ERROR_OK;
if (err = adi_hmc7044_device_spi_register_set(device, 0x009f, 0x4d), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_device_spi_register_set(device, 0x00a0, 0xdf), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_device_spi_register_set(device, 0x00a5, 0x6), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_device_spi_register_set(device, 0x00a8, 0x6), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_device_spi_register_set(device, 0x00b0, 0x4), err != API_CMS_ERROR_OK)
return err;
return API_CMS_ERROR_OK;
}
/*! @! */

549
vitis/radar/src/hmc7044/src/adi_hmc7044_pll.c Executable file
View File

@@ -0,0 +1,549 @@
/*!
* @brief DUAL PLL Clock Multiplier Support API implementation
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __HMC7044_PLL_API__
* @{
*/
/*============= I N C L U D E S ============*/
#include <stdlib.h>
#include "adi_utils.h"
#include "adi_hmc7044.h"
#include "hmc7044_hal.h"
#include "hmc7044_reg.h"
/*============= C O D E ====================*/
int32_t adi_hmc7044_input_reference_set(adi_hmc7044_device_t *device,
uint8_t clk_in, uint8_t config, uint8_t enable)
{
int32_t err;
uint16_t reg_addr;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((clk_in >= (HMC7044_NOF_CLK_IN + HMC7044_NOF_OSC_IN)) || (enable > 1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (((config & IPBUFFER_HIGH_Z_MODE_EN) && (config & IPBUFFER_AC_COUPLED_MODE_EN)) ||
((config & IPBUFFER_HIGH_Z_MODE_EN) && (config & IPBUFFER_LVPECL_MODE_EN)) ||
((config & IPBUFFER_AC_COUPLED_MODE_EN) && (config & IPBUFFER_LVPECL_MODE_EN)) ||
((config > IPBUFFER_CONFIG_MAX))) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = ((clk_in * HMC7044_CLK_IP_BUFF_OFFSET) + HMC7044_CLK_IP_BUFF_BASE_REG);
err = adi_hmc7044_device_spi_register_set(device, reg_addr, ((config <<1) | (enable)));
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_enable_input_reference_set(adi_hmc7044_device_t *device, uint8_t clk_in, uint8_t enable)
{
int32_t err;
uint8_t reg_val = 0x00;
uint16_t reg_addr = ((clk_in * HMC7044_CLK_IP_BUFF_OFFSET) + HMC7044_CLK_IP_BUFF_BASE_REG);
if (err = adi_hmc7044_device_spi_register_get(device, reg_addr, &reg_val), err != API_CMS_ERROR_OK) {
return err;
}
reg_val |= enable;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_input_reference_get(adi_hmc7044_device_t *device, uint8_t *status)
{
int32_t err;
uint8_t reg;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (err = adi_hmc7044_device_spi_register_get(device, 0x82, &reg), err != API_CMS_ERROR_OK) {
return err;
}
*status = (reg & 0x18);
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_input_reference_priority_set(adi_hmc7044_device_t *device,
uint8_t priority[4], uint8_t nof_ref)
{
int32_t err;
uint8_t i;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((priority == ADI_INVALID_POINTER) ||
(nof_ref > HMC7044_NOF_CLK_IN) ||
(nof_ref < 1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
for (i=0; i<HMC7044_NOF_CLK_IN; i++) {
if (i < nof_ref) {
reg_val |= priority[i] << (2*i);
} else {
reg_val |= priority[nof_ref-1] << (2*i);
}
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_CLK_IP_PRIORITY_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_input_reference_los_config_set(adi_hmc7044_device_t *device,
uint8_t timer_cycles, uint8_t prescaler_bypass, uint8_t vcxo_prescaler_en)
{
int32_t err;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (timer_cycles > HMC7044_PLL1_LOS_VALID_TIMER(ADI_UTILS_ALL)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((prescaler_bypass > 1) || (vcxo_prescaler_en > 1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_LOS_TIMER_CTRL_REG, timer_cycles);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val |= prescaler_bypass ? HMC7044_LOS_INPUT_PRESCALER_BYPASS : 0x0;
reg_val |= vcxo_prescaler_en ? HMC7044_LOS_VCXO_PRESCALER_EN : 0x0;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_LOS_MODE_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_input_reference_prescaler_config_set(adi_hmc7044_device_t *device,
uint8_t clk_in, uint8_t lcm_div)
{
int32_t err;
uint8_t reg_addr;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((clk_in >= HMC7044_NOF_CLK_IN) || (lcm_div < 1)) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (clk_in * HMC7044_CLKINX_PRESCALER_OFFSET) + HMC7044_CLKINX_PRESCALER_BASE_REG;
err = adi_hmc7044_device_spi_register_set(device, reg_addr, lcm_div);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_input_reference_oscin_prescaler_config_set(adi_hmc7044_device_t *device, uint8_t lcm_div)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (lcm_div < 1) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_OSCIN_PRESCALER_REG, lcm_div);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll1_config_set(adi_hmc7044_device_t *device, uint16_t r_div, uint16_t n_div)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((r_div < 1) || (n_div < 1 )) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_R_DIV_LSB_REG, ((uint8_t) (r_div & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_R_DIV_MSB_REG, ((uint8_t) ((r_div >>8) & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_N_DIV_LSB_REG, ((uint8_t) (n_div & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_N_DIV_MSB_REG, ((uint8_t) ((n_div >>8) & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll2_config_set(adi_hmc7044_device_t *device, uint8_t freq_dbl_en, uint16_t r_div, uint16_t n_div)
{
int32_t err;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((r_div < 1) || (n_div < 1) || (r_div > HMC7044_PLL2_R_DIV_MAX )) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (freq_dbl_en > 1) {
return API_CMS_ERROR_INVALID_PARAM;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL2_R_DIV_LSB_REG, ((uint8_t) (r_div & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL2_R_DIV_MSB_REG, ((uint8_t) ((r_div >>8) & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL2_N_DIV_LSB_REG, ((uint8_t) (n_div & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL2_N_DIV_MSB_REG, ((uint8_t) ((n_div >>8) & 0xFF)));
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val = freq_dbl_en ? HMC7044_PLL2_FREQ_DOUBLER_EN : 0x0;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL2_FREQ_DOUBLER_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_device_pll_lock_status_get(adi_hmc7044_device_t *device, uint8_t *status)
{
uint8_t reg_val = 0x0;
int32_t err;
if (status == NULL)
return API_CMS_ERROR_NULL_PARAM;
*status = 0;
if (err = adi_hmc7044_device_spi_register_get(device, 0x7D, &reg_val), err != API_CMS_ERROR_OK)
return err;
if (reg_val & 0x1)
*status |= HMC7044_PLL2_LOCK_ST;
if (reg_val & 0x8)
*status |= HMC7044_PLL1_AND_PLL2_LOCK_ST;
if (err = adi_hmc7044_device_spi_register_get(device, 0x7C, &reg_val), err != API_CMS_ERROR_OK)
return err;
if (reg_val & 0x20)
*status |= HMC7044_PLL1_LOCK_ST;
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll1_holdover_exit_ctrl_set(adi_hmc7044_device_t *device, adi_hmc_pll1_holdover_config_t *config)
{
int32_t err;
uint8_t reg_val = (config->exit_action << 2) | config ->exit_criteria;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_HOLDOVER_EXIT_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_HOLDOVER_DAC_CTRL_REG, config ->holdover_dac);
if (err != API_CMS_ERROR_OK) {
return err;
}
reg_val = (config ->adc_tracking << 3) | (config ->quick_mode << 2) | config ->holdover_bw;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_HOLDOVER_ADC_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll1_charge_pump_ctrl_set(adi_hmc7044_device_t *device, uint8_t charge_pump)
{
int32_t err;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_CHARGE_PUMP_CRTL_REG, charge_pump);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll1_lock_detect_set(adi_hmc7044_device_t *device, uint8_t slip_use, uint8_t lock_detect_timer)
{
int32_t err;
uint8_t reg_val = (slip_use << 5) | lock_detect_timer;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_LOCK_DETECT_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll1_reference_switch_ctrl_set(adi_hmc7044_device_t *device, uint8_t bypass_debounce, uint8_t manual_switch, uint8_t holdover_dac_use, uint8_t autorevert_switch, uint8_t automode_switch)
{
int32_t err;
uint8_t reg_val = (bypass_debounce << 5) | (manual_switch << 3) | (holdover_dac_use << 2) | (autorevert_switch << 1) | automode_switch;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_REF_SWITCH_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll1_holdoff_time_ctrl_set(adi_hmc7044_device_t *device, uint8_t hold_off_time)
{
int32_t err;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL1_HOLDOFF_TIME_CRTL_REG, hold_off_time);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll2_charge_pump_ctrl_set(adi_hmc7044_device_t *device, uint8_t charge_pump)
{
int32_t err;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL2_CHARGE_PUMP_CRTL_REG, charge_pump);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_oscout_path_config_set(adi_hmc7044_device_t *device, uint8_t divider, uint8_t enable)
{
int32_t err;
uint8_t reg_val = (divider << 1) | enable;
err = adi_hmc7044_device_spi_register_set(device, HMC7044_PLL2_OSCOUT_PATH_CTRL_REG, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_oscout_driver_config_set(adi_hmc7044_device_t *device, uint8_t oscout_ch, adi_hmc7044_op_driver_config_t *config)
{
int32_t err;
uint16_t reg_addr;
uint8_t reg_val = 0x0;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (oscout_ch >= HMC7044_NOF_OP_CH) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((config->mode != SIGNAL_CML) &&
(config->mode != SIGNAL_LVPECL) &&
(config->mode != SIGNAL_LVDS) &&
(config->mode != SIGNAL_CMOS)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if ((config->impedance != ADI_CMS_NO_INTERNAL_RESISTOR) &&
(config->impedance != ADI_CMS_INTERNAL_RESISTOR_100_OHM) &&
(config->impedance != ADI_CMS_INTERNAL_RESISTOR_50_OHM)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (config->dynamic_driver_en > 1) {
return API_CMS_ERROR_INVALID_PARAM;
}
reg_addr = (HMC7044_OSCOUT1_CTRL_REG + (oscout_ch * HMC7044_OSC_OP_CTRL_OFFSET));
if (config->impedance == ADI_CMS_INTERNAL_RESISTOR_100_OHM) {
reg_val |= HMC7044_OSC_OP_DRIVER_IMPEDANCE(0x1);
}
else if (config->impedance == ADI_CMS_INTERNAL_RESISTOR_50_OHM) {
reg_val |= HMC7044_OSC_OP_DRIVER_IMPEDANCE(0x3);
}
reg_val |= config->dynamic_driver_en ? 0x01 : 0x0;
switch (config->mode) {
case SIGNAL_CML:
reg_val |= HMC7044_OSC_OP_DRIVER_MODE(0x0);
break;
case SIGNAL_LVPECL:
reg_val |= HMC7044_OSC_OP_DRIVER_MODE(0x1);
break;
case SIGNAL_LVDS:
reg_val |= HMC7044_OSC_OP_DRIVER_MODE(0x2);
break;
case SIGNAL_CMOS:
default:
reg_val |= HMC7044_OSC_OP_DRIVER_MODE(0x3);
break;
}
err = adi_hmc7044_device_spi_register_set(device, reg_addr, reg_val);
if (err != API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_distribution_clk_config(adi_hmc7044_device_t *device, uint64_t ref_clk_freq_hz,
uint64_t pfd1_freq_hz, uint64_t dist_freq_hz, uint64_t pfd2_freq_hz)
{
int32_t err;
uint64_t R1, N1, N2, R2, Ra;
if (ref_clk_freq_hz > 800e6 || ref_clk_freq_hz < 0.00015e6) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (dist_freq_hz == 0 || pfd1_freq_hz == 0) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (ref_clk_freq_hz % (pfd1_freq_hz * 4) == 0) {
Ra = ref_clk_freq_hz / pfd1_freq_hz / 4;
if (Ra > 65535) {
return API_CMS_ERROR_ERROR;
}
} else {
return API_CMS_ERROR_INVALID_PARAM;
}
R1 = ref_clk_freq_hz / pfd1_freq_hz / 4;
N2 = dist_freq_hz / pfd2_freq_hz;
N1 = 245.76e6 / pfd1_freq_hz / 2;
R2 = 2 * 122.88e6 / pfd2_freq_hz;
err = adi_hmc7044_pll1_config_set(device, R1, N1);
if ( err != API_CMS_ERROR_OK) {
return err;
}
err = adi_hmc7044_pll2_config_set(device, 0x0, R2, N2);
if (err!= API_CMS_ERROR_OK) {
return err;
}
return API_CMS_ERROR_OK;
}
int32_t adi_hmc7044_pll_config(adi_hmc7044_device_t *device, adi_hmc7044_clk_in_e ref_ch, uint64_t ref_clk_freq_hz, uint64_t fvcxo_clk_freq_hz, uint64_t fpfd1_freq_hz, uint64_t fvco_freq_hz){
int32_t err;
uint64_t flcm_clk_hz, pfd1_clk_hz, pfd2_clk_hz, vcxo_prescaler, pll2ref_clk_hz;
uint64_t R1, N1, N2, R2;
uint8_t hmc_priority[] = { 0, 1, 2, 3 };
/*range check*/
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (ref_ch > HMC7044_CLK_IN_ALL) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if ((ref_clk_freq_hz > HMC7044_REF_CLK_FREQ_HZ_MAX || ref_clk_freq_hz < HMC7044_REF_CLK_FREQ_HZ_MIN)) {
return API_CMS_ERROR_INVALID_PARAM;
}
if (fvcxo_clk_freq_hz < HMC7044_VCXO_CLK_FREQ_HZ_MIN || fvcxo_clk_freq_hz > HMC7044_VCXO_CLK_FREQ_HZ_MAX) {
return API_CMS_ERROR_INVALID_PARAM;
}
/*enable clkin*/
if (err = adi_hmc7044_input_reference_set(device, 0, IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN, (ref_ch & HMC7044_CLK_IN_0)), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_set(device, 1, IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN, (ref_ch & HMC7044_CLK_IN_1) >> 1), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_set(device, 2, IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN, (ref_ch & HMC7044_CLK_IN_2) >> 2), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_set(device, 3, IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN, (ref_ch & HMC7044_CLK_IN_3) >> 3), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_priority_set(device, hmc_priority, 4), err != API_CMS_ERROR_OK)
return err;
/*calculate fLCM, typical range to be 30~40 MHz*/
flcm_clk_hz = ref_clk_freq_hz;
/*scale flcm to 30-40 range*/
if (ref_clk_freq_hz > HMC7044_PLL1REF_CLK_FREQ_HZ_MAX || ref_clk_freq_hz < HMC7044_PLL1REF_CLK_FREQ_HZ_MIN) {
uint8_t div = ref_clk_freq_hz / HMC7044_PLL1REF_CLK_FREQ_HZ_MIN;
flcm_clk_hz = ref_clk_freq_hz / div;
}
/*calculate vcxo prescaler*/
if (fvcxo_clk_freq_hz % flcm_clk_hz != 0) {
return API_CMS_ERROR_ERROR;
}
vcxo_prescaler = fvcxo_clk_freq_hz / flcm_clk_hz;
if (err = adi_hmc7044_input_reference_los_config_set(device, 7, 0, 0), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 0, vcxo_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 1, vcxo_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 2, vcxo_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_prescaler_config_set(device, 3, vcxo_prescaler), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_input_reference_oscin_prescaler_config_set(device, vcxo_prescaler), err != API_CMS_ERROR_OK)
return err;
/*calculate fPFD1*/
pfd1_clk_hz = gcd(flcm_clk_hz, fvcxo_clk_freq_hz);
if (fvcxo_clk_freq_hz / 65535 > pfd1_clk_hz) {
return API_CMS_ERROR_ERROR;
}
/* calculate pll2ref*/
pll2ref_clk_hz = fvcxo_clk_freq_hz <= 125e6 ? 2 * fvcxo_clk_freq_hz : fvcxo_clk_freq_hz;
/*calculate fpfd2*/
pfd2_clk_hz = gcd(fvco_freq_hz, pll2ref_clk_hz);
/*calculate R1, N1, R2, N2*/
R1 = flcm_clk_hz / pfd1_clk_hz;
N1 = fvcxo_clk_freq_hz / pfd1_clk_hz;
R2 = pll2ref_clk_hz / pfd2_clk_hz;
N2 = fvco_freq_hz / pfd2_clk_hz;
/*pll config*/
if (err = adi_hmc7044_pll1_config_set(device, R1, N1), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_pll2_config_set(device, 0x0, R2, N2), err != API_CMS_ERROR_OK)
return err;
if (err = adi_hmc7044_output_performance_set(device, 1), err != API_CMS_ERROR_OK)
return err;
return API_CMS_ERROR_OK;
}
/*! @! */

216
vitis/radar/src/hmc7044/src/hmc7044_hal.c Executable file
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@@ -0,0 +1,216 @@
/*!
* @brief Helper HAL functions
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __HMC7044_HAL__
* @{
*/
/*============= I N C L U D E S ============*/
#include <stdarg.h>
#include <stdlib.h>
#include "adi_hmc7044.h"
#include "hmc7044_hal.h"
/*============= D E F I N E S ==============*/
/*============= C O D E ====================*/
int32_t hmc7044_hw_open(adi_hmc7044_device_t *device)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (device->hal_info.hw_open != ADI_INVALID_POINTER) {
err = device->hal_info.hw_open(device->hal_info.user_data);
if (err != API_CMS_ERROR_OK) {
return API_CMS_ERROR_HW_OPEN;
}
}
return API_CMS_ERROR_OK;
}
int32_t hmc7044_hw_close(adi_hmc7044_device_t *device)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (device->hal_info.hw_close != ADI_INVALID_POINTER) {
err = device->hal_info.hw_close(device->hal_info.user_data);
if (err != API_CMS_ERROR_OK) {
return API_CMS_ERROR_HW_CLOSE;
}
}
return API_CMS_ERROR_OK;
}
int32_t hmc7044_sw_delay_us(adi_hmc7044_device_t *device, uint32_t us)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (device->hal_info.delay_us == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_DELAYUS_PTR;
}
err = device->hal_info.delay_us(device->hal_info.user_data, us);
if (err != API_CMS_ERROR_OK ) {
return API_CMS_ERROR_DELAY_US;
}
return API_CMS_ERROR_OK;
}
int32_t hmc7044_hw_reset(adi_hmc7044_device_t *device)
{
int32_t err;
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (device->hal_info.reset_pin_ctrl == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_RESET_CTRL_PTR;
}
if (device->hal_info.delay_us == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_DELAYUS_PTR;
}
err = device->hal_info.reset_pin_ctrl(device->hal_info.user_data, 0x1);
if (err != API_CMS_ERROR_OK) {
return API_CMS_ERROR_RESET_PIN_CTRL;
}
err = hmc7044_sw_delay_us(device, HMC7044_HW_RESET_PERIOD_US);
if (err != API_CMS_ERROR_OK) {
return err;
}
err = device->hal_info.reset_pin_ctrl(device->hal_info.user_data, 0x0);
if (err != API_CMS_ERROR_OK) {
return API_CMS_ERROR_RESET_PIN_CTRL;
}
return API_CMS_ERROR_OK;
}
int32_t hmc7044_spi_reg_get(adi_hmc7044_device_t *device , uint32_t reg, uint8_t *data)
{
int32_t err;
uint8_t in_data[SPI_IN_OUT_BUFF_SZ] = {0};
uint8_t out_data[SPI_IN_OUT_BUFF_SZ] = {0};
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (device->hal_info.spi_xfer == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_XFER_PTR;
}
if (data == ADI_INVALID_POINTER) {
return API_CMS_ERROR_NULL_PARAM;
}
in_data[0] = (((reg >> 8) & 0x1F) | 0x80);
in_data[1] = (reg & 0xFF);
err = device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, SPI_IN_OUT_BUFF_SZ);
if (err != API_CMS_ERROR_OK) {
return API_CMS_ERROR_SPI_XFER;
}
*data = out_data[2];
return API_CMS_ERROR_OK;
}
int32_t hmc7044_spi_reg_set(adi_hmc7044_device_t *device, uint32_t reg, uint8_t data)
{
int32_t err;
uint8_t in_data[SPI_IN_OUT_BUFF_SZ] = {0};
uint8_t out_data[SPI_IN_OUT_BUFF_SZ] = {0};
if (device == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_HANDLE_PTR;
}
if (device->hal_info.spi_xfer == ADI_INVALID_POINTER) {
return API_CMS_ERROR_INVALID_XFER_PTR;
}
in_data[0] = ((reg >> 8) & 0x1F);
in_data[1] = (reg & 0xFF);
in_data[2] = data;
err = device->hal_info.spi_xfer(device->hal_info.user_data, in_data, out_data, SPI_IN_OUT_BUFF_SZ);
if (err != API_CMS_ERROR_OK) {
return API_CMS_ERROR_SPI_XFER;
}
return API_CMS_ERROR_OK;
}
int32_t hmc7044_spi_reg_block_get(adi_hmc7044_device_t *device,
const uint16_t address, uint8_t *data, uint32_t count)
{
int err;
uint16_t i =0;
for (i = 0; i<count; i++) {
err = hmc7044_spi_reg_get(device, (address + i), &data[i]);
if (err != API_CMS_ERROR_OK) {
return err;
}
}
return API_CMS_ERROR_OK;
}
int32_t hmc7044_spi_reg_tbl_set(adi_hmc7044_device_t *device,
adi_cms_reg_data_t *tbl, uint32_t count)
{
uint16_t i =0;
int err;
for (i = 0; i<count; i++) {
err = hmc7044_spi_reg_set(device, tbl[i].reg, tbl[i].val);
if (err != API_CMS_ERROR_OK) {
return err;
}
}
return API_CMS_ERROR_OK;
}
uint64_t gcd(uint64_t value1, uint64_t value2)
{
uint64_t maxvalue;
while (value1 != 0 && value2 != 0) {
if (value1 > value2){
value1 %= value2;
}
else {
value2 %= value1;
}
}
maxvalue = value1 > value2 ? value1 : value2;
return maxvalue;
}
uint64_t lcm(uint64_t value1, uint64_t value2)
{
if (value1 == 0 && value2 == 0) {
return 0;
}
else {
return (value1 * value2) / gcd(value1, value2);
}
}
/*! @} */

217
vitis/radar/src/lscript.ld Executable file
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@@ -0,0 +1,217 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: 2018.3 */
/* */
/* Copyright (c) 2010-2019 Xilinx, Inc. All rights reserved. */
/* */
/* Description : MicroBlaze Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x8000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8000;
/* Define Memories in the system */
MEMORY
{
microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem : ORIGIN = 0x50, LENGTH = 0x7FB0
ddr4_0_C0_DDR4_MEMORY_MAP_BASEADDR_C0_DDR4_ADDRESS_BLOCK : ORIGIN = 0x80000000, LENGTH = 0x80000000
}
/* Specify the default entry point to the program */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
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KEEP (*(.vectors.reset))
}
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*(.got2)
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.eh_frame : {
*(.eh_frame)
} > ddr4_0_C0_DDR4_MEMORY_MAP_BASEADDR_C0_DDR4_ADDRESS_BLOCK
.jcr : {
*(.jcr)
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/* Generate Stack and Heap definitions */
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_end = .;
}

161
vitis/radar/src/main.c Executable file
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@@ -0,0 +1,161 @@
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
//#include "xscugic.h"
#include "xsysmon.h"
#include "xspi.h"
#include "project.h"
#include "ethernet.h"
#include "pl_udp_eth.h"
#include "hmc7044.h"
#include "ad9081_hal_functions.h"
#include "ad9081_app_helper.h"
#include "adi_ad9081.h"
#include "adi_hmc7044.h"
#include "novatel.h"
XSysMon SysMonInst;
//extern XScuGic xInterruptController;
void set_fan_pwm(int percent) {
// Set Fan PWM
// Don't try to turn on fan unless percent is above a certain value, fan has minimum turn on percent
int period = 1500000;
int pw = period * percent / 100;
Xil_Out32(0x40050010, period);
Xil_Out32(0x40050014, pw);
}
void update_fan_speed(int fpga_temp) {
int min_temp = 30;
int max_temp = 60;
int delta_temp = max_temp - min_temp;
int min_percent = 50;
int percent = 0;
int temp = fpga_temp - min_temp;
if (temp < 0) {
temp = 0;
set_fan_pwm(0);
}
else {
percent = temp * 100 / delta_temp;
if (percent < min_percent) {
percent = min_percent;
}
set_fan_pwm(percent);
}
// xil_printf("Temp - %d, Fan Percent - %d\r\n", fpga_temp, percent);
}
int setBit(uint32_t addr, uint32_t bit) {
int val = Xil_In32(addr);
val |= (1 << bit);
Xil_Out32(addr, val);
return 0;
}
int clearBit(uint32_t addr, uint32_t bit) {
int val = Xil_In32(addr);
val &= ~(1 << bit);
Xil_Out32(addr, val);
return 0;
}
int toggleBit(uint32_t addr, uint32_t bit) {
int val = Xil_In32(addr);
uint32_t current_bit = val & (1 << bit);
if (current_bit) {
val &= ~(1 << bit);
} else {
val |= (1 << bit);
}
Xil_Out32(addr, val);
return 0;
}
void error_print(int line_number, int err) {
xil_printf("Line %d, Error! %d\r\n", line_number, err);
vTaskDelay(1000);
}
void status_task( void *pvParameters ) {
XSysMon_Config *ConfigPtr;
XSysMon *SysMonInstPtr = &SysMonInst;
// Initialize the SysMon driver.
ConfigPtr = XSysMon_LookupConfig(XPAR_SYSMON_0_DEVICE_ID);
XSysMon_CfgInitialize(SysMonInstPtr, ConfigPtr,
ConfigPtr->BaseAddress);
XSysMon_SelfTest(SysMonInstPtr);
while (1) {
u16 temp_data = XSysMon_GetAdcData(SysMonInstPtr, XSM_CH_TEMP);
int fpga_temp = XSysMon_RawToTemperature(temp_data);
update_fan_speed(fpga_temp);
vTaskDelay(100);
}
}
static void pps_irq_handler(u32 context) {
xil_printf("pps irq %lu\r\n", utc_time);
Xil_Out32(TIMING_ENGINE_ADDR + 0x14, utc_time + 1);
}
void main_task( void *pvParameters ) {
// Connect PPS Interrupt
xPortInstallInterruptHandler(XPAR_MICROBLAZE_0_AXI_INTC_SYSTEM_PPS_INTR, (XInterruptHandler) pps_irq_handler, (void *)0);
vPortEnableInterrupt(XPAR_MICROBLAZE_0_AXI_INTC_SYSTEM_PPS_INTR);
setup_data_converter();
while (1) {
toggleBit(0x40050008, 0); // Toggle LED
}
}
int main(void) {
xil_printf("\n\r\n\r================= Start ====================\n\r\n\r");
Xil_Out32(0x40050008, 0x11);
xTaskCreate( status_task,
( const char * ) "status",
0x1000,
NULL,
TASK_PRIORITY_STATUS,
NULL );
xTaskCreate( main_task,
( const char * ) "main",
0x10000,
NULL,
TASK_PRIORITY_MAIN,
NULL );
#ifndef IBERT_TESTING
xTaskCreate( pl_udp_task,
( const char * ) "pludp",
0x8000,
NULL,
TASK_PRIORITY_MAIN,
NULL );
#endif
// This is the thread that hosts lwip. It must be created using sys_thread_new
sys_thread_new("tcp_server_task", (void(*)(void*))tcp_server_task, 0,
1024,
TASK_PRIORITY_LWIP);
/* Start the tasks and timer running. */
vTaskStartScheduler();
return 0;
}

1048
vitis/radar/src/main.c.backup Executable file
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120
vitis/radar/src/novatel.c Executable file
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#include "netif/xadapter.h"
#include "lwipopts.h"
#include "lwip/init.h"
#include "lwip/inet.h"
#include "lwip/tcp.h"
#include "lwip/ip_addr.h"
#include "lwip/sockets.h"
#include "lwip/sys.h"
#include "project.h"
#include "radar_manager_icd.h"
#include "novatel.h"
#define BUF_SIZE 1024
#define PWRPAK_PORT 3003
uint32_t utc_time;
void novatel_task()
{
int sockfd;
if ((sockfd = socket(AF_INET, SOCK_DGRAM, 0)) < 0)
{
xil_printf("Socket creation error\n");
}
struct timeval tv;
tv.tv_sec = 2;
tv.tv_usec = 0;
setsockopt(sockfd, SOL_SOCKET, SO_RCVTIMEO, (const char*)&tv, sizeof tv);
struct sockaddr_in serv_addr;
serv_addr.sin_family = AF_INET;
serv_addr.sin_port = htons(PWRPAK_PORT);
inet_pton(AF_INET, "0.0.0.0", &serv_addr.sin_addr);
if (bind(sockfd, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) == -1) {
xil_printf("Bind Failed\r\n");
}
xil_printf("Novatel Socket Opened\r\n");
static uint8_t buffer[BUF_SIZE];
NovatelLogShortHdrType * short_hdr = (NovatelLogShortHdrType *)buffer;
NovatelLogHdrType * long_hdr = (NovatelLogHdrType *)buffer;
int n;
socklen_t len;
struct sockaddr_in servaddr;
while (1) {
n = recvfrom(sockfd, buffer, BUF_SIZE, 0, (struct sockaddr *) &servaddr, &len);
if (n < 0) {
if (errno == EAGAIN) {
// This was just a timeout
continue;
}
xil_printf("Socket Read Error %d\n", errno);
}
int msg_length = 0;
if (short_hdr->sync == 0x1244aa) {
// This is a long header
// xil_printf("long ");
msg_length = long_hdr->msg_length;
}
else if (short_hdr->sync == 0x1344aa) {
// This is a short header
// xil_printf("short ");
msg_length = short_hdr->msg_length;
}
else {
xil_printf("Bad Header Sync, 0x%x\r\n", short_hdr->sync);
continue;
}
// xil_printf("PwrPak Msg ID - %d, length %d, %d, %d\r\n", short_hdr->msg_id, msg_length, sizeof(NovatelInspvasType), sizeof(NovatelTimeType));
if (n >= (msg_length + 16)) {
switch (short_hdr->msg_id)
{
case PWRPAK_MSG_ID_TIME:
{
NovatelTimeType * msg = (NovatelTimeType *)buffer;
// printf("GPS Week %d\r\n", msg->hdr.week);
// printf("GPS ms %lu\r\n", msg->hdr.ms);
// printf("offset %f\r\n", msg->offset);
// printf("offset_std_dev %f\r\n", msg->offset_std_dev);
// printf("utc_offset %f\r\n", msg->utc_offset);
uint32_t gps_sec = (msg->hdr.week * 7 * 24 * 60 * 60) + (msg->hdr.ms / 1000);
uint32_t utc_sec = gps_sec + 315964800 + msg->utc_offset;
utc_time = utc_sec;
xil_printf("gps_week %lu\r\n", msg->hdr.week);
xil_printf("gps_ms %lu\r\n", msg->hdr.ms);
xil_printf("utc_time %lu\r\n", utc_sec);
}
break;
case PWRPAK_MSG_ID_INSPVAS:
{
NovatelInspvasType * msg = (NovatelInspvasType *)buffer;
}
break;
default:
xil_printf("Unhandled PwrPak Msg ID - %d\r\n", short_hdr->msg_id);
break;
}
}
}
}

83
vitis/radar/src/novatel.h Executable file
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@@ -0,0 +1,83 @@
#ifndef NOVATEL_H /* prevent circular inclusions */
#define NOVATEL_H /* by using protection macros */
void novatel_task();
extern uint32_t utc_time;
#define PWRPAK_MSG_ID_TIME 101
#define PWRPAK_MSG_ID_INSPVAS 508
#pragma pack(push, 1)
typedef struct {
uint32_t sync : 24;
uint32_t hdr_length : 8;
uint16_t msg_id;
uint8_t msg_type;
uint8_t port_addr;
uint16_t msg_length;
uint16_t sequence;
uint8_t idle_time;
uint8_t time_status;
uint16_t week;
uint32_t ms;
uint32_t reciver_status;
uint16_t reserved;
uint16_t receiver_sw_version;
} NovatelLogHdrType;
typedef struct {
uint32_t sync : 24;
uint8_t msg_length;
uint16_t msg_id;
uint16_t week;
uint32_t ms;
} NovatelLogShortHdrType;
typedef struct {
NovatelLogShortHdrType hdr;
uint32_t ins_status;
uint32_t pos_type;
double lla[3];
float undulation;
double vel_neu[3];
double att[3];
float sig_lla[3];
float sig_vel[3];
float sig_att[3];
uint32_t ext_sol_status;
uint16_t time_since_update;
uint32_t crc;
} NovatelInspvaxType;
typedef struct {
NovatelLogShortHdrType hdr;
uint32_t week;
double seconds;
double lla[3];
double vel_neu[3];
double rpy[3];
uint32_t status;
uint32_t crc;
} NovatelInspvasType;
typedef struct {
NovatelLogHdrType hdr;
uint32_t clock_status;
double offset;
double offset_std_dev;
double utc_offset;
uint32_t utc_year;
uint8_t utc_month;
uint8_t utc_day;
uint8_t utc_hour;
uint8_t utc_min;
uint32_t utc_ms;
uint32_t utc_status;
uint32_t crc;
} NovatelTimeType;
#pragma pack(pop)
#endif /* end of protection macro */

142
vitis/radar/src/pl_udp_eth.c Executable file
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@@ -0,0 +1,142 @@
#include "FreeRTOS.h"
#include "task.h"
#include "xil_io.h"
#include "xstatus.h"
#include "xllfifo.h"
#include "pl_udp_eth.h"
#include "project.h"
static XLlFifo FifoInstance;
static unsigned char msg[MAX_MSG_LENGTH];
uint32_t pl_udp_init()
{
XLlFifo_Config *Config;
int Status;
Status = XST_SUCCESS;
/* Initialize the Device Configuration Interface driver */
Config = XLlFfio_LookupConfig(XPAR_AXI_FIFO_0_DEVICE_ID);
if (!Config) {
xil_printf("No config found for %d\r\n", XPAR_AXI_FIFO_0_DEVICE_ID);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XLlFifo_CfgInitialize(&FifoInstance, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Reset value */
Status = XLlFifo_Status(&FifoInstance);
XLlFifo_IntClear(&FifoInstance, 0xffffffff);
Status = XLlFifo_Status(&FifoInstance);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(&FifoInstance));
return XST_FAILURE;
}
return Status;
}
uint32_t pl_udp_getMsg(unsigned char *msg, int *length)
{
int i;
int ret;
u32 RxWord;
static u32 ReceiveLength;
u32 * msg_as_int = (u32*)msg;
u32 ind = 0;
ret = XST_NO_DATA;
while(XLlFifo_iRxOccupancy(&FifoInstance)) {
/* Read Receive Length */
ReceiveLength = XLlFifo_iRxGetLen(&FifoInstance) / 4;
xil_printf("PL UDP RX, %d, %d \n\r", XLlFifo_iRxOccupancy(&FifoInstance), ReceiveLength);
for (i=0; i < ReceiveLength; i++) {
RxWord = XLlFifo_RxGetWord(&FifoInstance);
msg_as_int[ind] = RxWord;
ind++;
}
ret = XST_SUCCESS;
}
*length = ind * 4;
return ret;
}
uint32_t pl_udp_sendMsg(unsigned char *msg, int length)
{
u32 udp_packet_size = 512;
u32 length_int = udp_packet_size >> 2;
u32 * msg_as_int = (u32*)msg;
u32 num_packets = length / udp_packet_size;
if (length % udp_packet_size) {
num_packets++;
}
// xil_printf(" Transmitting Data, Num Bytes - %d, Num Packets - %d\r\n", length, num_packets);
u32 ind = 0;
for (int i=0 ; i < num_packets ; i++){
/* Writing into the FIFO Transmit Port Buffer */
for (int j=0 ; j < length_int ; j++){
if( XLlFifo_iTxVacancy(&FifoInstance) ){
XLlFifo_TxPutWord(&FifoInstance, msg_as_int[ind]);
ind++;
}
}
/* Start Transmission by writing transmission length into the TLR */
XLlFifo_iTxSetLen(&FifoInstance, udp_packet_size);
/* Check for Transmission completion */
while( !(XLlFifo_IsTxDone(&FifoInstance)) ){
}
}
// xil_printf(" Done \r\n");
return XST_SUCCESS;
}
void pl_udp_task( void *pvParameters ) {
// Reset Ethernet
setBit(0x40050008, 15);
vTaskDelay(1);
clearBit(0x40050008, 15);
pl_udp_init();
int length;
while (1) {
if (pl_udp_getMsg(msg, &length) == XST_SUCCESS) {
// Looping back so hping will work, can do something more interesting
// with this later
pl_udp_sendMsg(msg, length);
} else {
vTaskDelay(0);
}
}
}

11
vitis/radar/src/pl_udp_eth.h Executable file
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@@ -0,0 +1,11 @@
#ifndef PL_UDP_ETH_H /* prevent circular inclusions */
#define PL_UDP_ETH_H /* by using protection macros */
#define MAX_MSG_LENGTH 2048
uint32_t pl_udp_init();
uint32_t pl_udp_getMsg(unsigned char *msg, int *length);
uint32_t pl_udp_sendMsg(unsigned char *msg, int length);
void pl_udp_task( void *pvParameters );
#endif /* end of protection macro */

83
vitis/radar/src/project.h Executable file
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@@ -0,0 +1,83 @@
#ifndef __PROJECT_H__
#define __PROJECT_H__
#include "registers.h"
#include "adi_ad9081.h"
//#define IBERT_TESTING
// Higher values are higher priority
#define TASK_PRIORITY_MAIN (tskIDLE_PRIORITY + 2)
#define TASK_PRIORITY_STATUS (tskIDLE_PRIORITY + 2)
#define TASK_PRIORITY_ETH_RX (tskIDLE_PRIORITY + 2)
#define TASK_PRIORITY_LWIP (tskIDLE_PRIORITY + 2)
#define TICK_RATE 100.0
#define TICK_PERIOD (1 / TICK_RATE)
#define TICK_PERIOD_US (TICK_PERIOD * 1e6)
#define DEBUG_ENABLE
#ifdef DEBUG_ENABLE
#define DEBUG_PRINT xil_printf
#else
#define DEBUG_PRINT
#endif
int setBit(uint32_t addr, uint32_t bit);
int clearBit(uint32_t addr, uint32_t bit);
int toggleBit(uint32_t addr, uint32_t bit);
void error_print(int line_number, int err);
void setup_data_converter();
extern adi_ad9081_device_t * ad9081_dev_ptr;
// register addresses from pg242
#define JESD_RX XPAR_JESD_JESD204C_0_BASEADDR
#define JESD_TX XPAR_JESD_JESD204C_1_BASEADDR
#define VERSION_REG 0x000
#define RESET_REG 0x020
#define RESET_ON 0x1
#define RESET_OFF 0x0
#define CTRL_ENABLE_REG 0x024
#define DISABLE_DATA_CMD 0x0
#define ENABLE_CMD 0x1
#define ENABLE_DATA 0x2
#define ENABLE_DATA_CMD 0x3
#define CTRL_MB_IN_EMB 0x30
#define CTRL_META_MODE 0x038
#define ENABLE_CRC12_MODE 0x0
#define ENABLE_CRC3_MODE 0x1
#define ENABLE_CMD_MODE 0x2
#define ENABLE_FEC_MODE 0x3
#define CTRL_RX_BUF_ADV 0x44
#define CTRL_SYSREF 0x050
#define STAT_STATUS_REG 0x060
#define STATUS_IRQ_PEND_BIT 1
#define STATUS_SYSREF_CAP_BIT 2
#define STATUS_SYSREF_ERR_BIT 4
#define STATUS_SH_LOCK_BIT 16
#define STATUS_EMB_LOCK_BIT 32
#define STATUS_BUFF_OVERR_BIT 1024
#define STAT_RX_BUF_LVL0 0x400
#define STAT_RX_BUF_LVL1 0x480
#define STAT_RX_BUF_LVL2 0x500
#define STAT_RX_BUF_LVL3 0x580
#define STAT_RX_BUF_LVL4 0x600
#define STAT_RX_BUF_LVL5 0x680
#define STAT_RX_BUF_LVL6 0x700
#define STAT_RX_BUF_LVL7 0x780
int32_t rf_spi_write(int dev_sel, int num_bits, int data);
#endif

157
vitis/radar/src/radar_manager_icd.c Executable file
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/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "project.h"
#include "radar_manager_icd.h"
#include "ethernet.h"
void radar_manager_get_message( unsigned char * recv_buf, int n, unsigned char * msg, int * msg_ind, int * header_found)
{
headerType *header;
header = (headerType *)msg;
for(int i = 0; i < n; i++)
{
// Copy Byte Into Message Buffer
msg[*msg_ind] = recv_buf[i];
(*msg_ind)++;
if (*header_found == 0)
{
if (*msg_ind == sizeof(headerType))
{
// Check for valid header
if (header->fsync == FSYNC)
{
// Mark that we have found a header
*header_found = 1;
}
else
{
// Shift bytes to front of buffer until a header is found
for (int j = 0; j < sizeof(headerType)-1; j++)
{
msg[j] = msg[j+1];
}
(*msg_ind)--;
}
}
}
if( (*header_found != 0) && (*msg_ind == header->length) )
{
// We now have a complete message, pass it to the message handling function.
// DEBUG_PRINT("Got Msg 0x%04X\r\n", header->type);
radar_manager_parse_message(msg);
// Reset State
*header_found = 0;
*msg_ind = 0;
}
}
}
void send_data(unsigned char * data, int size)
{
// uart_SendMessage(data, size);
eth_sendMessage(data, size);
}
void send_ack(unsigned int flags)
{
ackType resp;
// Form the header
resp.header.fsync = FSYNC;
resp.header.type = ACK_MSG;
resp.header.length = sizeof(resp);
// Set the data
resp.flags = flags;
// Send the message
send_data((u8 *)&resp, sizeof(resp));
}
void radar_manager_parse_message(u8 * msgBuffer)
{
headerType *header;
header = (headerType *)msgBuffer;
// DEBUG_PRINT("Parse Msg 0x%04X\r\n", header->type);
switch (header->type)
{
case AXI_WRITE_REG:
{
writeRegType *msg = (writeRegType *)msgBuffer;
// DEBUG_PRINT("Write Reg 0x%08X, %d\r\n", msg->addr, msg->data);
Xil_Out32(msg->addr, msg->data);
}
break;
case AXI_WRITE_REG_BURST:
{
writeRegBurstType *msg = (writeRegBurstType *)msgBuffer;
// DEBUG_PRINT("Write Reg 0x%08X, %d\r\n", msg->addr, msg->data);
for (int i = 0; i < msg->length; i++) {
Xil_Out32(msg->addr + i * 4, msg->data[i]);
}
}
break;
case AXI_READ_REG:
{
readRegType *msg = (readRegType *)msgBuffer;
readRespType resp;
resp.header.fsync = FSYNC;
resp.header.type = AXI_READ_RESP;
resp.header.length = sizeof(resp);
resp.data = Xil_In32(msg->addr);
// DEBUG_PRINT("Read Reg 0x%08X, %d\r\n", msg->addr, resp.data);
send_data((u8 *)&resp, sizeof(resp));
}
break;
case SET_AD9081_DAC_NCO:
{
ncoConfigType *msg = (ncoConfigType *)msgBuffer;
xil_printf("Set DAC NCO, Ch %d, Freq %d\r\n", msg->channel, (int)msg->frequency);
adi_ad9081_dac_duc_nco_set(ad9081_dev_ptr, AD9081_DAC_0 << msg->channel, AD9081_DAC_CH_NONE, msg->frequency);
}
break;
case SET_AD9081_ADC_NCO:
{
ncoConfigType *msg = (ncoConfigType *)msgBuffer;
xil_printf("Set ADC NCO, Ch %d, Freq %d\r\n", msg->channel, (int)msg->frequency);
adi_ad9081_adc_ddc_coarse_nco_set(ad9081_dev_ptr, AD9081_ADC_CDDC_0 << msg->channel, msg->frequency);
}
break;
case RF_SPI_WRITE:
{
rfSpiWriteType *msg = (rfSpiWriteType *)msgBuffer;
rf_spi_write(msg->dev_sel, msg->num_bits, msg->data);
}
break;
default:
DEBUG_PRINT("Unknown Type 0x%04X!\r\n", header->type);
break;
}
if ((header->flags & HDR_FLAG_REQ_ACK) > 0)
{
// A completion ACK had been requested
// DEBUG_PRINT("Send Ack 0x%04X\r\n", header->type);
send_ack(ACK_VALID_PACKET | ACK_VALID_EXECUTION);
}
}

87
vitis/radar/src/radar_manager_icd.h Executable file
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@@ -0,0 +1,87 @@
#ifndef RADAR_MANAGER_ICD_H /* prevent circular inclusions */
#define RADAR_MANAGER_ICD_H /* by using protection macros */
#define MAX_MSG_LENGTH 8192
#define MSG_TIMEOUT 2000
void radar_manager_get_message( unsigned char * recv_buf, int n, unsigned char * msgBuffer, int * msg_ind, int * header_found);
void radar_manager_parse_message(u8 * msgBuffer);
#define FSYNC 0xAABBCCDD
#define AXI_WRITE_REG 1
#define AXI_READ_REG 2
#define AXI_READ_RESP 3
#define ACK_MSG 4
#define NACK_MSG 5
#define AXI_WRITE_REG_BURST 6
#define RF_SPI_WRITE 7
#define SET_AD9081_DAC_NCO 128
#define SET_AD9081_ADC_NCO 129
#define HDR_FLAG_REQ_ACK 0x01
#define ACK_VALID_PACKET 0x01
#define ACK_VALID_EXECUTION 0x02
#pragma pack(push, 1)
typedef struct {
unsigned int fsync;
unsigned short type;
unsigned short flags;
unsigned short length;
} headerType;
typedef struct {
headerType header;
unsigned int flags;
} ackType;
typedef struct {
headerType header;
unsigned int addr;
unsigned int data;
} writeRegType;
typedef struct {
headerType header;
unsigned int addr;
unsigned int length;
unsigned int data[512];
} writeRegBurstType;
typedef struct {
headerType header;
unsigned int addr;
} readRegType;
typedef struct {
headerType header;
unsigned int data;
} readRespType;
typedef struct {
headerType header;
unsigned int channel;
float frequency;
} ncoConfigType;
typedef struct {
headerType header;
unsigned int dev_sel;
unsigned int num_bits;
unsigned int data;
} rfSpiWriteType;
//typedef struct {
// uint32_t num_pulses;
// uint32_t num_pulses;
// uint32_t num_pulses;
// uint32_t num_pulses;
// uint32_t num_pulses;
// uint32_t num_pulses;
//} configCpiType;
#pragma pack(pop)
#endif /* end of protection macro */

12
vitis/radar/src/registers.h Executable file
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@@ -0,0 +1,12 @@
#ifndef __REGISTERS_H__
#define __REGISTERS_H__
#define UTIL_ADDR 0x40050000
#define TIMING_ENGINE_ADDR 0x40051000
#define DIG_RX_ADDR 0x20000000
#define DIG_RX_STRIDE 0x10000
#define WAVEFORM_GEN_ADDR 0x40053000
#endif

40
vitis/radar/src/rf_spi.c Executable file
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@@ -0,0 +1,40 @@
#include <stdarg.h>
#include <stdio.h>
#include "FreeRTOS.h"
#include "task.h"
#include "project.h"
#define NUM_BITS_ADDR (UTIL_ADDR + 0x100)
#define DEV_SEL_ADDR (UTIL_ADDR + 0x104)
#define SPI_DATA_ADDR (UTIL_ADDR + 0x108)
#define SPI_CLK_DIV_ADDR (UTIL_ADDR + 0x10C)
#define SPI_ACTIVE_ADDR (UTIL_ADDR + 0x110)
#define SPI_CLK_DIV 16
uint32_t reverse_bits(int num_bits, uint32_t data) {
uint32_t result = 0;
for (int i = 0; i < num_bits; i++) {
result |= ((data >> i) & 1) << (num_bits - 1 - i);
}
return result;
}
int32_t rf_spi_write(int dev_sel, int num_bits, int data) {
uint32_t bit_reversed = reverse_bits(num_bits, data);
Xil_Out32(DEV_SEL_ADDR, dev_sel);
Xil_Out32(SPI_CLK_DIV_ADDR, SPI_CLK_DIV);
Xil_Out32(SPI_DATA_ADDR, bit_reversed);
// Writing this reg starts the transaction
Xil_Out32(NUM_BITS_ADDR, num_bits - 1);
// Poll to wait for transcation to complete
while (Xil_In32(SPI_ACTIVE_ADDR)) {
// Wait
}
return 0;
}

273
vitis/radar/src/uc_settings.c Executable file
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@@ -0,0 +1,273 @@
/*!
* @brief Use Case Settings
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __ADI_AD9081_APP__
* @{
*/
/******************************************************
The AD9081/AD9082/AD9988/AD9986 standalone application use-case Settings holds the AD9081/AD9082/AD9988/AD9986 configuration parameters of a number of modes of operation or "usecase" for the ad9081.
Currently the Standalone App is QA'd with 20+ usecases that. These are usecases that the AD9081/AD9082/AD9988/AD9986 ADI evaluation platforms can support and can be used as a reference to<74>
build a usecase parameters for a custom application.
*/
/*============= I N C L U D E S ============*/
#include <stdio.h>
#include <unistd.h>
#include "adi_ad9081.h"
/*============= D A T A ====================*/
/* Usecase Frequency Scheme Settings
* This array list the desired clocks required for the usecase.
* For each usecase an array of depth 4 provides the frequecy in Hz for the following clocks
* As this application targets the Txfe/MxFE evaluation board, that my have various XTAL as reference to the HMC7044.
* The comments following the usecase entry will indicate if the scheme can be used with the target hardware.
* The Comments also provide the expected lane rate of the usecase.
* clk_hz["usecase"][0] Txfe/MxFE Device reference Clock (dev_ref), if not using on chip pll, this should be equal to the dac_clk
* clk_hz["usecase"][1] The value of the reference clock to the ADS9 FPGA JESD Blocks, This is not used by MxFE/TxFE API. (204C lane rate/66) or (204B lane rate/20)
* clk_hz["usecase"][2] The MxFE TX data path DAC sampling clock (dac_clk) as per the desired usecase
* clk_hz["usecase"][3] The MxFE Rx data path ADC aampling clock (adc_clk) as per the desired usecase
* Notes:
* The Example Application will use adi_ad9081_device_clk_config_set to configure the MxFE/TxFE based on th dev_ref, dac_clk, and adc_clk.
* If the on-chip PLL feature of MxFe/Txfe is not required dev_ref and dac_clk should be set to the same value.
* If on chip PLL is required, then based on the applied dev_ref clock and the desired dac_clk the API will configure the onchip -pll appropriately
* The API will also configure the chip to generate the desired adc_clk based on the dac_clk.
*
*/
uint64_t clk_hz[][4] = {
/*dev_ref, fpga_ref, dac_clk, adc_clk */ /* UC, JESD, Crystal type, Lane rate, Comments */
// { 125e6, 275e6, 6000e6, 2000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
// { 125e6, 275e6, 8000e6, 4000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
// { 118.75e6, 237.5e6, 11400e6, 3800e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
{ 93.75e6, 187.5e6, 9000e6, 3000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
}; // 204B
#if !defined(AD9207_ID) && !defined(AD9209_ID)
/* TX DataPath Configuration Settings*/
/* DAC Crossbar Configuration
* Use this parameter to define Mapping from Map JRx Samples to DAC Channelizer to MAIN DAC Datapath
* For Modes that support Use Channel Interpolation > 1
* JRX Converter Samples are mapped to Channels Datapaths as follows:
* Note each AD9081_DAC_CH_X is made up of an IQ pair sample
* DUAL LINK | M | Default Channel Datapth Mapping (0-7)
* 0 | 2 | AD9081_DAC_CH_0
* 0 | 4 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1
* 0 | 6 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2
* 0 | 8 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3
* 0 | 12 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5
* 0 | 16 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
* 1 | 2 | Link 0: AD9081_DAC_CH_0 , Link1: AD9081_DAC_CH_4
* 1 | 4 | Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5
* 1 | 6 | Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1, AD9081_DAC_CH_3 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6
* 1 | 8 | Link 0:AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
* Each Main DAC Datapath may be a summation of the Channel datapaths. Use tx_dac_chan_xbar as follows to achieve that as described below.
* uint8_t tx_dac_chan_xbar[usecase][ORed List Channel (0-7) to be summed and mapped to DAC Datapath(0-3)]
* Each usecase has an Array of depth 4, each member value is the list of Channels to be mapped a Main DAC Datapath,
* where index 0 = DAC0, index 1 = DAC1 etc
* OR adi_ad9082_dac_channel_select_e enumerations to create the list
* For example: ad9081_dac_chan_xbar[0][0] =AD9081_DAC_CH_0 |AD9081_DAC_CH_1
* Map Channlizer 0 and Channelizer 1 to DAC 0
*
* For Modes that bypass Channel ie Channel Interpolation = 1 and Main DAC Interpolation > 1
* JRX Converter Samples are mapped by default to DAC Main Data apths as follows
* DUAL LINK | M | Default Main DAC Datapath Mapping (0-3) | DAC DP to DAC Mapping (0-3)
* 0 | 2 | AD9081_DAC_DP_0 | AD9081_DAC_DP_0 ->DAC 0
* 0 | 4 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1
* 0 | 6 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2
* 0 | 8 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2, AD9081_DAC_DP_3 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
* 1 | 2 | Link 0: AD9081_DAC_DP_0 , Link1: AD9081_DAC_DP_2 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_2 ->DAC 2
* 1 | 4 | Link 0: AD9081_DAC_DP_0,AD9081_DAC_DP_1 , Link1: AD9081_DAC_DP_2, AD9081_DAC_DP_3 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
* Each converter sample pair may be routed to an alternative Datapath. Use tx_dac_chan_xbar as follows to achieve that as described below.
*
* uint8_t tx_dac_chan_xbar[usecase][DAC Datapath(0-3) to be mapped to DAC (0-3)]
* Each usecase has an Array of depth 4, each member value is the DAC MAIN DP to be routed
* where index 0 = DAC0 index 1 = DAC1 etc
* For example: ad9081_dac_chan_xbar[0][1] =AD9081_DAC_DP _3
* DAC Datapath 3 is routed to DAC 1
*
*
*
*/
#define tx_if_freq 500e6
#define rx_if_freq 500e6
//#define if_freq 10e6
uint8_t tx_dac_chan_xbar[][4] = { /* dac0, dac1, dac2, dac3 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc13*/
// { AD9081_DAC_CH_0, AD9081_DAC_CH_1 }, /* uc13*/
};
int64_t tx_main_shift[][4] = { /* dac0, dac1, dac2, dac3 */
{ tx_if_freq, tx_if_freq, tx_if_freq, tx_if_freq }, /* uc13*/
};
int64_t tx_chan_shift[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
int8_t tx_chan_gain[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
uint8_t tx_interp[][2] = {
/* {main DUC Interpolation, Channelizer DUC Interpolation} */
{ 12, 1 }, /* uc13*/
// { 8, 1 }, /* uc13*/
};
#endif
/* RX Main Path DDC Enable Configuration */
/* MUX 0 & MUX 1 Settings
* List the ADC_Coarse DDCs to be mapped to logical ADCs
* OR<4F>adi_ad9082_adc_coarse_ddc_select_e enumerations to create the list
* Note all DDC are enabled for all use cases that configure main datapath.
* Deselect CDDCs and FDDCs to override default Mux3 settings and enable full bandwidth mode
*/
uint8_t rx_cddc_select[] = {
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
// AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1, /* uc13*/
};
/* RX Main Path DDC NCO Frequency Configuration
* List the ADC_Coarse DDCs desired Frequency Shift
* Each usecase has an Array of depth 4, each member value is the desired frequency shift (MHz)of a Coarse DDC Datapath,
* where index 0 = Frequency Shift for<6F> Coarse DDC 0, index 1 = Frequency Shift for<6F>Coarse DDC 1 etc
*
* For example: rx_cddc_shift[0][0] = 1842.5e6,
* For Use case 0, Frequency Shift for Coarse DDC0 is 1842.5e6MHz
*/
int64_t rx_cddc_shift[][4] = {
/* {cddc0, cddc1, cddc2, cddc3 }*/
{ rx_if_freq, rx_if_freq, rx_if_freq, rx_if_freq}, /* uc13*/
};
/* RX Main Path DDC Data Decimation
* List the ADC_Coarse DDCs desired data decimation
* Each usecase has an Array of depth 4, each member value is the desired decimation of a Coarse DDC Datapath,
* where index 0 = Decimation Factor for<6F> Coarse DDC 0, index 1 = decimation Factor for<6F>Coarse DDC 1 etc
*
* For example: rx_cddc_dcm[1][0] =AD9081_CDDC_DCM_2,
* For Use case 1, Frequency Factor for Coarse DDC0 is 1
* Use adi_ad9082_adc_coarse_ddc_dcm_e to set the decimation setting
*/
uint8_t rx_cddc_dcm[][4] = {
/*{cddc0, cddc1, cddc2, cddc3} */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
// { AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
};
/* RX Main Path DDC Has Optional Complex to Real Convertor
* rx_cddc_c2r sets the enable for Complex to Real Converter per Main/Coarse DDC
* Each usecase has an Array of depth 4, each member value is the enable of a Coarse DDC Datapath Complex to Real Converter
* where index 0 = Enable Complex to Real Convertor for Coarse DDC 0,
* index 1 = Enable Complex to Real Convertor for Coarse DDC 1
*
* For example: rx_cddc_c2r[1][0] = 0,
* For Use case 1, Complex to Real Converter for Coarse DDC 0 is Disabled
*
*/
uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
{ 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer/Fine DDC Datapath Selection
* List the ADC Fine DDCs data path for routing Data from Main/ Coarse DDC Datapth to the JESD Tx
* Each usecase has an Array of depth 1, each member value is the masked list of Fine DDCs to be selected
* Note Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC0- Fine DDC3 datapaths and
* Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC4- Fine DDC6 datapaths
* For example: rx_fddc_select[3] = AD9081_ADC_FDDC_0 |AD9081_ADC_FDDC_1,
* For Use case 3, Fine DDC 0 and Fine DDC 1 are enabled
* Use adi_ad9082_adc_fine_ddc_select_e to create the list of fine DDCs to be enabled
* Note: Based on the input from the user, will apply a recommended muxing from CDDC to FDDC,
* An Error will be returned if the muxing is not supported for that devices,
* Note: If Fine DDC Decimation Factor is set to 1, Fine DDC in the Channel will be disabled
*
*/
uint8_t rx_fddc_select[] = {
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
// AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc13*/
};
/* RX Channelizer Path DDC NCO Frequency Configuration
* List the ADC_Fine DDCs desired Frequency Shift
* Each usecase has an Array of depth 8, each member value is the desired frequency shift (MHz)of a Fine DDC Datapath,
* where index 0 = Frequency Shift for<6F> Fine DDC 0, index 1 = Frequency Shift for<6F>Fine DDC 1 etc
*
* For example: rx_fddc_shift[0][0] = 1842.5e6,
* For Use case 0, Frequency Shift for Fine DDC0 is 1842.5e6MHz
*/
int64_t rx_fddc_shift[][8] = {
/* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
/* RX Channelizer Data Decimation
* List the ADC Fine DDCs desired data decimation
* Each usecase has an Array of depth 8, each member value is the desired decimation of a Fine DDC Datapath,
* where index 0 = Decimation factor for<6F> Fine DDC 0, index 1 = decimation factor for<6F>Fine DDC 1 etc
* Note where No Fine DDC Decimation is required (bypassed), Decimation factor is set to 1,AD9081_FDDC_DCM_1
*
* For example: rx_fddc_dcm[1][0] =AD9081_FDDC_DCM_4,
* For Use case 1, Decimation Factor for FineDDC0 is 4
* Use adi_ad9082_adc_fine_ddc_dcm_e to set the decimation setting
*/
uint8_t rx_fddc_dcm[][8] = { /* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0 }, /* uc13*/
// { AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, 0, 0, 0, 0 }, /* uc13*/
};
uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
/* Link Settings */
/* Rx Channelizer Virtual Converter Mapping
* Maps the output of a Fine DDC Data Format O/P to a JESD TX virtual converter
* Refer to Mux 4 in the Rx Digital Datapath section of the System Developer Userguide
*
* adi_ad9082_adc_fine_ddc_converter_e enerates the Fine DCC I & Q Outputs
* Each virtual converter in the JESD TX link must be assigned a source data, Fine DDC X I or Q
* Note this should be set carefully and reflect the Fine DDC selected in rx_fddc_select and also JESD TX Configuration
*
* Each usecase has an Array of depth 2, each member a list of the source of data for the virtual converter for the JESD TX Link
* where index 0 = Sources of Data for JESD TX Link 0
* where index 1 = Sources of Data for JESD TX Link 1
*
* For example: For Use Case 29 with is a Dual link JESD Mode with M =4, we specify the I & Q source for each virtual Converter
* jtx_conv_sel[28][0]={AD9081_FDDC_0_I,AD9081_FDDC_0_Q,AD9081_FDDC_1_I,AD9081_FDDC_1_Q }
* jtx_conv_sel[28][1]={AD9081_FDDC_4_I,AD9081_FDDC_4_Q,AD9081_FDDC_5_I,AD9081_FDDC_5_Q }
*/
adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
// { { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc13.link0 */
};
/* Total Decimation Settings */
/* The total decimation is used to calculate lane rate for each link which in
* turn is used to determine FPGA clock sources and line rates for JESD204B
*
* Each usecase has an Array of depth 2,
* where index 0 = Total decimation for link 0
* where index 1 = Total decimation for link 1
*
* For example: For Use Case 3 with is a Dual link JESD Mode, total decimation for each link
* jtx_chip_dcm[3][0]= 8
* jtx_chip_dcm[3][1]= 8
*/
uint8_t jtx_chip_dcm[][2] = {
{ 4 }, /* uc13.link0 */
// { 4 }, /* uc13.link0 */
};
uint8_t jtx_logiclane_mapping_pe_brd[2][8] = { { 0, 1, 2, 3, 4, 5, 6, 7 }, { 4, 5, 6, 7, 0, 1, 2, 3 } };
uint8_t jtx_logiclane_mapping_ce_brd[2][8] = { { 6, 4, 3, 2, 1, 0, 7, 5 }, { 2, 0, 7, 7, 7, 7, 3, 1 } };
adi_cms_jesd_param_t jrx_param[] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
// { 8, 1, 4, 1, 0, 256, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 17 }, /* uc13: txmode = 378 */
};
adi_cms_jesd_param_t jtx_param[][2] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
// { { 8, 1, 4, 1, 0, 256, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 18, 0, 0 } }, /* uc13: rxmode = 227, link0 */
};

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/*!
* @brief Use Case Settings
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __ADI_AD9081_APP__
* @{
*/
/******************************************************
The AD9081/AD9082/AD9988/AD9986 standalone application use-case Settings holds the AD9081/AD9082/AD9988/AD9986 configuration parameters of a number of modes of operation or "usecase" for the ad9081.
Currently the Standalone App is QA'd with 20+ usecases that. These are usecases that the AD9081/AD9082/AD9988/AD9986 ADI evaluation platforms can support and can be used as a reference to<74>
build a usecase parameters for a custom application.
*/
/*============= I N C L U D E S ============*/
#include <stdio.h>
#include <unistd.h>
#include "adi_ad9081.h"
/*============= D A T A ====================*/
/* Usecase Frequency Scheme Settings
* This array list the desired clocks required for the usecase.
* For each usecase an array of depth 4 provides the frequecy in Hz for the following clocks
* As this application targets the Txfe/MxFE evaluation board, that my have various XTAL as reference to the HMC7044.
* The comments following the usecase entry will indicate if the scheme can be used with the target hardware.
* The Comments also provide the expected lane rate of the usecase.
* clk_hz["usecase"][0] Txfe/MxFE Device reference Clock (dev_ref), if not using on chip pll, this should be equal to the dac_clk
* clk_hz["usecase"][1] The value of the reference clock to the ADS9 FPGA JESD Blocks, This is not used by MxFE/TxFE API. (204C lane rate/66) or (204B lane rate/20)
* clk_hz["usecase"][2] The MxFE TX data path DAC sampling clock (dac_clk) as per the desired usecase
* clk_hz["usecase"][3] The MxFE Rx data path ADC aampling clock (adc_clk) as per the desired usecase
* Notes:
* The Example Application will use adi_ad9081_device_clk_config_set to configure the MxFE/TxFE based on th dev_ref, dac_clk, and adc_clk.
* If the on-chip PLL feature of MxFe/Txfe is not required dev_ref and dac_clk should be set to the same value.
* If on chip PLL is required, then based on the applied dev_ref clock and the desired dac_clk the API will configure the onchip -pll appropriately
* The API will also configure the chip to generate the desired adc_clk based on the dac_clk.
*
*/
uint64_t clk_hz[][4] = {
/*dev_ref, fpga_ref, dac_clk, adc_clk */ /* UC, JESD, Crystal type, Lane rate, Comments */
{ 122.88e6, 122.88e6, 5898.24e6, 2949.12e6 }, /* uc0, nco test */
{ 122.88e6, 737.28e6, 5898.24e6, 2949.12e6 }, /* uc1, 204B, 100MHz/122.88MHz 14.54560Gbps */
{ 122.88e6, 737.28e6, 8847.36e6, 2949.12e6 }, /* uc2, 204B, 100MHz/122.88MHz, 14.54560Gbps */
{ 122.88e6, 368.64e6, 5898.24e6, 2949.12e6 }, /* uc3, 204B, 100MHz/122.88MHz, 7.37280Gbps */
{ 122.88e6, 368.64e6, 8847.36e6, 2949.12e6 }, /* uc4, 204B, 100MHz/122.88MHz, 7.37280Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc5, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc6, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc7, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc8, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 122.88e6, 737.28e6, 5898.24e6, 2949.12e6 }, /* uc9, 204B, 100MHz/122.88MHz, 14.54560Gbps, 9082 rx FBW */
{ 122.88e6, 122.88e6, 5898.24e6, 1474.56e6 }, /* uc10, 204C, 100MHz/122.88MHz, 8.11008Gbps */
{ 11796.48e6,245.76e6,11796.48e6, 2949.12e6 }, /* uc11, 204C, Direct Clock, 16.22016Gbps Eye scan */
{ 122.88e6, 368.64e6, 11796.48e6, 2949.12e6 }, /* uc12, 204C, 100MHz/122.88MHz, 24.33024Gbps */
{ 125e6, 275e6, 12000e6, 4000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
{ 125e6, 375e6, 6000e6, 3000e6 }, /* uc14, 204C, 100MHz, 24.75000Gbps, 9081 rx FBW */
{ 122.88e6, 184.32e6, 7864.32e6, 3932.16e6 }, /* uc15, 204C, 100MHz/122.88MHz, 12.16512Gbps, 9082 rx FBW */
{ 5898.24e6,184.32e6, 5898.24e6, 2949.12e6 }, /* uc16, 204C, Direct Clock, 12.16512Gbps Eye scan */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc17, 204B, 100MHz/122.88MHz, 15.36000Gbps, tx only */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc18, 204B, 100MHz/122.88MHz, 15.36000Gbps, rx only */
{ 122.88e6, 245.76e6, 11796.48e6, 5898.24e6 }, /* uc19, 204C, 100MHz/122.88MHz, 16.22016Gbps, 9082/9986/9207 only */
{ 122.88e6, 368.64e6, 11796.48e6, 5898.24e6 }, /* uc20, 204C, 100MHz/122.88MHz, 24.33024Gbps 9082/9986/9207 only */
{ 122.88e6, 184.32e6, 5898.24e6, 2949.12e6 }, /* uc21, 204C, 100MHz/122.88MHz, 12.16512Gbps, subclass1 */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc22, 204C, 100MHz, 24.75000Gbps, rx only, 9081 rx FBW */
{ 125e6, 500e6, 12000e6, 4000e6 }, /* uc23, 204B, 100MHz, 10.00000Gbps */
{ 122.88e6, 491.52e6, 5898.24e6, 2949.12e6 }, /* uc24, 204B, 100MHz/122.88MHz, 9.83040Gbps */
{ 122.88e6, 368.64e6, 11796.48e6, 2949.12e6 }, /* uc25, 204C, 100MHz/122.88MHz, 24.33024Gbps */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc26, 204C, 100MHz, 24.75000Gbps, loopback, MCS */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc27, 204C, 100MHz, 24.75000Gbps, loopback, MCS */
{ 312.5e6, 625e6, 5000e6, 2500e6 }, /* uc28, 204B, 100MHz, 12.5000Gbps, tx only */
{ 312.5e6, 625e6, 5000e6, 2500e6 }, /* uc29, 204B, 100MHz, 12.5000Gbps, rx only */
{ 125e6, 375e6, 12000e6, 3000e6 }, /* uc30, 204C, 100MHz, 24.33024Gbps TPC MODE */
{ 3240e6, 202.5e6, 3240e6, 3240e6 }, /* uc31, 204C, Direct Clock Only 13.36500Gbps rx only */
{ 250e6, 250e6, 4000e6, 2000e6 }, /* uc32, 204C, 100MHz, 16.5, 9081 rx FBW */
{ 100e6, 400e6, 4800e6, 4800e6 }, /* uc33, 204B 100MHz, 8G/4G rx0/rx1 & 9082/9207 only */
{ 100e6, 400e6, 4800e6, 4800e6 }, /* uc34, 204B 100MHz, 8G/2G rx0/rx1 & 9082/9207 only */
{ 100e6, 400e6, 9600e6, 4800e6 }, /* uc35, 204B 100MHz, 8G/8G tx + rx & 9082/9207 only */
{ 100e6, 200e6, 4800e6, 2400e6 }, /* uc36, 204B 100MHz, 4G/4G tx + rx */
{ 100e6, 400e6, 3200e6, 1600e6 }, /* uc37, 204B 100MHz, 8G/4G tx + rx */
{ 100e6, 600e6, 4800e6, 2400e6 }, /* uc38, 204B 100MHz, 12G/3G,12G/6G tx0/rx0,tx1/rx1 */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc39, 204C, 100MHz, 24.75000Gbps, rx only, 9081 rx FBW */
{ 125e6, 250e6, 12000e6, 4000e6 }, /* uc40, 204C, 100MHz, 16.50000Gbps, txrx cap gate, subclass1 */
{ 125e6, 375e6, 12000e6, 3000e6 }, /* uc41, 204C, 100MHz, 24.75000Gbps, 9081 rx FBW ace uc */
};
#if !defined(AD9207_ID) && !defined(AD9209_ID)
/* TX DataPath Configuration Settings*/
/* DAC Crossbar Configuration
* Use this parameter to define Mapping from Map JRx Samples to DAC Channelizer to MAIN DAC Datapath
* For Modes that support Use Channel Interpolation > 1
* JRX Converter Samples are mapped to Channels Datapaths as follows:
* Note each AD9081_DAC_CH_X is made up of an IQ pair sample
* DUAL LINK | M | Default Channel Datapth Mapping (0-7)
* 0 | 2 | AD9081_DAC_CH_0
* 0 | 4 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1
* 0 | 6 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2
* 0 | 8 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3
* 0 | 12 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5
* 0 | 16 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
* 1 | 2 | Link 0: AD9081_DAC_CH_0 , Link1: AD9081_DAC_CH_4
* 1 | 4 | Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5
* 1 | 6 | Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1, AD9081_DAC_CH_3 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6
* 1 | 8 | Link 0:AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
* Each Main DAC Datapath may be a summation of the Channel datapaths. Use tx_dac_chan_xbar as follows to achieve that as described below.
* uint8_t tx_dac_chan_xbar[usecase][ORed List Channel (0-7) to be summed and mapped to DAC Datapath(0-3)]
* Each usecase has an Array of depth 4, each member value is the list of Channels to be mapped a Main DAC Datapath,
* where index 0 = DAC0, index 1 = DAC1 etc
* OR adi_ad9082_dac_channel_select_e enumerations to create the list
* For example: ad9081_dac_chan_xbar[0][0] =AD9081_DAC_CH_0 |AD9081_DAC_CH_1
* Map Channlizer 0 and Channelizer 1 to DAC 0
*
* For Modes that bypass Channel ie Channel Interpolation = 1 and Main DAC Interpolation > 1
* JRX Converter Samples are mapped by default to DAC Main Data apths as follows
* DUAL LINK | M | Default Main DAC Datapath Mapping (0-3) | DAC DP to DAC Mapping (0-3)
* 0 | 2 | AD9081_DAC_DP_0 | AD9081_DAC_DP_0 ->DAC 0
* 0 | 4 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1
* 0 | 6 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2
* 0 | 8 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2, AD9081_DAC_DP_3 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
* 1 | 2 | Link 0: AD9081_DAC_DP_0 , Link1: AD9081_DAC_DP_2 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_2 ->DAC 2
* 1 | 4 | Link 0: AD9081_DAC_DP_0,AD9081_DAC_DP_1 , Link1: AD9081_DAC_DP_2, AD9081_DAC_DP_3 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
* Each converter sample pair may be routed to an alternative Datapath. Use tx_dac_chan_xbar as follows to achieve that as described below.
*
* uint8_t tx_dac_chan_xbar[usecase][DAC Datapath(0-3) to be mapped to DAC (0-3)]
* Each usecase has an Array of depth 4, each member value is the DAC MAIN DP to be routed
* where index 0 = DAC0 index 1 = DAC1 etc
* For example: ad9081_dac_chan_xbar[0][1] =AD9081_DAC_DP _3
* DAC Datapath 3 is routed to DAC 1
*
*
*
*/
uint8_t tx_dac_chan_xbar[][4] = { /* dac0, dac1, dac2, dac3 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_0, AD9081_DAC_CH_0, AD9081_DAC_CH_0 }, /* uc0 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc1 */
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc2 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc3 */
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc4 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc5 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_1 }, /* uc6 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_3, AD9081_DAC_CH_2 }, /* uc7 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc8 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc9 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc10*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc11*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc12*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc13*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc14*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc15*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc16*/
{ AD9081_DAC_CH_2, AD9081_DAC_CH_0, AD9081_DAC_CH_3, AD9081_DAC_CH_1 }, /* uc17*/
{ 0 }, /* uc18*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc19*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc20*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc21*/
{ 0 }, /* uc22*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc23*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc24*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1 }, /* uc25*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc26*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc27*/
{ AD9081_DAC_CH_2, AD9081_DAC_CH_0, AD9081_DAC_CH_3, AD9081_DAC_CH_1 }, /* uc28*/
{ 0 }, /* uc29*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc30*/
{ 0 }, /* uc31*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc32*/
{ 0 }, /* uc33 */
{ 0 }, /* uc34 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc35 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc36 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc37 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1 }, /* uc38 */
{ 0 }, /* uc39*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc40*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc41*/
};
int64_t tx_main_shift[][4] = { /* dac0, dac1, dac2, dac3 */
{ 1000.00e6, 1000.00e6, 1000.00e6, 1000.00e6 }, /* uc0 */
{ 1842.50e6, 1842.50e6, 1842.50e6, 1842.50e6 }, /* uc1 */
{ 1991.25e6, 1991.25e6, 1991.25e6, 1991.25e6 }, /* uc2 */
{ 1842.50e6, 1842.50e6, 0, 0 }, /* uc3 */
{ 1991.25e6, 0, 0, 0 }, /* uc4 */
{ 672.00e6, 0, 0, 0 }, /* uc5 */
{ 396.00e6, 0, 0, 396.00e6 }, /* uc6 */
{ 396.00e6, 0, 0, 396.00e6 }, /* uc7 */
{ 672.00e6, 0, 0, 0 }, /* uc8 */
{ 1000e6, 1000e6, 0, 0 }, /* uc9 */
{ 0e6, 0e6, 0e6, 0e6 }, /* uc10*/
{ 0e6, 0e6, 0e6, 0e6 }, /* uc11*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc12*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc13*/
{ 3000e6, 3000e6, 3000e6, 3000e6 }, /* uc14*/
{ 4000e6, 4000e6, 0, 0 }, /* uc15*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc16*/
{ 0, 396.00e6, 0, 396.00e6 }, /* uc17*/
{ 0, 0, 0, 0 }, /* uc18*/
{ 1100e6, 1900e6, 1100e6, 1900e6 }, /* uc19*/
{ 900e6, 2100e6, 900e6, 2100e6 }, /* uc20*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc21*/
{ 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0 }, /* uc23*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc24*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc25*/
{ 1300e6, 0e6, 1300e6, 0e6 }, /* uc26*/
{ 1300e6, 0e6, 1300e6, 0e6 }, /* uc27*/
{ 0, 1000e6, 0, 1000e6 }, /* uc28*/
{ 0, 0, 0, 0 }, /* uc29*/
{ 3552e6, 3552e6, 3552e6, 3552e6 }, /* uc30*/
{ 1000e6, 2000e6, 3000e6, 4000e6 }, /* uc31*/
{ 1000e6, 2000e6, 3000e6, 4000e6 }, /* uc32*/
{ 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0 }, /* uc37*/
{ 500e6, 500e6, 500e6, 500e6 }, /* uc38*/
{ 0, 0, 0, 0 }, /* uc39*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc40*/
{ 1991.25e6, 1991.25e6, 1991.25e6, 1991.25e6 }, /* uc41*/
};
int64_t tx_chan_shift[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 100e6, 0, 0, 0, 0, 0, 0, 0 }, /* uc0 */
{ 0e6, 0e6, 0e6, 0e6, 0, 0, 0, 0 }, /* uc1 */
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc2 */
{ 0e6, 0e6, 0, 0, 0, 0, 0, 0 }, /* uc3 */
{ -148.75e6, 148.75e6, 0, 0, 0, 0, 0, 0 }, /* uc4 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc5 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc6 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc8 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc11*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc12*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc14*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc15*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc16*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc17*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc18*/
{ -200e6, 200e6, -200e6, 200e6, -200e6, 200e6, -200e6, 200e6 }, /* uc19*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc20*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc21*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc27*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc28*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc41*/
};
int8_t tx_chan_gain[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc0 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc1 */
{ -7, 0, 0, 0, 0, 0, 0, 0 }, /* uc2 */
{ -9, -9, -9, -9, -9, -9, -9, -9 }, /* uc3 */
{-12, -12, -12, -12, -12, -12, -12, -12 }, /* uc4 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc5 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc6 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc7 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc8 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc11*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc12*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc15*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc16*/
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc17*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc18*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc19*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc20*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc21*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc27*/
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc28*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc41*/
};
uint8_t tx_interp[][2] = {
/* {main DUC Interpolation, Channelizer DUC Interpolation} */
{ 8, 2 }, /* uc0 */
{ 4, 4 }, /* uc1 */
{ 6, 4 }, /* uc2 */
{ 4, 4 }, /* uc3 */
{ 6, 4 }, /* uc4 */
{ 4, 1 }, /* uc5 */
{ 4, 1 }, /* uc6 */
{ 4, 1 }, /* uc7 */
{ 4, 1 }, /* uc8 */
{ 4, 1 }, /* uc9 */
{ 12, 1 }, /* uc10*/
{ 12, 1 }, /* uc11*/
{ 8, 2 }, /* uc12*/
{ 12, 2 }, /* uc13*/
{ 4, 2 }, /* uc14*/
{ 4, 1 }, /* uc15*/
{ 8, 2 }, /* uc16*/
{ 4, 1 }, /* uc17*/
{ 0, 0 }, /* uc18*/
{ 8, 3 }, /* uc19*/
{ 8, 1 }, /* uc20*/
{ 8, 2 }, /* uc21*/
{ 0, 0 }, /* uc22*/
{ 8, 6 }, /* uc23*/
{ 6, 2 }, /* uc24*/
{ 8, 1 }, /* uc25*/
{ 4, 1 }, /* uc26*/
{ 4, 1 }, /* uc27*/
{ 4, 1 }, /* uc28*/
{ 0, 0 }, /* uc29*/
{ 8, 1 }, /* uc30*/
{ 0, 0 }, /* uc31*/
{ 2, 1 }, /* uc32*/
{ 0, 0 }, /* uc33*/
{ 0, 0 }, /* uc34*/
{ 8, 3 }, /* uc35*/
{ 8, 3 }, /* uc36*/
{ 4, 2 }, /* uc37*/
{ 4, 2 }, /* uc38*/
{ 0, 0 }, /* uc39*/
{ 12, 1 }, /* uc40*/
{ 8, 1 }, /* uc41*/
};
#endif
/* RX Main Path DDC Enable Configuration */
/* MUX 0 & MUX 1 Settings
* List the ADC_Coarse DDCs to be mapped to logical ADCs
* OR<4F>adi_ad9082_adc_coarse_ddc_select_e enumerations to create the list
* Note all DDC are enabled for all use cases that configure main datapath.
* Deselect CDDCs and FDDCs to override default Mux3 settings and enable full bandwidth mode
*/
uint8_t rx_cddc_select[] = {
0, /* uc0 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc1 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc2 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc3 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc4 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc5 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc6 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc7 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc8 */
0, /* uc9 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc10*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc11*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc12*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
0, /* uc14*/
0, /* uc15*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc16*/
0, /* uc17*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc18*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc19*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc20*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc21*/
0, /* uc22*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc23*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc24*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc25*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc26*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc27*/
0, /* uc28*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc29*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc30*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc31*/
0, /* uc32*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc33*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc34*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc35*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc36*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc37*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc38*/
0, /* uc39*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc40*/
0, /* uc41*/
};
/* RX Main Path DDC NCO Frequency Configuration
* List the ADC_Coarse DDCs desired Frequency Shift
* Each usecase has an Array of depth 4, each member value is the desired frequency shift (MHz)of a Coarse DDC Datapath,
* where index 0 = Frequency Shift for<6F> Coarse DDC 0, index 1 = Frequency Shift for<6F>Coarse DDC 1 etc
*
* For example: rx_cddc_shift[0][0] = 1842.5e6,
* For Use case 0, Frequency Shift for Coarse DDC0 is 1842.5e6MHz
*/
int64_t rx_cddc_shift[][4] = {
/* {cddc0, cddc1, cddc2, cddc3 }*/
{ 0, 0, 0, 0 }, /* uc0 */
{ 1842.5e6, 1842.5e6, 350e6, 350e6 }, /* uc1 */
{ 1842.5e6, 1842.5e6, 350e6, 350e6 }, /* uc2 */
{ 1842.5e6, 350e6, 0, 0 }, /* uc3 */
{ 1842.5e6, 350e6, 0, 0 }, /* uc4 */
{ 396e6, 55e6, 768e6, 0 }, /* uc5 */
{ 396e6, 396e6, 396e6, 396e6 }, /* uc6 */
{ 396e6, 396e6, 396e6, 396e6 }, /* uc7 */
{ 396e6, 55e6, 768e6, 0 }, /* uc8 */
{ 0, 0, 0, 0 }, /* uc9 */
{ 366e6, 376e6, 386e6, 396e6 }, /* uc10*/
{ 366e6, 376e6, 386e6, 396e6 }, /* uc11*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc12*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc13*/
{ 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0 }, /* uc15*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc16*/
{ 0, 0, 0, 0 }, /* uc17*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc18*/
{ 1100e6, 1100e6, 1900e6, 1900e6}, /* uc19*/
{ 900e6, 900e6, 2100e6, 2100e6}, /* uc20*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc21*/
{ 0, 0, 0, 0 }, /* uc22*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc23*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc24*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc25*/
{-125e6, -700e6, -125e6, -700e6 }, /* uc26*/
{-125e6, -700e6, -125e6, -700e6 }, /* uc27*/
{ 0, 0, 0, 0 }, /* uc28*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc29*/
{ 1000e6, 1000e6, 0, 0 }, /* uc30*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc31*/
{ 0, 0, 0, 0 }, /* uc32*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc33*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc34*/
{ 0, 0, 0, 0 }, /* uc35*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc36*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc37*/
{ 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0 }, /* uc39*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc40*/
{ 0, 0, 0, 0 }, /* uc41*/
};
/* RX Main Path DDC Data Decimation
* List the ADC_Coarse DDCs desired data decimation
* Each usecase has an Array of depth 4, each member value is the desired decimation of a Coarse DDC Datapath,
* where index 0 = Decimation Factor for<6F> Coarse DDC 0, index 1 = decimation Factor for<6F>Coarse DDC 1 etc
*
* For example: rx_cddc_dcm[1][0] =AD9081_CDDC_DCM_2,
* For Use case 1, Frequency Factor for Coarse DDC0 is 1
* Use adi_ad9082_adc_coarse_ddc_dcm_e to set the decimation setting
*/
uint8_t rx_cddc_dcm[][4] = {
/*{cddc0, cddc1, cddc2, cddc3} */
{ 0 }, /* uc0 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc1 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc2 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc3 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc4 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_4 }, /* uc5 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc6 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc7 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_1, AD9081_CDDC_DCM_4 }, /* uc8 */
{ 0 }, /* uc9 */
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc10*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc11*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc12*/
{ AD9081_CDDC_DCM_8, AD9081_CDDC_DCM_8, AD9081_CDDC_DCM_8, AD9081_CDDC_DCM_8 }, /* uc13*/
{ 0 }, /* uc14*/
{ 0 }, /* uc15*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc16*/
{ 0 }, /* uc17*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc18*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc19*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc20*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc21*/
{ 0 }, /* uc22*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc23*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc24*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc25*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc26*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc27*/
{ 0 }, /* uc28*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc29*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc30*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc31*/
{ 0 }, /* uc32*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc33*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc34*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc35*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc36*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc37*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc38*/
{ 0 }, /* uc39*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc40*/
{ 0 }, /* uc41*/
};
/* RX Main Path DDC Has Optional Complex to Real Convertor
* rx_cddc_c2r sets the enable for Complex to Real Converter per Main/Coarse DDC
* Each usecase has an Array of depth 4, each member value is the enable of a Coarse DDC Datapath Complex to Real Converter
* where index 0 = Enable Complex to Real Convertor for Coarse DDC 0,
* index 1 = Enable Complex to Real Convertor for Coarse DDC 1
*
* For example: rx_cddc_c2r[1][0] = 0,
* For Use case 1, Complex to Real Converter for Coarse DDC 0 is Disabled
*
*/
uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
{ 0, 0, 0, 0 }, /* uc0 */
{ 0, 0, 0, 0 }, /* uc1 */
{ 0, 0, 0, 0 }, /* uc2 */
{ 0, 0, 0, 0 }, /* uc3 */
{ 0, 0, 0, 0 }, /* uc4 */
{ 0, 0, 0, 0 }, /* uc5 */
{ 0, 0, 0, 0 }, /* uc6 */
{ 0, 0, 0, 0 }, /* uc7 */
{ 0, 0, 0, 0 }, /* uc8 */
{ 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0 }, /* uc11*/
{ 0, 0, 0, 0 }, /* uc12*/
{ 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0 }, /* uc15*/
{ 0, 0, 0, 0 }, /* uc16*/
{ 0, 0, 0, 0 }, /* uc17*/
{ 0, 0, 0, 0 }, /* uc18*/
{ 0, 0, 0, 0 }, /* uc19*/
{ 0, 0, 0, 0 }, /* uc20*/
{ 0, 0, 0, 0 }, /* uc21*/
{ 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0 }, /* uc27*/
{ 0, 0, 0, 0 }, /* uc28*/
{ 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0 }, /* uc41*/
};
/* RX Channelizer/Fine DDC Datapath Selection
* List the ADC Fine DDCs data path for routing Data from Main/ Coarse DDC Datapth to the JESD Tx
* Each usecase has an Array of depth 1, each member value is the masked list of Fine DDCs to be selected
* Note Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC0- Fine DDC3 datapaths and
* Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC4- Fine DDC6 datapaths
* For example: rx_fddc_select[3] = AD9081_ADC_FDDC_0 |AD9081_ADC_FDDC_1,
* For Use case 3, Fine DDC 0 and Fine DDC 1 are enabled
* Use adi_ad9082_adc_fine_ddc_select_e to create the list of fine DDCs to be enabled
* Note: Based on the input from the user, will apply a recommended muxing from CDDC to FDDC,
* An Error will be returned if the muxing is not supported for that devices,
* Note: If Fine DDC Decimation Factor is set to 1, Fine DDC in the Channel will be disabled
*
*/
uint8_t rx_fddc_select[] = {
0, /* uc0 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc1 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc2 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc3 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc4 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc5 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc6 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc7 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc8 */
0, /* uc9 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc10*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc11*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_2 | AD9081_ADC_FDDC_3 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5 | AD9081_ADC_FDDC_6 | AD9081_ADC_FDDC_7, /* uc12*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
0, /* uc14*/
0, /* uc15*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc16*/
0, /* uc17*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc18*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_2 | AD9081_ADC_FDDC_3 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5 | AD9081_ADC_FDDC_6 | AD9081_ADC_FDDC_7, /* uc19*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc20*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc21*/
0, /* uc22*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc23*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc24*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc25*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc26*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc27*/
0, /* uc28*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc29*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc30*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc31*/
0, /* uc32*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc33*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc34*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc35*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc36*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_4, /* uc37*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc38*/
0, /* uc39*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc40*/
0, /* uc41*/
};
/* RX Channelizer Path DDC NCO Frequency Configuration
* List the ADC_Fine DDCs desired Frequency Shift
* Each usecase has an Array of depth 8, each member value is the desired frequency shift (MHz)of a Fine DDC Datapath,
* where index 0 = Frequency Shift for<6F> Fine DDC 0, index 1 = Frequency Shift for<6F>Fine DDC 1 etc
*
* For example: rx_fddc_shift[0][0] = 1842.5e6,
* For Use case 0, Frequency Shift for Fine DDC0 is 1842.5e6MHz
*/
int64_t rx_fddc_shift[][8] = {
/* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc0 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc1 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc2 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc3 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc4 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc5 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc6 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc8 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc11*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc12*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc15*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc16*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc17*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc18*/
{-200e6, 200e6, -200e6, 200e6, -200e6, 200e6, -200e6, 200e6 }, /* uc19*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc20*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc21*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc27*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc28*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc41*/
};
/* RX Channelizer Data Decimation
* List the ADC Fine DDCs desired data decimation
* Each usecase has an Array of depth 8, each member value is the desired decimation of a Fine DDC Datapath,
* where index 0 = Decimation factor for<6F> Fine DDC 0, index 1 = decimation factor for<6F>Fine DDC 1 etc
* Note where No Fine DDC Decimation is required (bypassed), Decimation factor is set to 1,AD9081_FDDC_DCM_1
*
* For example: rx_fddc_dcm[1][0] =AD9081_FDDC_DCM_4,
* For Use case 1, Decimation Factor for FineDDC0 is 4
* Use adi_ad9082_adc_fine_ddc_dcm_e to set the decimation setting
*/
uint8_t rx_fddc_dcm[][8] = { /* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0 }, /* uc0 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc1 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc2 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc3 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc4 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc5 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc6 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc7 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc8 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc9 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc10*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc11*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2 }, /* uc12*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc13*/
{ 0 }, /* uc14*/
{ 0 }, /* uc15*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc16*/
{ 0 }, /* uc17*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc18*/
{ AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3 }, /* uc19*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc20*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc21*/
{ 0 }, /* uc22*/
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc23*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2 }, /* uc24*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc25*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc26*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc27*/
{ 0 }, /* uc28*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc29*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc30*/
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc31*/
{ 0 }, /* uc32*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc33*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0, AD9081_FDDC_DCM_8, AD9081_FDDC_DCM_8 }, /* uc34*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc35*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc36*/
{ AD9081_FDDC_DCM_1, 0, 0, 0, AD9081_FDDC_DCM_1 }, /* uc37*/
{ AD9081_FDDC_DCM_2, 0, 0, 0, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2 }, /* uc38*/
{ 0 }, /* uc39*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc40*/
{ 0 }, /* uc41*/
};
uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
/* Link Settings */
/* Rx Channelizer Virtual Converter Mapping
* Maps the output of a Fine DDC Data Format O/P to a JESD TX virtual converter
* Refer to Mux 4 in the Rx Digital Datapath section of the System Developer Userguide
*
* adi_ad9082_adc_fine_ddc_converter_e enerates the Fine DCC I & Q Outputs
* Each virtual converter in the JESD TX link must be assigned a source data, Fine DDC X I or Q
* Note this should be set carefully and reflect the Fine DDC selected in rx_fddc_select and also JESD TX Configuration
*
* Each usecase has an Array of depth 2, each member a list of the source of data for the virtual converter for the JESD TX Link
* where index 0 = Sources of Data for JESD TX Link 0
* where index 1 = Sources of Data for JESD TX Link 1
*
* For example: For Use Case 29 with is a Dual link JESD Mode with M =4, we specify the I & Q source for each virtual Converter
* jtx_conv_sel[28][0]={AD9081_FDDC_0_I,AD9081_FDDC_0_Q,AD9081_FDDC_1_I,AD9081_FDDC_1_Q }
* jtx_conv_sel[28][1]={AD9081_FDDC_4_I,AD9081_FDDC_4_Q,AD9081_FDDC_5_I,AD9081_FDDC_5_Q }
*/
adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
{ { 0 } }, /* uc0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc1.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc2.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc3.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc3.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc4.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc4.link1 */
{ { AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q }, /* uc5.link0 */
{ AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc5.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc6.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc6.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc7.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc7.link1 */
{ { AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q }, /* uc8.link0 */
{ AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc8.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q } }, /* uc9.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc10.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc11.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_2_I, AD9081_FDDC_2_Q, AD9081_FDDC_3_I, AD9081_FDDC_3_Q, /* uc12.link0 */
AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q, AD9081_FDDC_6_I, AD9081_FDDC_6_Q, AD9081_FDDC_7_I, AD9081_FDDC_7_Q } }, /* uc12.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc14.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q } }, /* uc15.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc16.link0 */
{ { 0 } }, /* uc17.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc18.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc18.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_2_I, AD9081_FDDC_2_Q, AD9081_FDDC_3_I, AD9081_FDDC_3_Q, /* uc19.link0 */
AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q, AD9081_FDDC_6_I, AD9081_FDDC_6_Q, AD9081_FDDC_7_I, AD9081_FDDC_7_Q } }, /* uc19.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc20.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc21.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc22.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc23.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc24.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc24.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc25.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc26.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc27.link0 */
{ { 0 } }, /* uc28.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc29.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc29.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc30.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc31.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc32.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc33.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc33.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc34.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc34.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc35.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc36.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q } }, /* uc37.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc38.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc38.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc39.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc39.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc40.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc41.link0 */
};
/* Total Decimation Settings */
/* The total decimation is used to calculate lane rate for each link which in
* turn is used to determine FPGA clock sources and line rates for JESD204B
*
* Each usecase has an Array of depth 2,
* where index 0 = Total decimation for link 0
* where index 1 = Total decimation for link 1
*
* For example: For Use Case 3 with is a Dual link JESD Mode, total decimation for each link
* jtx_chip_dcm[3][0]= 8
* jtx_chip_dcm[3][1]= 8
*/
uint8_t jtx_chip_dcm[][2] = {
{ 0 }, /* uc0.link0 */
{ 8 }, /* uc1.link0 */
{ 8 }, /* uc2.link0 */
{ 8 , /* uc3.link0 */
8 }, /* uc3.link1 */
{ 8 , /* uc4.link0 */
8 }, /* uc4.link1 */
{ 2 , /* uc5.link0 */
4 }, /* uc5.link1 */
{ 4 , /* uc6.link0 */
4 }, /* uc6.link1 */
{ 4 , /* uc7.link0 */
4 }, /* uc7.link1 */
{ 1 , /* uc8.link0 */
4 }, /* uc8.link1 */
{ 1 }, /* uc9.link0 */
{ 3 }, /* uc10.link0 */
{ 3 }, /* uc11.link0 */
{ 4 }, /* uc12.link0 */
{ 8 }, /* uc13.link0 */
{ 1 }, /* uc14.link0 */
{ 1 }, /* uc15.link0 */
{ 3 }, /* uc16.link0 */
{ 0 }, /* uc17.link0 */
{ 4 , /* uc18.link0 */
4 }, /* uc18.link1 */
{ 12}, /* uc19.link0 */
{ 4 }, /* uc20.link0 */
{ 3 }, /* uc21.link0 */
{ 1 }, /* uc22.link0 */
{ 16}, /* uc23.link0 */
{ 6 , /* uc24.link0 */
6 }, /* uc24.link1 */
{ 2 }, /* uc25.link0 */
{ 2 }, /* uc26.link0 */
{ 2 }, /* uc27.link0 */
{ 0 }, /* uc28.link0 */
{ 4 , /* uc29.link0 */
4 }, /* uc29.link1 */
{ 2 }, /* uc30.link0 */
{ 16}, /* uc31.link0 */
{ 1 }, /* uc32.link0 */
{ 12 , /* uc33.link0 */
24}, /* uc33.link1 */
{ 12 , /* uc34.link0 */
48}, /* uc34.link1 */
{ 6 }, /* uc35.link0 */
{ 6 }, /* uc36.link0 */
{ 4 }, /* uc37.link0 */
{ 8 , /* uc38.link0 */
8 }, /* uc38.link1 */
{ 1 , /* uc39.link0 */
1 }, /* uc39.link1 */
{ 4 }, /* uc40.link0 */
{ 1 }, /* uc41.link0 */
};
uint8_t jtx_logiclane_mapping_pe_brd[2][8] = { { 0, 1, 2, 3, 4, 5, 6, 7 }, { 4, 5, 6, 7, 0, 1, 2, 3 } };
uint8_t jtx_logiclane_mapping_ce_brd[2][8] = { { 6, 4, 3, 2, 1, 0, 7, 5 }, { 2, 0, 7, 7, 7, 7, 3, 1 } };
adi_cms_jesd_param_t jrx_param[] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
{ 8, 4, 16, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 16 }, /* uc0 : nco test */
{ 4, 4, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 9, }, /* uc1 : txmode = 194 */
{ 8, 4, 16, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 16 }, /* uc2 : txmode = 214 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10 }, /* uc3 : txmode = 437 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10 }, /* uc4 : txmode = 440 */
{ 4, 1, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 62 }, /* uc5 : txmode = 263 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc6 : txmode = 258 */
{ 4, 1, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 62 }, /* uc7 : txmode = 266 */
{ 4, 1, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 62 }, /* uc8 : txmode = 263 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc9 : txmode = 258 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc10: txmode = 378 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc11: txmode = 378 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc12: txmode = 91 */
// { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16 }, /* uc13: txmode = 378 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc14: txmode = 88 */
{ 8, 3, 4, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 35 }, /* uc15: txmode = 573 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc16: txmode = 91 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc17: txmode = 258 */
{ 0 }, /* uc18: rx only */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc19: txmode = 371 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc20: txmode = 99 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16 }, /* uc21: txmode = 91 */
{ 0 }, /* uc22: rx only */
{ 4, 4, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 9 }, /* uc23: txmode = 417 */
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc24: txmode = 248 */
{ 4, 2, 4, 1, 1, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 10 }, /* uc25: txmode = 97 */
{ 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 24 }, /* uc26: txmode = 140 */
{ 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 24 }, /* uc27: txmode = 140 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc28: txmode = 258 */
{ 0 }, /* uc29: rx only */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc30: txmode = 99 */
{ 0 }, /* uc31: rx only */
{ 8, 1, 4, 1, 1, 256, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 17 }, /* uc32: txmode = ??? */
{ 0 }, /* uc33: rx only */
{ 0 }, /* uc34: rx only */
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc35: */
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc36: */
{ 8, 2, 8, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc37: */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 10 }, /* uc38 */
{ 0 }, /* uc39: rx only */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc40: txmode = 378 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc41: txmode = 378 */
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
};
adi_cms_jesd_param_t jtx_param[][2] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
{ { 0 } }, /* uc0 : nco test */
{ { 4, 4, 8, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10, 0, 0 } }, /* uc1 : rxmode = 392, link0 */
{ { 4, 4, 8, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10, 0, 0 } }, /* uc2 : rxmode = 392, link0 */
{ { 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 }, /* uc3 : rxmode = 360, link0 */
{ 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 } }, /* uc3 : rxmode = 360, link1 */
{ { 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 }, /* uc4 : rxmode = 360, link0 */
{ 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 } }, /* uc4 : rxmode = 360, link1 */
{ { 4, 1, 1, 2, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 13, 0, 0 }, /* uc5 : rxmode = 1088,link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc5 : rxmode = 411, link1 */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc6 : rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc6 : rxmode = 411, link1 */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc7 : rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc7 : rxmode = 411, link1 */
{ { 4, 1, 1, 2, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 13, 0, 0 }, /* uc8 : rxmode = 1087,link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc8 : rxmode = 411, link1 */
{ { 8, 1, 2, 2, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 19, 0, 0 } }, /* uc9 : rxmode = 502, link0 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc10: rxmode = 226, link0 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc11: rxmode = 226, link0 */
{ { 8, 4, 16, 1, 0, 64, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 17, 0, 0 } }, /* uc12: rxmode = 234, link0 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
{ { 8, 1, 4, 1, 0, 256, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 18, 0, 0 } }, /* uc14: rxmode = 252, link0 */
{ { 8, 3, 2, 8, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 28, 0, 0 } }, /* uc15: rxmode = 1263,link0 */
{ { 8, 6, 8, 4, 0, 128, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 26, 0, 1 } }, /* uc16: rxmode = 1260,link0 */
{ { 0 } }, /* uc17: tx only */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc18: rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc18: rxmode = 411, link1 */
{ { 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 17, 0, 0 } }, /* uc19: rxmode = 239, link0 */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc20: rxmode = 227, link0 */
{ { 8, 6, 8, 4, 0, 128, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 26, 0, 1 } }, /* uc21: rxmode = 1260,link0 */
{ { 8, 3, 4, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 27, 0, 0 } }, /* uc22: rxmode = 1261,link0 */
{ { 4, 4, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10, 0, 0 } }, /* uc23: rxmode = 397, link0 */
{ { 2, 2, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 }, /* uc24: rxmode = 358, link0 */
{ 2, 2, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 } }, /* uc24: rxmode = 358, link1 */
{ { 4, 2, 4, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 11, 0, 0 } }, /* uc25: rxmode = 1452,link0 */
{ { 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 26, 0, 0 } }, /* uc26: rxmode = 1565,link0 */
{ { 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 26, 0, 0 } }, /* uc27: rxmode = 1565,link0 */
{ { 0 } }, /* uc28: tx only */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc29: rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc29: rxmode = 411, link1 */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc30: rxmode = 225,link0 */
{ { 2, 8, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 4, 0, 0 } }, /* uc31: rxmode = 411, link0 */
{ { 8, 1, 4, 1, 1, 256, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 18, 0, 0 } }, /* uc32: rxmode = ???, link0 */
{ { 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc33: rxmode = , link0 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc33: rxmode = , link1 */
{ { 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc34: rxmode = , link0 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc34: rxmode = , link1 */
{ { 8, 1, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 18, 0, 0 } }, /* uc35: rxmode */
{ { 8, 1, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 18, 0, 0 } }, /* uc36: rxmode */
{ { 8, 1, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 18, 0, 0 } }, /* uc37: rxmode */
{ { 4, 1, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 13, 0, 0 }, /* uc38: rxmode = , link0 */
{ 4, 2, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc38: rxmode = , link1 */
{ { 4, 3, 2, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 1, 2, 14, 0, 0 }, /* uc39: rxmode = 1261,link0 */
{ 4, 3, 2, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 1, 2, 14, 0, 0 } }, /* uc39: rxmode = 1261,link1 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc40: rxmode = 227, link0 */
{ { 8, 1, 4, 1, 0, 256, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 18, 0, 0 } }, /* uc41: rxmode = 252, link0 */
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
};

997
vitis/radar/src/uc_settings.c.bak Executable file
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@@ -0,0 +1,997 @@
/*!
* @brief Use Case Settings
*
* @copyright copyright(c) 2018 analog devices, inc. all rights reserved.
* This software is proprietary to Analog Devices, Inc. and its
* licensor. By using this software you agree to the terms of the
* associated analog devices software license agreement.
*/
/*!
* @addtogroup __ADI_AD9081_APP__
* @{
*/
/******************************************************
The AD9081/AD9082/AD9988/AD9986 standalone application use-case Settings holds the AD9081/AD9082/AD9988/AD9986 configuration parameters of a number of modes of operation or "usecase" for the ad9081.
Currently the Standalone App is QA'd with 20+ usecases that. These are usecases that the AD9081/AD9082/AD9988/AD9986 ADI evaluation platforms can support and can be used as a reference to<74>
build a usecase parameters for a custom application.
*/
/*============= I N C L U D E S ============*/
#include <stdio.h>
#include <unistd.h>
#include "adi_ad9081.h"
/*============= D A T A ====================*/
/* Usecase Frequency Scheme Settings
* This array list the desired clocks required for the usecase.
* For each usecase an array of depth 4 provides the frequecy in Hz for the following clocks
* As this application targets the Txfe/MxFE evaluation board, that my have various XTAL as reference to the HMC7044.
* The comments following the usecase entry will indicate if the scheme can be used with the target hardware.
* The Comments also provide the expected lane rate of the usecase.
* clk_hz["usecase"][0] Txfe/MxFE Device reference Clock (dev_ref), if not using on chip pll, this should be equal to the dac_clk
* clk_hz["usecase"][1] The value of the reference clock to the ADS9 FPGA JESD Blocks, This is not used by MxFE/TxFE API. (204C lane rate/66) or (204B lane rate/20)
* clk_hz["usecase"][2] The MxFE TX data path DAC sampling clock (dac_clk) as per the desired usecase
* clk_hz["usecase"][3] The MxFE Rx data path ADC aampling clock (adc_clk) as per the desired usecase
* Notes:
* The Example Application will use adi_ad9081_device_clk_config_set to configure the MxFE/TxFE based on th dev_ref, dac_clk, and adc_clk.
* If the on-chip PLL feature of MxFe/Txfe is not required dev_ref and dac_clk should be set to the same value.
* If on chip PLL is required, then based on the applied dev_ref clock and the desired dac_clk the API will configure the onchip -pll appropriately
* The API will also configure the chip to generate the desired adc_clk based on the dac_clk.
*
*/
uint64_t clk_hz[][4] = {
/*dev_ref, fpga_ref, dac_clk, adc_clk */ /* UC, JESD, Crystal type, Lane rate, Comments */
{ 122.88e6, 122.88e6, 5898.24e6, 2949.12e6 }, /* uc0, nco test */
{ 122.88e6, 737.28e6, 5898.24e6, 2949.12e6 }, /* uc1, 204B, 100MHz/122.88MHz 14.54560Gbps */
{ 122.88e6, 737.28e6, 8847.36e6, 2949.12e6 }, /* uc2, 204B, 100MHz/122.88MHz, 14.54560Gbps */
{ 122.88e6, 368.64e6, 5898.24e6, 2949.12e6 }, /* uc3, 204B, 100MHz/122.88MHz, 7.37280Gbps */
{ 122.88e6, 368.64e6, 8847.36e6, 2949.12e6 }, /* uc4, 204B, 100MHz/122.88MHz, 7.37280Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc5, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc6, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc7, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc8, 204B, 100MHz/122.88MHz, 15.36000Gbps */
{ 122.88e6, 737.28e6, 5898.24e6, 2949.12e6 }, /* uc9, 204B, 100MHz/122.88MHz, 14.54560Gbps, 9082 rx FBW */
{ 122.88e6, 122.88e6, 5898.24e6, 1474.56e6 }, /* uc10, 204C, 100MHz/122.88MHz, 8.11008Gbps */
{ 11796.48e6,245.76e6,11796.48e6, 2949.12e6 }, /* uc11, 204C, Direct Clock, 16.22016Gbps Eye scan */
{ 122.88e6, 368.64e6, 11796.48e6, 2949.12e6 }, /* uc12, 204C, 100MHz/122.88MHz, 24.33024Gbps */
{ 125e6, 250e6, 12000e6, 4000e6 }, /* uc13, 204C, 100MHz, 16.50000Gbps, loopback */
{ 125e6, 375e6, 6000e6, 3000e6 }, /* uc14, 204C, 100MHz, 24.75000Gbps, 9081 rx FBW */
{ 122.88e6, 184.32e6, 7864.32e6, 3932.16e6 }, /* uc15, 204C, 100MHz/122.88MHz, 12.16512Gbps, 9082 rx FBW */
{ 5898.24e6,184.32e6, 5898.24e6, 2949.12e6 }, /* uc16, 204C, Direct Clock, 12.16512Gbps Eye scan */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc17, 204B, 100MHz/122.88MHz, 15.36000Gbps, tx only */
{ 384e6, 768e6, 6144e6, 3072e6 }, /* uc18, 204B, 100MHz/122.88MHz, 15.36000Gbps, rx only */
{ 122.88e6, 245.76e6, 11796.48e6, 5898.24e6 }, /* uc19, 204C, 100MHz/122.88MHz, 16.22016Gbps, 9082/9986/9207 only */
{ 122.88e6, 368.64e6, 11796.48e6, 5898.24e6 }, /* uc20, 204C, 100MHz/122.88MHz, 24.33024Gbps 9082/9986/9207 only */
{ 122.88e6, 184.32e6, 5898.24e6, 2949.12e6 }, /* uc21, 204C, 100MHz/122.88MHz, 12.16512Gbps, subclass1 */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc22, 204C, 100MHz, 24.75000Gbps, rx only, 9081 rx FBW */
{ 125e6, 500e6, 12000e6, 4000e6 }, /* uc23, 204B, 100MHz, 10.00000Gbps */
{ 122.88e6, 491.52e6, 5898.24e6, 2949.12e6 }, /* uc24, 204B, 100MHz/122.88MHz, 9.83040Gbps */
{ 122.88e6, 368.64e6, 11796.48e6, 2949.12e6 }, /* uc25, 204C, 100MHz/122.88MHz, 24.33024Gbps */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc26, 204C, 100MHz, 24.75000Gbps, loopback, MCS */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc27, 204C, 100MHz, 24.75000Gbps, loopback, MCS */
{ 312.5e6, 625e6, 5000e6, 2500e6 }, /* uc28, 204B, 100MHz, 12.5000Gbps, tx only */
{ 312.5e6, 625e6, 5000e6, 2500e6 }, /* uc29, 204B, 100MHz, 12.5000Gbps, rx only */
{ 125e6, 375e6, 12000e6, 3000e6 }, /* uc30, 204C, 100MHz, 24.33024Gbps TPC MODE */
{ 3240e6, 202.5e6, 3240e6, 3240e6 }, /* uc31, 204C, Direct Clock Only 13.36500Gbps rx only */
{ 250e6, 250e6, 4000e6, 2000e6 }, /* uc32, 204C, 100MHz, 16.5, 9081 rx FBW */
{ 100e6, 400e6, 4800e6, 4800e6 }, /* uc33, 204B 100MHz, 8G/4G rx0/rx1 & 9082/9207 only */
{ 100e6, 400e6, 4800e6, 4800e6 }, /* uc34, 204B 100MHz, 8G/2G rx0/rx1 & 9082/9207 only */
{ 100e6, 400e6, 9600e6, 4800e6 }, /* uc35, 204B 100MHz, 8G/8G tx + rx & 9082/9207 only */
{ 100e6, 200e6, 4800e6, 2400e6 }, /* uc36, 204B 100MHz, 4G/4G tx + rx */
{ 100e6, 400e6, 3200e6, 1600e6 }, /* uc37, 204B 100MHz, 8G/4G tx + rx */
{ 100e6, 600e6, 4800e6, 2400e6 }, /* uc38, 204B 100MHz, 12G/3G,12G/6G tx0/rx0,tx1/rx1 */
{ 125e6, 375e6, 8000e6, 4000e6 }, /* uc39, 204C, 100MHz, 24.75000Gbps, rx only, 9081 rx FBW */
{ 125e6, 250e6, 12000e6, 4000e6 }, /* uc40, 204C, 100MHz, 16.50000Gbps, txrx cap gate, subclass1 */
{ 125e6, 375e6, 12000e6, 3000e6 }, /* uc41, 204C, 100MHz, 24.75000Gbps, 9081 rx FBW ace uc */
};
#if !defined(AD9207_ID) && !defined(AD9209_ID)
/* TX DataPath Configuration Settings*/
/* DAC Crossbar Configuration
* Use this parameter to define Mapping from Map JRx Samples to DAC Channelizer to MAIN DAC Datapath
* For Modes that support Use Channel Interpolation > 1
* JRX Converter Samples are mapped to Channels Datapaths as follows:
* Note each AD9081_DAC_CH_X is made up of an IQ pair sample
* DUAL LINK | M | Default Channel Datapth Mapping (0-7)
* 0 | 2 | AD9081_DAC_CH_0
* 0 | 4 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1
* 0 | 6 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2
* 0 | 8 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3
* 0 | 12 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5
* 0 | 16 | AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
* 1 | 2 | Link 0: AD9081_DAC_CH_0 , Link1: AD9081_DAC_CH_4
* 1 | 4 | Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5
* 1 | 6 | Link 0: AD9081_DAC_CH_0,AD9081_DAC_CH_1, AD9081_DAC_CH_3 , Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6
* 1 | 8 | Link 0:AD9081_DAC_CH_0 , AD9081_DAC_CH_1 , AD9081_DAC_CH_2, AD9081_DAC_CH_3, Link1: AD9081_DAC_CH_4, AD9081_DAC_CH_5, AD9081_DAC_CH_6, AD9081_DAC_CH_7
* Each Main DAC Datapath may be a summation of the Channel datapaths. Use tx_dac_chan_xbar as follows to achieve that as described below.
* uint8_t tx_dac_chan_xbar[usecase][ORed List Channel (0-7) to be summed and mapped to DAC Datapath(0-3)]
* Each usecase has an Array of depth 4, each member value is the list of Channels to be mapped a Main DAC Datapath,
* where index 0 = DAC0, index 1 = DAC1 etc
* OR adi_ad9082_dac_channel_select_e enumerations to create the list
* For example: ad9081_dac_chan_xbar[0][0] =AD9081_DAC_CH_0 |AD9081_DAC_CH_1
* Map Channlizer 0 and Channelizer 1 to DAC 0
*
* For Modes that bypass Channel ie Channel Interpolation = 1 and Main DAC Interpolation > 1
* JRX Converter Samples are mapped by default to DAC Main Data apths as follows
* DUAL LINK | M | Default Main DAC Datapath Mapping (0-3) | DAC DP to DAC Mapping (0-3)
* 0 | 2 | AD9081_DAC_DP_0 | AD9081_DAC_DP_0 ->DAC 0
* 0 | 4 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1
* 0 | 6 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2
* 0 | 8 | AD9081_DAC_DP_0 , AD9081_DAC_DP_1 , AD9081_DAC_DP_2, AD9081_DAC_DP_3 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
* 1 | 2 | Link 0: AD9081_DAC_DP_0 , Link1: AD9081_DAC_DP_2 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_2 ->DAC 2
* 1 | 4 | Link 0: AD9081_DAC_DP_0,AD9081_DAC_DP_1 , Link1: AD9081_DAC_DP_2, AD9081_DAC_DP_3 | AD9081_DAC_DP_0 ->DAC 0, AD9081_DAC_DP_1 ->DAC 1, AD9081_DAC_DP_2 ->DAC 2 , AD9081_DAC_DP_3 ->DAC 3
* Each converter sample pair may be routed to an alternative Datapath. Use tx_dac_chan_xbar as follows to achieve that as described below.
*
* uint8_t tx_dac_chan_xbar[usecase][DAC Datapath(0-3) to be mapped to DAC (0-3)]
* Each usecase has an Array of depth 4, each member value is the DAC MAIN DP to be routed
* where index 0 = DAC0 index 1 = DAC1 etc
* For example: ad9081_dac_chan_xbar[0][1] =AD9081_DAC_DP _3
* DAC Datapath 3 is routed to DAC 1
*
*
*
*/
uint8_t tx_dac_chan_xbar[][4] = { /* dac0, dac1, dac2, dac3 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_0, AD9081_DAC_CH_0, AD9081_DAC_CH_0 }, /* uc0 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc1 */
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc2 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc3 */
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc4 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc5 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_2, AD9081_DAC_CH_3, AD9081_DAC_CH_1 }, /* uc6 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_3, AD9081_DAC_CH_2 }, /* uc7 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc8 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc9 */
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc10*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc11*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc12*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc13*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc14*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc15*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc16*/
{ AD9081_DAC_CH_2, AD9081_DAC_CH_0, AD9081_DAC_CH_3, AD9081_DAC_CH_1 }, /* uc17*/
{ 0 }, /* uc18*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc19*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc20*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc21*/
{ 0 }, /* uc22*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc23*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc24*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1 }, /* uc25*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc26*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc27*/
{ AD9081_DAC_CH_2, AD9081_DAC_CH_0, AD9081_DAC_CH_3, AD9081_DAC_CH_1 }, /* uc28*/
{ 0 }, /* uc29*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc30*/
{ 0 }, /* uc31*/
{ AD9081_DAC_CH_0 | AD9081_DAC_CH_1, AD9081_DAC_CH_2 | AD9081_DAC_CH_3, AD9081_DAC_CH_4 | AD9081_DAC_CH_5, AD9081_DAC_CH_6 | AD9081_DAC_CH_7 }, /* uc32*/
{ 0 }, /* uc33 */
{ 0 }, /* uc34 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc35 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc36 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc37 */
{ AD9081_DAC_CH_0 , AD9081_DAC_CH_1 }, /* uc38 */
{ 0 }, /* uc39*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc40*/
{ AD9081_DAC_CH_0, AD9081_DAC_CH_1, AD9081_DAC_CH_2, AD9081_DAC_CH_3 }, /* uc41*/
};
int64_t tx_main_shift[][4] = { /* dac0, dac1, dac2, dac3 */
{ 1000.00e6, 1000.00e6, 1000.00e6, 1000.00e6 }, /* uc0 */
{ 1842.50e6, 1842.50e6, 1842.50e6, 1842.50e6 }, /* uc1 */
{ 1991.25e6, 1991.25e6, 1991.25e6, 1991.25e6 }, /* uc2 */
{ 1842.50e6, 1842.50e6, 0, 0 }, /* uc3 */
{ 1991.25e6, 0, 0, 0 }, /* uc4 */
{ 672.00e6, 0, 0, 0 }, /* uc5 */
{ 396.00e6, 0, 0, 396.00e6 }, /* uc6 */
{ 396.00e6, 0, 0, 396.00e6 }, /* uc7 */
{ 672.00e6, 0, 0, 0 }, /* uc8 */
{ 1000e6, 1000e6, 0, 0 }, /* uc9 */
{ 0e6, 0e6, 0e6, 0e6 }, /* uc10*/
{ 0e6, 0e6, 0e6, 0e6 }, /* uc11*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc12*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc13*/
{ 3000e6, 3000e6, 3000e6, 3000e6 }, /* uc14*/
{ 4000e6, 4000e6, 0, 0 }, /* uc15*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc16*/
{ 0, 396.00e6, 0, 396.00e6 }, /* uc17*/
{ 0, 0, 0, 0 }, /* uc18*/
{ 1100e6, 1900e6, 1100e6, 1900e6 }, /* uc19*/
{ 900e6, 2100e6, 900e6, 2100e6 }, /* uc20*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc21*/
{ 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0 }, /* uc23*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc24*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc25*/
{ 1300e6, 0e6, 1300e6, 0e6 }, /* uc26*/
{ 1300e6, 0e6, 1300e6, 0e6 }, /* uc27*/
{ 0, 1000e6, 0, 1000e6 }, /* uc28*/
{ 0, 0, 0, 0 }, /* uc29*/
{ 3552e6, 3552e6, 3552e6, 3552e6 }, /* uc30*/
{ 1000e6, 2000e6, 3000e6, 4000e6 }, /* uc31*/
{ 1000e6, 2000e6, 3000e6, 4000e6 }, /* uc32*/
{ 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0 }, /* uc37*/
{ 500e6, 500e6, 500e6, 500e6 }, /* uc38*/
{ 0, 0, 0, 0 }, /* uc39*/
{ 1000e6, 1000e6, 1000e6, 1000e6 }, /* uc40*/
{ 1991.25e6, 1991.25e6, 1991.25e6, 1991.25e6 }, /* uc41*/
};
int64_t tx_chan_shift[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 100e6, 0, 0, 0, 0, 0, 0, 0 }, /* uc0 */
{ 0e6, 0e6, 0e6, 0e6, 0, 0, 0, 0 }, /* uc1 */
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc2 */
{ 0e6, 0e6, 0, 0, 0, 0, 0, 0 }, /* uc3 */
{ -148.75e6, 148.75e6, 0, 0, 0, 0, 0, 0 }, /* uc4 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc5 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc6 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc8 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc11*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc12*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc14*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc15*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc16*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc17*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc18*/
{ -200e6, 200e6, -200e6, 200e6, -200e6, 200e6, -200e6, 200e6 }, /* uc19*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc20*/
{ -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6, -148.75e6, 148.75e6 }, /* uc21*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc27*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc28*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc41*/
};
int8_t tx_chan_gain[][8] = { /* ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc0 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc1 */
{ -7, 0, 0, 0, 0, 0, 0, 0 }, /* uc2 */
{ -9, -9, -9, -9, -9, -9, -9, -9 }, /* uc3 */
{-12, -12, -12, -12, -12, -12, -12, -12 }, /* uc4 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc5 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc6 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc7 */
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc8 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc11*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc12*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc15*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc16*/
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc17*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc18*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc19*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc20*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc21*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc27*/
{ -7, -7, -7, -7, -7, -7, -7, -7 }, /* uc28*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc41*/
};
uint8_t tx_interp[][2] = {
/* {main DUC Interpolation, Channelizer DUC Interpolation} */
{ 8, 2 }, /* uc0 */
{ 4, 4 }, /* uc1 */
{ 6, 4 }, /* uc2 */
{ 4, 4 }, /* uc3 */
{ 6, 4 }, /* uc4 */
{ 4, 1 }, /* uc5 */
{ 4, 1 }, /* uc6 */
{ 4, 1 }, /* uc7 */
{ 4, 1 }, /* uc8 */
{ 4, 1 }, /* uc9 */
{ 12, 1 }, /* uc10*/
{ 12, 1 }, /* uc11*/
{ 8, 2 }, /* uc12*/
{ 12, 1 }, /* uc13*/
{ 4, 2 }, /* uc14*/
{ 4, 1 }, /* uc15*/
{ 8, 2 }, /* uc16*/
{ 4, 1 }, /* uc17*/
{ 0, 0 }, /* uc18*/
{ 8, 3 }, /* uc19*/
{ 8, 1 }, /* uc20*/
{ 8, 2 }, /* uc21*/
{ 0, 0 }, /* uc22*/
{ 8, 6 }, /* uc23*/
{ 6, 2 }, /* uc24*/
{ 8, 1 }, /* uc25*/
{ 4, 1 }, /* uc26*/
{ 4, 1 }, /* uc27*/
{ 4, 1 }, /* uc28*/
{ 0, 0 }, /* uc29*/
{ 8, 1 }, /* uc30*/
{ 0, 0 }, /* uc31*/
{ 2, 1 }, /* uc32*/
{ 0, 0 }, /* uc33*/
{ 0, 0 }, /* uc34*/
{ 8, 3 }, /* uc35*/
{ 8, 3 }, /* uc36*/
{ 4, 2 }, /* uc37*/
{ 4, 2 }, /* uc38*/
{ 0, 0 }, /* uc39*/
{ 12, 1 }, /* uc40*/
{ 8, 1 }, /* uc41*/
};
#endif
/* RX Main Path DDC Enable Configuration */
/* MUX 0 & MUX 1 Settings
* List the ADC_Coarse DDCs to be mapped to logical ADCs
* OR<4F>adi_ad9082_adc_coarse_ddc_select_e enumerations to create the list
* Note all DDC are enabled for all use cases that configure main datapath.
* Deselect CDDCs and FDDCs to override default Mux3 settings and enable full bandwidth mode
*/
uint8_t rx_cddc_select[] = {
0, /* uc0 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc1 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc2 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc3 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc4 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc5 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc6 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc7 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc8 */
0, /* uc9 */
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc10*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc11*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc12*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc13*/
0, /* uc14*/
0, /* uc15*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc16*/
0, /* uc17*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc18*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc19*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc20*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc21*/
0, /* uc22*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc23*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc24*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc25*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc26*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc27*/
0, /* uc28*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc29*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc30*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc31*/
0, /* uc32*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc33*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc34*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc35*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc36*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc37*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc38*/
0, /* uc39*/
AD9081_ADC_CDDC_0 | AD9081_ADC_CDDC_1 | AD9081_ADC_CDDC_2 | AD9081_ADC_CDDC_3, /* uc40*/
0, /* uc41*/
};
/* RX Main Path DDC NCO Frequency Configuration
* List the ADC_Coarse DDCs desired Frequency Shift
* Each usecase has an Array of depth 4, each member value is the desired frequency shift (MHz)of a Coarse DDC Datapath,
* where index 0 = Frequency Shift for<6F> Coarse DDC 0, index 1 = Frequency Shift for<6F>Coarse DDC 1 etc
*
* For example: rx_cddc_shift[0][0] = 1842.5e6,
* For Use case 0, Frequency Shift for Coarse DDC0 is 1842.5e6MHz
*/
int64_t rx_cddc_shift[][4] = {
/* {cddc0, cddc1, cddc2, cddc3 }*/
{ 0, 0, 0, 0 }, /* uc0 */
{ 1842.5e6, 1842.5e6, 350e6, 350e6 }, /* uc1 */
{ 1842.5e6, 1842.5e6, 350e6, 350e6 }, /* uc2 */
{ 1842.5e6, 350e6, 0, 0 }, /* uc3 */
{ 1842.5e6, 350e6, 0, 0 }, /* uc4 */
{ 396e6, 55e6, 768e6, 0 }, /* uc5 */
{ 396e6, 396e6, 396e6, 396e6 }, /* uc6 */
{ 396e6, 396e6, 396e6, 396e6 }, /* uc7 */
{ 396e6, 55e6, 768e6, 0 }, /* uc8 */
{ 0, 0, 0, 0 }, /* uc9 */
{ 366e6, 376e6, 386e6, 396e6 }, /* uc10*/
{ 366e6, 376e6, 386e6, 396e6 }, /* uc11*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc12*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc13*/
{ 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0 }, /* uc15*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc16*/
{ 0, 0, 0, 0 }, /* uc17*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc18*/
{ 1100e6, 1100e6, 1900e6, 1900e6}, /* uc19*/
{ 900e6, 900e6, 2100e6, 2100e6}, /* uc20*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc21*/
{ 0, 0, 0, 0 }, /* uc22*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc23*/
{ 396e6, 396e6, 396e6, 396e6 }, /* uc24*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc25*/
{-125e6, -700e6, -125e6, -700e6 }, /* uc26*/
{-125e6, -700e6, -125e6, -700e6 }, /* uc27*/
{ 0, 0, 0, 0 }, /* uc28*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc29*/
{ 1000e6, 1000e6, 0, 0 }, /* uc30*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc31*/
{ 0, 0, 0, 0 }, /* uc32*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc33*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc34*/
{ 0, 0, 0, 0 }, /* uc35*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc36*/
{ 120e6, 120e6, 120e6, 120e6 }, /* uc37*/
{ 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0 }, /* uc39*/
{ 1000e6, 1000e6, 1000e6, 1000e6}, /* uc40*/
{ 0, 0, 0, 0 }, /* uc41*/
};
/* RX Main Path DDC Data Decimation
* List the ADC_Coarse DDCs desired data decimation
* Each usecase has an Array of depth 4, each member value is the desired decimation of a Coarse DDC Datapath,
* where index 0 = Decimation Factor for<6F> Coarse DDC 0, index 1 = decimation Factor for<6F>Coarse DDC 1 etc
*
* For example: rx_cddc_dcm[1][0] =AD9081_CDDC_DCM_2,
* For Use case 1, Frequency Factor for Coarse DDC0 is 1
* Use adi_ad9082_adc_coarse_ddc_dcm_e to set the decimation setting
*/
uint8_t rx_cddc_dcm[][4] = {
/*{cddc0, cddc1, cddc2, cddc3} */
{ 0 }, /* uc0 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc1 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc2 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc3 */
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc4 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_4 }, /* uc5 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc6 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc7 */
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_1, AD9081_CDDC_DCM_4 }, /* uc8 */
{ 0 }, /* uc9 */
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc10*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc11*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc12*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc13*/
{ 0 }, /* uc14*/
{ 0 }, /* uc15*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc16*/
{ 0 }, /* uc17*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc18*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc19*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc20*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc21*/
{ 0 }, /* uc22*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc23*/
{ AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3, AD9081_CDDC_DCM_3 }, /* uc24*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc25*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc26*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc27*/
{ 0 }, /* uc28*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc29*/
{ AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2, AD9081_CDDC_DCM_2 }, /* uc30*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc31*/
{ 0 }, /* uc32*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc33*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc34*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc35*/
{ AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6, AD9081_CDDC_DCM_6 }, /* uc36*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc37*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc38*/
{ 0 }, /* uc39*/
{ AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4, AD9081_CDDC_DCM_4 }, /* uc40*/
{ 0 }, /* uc41*/
};
/* RX Main Path DDC Has Optional Complex to Real Convertor
* rx_cddc_c2r sets the enable for Complex to Real Converter per Main/Coarse DDC
* Each usecase has an Array of depth 4, each member value is the enable of a Coarse DDC Datapath Complex to Real Converter
* where index 0 = Enable Complex to Real Convertor for Coarse DDC 0,
* index 1 = Enable Complex to Real Convertor for Coarse DDC 1
*
* For example: rx_cddc_c2r[1][0] = 0,
* For Use case 1, Complex to Real Converter for Coarse DDC 0 is Disabled
*
*/
uint8_t rx_cddc_c2r[][4] = { /* cddc0, cddc1, cddc2, cddc3 */
{ 0, 0, 0, 0 }, /* uc0 */
{ 0, 0, 0, 0 }, /* uc1 */
{ 0, 0, 0, 0 }, /* uc2 */
{ 0, 0, 0, 0 }, /* uc3 */
{ 0, 0, 0, 0 }, /* uc4 */
{ 0, 0, 0, 0 }, /* uc5 */
{ 0, 0, 0, 0 }, /* uc6 */
{ 0, 0, 0, 0 }, /* uc7 */
{ 0, 0, 0, 0 }, /* uc8 */
{ 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0 }, /* uc11*/
{ 0, 0, 0, 0 }, /* uc12*/
{ 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0 }, /* uc15*/
{ 0, 0, 0, 0 }, /* uc16*/
{ 0, 0, 0, 0 }, /* uc17*/
{ 0, 0, 0, 0 }, /* uc18*/
{ 0, 0, 0, 0 }, /* uc19*/
{ 0, 0, 0, 0 }, /* uc20*/
{ 0, 0, 0, 0 }, /* uc21*/
{ 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0 }, /* uc27*/
{ 0, 0, 0, 0 }, /* uc28*/
{ 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0 }, /* uc41*/
};
/* RX Channelizer/Fine DDC Datapath Selection
* List the ADC Fine DDCs data path for routing Data from Main/ Coarse DDC Datapth to the JESD Tx
* Each usecase has an Array of depth 1, each member value is the masked list of Fine DDCs to be selected
* Note Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC0- Fine DDC3 datapaths and
* Coarse DDC0 & Coarse DDC1 can be routed to Fine DDC4- Fine DDC6 datapaths
* For example: rx_fddc_select[3] = AD9081_ADC_FDDC_0 |AD9081_ADC_FDDC_1,
* For Use case 3, Fine DDC 0 and Fine DDC 1 are enabled
* Use adi_ad9082_adc_fine_ddc_select_e to create the list of fine DDCs to be enabled
* Note: Based on the input from the user, will apply a recommended muxing from CDDC to FDDC,
* An Error will be returned if the muxing is not supported for that devices,
* Note: If Fine DDC Decimation Factor is set to 1, Fine DDC in the Channel will be disabled
*
*/
uint8_t rx_fddc_select[] = {
0, /* uc0 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc1 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc2 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc3 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc4 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc5 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc6 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc7 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc8 */
0, /* uc9 */
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc10*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc11*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_2 | AD9081_ADC_FDDC_3 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5 | AD9081_ADC_FDDC_6 | AD9081_ADC_FDDC_7, /* uc12*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc13*/
0, /* uc14*/
0, /* uc15*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc16*/
0, /* uc17*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc18*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_2 | AD9081_ADC_FDDC_3 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5 | AD9081_ADC_FDDC_6 | AD9081_ADC_FDDC_7, /* uc19*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc20*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc21*/
0, /* uc22*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc23*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc24*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc25*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc26*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc27*/
0, /* uc28*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc29*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc30*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc31*/
0, /* uc32*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc33*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc34*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc35*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1, /* uc36*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_4, /* uc37*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc38*/
0, /* uc39*/
AD9081_ADC_FDDC_0 | AD9081_ADC_FDDC_1 | AD9081_ADC_FDDC_4 | AD9081_ADC_FDDC_5, /* uc40*/
0, /* uc41*/
};
/* RX Channelizer Path DDC NCO Frequency Configuration
* List the ADC_Fine DDCs desired Frequency Shift
* Each usecase has an Array of depth 8, each member value is the desired frequency shift (MHz)of a Fine DDC Datapath,
* where index 0 = Frequency Shift for<6F> Fine DDC 0, index 1 = Frequency Shift for<6F>Fine DDC 1 etc
*
* For example: rx_fddc_shift[0][0] = 1842.5e6,
* For Use case 0, Frequency Shift for Fine DDC0 is 1842.5e6MHz
*/
int64_t rx_fddc_shift[][8] = {
/* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc0 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc1 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc2 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc3 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc4 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc5 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc6 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc7 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc8 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc9 */
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc10*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc11*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc12*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc13*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc14*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc15*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc16*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc17*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc18*/
{-200e6, 200e6, -200e6, 200e6, -200e6, 200e6, -200e6, 200e6 }, /* uc19*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc20*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc21*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc22*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc23*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc24*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc25*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc26*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc27*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc28*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc29*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc30*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc31*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc32*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc33*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc34*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc35*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc36*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc37*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc38*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc39*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc40*/
{ 0, 0, 0, 0, 0, 0, 0, 0 }, /* uc41*/
};
/* RX Channelizer Data Decimation
* List the ADC Fine DDCs desired data decimation
* Each usecase has an Array of depth 8, each member value is the desired decimation of a Fine DDC Datapath,
* where index 0 = Decimation factor for<6F> Fine DDC 0, index 1 = decimation factor for<6F>Fine DDC 1 etc
* Note where No Fine DDC Decimation is required (bypassed), Decimation factor is set to 1,AD9081_FDDC_DCM_1
*
* For example: rx_fddc_dcm[1][0] =AD9081_FDDC_DCM_4,
* For Use case 1, Decimation Factor for FineDDC0 is 4
* Use adi_ad9082_adc_fine_ddc_dcm_e to set the decimation setting
*/
uint8_t rx_fddc_dcm[][8] = { /* fddc0, fddc1, fddc2, fddc3, fddc4, fddc5, fdddc6, fddc7 */
{ 0 }, /* uc0 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc1 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc2 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc3 */
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc4 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc5 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc6 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc7 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc8 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc9 */
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc10*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc11*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2 }, /* uc12*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc13*/
{ 0 }, /* uc14*/
{ 0 }, /* uc15*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc16*/
{ 0 }, /* uc17*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc18*/
{ AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3, AD9081_FDDC_DCM_3 }, /* uc19*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc20*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc21*/
{ 0 }, /* uc22*/
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc23*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2 }, /* uc24*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc25*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc26*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc27*/
{ 0 }, /* uc28*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc29*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc30*/
{ AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc31*/
{ 0 }, /* uc32*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0, AD9081_FDDC_DCM_4, AD9081_FDDC_DCM_4 }, /* uc33*/
{ AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2, 0, 0, AD9081_FDDC_DCM_8, AD9081_FDDC_DCM_8 }, /* uc34*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc35*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc36*/
{ AD9081_FDDC_DCM_1, 0, 0, 0, AD9081_FDDC_DCM_1 }, /* uc37*/
{ AD9081_FDDC_DCM_2, 0, 0, 0, AD9081_FDDC_DCM_2, AD9081_FDDC_DCM_2 }, /* uc38*/
{ 0 }, /* uc39*/
{ AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1, 0, 0, AD9081_FDDC_DCM_1, AD9081_FDDC_DCM_1 }, /* uc40*/
{ 0 }, /* uc41*/
};
uint8_t rx_fddc_c2r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* uc */
/* Link Settings */
/* Rx Channelizer Virtual Converter Mapping
* Maps the output of a Fine DDC Data Format O/P to a JESD TX virtual converter
* Refer to Mux 4 in the Rx Digital Datapath section of the System Developer Userguide
*
* adi_ad9082_adc_fine_ddc_converter_e enerates the Fine DCC I & Q Outputs
* Each virtual converter in the JESD TX link must be assigned a source data, Fine DDC X I or Q
* Note this should be set carefully and reflect the Fine DDC selected in rx_fddc_select and also JESD TX Configuration
*
* Each usecase has an Array of depth 2, each member a list of the source of data for the virtual converter for the JESD TX Link
* where index 0 = Sources of Data for JESD TX Link 0
* where index 1 = Sources of Data for JESD TX Link 1
*
* For example: For Use Case 29 with is a Dual link JESD Mode with M =4, we specify the I & Q source for each virtual Converter
* jtx_conv_sel[28][0]={AD9081_FDDC_0_I,AD9081_FDDC_0_Q,AD9081_FDDC_1_I,AD9081_FDDC_1_Q }
* jtx_conv_sel[28][1]={AD9081_FDDC_4_I,AD9081_FDDC_4_Q,AD9081_FDDC_5_I,AD9081_FDDC_5_Q }
*/
adi_ad9081_jtx_conv_sel_t jtx_conv_sel[][2] = {
{ { 0 } }, /* uc0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc1.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc2.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc3.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc3.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc4.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc4.link1 */
{ { AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q }, /* uc5.link0 */
{ AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc5.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc6.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc6.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc7.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc7.link1 */
{ { AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q }, /* uc8.link0 */
{ AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc8.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q } }, /* uc9.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc10.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc11.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_2_I, AD9081_FDDC_2_Q, AD9081_FDDC_3_I, AD9081_FDDC_3_Q, /* uc12.link0 */
AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q, AD9081_FDDC_6_I, AD9081_FDDC_6_Q, AD9081_FDDC_7_I, AD9081_FDDC_7_Q } }, /* uc12.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc13.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc14.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q } }, /* uc15.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc16.link0 */
{ { 0 } }, /* uc17.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc18.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc18.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_2_I, AD9081_FDDC_2_Q, AD9081_FDDC_3_I, AD9081_FDDC_3_Q, /* uc19.link0 */
AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q, AD9081_FDDC_6_I, AD9081_FDDC_6_Q, AD9081_FDDC_7_I, AD9081_FDDC_7_Q } }, /* uc19.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc20.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc21.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc22.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc23.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc24.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc24.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc25.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc26.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc27.link0 */
{ { 0 } }, /* uc28.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc29.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc29.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc30.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc31.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc32.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc33.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc33.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q }, /* uc34.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc34.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc35.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc36.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q } }, /* uc37.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc38.link0 */
{ AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc38.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q }, /* uc39.link0 */
{ AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc39.link1 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q, AD9081_FDDC_4_I, AD9081_FDDC_4_Q, AD9081_FDDC_5_I, AD9081_FDDC_5_Q } }, /* uc40.link0 */
{ { AD9081_FDDC_0_I, AD9081_FDDC_0_Q, AD9081_FDDC_1_I, AD9081_FDDC_1_Q } }, /* uc41.link0 */
};
/* Total Decimation Settings */
/* The total decimation is used to calculate lane rate for each link which in
* turn is used to determine FPGA clock sources and line rates for JESD204B
*
* Each usecase has an Array of depth 2,
* where index 0 = Total decimation for link 0
* where index 1 = Total decimation for link 1
*
* For example: For Use Case 3 with is a Dual link JESD Mode, total decimation for each link
* jtx_chip_dcm[3][0]= 8
* jtx_chip_dcm[3][1]= 8
*/
uint8_t jtx_chip_dcm[][2] = {
{ 0 }, /* uc0.link0 */
{ 8 }, /* uc1.link0 */
{ 8 }, /* uc2.link0 */
{ 8 , /* uc3.link0 */
8 }, /* uc3.link1 */
{ 8 , /* uc4.link0 */
8 }, /* uc4.link1 */
{ 2 , /* uc5.link0 */
4 }, /* uc5.link1 */
{ 4 , /* uc6.link0 */
4 }, /* uc6.link1 */
{ 4 , /* uc7.link0 */
4 }, /* uc7.link1 */
{ 1 , /* uc8.link0 */
4 }, /* uc8.link1 */
{ 1 }, /* uc9.link0 */
{ 3 }, /* uc10.link0 */
{ 3 }, /* uc11.link0 */
{ 4 }, /* uc12.link0 */
{ 4 }, /* uc13.link0 */
{ 1 }, /* uc14.link0 */
{ 1 }, /* uc15.link0 */
{ 3 }, /* uc16.link0 */
{ 0 }, /* uc17.link0 */
{ 4 , /* uc18.link0 */
4 }, /* uc18.link1 */
{ 12}, /* uc19.link0 */
{ 4 }, /* uc20.link0 */
{ 3 }, /* uc21.link0 */
{ 1 }, /* uc22.link0 */
{ 16}, /* uc23.link0 */
{ 6 , /* uc24.link0 */
6 }, /* uc24.link1 */
{ 2 }, /* uc25.link0 */
{ 2 }, /* uc26.link0 */
{ 2 }, /* uc27.link0 */
{ 0 }, /* uc28.link0 */
{ 4 , /* uc29.link0 */
4 }, /* uc29.link1 */
{ 2 }, /* uc30.link0 */
{ 16}, /* uc31.link0 */
{ 1 }, /* uc32.link0 */
{ 12 , /* uc33.link0 */
24}, /* uc33.link1 */
{ 12 , /* uc34.link0 */
48}, /* uc34.link1 */
{ 6 }, /* uc35.link0 */
{ 6 }, /* uc36.link0 */
{ 4 }, /* uc37.link0 */
{ 8 , /* uc38.link0 */
8 }, /* uc38.link1 */
{ 1 , /* uc39.link0 */
1 }, /* uc39.link1 */
{ 4 }, /* uc40.link0 */
{ 1 }, /* uc41.link0 */
};
uint8_t jtx_logiclane_mapping_pe_brd[2][8] = { { 0, 1, 2, 3, 4, 5, 6, 7 }, { 4, 5, 6, 7, 0, 1, 2, 3 } };
uint8_t jtx_logiclane_mapping_ce_brd[2][8] = { { 6, 4, 3, 2, 1, 0, 7, 5 }, { 2, 0, 7, 7, 7, 7, 3, 1 } };
adi_cms_jesd_param_t jrx_param[] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
{ 8, 4, 16, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 16 }, /* uc0 : nco test */
{ 4, 4, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 9, }, /* uc1 : txmode = 194 */
{ 8, 4, 16, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 16 }, /* uc2 : txmode = 214 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10 }, /* uc3 : txmode = 437 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10 }, /* uc4 : txmode = 440 */
{ 4, 1, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 62 }, /* uc5 : txmode = 263 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc6 : txmode = 258 */
{ 4, 1, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 62 }, /* uc7 : txmode = 266 */
{ 4, 1, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 62 }, /* uc8 : txmode = 263 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc9 : txmode = 258 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc10: txmode = 378 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc11: txmode = 378 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc12: txmode = 91 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc13: txmode = 378 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc14: txmode = 88 */
{ 8, 3, 4, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 35 }, /* uc15: txmode = 573 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc16: txmode = 91 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc17: txmode = 258 */
{ 0 }, /* uc18: rx only */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16 }, /* uc19: txmode = 371 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc20: txmode = 99 */
{ 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16 }, /* uc21: txmode = 91 */
{ 0 }, /* uc22: rx only */
{ 4, 4, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 9 }, /* uc23: txmode = 417 */
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc24: txmode = 248 */
{ 4, 2, 4, 1, 1, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 10 }, /* uc25: txmode = 97 */
{ 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 24 }, /* uc26: txmode = 140 */
{ 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 24 }, /* uc27: txmode = 140 */
{ 8, 1, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 17 }, /* uc28: txmode = 258 */
{ 0 }, /* uc29: rx only */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc30: txmode = 99 */
{ 0 }, /* uc31: rx only */
{ 8, 1, 4, 1, 1, 256, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 17 }, /* uc32: txmode = ??? */
{ 0 }, /* uc33: rx only */
{ 0 }, /* uc34: rx only */
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc35: */
{ 8, 2, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc36: */
{ 8, 2, 8, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 15 }, /* uc37: */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 10 }, /* uc38 */
{ 0 }, /* uc39: rx only */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 15 }, /* uc40: txmode = 378 */
{ 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 15 }, /* uc41: txmode = 378 */
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode */
};
adi_cms_jesd_param_t jtx_param[][2] = {
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
{ { 0 } }, /* uc0 : nco test */
{ { 4, 4, 8, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10, 0, 0 } }, /* uc1 : rxmode = 392, link0 */
{ { 4, 4, 8, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10, 0, 0 } }, /* uc2 : rxmode = 392, link0 */
{ { 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 }, /* uc3 : rxmode = 360, link0 */
{ 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 } }, /* uc3 : rxmode = 360, link1 */
{ { 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 }, /* uc4 : rxmode = 360, link0 */
{ 2, 2, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 } }, /* uc4 : rxmode = 360, link1 */
{ { 4, 1, 1, 2, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 13, 0, 0 }, /* uc5 : rxmode = 1088,link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc5 : rxmode = 411, link1 */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc6 : rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc6 : rxmode = 411, link1 */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc7 : rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc7 : rxmode = 411, link1 */
{ { 4, 1, 1, 2, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 13, 0, 0 }, /* uc8 : rxmode = 1087,link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc8 : rxmode = 411, link1 */
{ { 8, 1, 2, 2, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 19, 0, 0 } }, /* uc9 : rxmode = 502, link0 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc10: rxmode = 226, link0 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc11: rxmode = 226, link0 */
{ { 8, 4, 16, 1, 0, 64, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 17, 0, 0 } }, /* uc12: rxmode = 234, link0 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc13: rxmode = 227, link0 */
{ { 8, 1, 4, 1, 0, 256, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 18, 0, 0 } }, /* uc14: rxmode = 252, link0 */
{ { 8, 3, 2, 8, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 28, 0, 0 } }, /* uc15: rxmode = 1263,link0 */
{ { 8, 6, 8, 4, 0, 128, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 26, 0, 1 } }, /* uc16: rxmode = 1260,link0 */
{ { 0 } }, /* uc17: tx only */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc18: rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc18: rxmode = 411, link1 */
{ { 8, 4, 16, 1, 0, 64, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 17, 0, 0 } }, /* uc19: rxmode = 239, link0 */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc20: rxmode = 227, link0 */
{ { 8, 6, 8, 4, 0, 128, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 26, 0, 1 } }, /* uc21: rxmode = 1260,link0 */
{ { 8, 3, 4, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 0, 2, 27, 0, 0 } }, /* uc22: rxmode = 1261,link0 */
{ { 4, 4, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 10, 0, 0 } }, /* uc23: rxmode = 397, link0 */
{ { 2, 2, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 }, /* uc24: rxmode = 358, link0 */
{ 2, 2, 2, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 7, 0, 0 } }, /* uc24: rxmode = 358, link1 */
{ { 4, 2, 4, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 11, 0, 0 } }, /* uc25: rxmode = 1452,link0 */
{ { 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 26, 0, 0 } }, /* uc26: rxmode = 1565,link0 */
{ { 8, 3, 8, 2, 0, 256, 12, 12, 0, 0, 0, 0, 0, 1, 1, 0, 2, 26, 0, 0 } }, /* uc27: rxmode = 1565,link0 */
{ { 0 } }, /* uc28: tx only */
{ { 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc29: rxmode = 411, link0 */
{ 4, 2, 4, 1, 1, 32, 12, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc29: rxmode = 411, link1 */
{ { 8, 2, 8, 1, 0, 128, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 16, 0, 0 } }, /* uc30: rxmode = 225,link0 */
{ { 2, 8, 8, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 4, 0, 0 } }, /* uc31: rxmode = 411, link0 */
{ { 8, 1, 4, 1, 1, 256, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 18, 0, 0 } }, /* uc32: rxmode = ???, link0 */
{ { 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc33: rxmode = , link0 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc33: rxmode = , link1 */
{ { 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 }, /* uc34: rxmode = , link0 */
{ 4, 2, 4, 1, 0, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc34: rxmode = , link1 */
{ { 8, 1, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 18, 0, 0 } }, /* uc35: rxmode */
{ { 8, 1, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 18, 0, 0 } }, /* uc36: rxmode */
{ { 8, 1, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 0, 1, 18, 0, 0 } }, /* uc37: rxmode */
{ { 4, 1, 2, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 13, 0, 0 }, /* uc38: rxmode = , link0 */
{ 4, 2, 4, 1, 1, 32, 16, 16, 0, 0, 0, 0, 0, 0, 1, 1, 1, 11, 0, 0 } }, /* uc38: rxmode = , link1 */
{ { 4, 3, 2, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 1, 2, 14, 0, 0 }, /* uc39: rxmode = 1261,link0 */
{ 4, 3, 2, 4, 0, 256, 12, 12, 0, 0, 0, 0, 0, 0, 1, 1, 2, 14, 0, 0 } }, /* uc39: rxmode = 1261,link1 */
{ { 8, 2, 8, 1, 0, 128, 12, 16, 0, 0, 0, 0, 0, 1, 1, 0, 2, 16, 0, 0 } }, /* uc40: rxmode = 227, link0 */
{ { 8, 1, 4, 1, 0, 256, 12, 16, 0, 0, 0, 0, 0, 0, 1, 0, 2, 18, 0, 0 } }, /* uc41: rxmode = 252, link0 */
/*L F M S HD K N N' CF CS DID BID LID SC SCR Dual V Mode C2R ModeS */
};