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Brian Kiedinger
2025-03-30 21:43:59 -05:00
commit 18988b8656
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.gitignore vendored Normal file
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Packages
radar_alinx_kintex.cache
radar_alinx_kintex.gen
radar_alinx_kintex.hw
radar_alinx_kintex.ioplanning
radar_alinx_kintex.ip_user_files
radar_alinx_kintex.runs
radar_alinx_kintex.sim

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python/.gitignore vendored Normal file
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__pycache__
.idea
*.zip
*.bin

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python/data_recorder.py Executable file
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import socket
import numpy as np
import ctypes
import data_structures
import threading
import queue
import os
import mmap
class DataRecorder:
def __init__(self,
host="192.168.2.128",
port=1234,
packet_size=4096):
# # TESTTTT
# self.s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
# print('SO_RCVBUF', self.s.getsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF))
# self.s.setsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF, 4 * 1024 * 1024)
# print('SO_RCVBUF', self.s.getsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF))
# self.s.settimeout(1)
# self.s.bind(("", 1234))
# data = np.arange(16, dtype=np.uint32)
# data = data.tobytes()
# self.s.sendto(data, (host, 1234))
# self.s.close()
# # TESTTTTT
# UDP Socket for High Speed Data
self.ip = host
self.port = port
self.s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
print('SO_RCVBUF', self.s.getsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF))
self.s.setsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF, 4 * 1024 * 1024)
print('SO_RCVBUF', self.s.getsockopt(socket.SOL_SOCKET, socket.SO_RCVBUF))
self.s.settimeout(1)
self.s.bind(("", port))
# Need to send one udp message to set IP and port info inside FPGA
data = np.arange(16, dtype=np.uint32)
data = data.tobytes()
self.s.sendto(data, (self.ip, self.port))
self.max_packet_size = packet_size
# Data Buffer
# self.buffer = bytearray(512 * 1024 * 1024)
self.buffer = mmap.mmap(-1, 512 * 1024 * 1024)
self.buffer_view = memoryview(self.buffer)
self.stop_event = threading.Event()
self.fid = None
self.write_to_disk = False
self.write_offset = 0
self.write_count = 0
self.write_queue = queue.SimpleQueue()
def start_recording(self, filename, write_to_disk=False):
self.write_to_disk = write_to_disk
if write_to_disk:
self.write_offset = 0
self.write_count = 0
self.fid = os.open(filename, os.O_WRONLY | os.O_CREAT | os.O_TRUNC | os.O_DIRECT )
self.write_queue = queue.SimpleQueue()
self.write_data_thread = threading.Thread(target=self.write_data)
self.write_data_thread.start()
self.get_data_thread = threading.Thread(target=self.get_data)
self.get_data_thread.start()
def stop_recording(self):
print('Stop Thread')
self.stop_event.set()
self.get_data_thread.join()
print('Get Data Thread Joined')
if self.write_to_disk:
self.write_data_thread.join()
print('Write Data Thread Joined')
def write_data(self):
write_chunk_size = 4 * 1024 * 1024
buffer_view = memoryview(self.buffer)
print('Waiting For Data to Write')
while not self.stop_event.is_set():
try:
num_bytes = self.write_queue.get(timeout=1)
self.write_count += num_bytes
if self.write_count > write_chunk_size:
# print(self.write_offset)
# os.write(self.fid, self.buffer[self.write_offset:self.write_offset + write_chunk_size])
os.write(self.fid, buffer_view[self.write_offset:self.write_offset + write_chunk_size])
self.write_offset += write_chunk_size
self.write_count -= write_chunk_size
self.write_offset = self.write_offset % len(self.buffer)
except queue.Empty:
print('DR Queue Empty!', self.ip)
def get_data(self):
offset = 0
print('Waiting For Data From Socket')
while not self.stop_event.is_set():
try:
n = self.s.recv_into(self.buffer_view[offset:offset + self.max_packet_size])
if self.write_to_disk:
self.write_queue.put(n)
offset += n
offset = offset % len(self.buffer)
# print(offset)
except socket.timeout:
continue

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python/data_structures.py Executable file
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import ctypes
from ctypes import Structure, c_uint64, c_uint32, c_uint16, c_uint8, c_float
AXI_WRITE_REG = 1
AXI_READ_REG = 2
AXI_READ_RESP = 3
ACK_MSG = 4
NACK_MSG = 5
AXI_WRITE_REG_BURST = 6
RF_SPI_WRITE = 7
SET_AD9081_DAC_NCO = 128
SET_AD9081_ADC_NCO = 129
ACK_FLAG_VALID_PACKET = 0x01
ACK_FLAG_VALID_EXECUTION = 0x02
ACK_FLAG_GOT_FRAME_END = 0x04
MAX_BURST_LENGTH = 512
HDR_FLAG_REQ_ACK = 0x01
class CpiHeader(Structure):
_pack_ = 1
_fields_ = [
("sync", c_uint32),
("num_pulses", c_uint32),
("num_samples", c_uint32),
("start_sample", c_uint32),
("tx_num_samples", c_uint32),
("tx_start_sample", c_uint32),
("pri", c_uint32),
("inter_cpi", c_uint32),
# ("spare", c_uint32), # Populated by FPGA
("pps_sec", c_uint64), # Populated by FPGA
("pps_frac_sec", c_uint64), # Populated by FPGA
("system_time", c_uint64), # Populated by FPGA
("tx_lo_offset", c_float),
("rx_lo_offset", c_float),
("data1", c_uint32 * 240) # Populated by user
]
class Header(Structure):
_pack_ = 1
_fields_ = [
("fsync", c_uint32),
("type", c_uint16),
("flags", c_uint16),
("length", c_uint16)
]
# Have to put this here to get pycharm autocomplete to work, don't like this, but autocomplete is too convenient
def __init__(self):
self.fsync = 0xAABBCCDD
self.type = 0
self.flags = 0
self.length = 0
def init_header(self, msg_id):
self.header = Header()
self.header.type = msg_id
self.header.length = ctypes.sizeof(self)
class WriteRegType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("address", c_uint32),
("data", c_uint32)
]
def __init__(self):
init_header(self, AXI_WRITE_REG)
self.address = 0
self.data = 0
class WriteRegBurstType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("address", c_uint32),
("length", c_uint32),
("data", c_uint32 * MAX_BURST_LENGTH)
]
def __init__(self):
init_header(self, AXI_WRITE_REG_BURST)
self.address = 0
self.length = 0
class AckType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("flags", c_uint32)
]
def __init__(self):
init_header(self, ACK_MSG)
self.flags = 0
class ReadRequestType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("address", c_uint32)
]
def __init__(self):
init_header(self, AXI_READ_REG)
self.address = 0
class ReadResponseType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("data", c_uint32)
]
def __init__(self):
init_header(self, AXI_READ_RESP)
self.data = 0
class DacNcoConfigType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("channel", c_uint32),
("frequency", c_float)
]
def __init__(self):
init_header(self, SET_AD9081_DAC_NCO)
self.channel = 0
self.frequency = 0
class AdcNcoConfigType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("channel", c_uint32),
("frequency", c_float)
]
def __init__(self):
init_header(self, SET_AD9081_ADC_NCO)
self.channel = 0
self.frequency = 0
class RfSpiWriteType(Structure):
_pack_ = 1
_fields_ = [
("header", Header),
("dev_sel", c_uint32),
("num_bits", c_uint32),
("data", c_uint32)
]
def __init__(self):
init_header(self, RF_SPI_WRITE)
self.dev_sel = 0
self.num_bits = 0
self.data = 0

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import ctypes
import datetime
import ipaddress
import socket
import struct
import time
import numpy as np
import data_structures as msg_types
from data_structures import CpiHeader
TIMING_ENGINE_ADDR = 0x40051000
DIG_RX_ADDR = 0x20000000
DIG_RX_STRIDE = 0x10000
WAVEFORM_GEN_ADDR = 0x40053000
NUM_RX = 2
def form_chirp(pulsewidth, bw, sample_rate, win=None, ):
n = int(np.round(pulsewidth * sample_rate))
d_t = 1 / sample_rate
f = np.linspace(-bw/2, bw/2, n)
phi = np.cumsum(2 * np.pi * f * d_t)
x = np.exp(-1j * phi)
return x.astype(np.complex64)
class RadarManager:
def __init__(self,
host="192.168.1.200",
port=5001):
self.host = host
self.port = port
self.s = None
self.CONNECTED = False
self.connect()
# Update UDP packet size
self.packet_size = 4096
self.axi_write_register(0x4005001C, self.packet_size)
self.reset_10g_udp()
self.stop_running()
def connect(self):
self.CONNECTED = False
retry_cnt = 0
while True:
try:
self.s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
self.s.settimeout(5)
self.s.connect((self.host, self.port))
self.s.setsockopt(socket.IPPROTO_TCP, socket.TCP_NODELAY, 1)
self.s.settimeout(5)
self.CONNECTED = True
break
except socket.error as e:
print("Connection Error %s" % e)
# print("Connection Timeout, trying again %d" % retry_cnt)
self.CONNECTED = False
retry_cnt += 1
if retry_cnt >= 1:
break
return self.CONNECTED
def disconnect(self):
self.s.close()
self.CONNECTED = False
def is_connected(self):
return self.CONNECTED
def send_bytes(self, msg_bytes):
self.s.sendall(msg_bytes)
def send_message(self, msg, update_hdr=True, enable_ack=True, wait_for_ack=True, timeout=10):
self.s.settimeout(timeout)
ret = True
msg.header.flags = 0
# Request a completion ACK
if enable_ack:
msg.header.flags = msg_types.HDR_FLAG_REQ_ACK
# Serialize message and send
self.send_bytes(bytes(msg))
# Need to wait for response
if wait_for_ack:
recv_bytes, err = self.get_response(ctypes.sizeof(msg_types.AckType))
resp = msg_types.AckType.from_buffer_copy(recv_bytes)
ret = True
return ret
def get_response(self, size):
recv_data = bytearray()
while len(recv_data) < size:
try:
recv_data += self.s.recv(size, 0)
except socket.timeout as e:
return 0, -1
return recv_data, 0
def axi_write_register(self, address, data):
# Make sure address is word aligned
address -= (address % 4)
# Form message
msg = msg_types.WriteRegType()
msg.address = address
msg.data = data
self.send_message(msg)
return
def axi_write_register_burst(self, address, data):
# Make sure address is word aligned
address -= (address % 4)
# Form message
msg = msg_types.WriteRegBurstType()
msg.address = address
msg.length = len(data)
for i in range(len(data)):
msg.data[i] = data[i]
self.send_message(msg)
return
def axi_read_register(self, address):
# Make sure address is word aligned
address -= (address % 4)
# Form message
msg = msg_types.ReadRequestType()
msg.address = address
self.send_message(msg, enable_ack=False, wait_for_ack=False)
# Get response
recv_bytes, _ = self.get_response(ctypes.sizeof(msg_types.ReadResponseType))
resp = msg_types.ReadResponseType.from_buffer_copy(recv_bytes)
return resp.data
def set_dac_nco(self, channel, frequency):
# Form message
msg = msg_types.DacNcoConfigType()
msg.channel = channel
msg.frequency = frequency
self.send_message(msg)
return
def set_adc_nco(self, channel, frequency):
# Form message
msg = msg_types.AdcNcoConfigType()
msg.channel = channel
msg.frequency = frequency
self.send_message(msg)
return
def rf_spi_write(self, dev_sel, num_bits, data):
# Form message
msg = msg_types.RfSpiWriteType()
msg.dev_sel = dev_sel
msg.num_bits = num_bits
msg.data = data
self.send_message(msg)
return
def load_waveform(self, ch, amp, bw, pw):
addr = 0x0010000 + 0x0010000 * ch
print('Load', hex(addr))
num_samples = pw
wf = form_chirp(pw, bw, 1)
wf = wf * amp
bram_address = addr
iq = wf * 0x7FFF
iq_real = iq.real.astype(np.uint16)
iq_imag = iq.imag.astype(np.uint16)
iq_real = iq_real.astype(np.uint32)
iq_imag = iq_imag.astype(np.uint32)
data = iq_real | (iq_imag << 16)
num_bursts = num_samples / msg_types.MAX_BURST_LENGTH
num_bursts = int(np.ceil(num_bursts))
for i in range(num_bursts):
start_ind = i * msg_types.MAX_BURST_LENGTH
stop_ind = start_ind + msg_types.MAX_BURST_LENGTH
stop_ind = min(stop_ind, num_samples)
burst_data = data[start_ind:stop_ind]
self.axi_write_register_burst(bram_address + i * 4 * msg_types.MAX_BURST_LENGTH, burst_data)
def reset_10g_udp(self):
val = self.axi_read_register(0x40050008)
self.axi_write_register(0x40050008, val | (1 << 15))
self.axi_write_register(0x40050008, val)
time.sleep(2)
def setup_cpi_header(self, pri, inter_cpi, num_pulses, num_samples, start_sample,
tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset):
# Load Up header BRAM
header = CpiHeader()
header.sync = 0xAABBCCDD
header.num_pulses = num_pulses
header.num_samples = num_samples
header.start_sample = start_sample
header.tx_num_samples = tx_num_samples
header.tx_start_sample = tx_start_sample
header.pri = pri
header.inter_cpi = inter_cpi
header.tx_lo_offset = tx_lo_offset
header.rx_lo_offset = rx_lo_offset
data = np.frombuffer(bytes(header), dtype=np.uint32)
self.axi_write_register_burst(TIMING_ENGINE_ADDR + 0xC00, data)
def setup_timing_engine(self, pri, num_pulses, inter_cpi):
self.axi_write_register(TIMING_ENGINE_ADDR + 0x4, pri - 1)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x8, num_pulses)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x10, inter_cpi - 1)
def setup_rx(self, num_samples, start_sample):
for i in range(NUM_RX):
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x4, num_samples >> 2)
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x8, start_sample >> 2)
def setup_tx(self, num_samples, start_sample):
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 2)
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 2)
def start_running(self):
for i in range(NUM_RX):
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x0, 0) # RX Reset
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x0, 0) # TX Reset
self.axi_write_register(TIMING_ENGINE_ADDR + 0x0, 0) # Timing Reset (do this last)
def stop_running(self):
self.axi_write_register(TIMING_ENGINE_ADDR + 0x0, 1) # Timing Engine Reset
for i in range(NUM_RX):
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x0, 1) # RX Reset
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x0, 1) # TX Reset
def setup_rf_attenuators(self, rf_atten):
self.rf_spi_write(0, 6, rf_atten[0]) # TX0 RF (ADRF5730)
self.rf_spi_write(1, 6, rf_atten[1]) # TX1 RF (ADRF5730)
self.rf_spi_write(2, 6, rf_atten[2]) # RX0 RF (ADRF5721)
self.rf_spi_write(3, 6, rf_atten[3]) # RX0 IF (HMC624)
self.rf_spi_write(4, 6, rf_atten[4]) # RX1 RF (ADRF5721)
self.rf_spi_write(5, 6, rf_atten[5]) # RX1 IF (HMC624)
def configure_cpi(self, pri, inter_cpi, num_pulses, num_samples, start_sample,
tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset):
self.load_waveform(0, 1, 0.1, tx_num_samples)
self.load_waveform(1, 1, 0.1, tx_num_samples)
rf_atten = [1, 2, 3, 4, 5, 6]
self.setup_rf_attenuators(rf_atten)
# DAC at 5.25 GHz is in second nyquist
# ADC would be in 3rd nyquist
lo = 5.25e9
f_dac = 9e9
f_adc = 3e9
tx_lo = 5.25e9 % f_dac
rx_lo = 5.25e9 % f_adc
for i in range(4):
self.set_adc_nco(i, rx_lo)
self.set_dac_nco(0, tx_lo)
self.set_dac_nco(1, tx_lo)
self.set_dac_nco(2, tx_lo + tx_lo_offset)
self.set_dac_nco(3, tx_lo + rx_lo_offset)
self.setup_timing_engine(pri, num_pulses, inter_cpi)
self.setup_rx(num_samples, start_sample)
self.setup_tx(tx_num_samples, tx_start_sample)
self.setup_cpi_header(pri, inter_cpi, num_pulses, num_samples, start_sample,
tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset)

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import ctypes
import os.path
import time
import numpy as np
from matplotlib import pyplot as plt
import socket
import data_structures
import radar_manager
from data_recorder import DataRecorder
def db20(x):
return 20*np.log10(np.abs(x))
def db20n(x):
x = db20(x)
x = x - np.max(x)
return x
def main():
print('Hello')
clk = 187.5e6
# Parse Data
headers = []
offset = 0
file = 'test0.bin'
fid = open(file, 'rb')
# Find header, recording buffer could have wrapped depending on data rate and how long we ran for
hdr_sync = False
while not hdr_sync:
# data = recorder.buffer[offset:offset + 4]
data = fid.read(4)
sync_word = np.frombuffer(data, dtype=np.uint32)[0]
if sync_word == 0xAABBCCDD:
hdr_sync = True
print('Header found at offset', offset)
fid.seek(-4, 1)
# Get the first header
header = fid.read(ctypes.sizeof(data_structures.CpiHeader))
header = data_structures.CpiHeader.from_buffer_copy(header)
fid.seek(-ctypes.sizeof(data_structures.CpiHeader), 1)
# CPI Parameters (timing values are in clk ticks)
num_pulses = header.num_pulses
num_samples = header.num_samples
pri = header.pri
inter_cpi = header.inter_cpi
data_size = num_pulses * num_samples * 4
file_size = os.path.getsize(file)
expected_num_cpis = int(file_size / (ctypes.sizeof(data_structures.CpiHeader) + data_size))
print('Expected CPIS:', expected_num_cpis)
for i in range(expected_num_cpis):
# Get Header
data = fid.read(ctypes.sizeof(data_structures.CpiHeader))
headers.append(data_structures.CpiHeader.from_buffer_copy(data))
# Get CPI
data = fid.read(data_size)
# Check some header fields
cpi_times = np.array([x.system_time for x in headers]) / 187.5e6
pps_frac = np.array([x.pps_frac_sec for x in headers]) / 187.5e6
pps_sec = np.array([x.pps_sec for x in headers])
utc_time = pps_sec + pps_frac
print(pri, inter_cpi, num_pulses * pri + inter_cpi)
print(cpi_times - cpi_times[0])
print(pps_frac)
print(pps_sec - pps_sec[0])
# Plot last CPI
data2 = np.frombuffer(data, dtype=np.int16)
i = data2[0::2]
q = data2[1::2]
iq = i + 1j * q
iq = iq.reshape(-1, num_samples)
iq = iq + 1e-15
vmin = -60
vmax = 0
plt.figure()
plt.plot(np.diff(cpi_times))
plt.figure()
plt.plot(iq.T.real, '.-')
plt.plot(iq.T.imag, '--.')
plt.grid()
plt.figure()
plt.imshow(db20n(iq), aspect='auto', interpolation='nearest', vmin=vmin, vmax=vmax)
plt.ylabel('Pulse Count')
plt.xlabel('Sample Count')
plt.colorbar()
plt.show()
if __name__ == '__main__':
main()

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import ctypes
import time
import numpy as np
from matplotlib import pyplot as plt
import data_structures
import radar_manager
from data_recorder import DataRecorder
# Give 10g eth interface an ip and set MTU for better performance
# sudo ifconfig enp5s0f0 192.168.2.10 up mtu 5000
# sudo ifconfig enp5s0f1 192.168.3.10 up mtu 5000
# Note that increases the size of rmem_max in the linux kernel improves performance for data recording
# this can be done witht the following terminal command
# sudo sysctl -w net.core.rmem_max=1048576
def db20(x):
return 20*np.log10(np.abs(x))
def db20n(x):
x = db20(x)
x = x - np.max(x)
return x
def main():
print('Hello')
clk = 187.5e6
# CPI Parameters (timing values are in clk ticks)
num_pulses = 128
num_samples = 8192
start_sample = 0
tx_num_samples = 1024
tx_start_sample = start_sample
pri = int(.001 * clk)
inter_cpi = 50
tx_lo_offset = 10e6
rx_lo_offset = 0
pri_float = pri / clk
print('PRI', pri_float, 'PRF', 1 / pri_float)
print('Expected Data Rate', num_samples * 4 / pri_float / 1e6)
radar = radar_manager.RadarManager()
recorder0 = DataRecorder("192.168.2.128", 1234, packet_size=radar.packet_size)
recorder1 = DataRecorder("192.168.3.128", 1235, packet_size=radar.packet_size)
recorder0.start_recording('test0.bin', True)
recorder1.start_recording('test1.bin', True)
radar.configure_cpi(pri, inter_cpi, num_pulses, num_samples, start_sample,
tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset)
print('Start Running')
radar.start_running()
# Let it run for a bit
time.sleep(5)
# Stop running
radar.stop_running()
# Stop the data recorder
recorder0.stop_recording()
recorder1.stop_recording()
# Parse some data
# Find header, recording buffer could have wrapped depending on data rate and how long we ran for
recorders = [recorder0, recorder1]
for recorder in recorders:
headers = []
offset = 0
plot_recorder = recorder
hdr_sync = False
while not hdr_sync:
data = plot_recorder.buffer[offset:offset + 4]
sync_word = np.frombuffer(data, dtype=np.uint32)[0]
if sync_word == 0xAABBCCDD:
hdr_sync = True
print('Header found at offset', offset)
else:
offset += 4
num_cpi = 16
for i in range(num_cpi):
# Get Header
data = plot_recorder.buffer[offset:offset + ctypes.sizeof(data_structures.CpiHeader)]
offset += ctypes.sizeof(data_structures.CpiHeader)
headers.append(data_structures.CpiHeader.from_buffer_copy(data))
# Get CPI
data_size = num_pulses * num_samples * 4
data = plot_recorder.buffer[offset:offset + data_size]
offset += data_size
# Check some header fields
cpi_times = np.array([x.system_time for x in headers]) / 187.5e6
pps_frac = np.array([x.pps_frac_sec for x in headers]) / 187.5e6
pps_sec = np.array([x.pps_sec for x in headers])
utc_time = pps_sec + pps_frac
print(pri, inter_cpi, num_pulses * pri + inter_cpi)
print(cpi_times - cpi_times[0])
print(pps_frac)
print(pps_sec - pps_sec[0])
# Plot last CPI
data2 = np.frombuffer(data, dtype=np.int16)
i = data2[0::2]
q = data2[1::2]
iq = i + 1j * q
iq = iq.reshape(-1, num_samples)
iq = iq + 1e-15
vmin = -60
vmax = 0
fid, axs = plt.subplots(2)
axs[0].plot(iq.T.real, '.-')
axs[0].plot(iq.T.imag, '--.')
axs[0].grid()
axs[1].imshow(db20n(iq), aspect='auto', interpolation='nearest', vmin=vmin, vmax=vmax)
axs[1].set_ylabel('Pulse Count')
axs[1].set_xlabel('Sample Count')
plt.show()
if __name__ == '__main__':
main()

504
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc Executable file
View File

@@ -0,0 +1,504 @@
#-------------------------------------------
# Config
#-------------------------------------------
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
#-------------------------------------------
# Register False Paths
#-------------------------------------------
set_false_path -from [get_cells util_reg_i/reg_*]
set_false_path -from [get_cells timing_engine_i/reg_*]
set_false_path -from [get_cells timing_engine_i/system_time_start_of_cpi*]
set_false_path -from [get_cells *digital_rx_chain_i/reg_*]
set_false_path -from [get_cells waveform_gen_i/reg_*]
#-------------------------------------------
# Clocks
#-------------------------------------------
set_property PACKAGE_PIN AK17 [get_ports clk_200_p]
set_property PACKAGE_PIN AK16 [get_ports clk_200_n]
#create_clock -period 5.000 -name clk_200 [get_ports clk_200_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_n]
#set_property PACKAGE_PIN AF6 [get_ports clk_125_p]
#set_property PACKAGE_PIN AF5 [get_ports clk_125_n]
#create_clock -period 8.000 -name clk_125 [get_ports clk_125_p]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_p]
# set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_125_n]
#-------------------------------------------
# RF Attenautors
#-------------------------------------------
set_property PACKAGE_PIN G26 [get_ports tx0_rf_attn_sin]
set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]
set_property PACKAGE_PIN P23 [get_ports tx1_rf_attn_clk]
set_property PACKAGE_PIN R23 [get_ports tx1_rf_attn_le]
set_property PACKAGE_PIN K25 [get_ports txlo_drv_en]
set_property PACKAGE_PIN R25 [get_ports rx0_rf_attn_sin]
set_property PACKAGE_PIN T25 [get_ports rx0_rf_attn_clk]
set_property PACKAGE_PIN T24 [get_ports rx0_rf_attn_le]
set_property PACKAGE_PIN AM11 [get_ports rx0_if_attn_sin]
set_property PACKAGE_PIN AF13 [get_ports rx0_if_attn_clk]
set_property PACKAGE_PIN AE13 [get_ports rx0_if_attn_le]
set_property PACKAGE_PIN AN11 [get_ports rx0_lna_en]
set_property PACKAGE_PIN J24 [get_ports rx1_rf_attn_sin]
set_property PACKAGE_PIN G27 [get_ports rx1_rf_attn_clk]
set_property PACKAGE_PIN H27 [get_ports rx1_rf_attn_le]
set_property PACKAGE_PIN K26 [get_ports rx1_if_attn_sin]
set_property PACKAGE_PIN L27 [get_ports rx1_if_attn_clk]
set_property PACKAGE_PIN M27 [get_ports rx1_if_attn_le]
set_property PACKAGE_PIN K27 [get_ports rx1_lna_en]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports tx0_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports tx1_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports tx1_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports tx1_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports txlo_drv_en]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_if_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_if_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_if_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx0_lna_en]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_rf_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_rf_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_rf_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_if_attn_sin]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_if_attn_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_if_attn_le]
set_property IOSTANDARD LVCMOS18 [get_ports rx1_lna_en]
#-------------------------------------------
# PPS
#-------------------------------------------
set_property PACKAGE_PIN H24 [get_ports pps]
set_property IOSTANDARD LVCMOS18 [get_ports pps]
#-------------------------------------------
# FAN PWM
#-------------------------------------------
set_property PACKAGE_PIN P20 [get_ports fan_pwm]
set_property IOSTANDARD LVCMOS18 [get_ports fan_pwm]
set_property PACKAGE_PIN L17 [get_ports fmc_power_en]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_power_en]
#-------------------------------------------
# LEDs
#-------------------------------------------
set_property PACKAGE_PIN L20 [get_ports {leds[0]}]
set_property PACKAGE_PIN M20 [get_ports {leds[1]}]
set_property PACKAGE_PIN M21 [get_ports {leds[2]}]
set_property PACKAGE_PIN N21 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[*]}]
#-------------------------------------------
# UART
#-------------------------------------------
set_property PACKAGE_PIN N27 [get_ports uart_rxd]
set_property PACKAGE_PIN K22 [get_ports uart_txd]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rxd]
set_property IOSTANDARD LVCMOS18 [get_ports uart_txd]
#-------------------------------------------
# SFP
#-------------------------------------------
set_property PACKAGE_PIN AP2 [get_ports sfp0_rx_p]
set_property PACKAGE_PIN AP1 [get_ports sfp0_rx_n]
set_property PACKAGE_PIN AN4 [get_ports sfp0_tx_p]
set_property PACKAGE_PIN AN3 [get_ports sfp0_tx_n]
set_property PACKAGE_PIN AM2 [get_ports sfp1_rx_p]
set_property PACKAGE_PIN AM1 [get_ports sfp1_rx_n]
set_property PACKAGE_PIN AM6 [get_ports sfp1_tx_p]
set_property PACKAGE_PIN AM5 [get_ports sfp1_tx_n]
set_property PACKAGE_PIN AK2 [get_ports sfp2_rx_p]
set_property PACKAGE_PIN AK1 [get_ports sfp2_rx_n]
set_property PACKAGE_PIN AL4 [get_ports sfp2_tx_p]
set_property PACKAGE_PIN AL3 [get_ports sfp2_tx_n]
set_property PACKAGE_PIN AJ4 [get_ports sfp3_rx_p]
set_property PACKAGE_PIN AJ3 [get_ports sfp3_rx_n]
set_property PACKAGE_PIN AK6 [get_ports sfp3_tx_p]
set_property PACKAGE_PIN AK5 [get_ports sfp3_tx_n]
set_property PACKAGE_PIN AF5 [get_ports sfp_mgt_refclk_0_n]
set_property PACKAGE_PIN AF6 [get_ports sfp_mgt_refclk_0_p]
set_property PACKAGE_PIN AM10 [get_ports sfp0_tx_disable_b]
set_property PACKAGE_PIN AL10 [get_ports sfp1_tx_disable_b]
set_property PACKAGE_PIN AP9 [get_ports sfp2_tx_disable_b]
set_property PACKAGE_PIN AN9 [get_ports sfp3_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp0_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp1_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp2_tx_disable_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp3_tx_disable_b]
set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]
set_output_delay 0.000 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]
#-------------------------------------------
# 1 Gb Ethernet (PHY 2)
#-------------------------------------------
set_property PACKAGE_PIN A23 [get_ports mdc]
set_property PACKAGE_PIN A22 [get_ports mdio]
set_property PACKAGE_PIN H22 [get_ports phy_rst_n]
set_property PACKAGE_PIN D23 [get_ports rgmii_rxc]
set_property PACKAGE_PIN A29 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN B29 [get_ports {rgmii_rd[0]}]
set_property PACKAGE_PIN A28 [get_ports {rgmii_rd[1]}]
set_property PACKAGE_PIN A27 [get_ports {rgmii_rd[2]}]
set_property PACKAGE_PIN C23 [get_ports {rgmii_rd[3]}]
set_property PACKAGE_PIN B24 [get_ports rgmii_txc]
set_property PACKAGE_PIN A24 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN B20 [get_ports {rgmii_td[0]}]
set_property PACKAGE_PIN A20 [get_ports {rgmii_td[1]}]
set_property PACKAGE_PIN B21 [get_ports {rgmii_td[2]}]
set_property PACKAGE_PIN B22 [get_ports {rgmii_td[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdc]
set_property IOSTANDARD LVCMOS18 [get_ports mdio]
set_property IOSTANDARD LVCMOS18 [get_ports phy_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_txc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_td[3]}]
#-------------------------------------------
# FMC (HPC)
#-------------------------------------------
set_property PACKAGE_PIN C27 [get_ports fmc_spi0_mosi]
set_property PACKAGE_PIN A25 [get_ports fmc_spi0_miso]
set_property PACKAGE_PIN B27 [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN B25 [get_ports fmc_spi0_ss]
set_property PACKAGE_PIN C22 [get_ports fmc_spi1_mosi]
set_property PACKAGE_PIN D20 [get_ports fmc_spi1_sck]
set_property PACKAGE_PIN C21 [get_ports fmc_spi1_ss]
set_property PACKAGE_PIN F27 [get_ports resetb]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_miso]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_sck]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_ss]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi1_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi1_sck]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi1_ss]
set_property IOSTANDARD LVCMOS18 [get_ports resetb]
set_property PACKAGE_PIN E25 [get_ports jesd_sysref_p]
set_property PACKAGE_PIN D25 [get_ports jesd_sysref_n]
set_property IOSTANDARD LVDS [get_ports jesd_sysref_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports jesd_sysref_p]
set_property PACKAGE_PIN K5 [get_ports jesd_qpll0_refclk_n]
set_property PACKAGE_PIN K6 [get_ports jesd_qpll0_refclk_p]
create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p]
#set_property PACKAGE_PIN P5 [get_ports jesd_qpll0_refclk_n]
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
#set_property PACKAGE_PIN H2 [get_ports {jesd_rxp_in[1]}]
#set_property PACKAGE_PIN K2 [get_ports {jesd_rxp_in[2]}]
#set_property PACKAGE_PIN M2 [get_ports {jesd_rxp_in[3]}]
#set_property PACKAGE_PIN A4 [get_ports {jesd_rxp_in[4]}]
#set_property PACKAGE_PIN B2 [get_ports {jesd_rxp_in[5]}]
#set_property PACKAGE_PIN D2 [get_ports {jesd_rxp_in[6]}]
#set_property PACKAGE_PIN E4 [get_ports {jesd_rxp_in[7]}]
#set_property PACKAGE_PIN G4 [get_ports {jesd_txp_out[0]}]
#set_property PACKAGE_PIN J4 [get_ports {jesd_txp_out[1]}]
#set_property PACKAGE_PIN L4 [get_ports {jesd_txp_out[2]}]
#set_property PACKAGE_PIN N4 [get_ports {jesd_txp_out[3]}]
#set_property PACKAGE_PIN B6 [get_ports {jesd_txp_out[4]}]
#set_property PACKAGE_PIN C4 [get_ports {jesd_txp_out[5]}]
#set_property PACKAGE_PIN D6 [get_ports {jesd_txp_out[6]}]
#set_property PACKAGE_PIN F6 [get_ports {jesd_txp_out[7]}]
#-------------------------------------------
# DDR
#-------------------------------------------
set_property PACKAGE_PIN AG14 [get_ports {ddr_adr[0]}]
set_property PACKAGE_PIN AF17 [get_ports {ddr_adr[1]}]
set_property PACKAGE_PIN AF15 [get_ports {ddr_adr[2]}]
set_property PACKAGE_PIN AJ14 [get_ports {ddr_adr[3]}]
set_property PACKAGE_PIN AD18 [get_ports {ddr_adr[4]}]
set_property PACKAGE_PIN AG17 [get_ports {ddr_adr[5]}]
set_property PACKAGE_PIN AE17 [get_ports {ddr_adr[6]}]
set_property PACKAGE_PIN AK18 [get_ports {ddr_adr[7]}]
set_property PACKAGE_PIN AD16 [get_ports {ddr_adr[8]}]
set_property PACKAGE_PIN AH18 [get_ports {ddr_adr[9]}]
set_property PACKAGE_PIN AD19 [get_ports {ddr_adr[10]}]
set_property PACKAGE_PIN AD15 [get_ports {ddr_adr[11]}]
set_property PACKAGE_PIN AH16 [get_ports {ddr_adr[12]}]
set_property PACKAGE_PIN AL17 [get_ports {ddr_adr[13]}]
set_property PACKAGE_PIN AL15 [get_ports {ddr_adr[14]}]
set_property PACKAGE_PIN AL19 [get_ports {ddr_adr[15]}]
set_property PACKAGE_PIN AM19 [get_ports {ddr_adr[16]}]
set_property PACKAGE_PIN AG15 [get_ports {ddr_ba[0]}]
set_property PACKAGE_PIN AL18 [get_ports {ddr_ba[1]}]
set_property PACKAGE_PIN AJ15 [get_ports {ddr_bg[0]}]
set_property PACKAGE_PIN AE16 [get_ports {ddr_ck_t[0]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr_ck_c[0]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr_cs_n[0]}]
set_property PACKAGE_PIN AJ16 [get_ports {ddr_cke[0]}]
set_property PACKAGE_PIN AG19 [get_ports {ddr_odt[0]}]
set_property PACKAGE_PIN AF18 [get_ports ddr_act_n]
set_property PACKAGE_PIN AG16 [get_ports ddr_reset_n]
set_property PACKAGE_PIN AN34 [get_ports {ddr_dqs_t[7]}]
set_property PACKAGE_PIN AP34 [get_ports {ddr_dqs_c[7]}]
set_property PACKAGE_PIN AL32 [get_ports {ddr_dm_n[7]}]
set_property PACKAGE_PIN AN31 [get_ports {ddr_dq[56]}]
set_property PACKAGE_PIN AL34 [get_ports {ddr_dq[57]}]
set_property PACKAGE_PIN AN32 [get_ports {ddr_dq[58]}]
set_property PACKAGE_PIN AN33 [get_ports {ddr_dq[59]}]
set_property PACKAGE_PIN AM32 [get_ports {ddr_dq[60]}]
set_property PACKAGE_PIN AM34 [get_ports {ddr_dq[61]}]
set_property PACKAGE_PIN AP31 [get_ports {ddr_dq[62]}]
set_property PACKAGE_PIN AP33 [get_ports {ddr_dq[63]}]
set_property PACKAGE_PIN AH33 [get_ports {ddr_dqs_t[6]}]
set_property PACKAGE_PIN AJ33 [get_ports {ddr_dqs_c[6]}]
set_property PACKAGE_PIN AJ29 [get_ports {ddr_dm_n[6]}]
set_property PACKAGE_PIN AK31 [get_ports {ddr_dq[48]}]
set_property PACKAGE_PIN AH34 [get_ports {ddr_dq[49]}]
set_property PACKAGE_PIN AK32 [get_ports {ddr_dq[50]}]
set_property PACKAGE_PIN AJ31 [get_ports {ddr_dq[51]}]
set_property PACKAGE_PIN AJ30 [get_ports {ddr_dq[52]}]
set_property PACKAGE_PIN AH31 [get_ports {ddr_dq[53]}]
set_property PACKAGE_PIN AJ34 [get_ports {ddr_dq[54]}]
set_property PACKAGE_PIN AH32 [get_ports {ddr_dq[55]}]
set_property PACKAGE_PIN AN29 [get_ports {ddr_dqs_t[5]}]
set_property PACKAGE_PIN AP30 [get_ports {ddr_dqs_c[5]}]
set_property PACKAGE_PIN AN26 [get_ports {ddr_dm_n[5]}]
set_property PACKAGE_PIN AN28 [get_ports {ddr_dq[40]}]
set_property PACKAGE_PIN AM30 [get_ports {ddr_dq[41]}]
set_property PACKAGE_PIN AP28 [get_ports {ddr_dq[42]}]
set_property PACKAGE_PIN AM29 [get_ports {ddr_dq[43]}]
set_property PACKAGE_PIN AN27 [get_ports {ddr_dq[44]}]
set_property PACKAGE_PIN AL30 [get_ports {ddr_dq[45]}]
set_property PACKAGE_PIN AL29 [get_ports {ddr_dq[46]}]
set_property PACKAGE_PIN AP29 [get_ports {ddr_dq[47]}]
set_property PACKAGE_PIN AL27 [get_ports {ddr_dqs_t[4]}]
set_property PACKAGE_PIN AL28 [get_ports {ddr_dqs_c[4]}]
set_property PACKAGE_PIN AH26 [get_ports {ddr_dm_n[4]}]
set_property PACKAGE_PIN AM26 [get_ports {ddr_dq[32]}]
set_property PACKAGE_PIN AJ28 [get_ports {ddr_dq[33]}]
set_property PACKAGE_PIN AM27 [get_ports {ddr_dq[34]}]
set_property PACKAGE_PIN AK28 [get_ports {ddr_dq[35]}]
set_property PACKAGE_PIN AH27 [get_ports {ddr_dq[36]}]
set_property PACKAGE_PIN AH28 [get_ports {ddr_dq[37]}]
set_property PACKAGE_PIN AK26 [get_ports {ddr_dq[38]}]
set_property PACKAGE_PIN AK27 [get_ports {ddr_dq[39]}]
set_property PACKAGE_PIN AP20 [get_ports {ddr_dqs_t[3]}]
set_property PACKAGE_PIN AP21 [get_ports {ddr_dqs_c[3]}]
set_property PACKAGE_PIN AM21 [get_ports {ddr_dm_n[3]}]
set_property PACKAGE_PIN AM22 [get_ports {ddr_dq[24]}]
set_property PACKAGE_PIN AP24 [get_ports {ddr_dq[25]}]
set_property PACKAGE_PIN AN22 [get_ports {ddr_dq[26]}]
set_property PACKAGE_PIN AN24 [get_ports {ddr_dq[27]}]
set_property PACKAGE_PIN AN23 [get_ports {ddr_dq[28]}]
set_property PACKAGE_PIN AP25 [get_ports {ddr_dq[29]}]
set_property PACKAGE_PIN AP23 [get_ports {ddr_dq[30]}]
set_property PACKAGE_PIN AM24 [get_ports {ddr_dq[31]}]
set_property PACKAGE_PIN AJ20 [get_ports {ddr_dqs_t[2]}]
set_property PACKAGE_PIN AK20 [get_ports {ddr_dqs_c[2]}]
set_property PACKAGE_PIN AJ21 [get_ports {ddr_dm_n[2]}]
set_property PACKAGE_PIN AK22 [get_ports {ddr_dq[16]}]
set_property PACKAGE_PIN AL22 [get_ports {ddr_dq[17]}]
set_property PACKAGE_PIN AM20 [get_ports {ddr_dq[18]}]
set_property PACKAGE_PIN AL23 [get_ports {ddr_dq[19]}]
set_property PACKAGE_PIN AK23 [get_ports {ddr_dq[20]}]
set_property PACKAGE_PIN AL25 [get_ports {ddr_dq[21]}]
set_property PACKAGE_PIN AL20 [get_ports {ddr_dq[22]}]
set_property PACKAGE_PIN AL24 [get_ports {ddr_dq[23]}]
set_property PACKAGE_PIN AH24 [get_ports {ddr_dqs_t[1]}]
set_property PACKAGE_PIN AJ25 [get_ports {ddr_dqs_c[1]}]
set_property PACKAGE_PIN AE25 [get_ports {ddr_dm_n[1]}]
set_property PACKAGE_PIN AF24 [get_ports {ddr_dq[8]}]
set_property PACKAGE_PIN AJ23 [get_ports {ddr_dq[9]}]
set_property PACKAGE_PIN AF23 [get_ports {ddr_dq[10]}]
set_property PACKAGE_PIN AH23 [get_ports {ddr_dq[11]}]
set_property PACKAGE_PIN AG25 [get_ports {ddr_dq[12]}]
set_property PACKAGE_PIN AJ24 [get_ports {ddr_dq[13]}]
set_property PACKAGE_PIN AG24 [get_ports {ddr_dq[14]}]
set_property PACKAGE_PIN AH22 [get_ports {ddr_dq[15]}]
set_property PACKAGE_PIN AG21 [get_ports {ddr_dqs_t[0]}]
set_property PACKAGE_PIN AH21 [get_ports {ddr_dqs_c[0]}]
set_property PACKAGE_PIN AD21 [get_ports {ddr_dm_n[0]}]
set_property PACKAGE_PIN AE20 [get_ports {ddr_dq[0]}]
set_property PACKAGE_PIN AG20 [get_ports {ddr_dq[1]}]
set_property PACKAGE_PIN AF20 [get_ports {ddr_dq[2]}]
set_property PACKAGE_PIN AE22 [get_ports {ddr_dq[3]}]
set_property PACKAGE_PIN AD20 [get_ports {ddr_dq[4]}]
set_property PACKAGE_PIN AG22 [get_ports {ddr_dq[5]}]
set_property PACKAGE_PIN AF22 [get_ports {ddr_dq[6]}]
set_property PACKAGE_PIN AE23 [get_ports {ddr_dq[7]}]
connect_debug_port u_ila_0/probe1 [get_nets [list pps_q2]]
connect_debug_port u_ila_0/probe3 [get_nets [list pps_red_i_1__0_n_0]]
connect_debug_port u_ila_0/probe4 [get_nets [list util_reg_i/spi_active]]
connect_debug_port u_ila_0/probe5 [get_nets [list util_reg_i/spi_shift_data]]
connect_debug_port u_ila_0/probe10 [get_nets [list util_reg_i/le_active]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list microblaze_bd_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {util_reg_i/spi_bit_cnt_reg[0]} {util_reg_i/spi_bit_cnt_reg[1]} {util_reg_i/spi_bit_cnt_reg[2]} {util_reg_i/spi_bit_cnt_reg[3]} {util_reg_i/spi_bit_cnt_reg[4]} {util_reg_i/spi_bit_cnt_reg[5]} {util_reg_i/spi_bit_cnt_reg[6]} {util_reg_i/spi_bit_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {util_reg_i/reg_spi_data[0]} {util_reg_i/reg_spi_data[1]} {util_reg_i/reg_spi_data[2]} {util_reg_i/reg_spi_data[3]} {util_reg_i/reg_spi_data[4]} {util_reg_i/reg_spi_data[5]} {util_reg_i/reg_spi_data[6]} {util_reg_i/reg_spi_data[7]} {util_reg_i/reg_spi_data[8]} {util_reg_i/reg_spi_data[9]} {util_reg_i/reg_spi_data[10]} {util_reg_i/reg_spi_data[11]} {util_reg_i/reg_spi_data[12]} {util_reg_i/reg_spi_data[13]} {util_reg_i/reg_spi_data[14]} {util_reg_i/reg_spi_data[15]} {util_reg_i/reg_spi_data[16]} {util_reg_i/reg_spi_data[17]} {util_reg_i/reg_spi_data[18]} {util_reg_i/reg_spi_data[19]} {util_reg_i/reg_spi_data[20]} {util_reg_i/reg_spi_data[21]} {util_reg_i/reg_spi_data[22]} {util_reg_i/reg_spi_data[23]} {util_reg_i/reg_spi_data[24]} {util_reg_i/reg_spi_data[25]} {util_reg_i/reg_spi_data[26]} {util_reg_i/reg_spi_data[27]} {util_reg_i/reg_spi_data[28]} {util_reg_i/reg_spi_data[29]} {util_reg_i/reg_spi_data[30]} {util_reg_i/reg_spi_data[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {util_reg_i/spi_clk_cnt_reg[0]} {util_reg_i/spi_clk_cnt_reg[1]} {util_reg_i/spi_clk_cnt_reg[2]} {util_reg_i/spi_clk_cnt_reg[3]} {util_reg_i/spi_clk_cnt_reg[4]} {util_reg_i/spi_clk_cnt_reg[5]} {util_reg_i/spi_clk_cnt_reg[6]} {util_reg_i/spi_clk_cnt_reg[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 5 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {util_reg_i/le_count_reg[0]} {util_reg_i/le_count_reg[1]} {util_reg_i/le_count_reg[2]} {util_reg_i/le_count_reg[3]} {util_reg_i/le_count_reg[4]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list util_reg_i/start_spi_transaction]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list tx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list tx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list tx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list rx0_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list rx0_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list rx0_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list rx0_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list rx0_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list rx0_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list rx1_if_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list rx1_if_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list rx1_if_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list rx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list rx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list rx1_rf_attn_sin_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list tx1_rf_attn_clk_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list tx1_rf_attn_le_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list tx1_rf_attn_sin_OBUF]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

4
radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/.gitignore vendored Normal file
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@@ -0,0 +1,4 @@
ip
ipshared
ui
*.bda

9021
radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd Executable file
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File diff suppressed because it is too large Load Diff

281
radar_alinx_kintex.srcs/sources_1/hdl/axi_intf.sv Executable file
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interface axi4_intf#(
// Width of S_AXI address araddr
parameter integer AXI_ADDR_WIDTH = 32,
// Width of S_AXI data bus
parameter integer AXI_DATA_WIDTH = 32
) (
input wire clk,
input wire resetn
);
logic [(AXI_ADDR_WIDTH-1):0] araddr;
logic [ 1:0] arburst;
logic [ 3:0] arcache;
logic [ 7:0] arlen;
logic arlock;
logic [ 2:0] arprot;
logic [ 3:0] arqos;
logic arready;
logic [ 2:0] arsize;
logic arvalid;
logic [(AXI_ADDR_WIDTH-1):0] awaddr;
logic [ 1:0] awburst;
logic [ 3:0] awcache;
logic [ 7:0] awlen;
logic awlock;
logic [ 2:0] awprot;
logic [ 3:0] awqos;
logic awready;
logic [ 2:0] awsize;
logic awvalid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(AXI_DATA_WIDTH-1):0] rdata;
logic rlast;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(AXI_DATA_WIDTH-1):0] wdata;
logic wlast;
logic wready;
logic [((AXI_DATA_WIDTH/8)-1):0] wstrb;
logic wvalid;
modport master (
input clk,
input resetn,
output araddr,
output arburst,
output arcache,
output arlen,
output arlock,
output arprot,
output arqos,
input arready,
output arsize,
output arvalid,
output awaddr,
output awburst,
output awcache,
output awlen,
output awlock,
output awprot,
output awqos,
input awready,
output awsize,
output awvalid,
output bready,
input bresp,
input bvalid,
input rdata,
input rlast,
output rready,
input rresp,
input rvalid,
output wdata,
output wlast,
input wready,
output wstrb,
output wvalid);
modport slave (
input clk,
input resetn,
input araddr,
input arburst,
input arcache,
input arlen,
input arlock,
input arprot,
input arqos,
output arready,
input arsize,
input arvalid,
input awaddr,
input awburst,
input awcache,
input awlen,
input awlock,
input awprot,
input awqos,
output awready,
input awsize,
input awvalid,
input bready,
output bresp,
output bvalid,
output rdata,
output rlast,
input rready,
output rresp,
output rvalid,
input wdata,
input wlast,
output wready,
input wstrb,
input wvalid);
endinterface
interface axi4l_intf#(
// Width of S_AXI address araddr
parameter integer AXI_ADDR_WIDTH = 32,
// Width of S_AXI data bus
parameter integer AXI_DATA_WIDTH = 32
) (
input wire clk,
input wire resetn
);
logic [(AXI_ADDR_WIDTH-1):0] araddr;
logic [2:0] arprot;
logic arready;
logic arvalid;
logic [(AXI_ADDR_WIDTH-1):0] awaddr;
logic [2:0] awprot;
logic awready;
logic awvalid;
logic bready;
logic [1:0] bresp;
logic bvalid;
logic [(AXI_DATA_WIDTH-1):0] rdata;
logic rready;
logic [1:0] rresp;
logic rvalid;
logic [(AXI_DATA_WIDTH-1):0] wdata;
logic wready;
logic [((AXI_DATA_WIDTH/8)-1):0] wstrb;
logic wvalid;
modport master (
input clk,
input resetn,
output araddr,
output arprot,
input arready,
output arvalid,
output awaddr,
output awprot,
input awready,
output awvalid,
output bready,
input bresp,
input bvalid,
input rdata,
output rready,
input rresp,
input rvalid,
output wdata,
input wready,
output wstrb,
output wvalid);
modport slave (
input clk,
input resetn,
input araddr,
input arprot,
output arready,
input arvalid,
input awaddr,
input awprot,
output awready,
input awvalid,
input bready,
output bresp,
output bvalid,
output rdata,
input rready,
output rresp,
output rvalid,
input wdata,
output wready,
input wstrb,
input wvalid);
endinterface
interface axi4s_intf#(
// Width of S_AXI data bus
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ID_WIDTH = 4,
parameter integer AXI_DEST_WIDTH = 4,
parameter integer AXI_USER_WIDTH = 4
) (
input wire clk,
input wire resetn
);
logic [(AXI_DATA_WIDTH-1):0] tdata;
logic tready;
logic [((AXI_DATA_WIDTH/8)-1):0] tstrb;
logic [((AXI_DATA_WIDTH/8)-1):0] tkeep;
logic tvalid;
logic tlast;
logic [(AXI_ID_WIDTH-1):0] tid;
logic [(AXI_DEST_WIDTH-1):0] tdest;
logic [(AXI_USER_WIDTH-1):0] tuser;
modport master (
input clk,
input resetn,
output tdata,
input tready,
output tstrb,
output tkeep,
output tvalid,
output tlast,
output tid,
output tdest,
output tuser);
modport slave (
input clk,
input resetn,
input tdata,
output tready,
input tstrb,
input tkeep,
input tvalid,
input tlast,
input tid,
input tdest,
input tuser);
endinterface

294
radar_alinx_kintex.srcs/sources_1/hdl/axil_slave.v Executable file
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`timescale 1 ns / 1 ps
module axil_slave #
(
parameter integer DATA_WIDTH = 32,
parameter integer ADDR_WIDTH = 9
)
(
// AXIL Slave
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [DATA_WIDTH-1 : 0] S_AXI_WDATA,
input wire [(DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1 : 0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [DATA_WIDTH-1 : 0] S_AXI_RDATA,
output wire [1 : 0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
output wire [ADDR_WIDTH-1 : 0] raddr,
output wire [ADDR_WIDTH-1 : 0] waddr,
output wire wren,
output wire rden,
output wire [DATA_WIDTH-1 : 0] wdata,
input wire [DATA_WIDTH-1 : 0] rdata
);
// AXI4LITE signals
reg [ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
wire [DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 6;
wire slv_reg_rden;
wire slv_reg_wren;
wire [DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
//----------------------------------------------
//-- AXIL Protocl Implementation
//------------------------------------------------
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
// // Output register or memory read data
// always @( posedge S_AXI_ACLK )
// begin
// if ( S_AXI_ARESETN == 1'b0 )
// begin
// axi_rdata <= 0;
// end
// else
// begin
// // When there is a valid read address (S_AXI_ARVALID) with
// // acceptance of read address by the slave (axi_arready),
// // output the read dada
// if (slv_reg_rden)
// begin
// axi_rdata <= reg_data_out; // register read data
// end
// end
// end
assign axi_rdata = rdata;
assign wren = slv_reg_wren;
assign rden = slv_reg_rden;
assign wdata = S_AXI_WDATA;
assign waddr = axi_awaddr;
assign raddr = axi_araddr;
// assign reg_data_out = rdata;
endmodule

355
radar_alinx_kintex.srcs/sources_1/hdl/digital_rx_chain.v Executable file
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`resetall
`timescale 1ns / 1ps
`default_nettype none
module digital_rx_chain #
(
parameter CTRL_REG_ADDR = 32'h00000000,
parameter NUM_SAMPLES_REG_ADDR = 32'h00000004,
parameter START_SAMPLE_REG_ADDR = 32'h00000008,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
)
(
input wire clk,
// AXI4L Config Interface
axi4l_intf.slave ctrl_if,
input wire start_of_pulse,
// Input Data
input wire in_tvalid,
input wire [63:0] in_tdata_i,
input wire [63:0] in_tdata_q,
// Output Data
axi4s_intf.master rx_out
);
reg out_tvalid_r;
wire out_tlast_r;
wire out_tstart_r;
// ------------------------------
// Register Inputs for timing
// ------------------------------
reg in_tstart_reg;
reg in_tvalid_reg;
reg [63:0] in_tdata_i_reg;
reg [63:0] in_tdata_q_reg;
always @ (posedge clk) begin
in_tstart_reg <= start_of_pulse;
in_tvalid_reg <= in_tvalid;
in_tdata_i_reg <= in_tdata_i;
in_tdata_q_reg <= in_tdata_q;
end
// ------------------------------
// AXIL Decode
// ------------------------------
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
wire rden;
wire wren;
wire [AXI_DATA_WIDTH-1 : 0] wdata;
reg [AXI_DATA_WIDTH-1 : 0] rdata;
axil_slave
# (
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH)
) axil_slave_i
(
// AXIL Slave
.S_AXI_ACLK(ctrl_if.clk),
.S_AXI_ARESETN(ctrl_if.resetn),
.S_AXI_AWADDR(ctrl_if.awaddr),
.S_AXI_AWPROT(ctrl_if.awprot),
.S_AXI_AWVALID(ctrl_if.awvalid),
.S_AXI_AWREADY(ctrl_if.awready),
.S_AXI_WDATA(ctrl_if.wdata),
.S_AXI_WSTRB(ctrl_if.wstrb),
.S_AXI_WVALID(ctrl_if.wvalid),
.S_AXI_WREADY(ctrl_if.wready),
.S_AXI_BRESP(ctrl_if.bresp),
.S_AXI_BVALID(ctrl_if.bvalid),
.S_AXI_BREADY(ctrl_if.bready),
.S_AXI_ARADDR(ctrl_if.araddr),
.S_AXI_ARPROT(ctrl_if.arprot),
.S_AXI_ARVALID(ctrl_if.arvalid),
.S_AXI_ARREADY(ctrl_if.arready),
.S_AXI_RDATA(ctrl_if.rdata),
.S_AXI_RRESP(ctrl_if.rresp),
.S_AXI_RVALID(ctrl_if.rvalid),
.S_AXI_RREADY(ctrl_if.rready),
.raddr(raddr),
.waddr(waddr),
.wren(wren),
.rden(rden),
.wdata(wdata),
.rdata(rdata)
);
// ------------------------------
// Config Registers
// ------------------------------
wire reset;
reg [31:0] reg_ctrl;
reg [15:0] reg_num_samples;
reg [27:0] reg_start_sample;
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_ctrl <= 0;
end else if (wren && waddr[11:0] == CTRL_REG_ADDR) begin
reg_ctrl <= wdata[15:0];
end
end
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_num_samples <= 0;
end else if (wren && waddr[11:0] == NUM_SAMPLES_REG_ADDR) begin
reg_num_samples <= wdata[15:0];
end
end
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_start_sample <= 0;
end else if (wren && waddr[11:0] == START_SAMPLE_REG_ADDR) begin
reg_start_sample <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (rden) begin
if ( raddr[11:0] == CTRL_REG_ADDR )
rdata <= reg_ctrl;
if ( raddr[11:0] == NUM_SAMPLES_REG_ADDR )
rdata <= reg_num_samples;
if ( raddr[11:0] == START_SAMPLE_REG_ADDR )
rdata <= reg_start_sample;
end
end
assign reset = reg_ctrl[0];
// ------------------------------
// Event Counter
// ------------------------------
reg [15:0] event_cnt;
always @ (posedge clk) begin
if (reset == 1'b1) begin
event_cnt <= 0;
end else begin
if (in_tstart_reg) begin
event_cnt <= event_cnt + 1;
end
end
end
// ------------------------------
// Sample gating
// ------------------------------
reg [16:0] sample_cnt;
reg pulse_active;
reg pulse_active_q;
reg pulse_active_fed;
reg pulse_active_fed_q;
// Delay event pulse by start sample
reg [27:0] start_sample_cnt;
reg [27:0] start_sample_this_pulse;
reg delay_active;
reg delay_active_q;
reg delay_active_fed;
always @ (posedge clk) begin
if (reset == 1'b1) begin
start_sample_cnt <= 0;
delay_active <= 0;
end else begin
delay_active_q <= delay_active;
delay_active_fed <= ~delay_active && delay_active_q;
if (in_tstart_reg && in_tvalid_reg) begin
start_sample_cnt <= reg_start_sample;
start_sample_this_pulse <= reg_start_sample;
delay_active <= 1;
end
if (delay_active) begin
start_sample_cnt <= start_sample_cnt - 1;
if (start_sample_cnt == 0) begin
delay_active <= 0;
end
end
end
end
always @ (posedge clk) begin
if (reset == 1'b1) begin
sample_cnt <= 0;
pulse_active <= 0;
pulse_active_q <= 0;
pulse_active_fed <= 1;
pulse_active_fed_q <= 1;
end else begin
pulse_active_q <= pulse_active;
pulse_active_fed <= ~pulse_active && pulse_active_q;
pulse_active_fed_q <= pulse_active_fed;
// if (in_tstart_reg && in_tvalid_reg) begin
if (delay_active_fed && in_tvalid_reg) begin
sample_cnt <= 0;
pulse_active <= 1;
end;
if (out_tvalid_r) begin
sample_cnt <= sample_cnt + 1;
if (sample_cnt == reg_num_samples-1) begin
sample_cnt <= 0;
pulse_active <= 0;
end
end
end
end
assign out_tlast_r = ((sample_cnt == reg_num_samples-1) && out_tvalid_r) ? 1'b1 : 1'b0;
assign out_tstart_r = ((sample_cnt == 0) && out_tvalid_r) ? 1'b1 : 1'b0;
assign out_tvalid_r = in_tvalid_reg && (pulse_active || delay_active_fed);
// ------------------------------
// Buffer
// ------------------------------
axi4s_intf # (
.AXI_DATA_WIDTH(128),
.AXI_USER_WIDTH(1)
)
axis_odec_out (
.clk(clk),
.resetn(~reset)
);
axi4s_intf # (
.AXI_DATA_WIDTH(128),
.AXI_USER_WIDTH(1)
)
axis_pulse_buffer_out (
.clk(clk),
.resetn(~reset)
);
axi4s_intf # (
.AXI_DATA_WIDTH(64),
.AXI_USER_WIDTH(8)
)
axis_dwidth_conv_out (
.clk(clk),
.resetn(~reset)
);
assign axis_odec_out.tvalid = out_tvalid_r && (pulse_active || delay_active_fed);
assign axis_odec_out.tlast = out_tlast_r;
assign axis_odec_out.tuser = out_tstart_r;
assign axis_odec_out.tdata[15:0] = in_tdata_i_reg[63:48];
assign axis_odec_out.tdata[31:16] = in_tdata_q_reg[63:48];
assign axis_odec_out.tdata[47:32] = in_tdata_i_reg[47:32];
assign axis_odec_out.tdata[63:48] = in_tdata_q_reg[47:32];
assign axis_odec_out.tdata[79:64] = in_tdata_i_reg[31:16];
assign axis_odec_out.tdata[95:80] = in_tdata_q_reg[31:16];
assign axis_odec_out.tdata[111:96] = in_tdata_i_reg[15:0];
assign axis_odec_out.tdata[127:112] = in_tdata_q_reg[15:0];
//assign axis_odec_out.tdata[15:0] = in_tdata_i_reg[15:0];
//assign axis_odec_out.tdata[31:16] = in_tdata_q_reg[15:0];
//assign axis_odec_out.tdata[47:32] = in_tdata_i_reg[31:16];
//assign axis_odec_out.tdata[63:48] = in_tdata_q_reg[31:16];
//assign axis_odec_out.tdata[79:64] = in_tdata_i_reg[47:32];
//assign axis_odec_out.tdata[95:80] = in_tdata_q_reg[47:32];
//assign axis_odec_out.tdata[111:96] = in_tdata_i_reg[63:48];
//assign axis_odec_out.tdata[127:112] = in_tdata_q_reg[63:48];
// assign axis_odec_out.tdata[63:0] = in_tdata_i_reg[63:0];
// assign axis_odec_out.tdata[127:64] = in_tdata_q_reg[63:0];
pulse_buffer_fifo pulse_buffer_fifo_i (
.s_axis_aresetn(~reset),
.s_axis_aclk(clk),
.s_axis_tvalid(axis_odec_out.tvalid),
.s_axis_tready(),
.s_axis_tdata(axis_odec_out.tdata),
.s_axis_tlast(axis_odec_out.tlast),
.s_axis_tuser(axis_odec_out.tuser),
.m_axis_tvalid(axis_pulse_buffer_out.tvalid),
.m_axis_tready(axis_pulse_buffer_out.tready),
.m_axis_tdata(axis_pulse_buffer_out.tdata),
.m_axis_tlast(axis_pulse_buffer_out.tlast),
.m_axis_tuser(axis_pulse_buffer_out.tuser)
);
wire [15:0] dwidth_conv_tuser_in;
assign dwidth_conv_tuser_in[15:1] = '0;
assign dwidth_conv_tuser_in[0] = axis_pulse_buffer_out.tuser;
// This is going from 128 bits to 64 bits
dig_rx_dwidth_converter dig_rx_dwidth_converter_i (
.aresetn(~reset),
.aclk(clk),
.s_axis_tvalid(axis_pulse_buffer_out.tvalid),
.s_axis_tready(axis_pulse_buffer_out.tready),
.s_axis_tdata(axis_pulse_buffer_out.tdata),
.s_axis_tlast(axis_pulse_buffer_out.tlast),
.s_axis_tuser(dwidth_conv_tuser_in),
.m_axis_tvalid(axis_dwidth_conv_out.tvalid),
.m_axis_tready(axis_dwidth_conv_out.tready),
.m_axis_tdata(axis_dwidth_conv_out.tdata),
.m_axis_tlast(axis_dwidth_conv_out.tlast),
.m_axis_tuser(axis_dwidth_conv_out.tuser)
);
// Now need a clock converter to go to output which is connected directly to eth udp
dig_rx_clock_converter dig_rx_clock_converter_i (
.s_axis_aresetn(axis_dwidth_conv_out.resetn),
.s_axis_aclk(axis_dwidth_conv_out.clk),
.s_axis_tvalid(axis_dwidth_conv_out.tvalid),
.s_axis_tready(axis_dwidth_conv_out.tready),
.s_axis_tdata(axis_dwidth_conv_out.tdata),
.s_axis_tlast(axis_dwidth_conv_out.tlast),
.s_axis_tuser(axis_dwidth_conv_out.tuser),
.m_axis_aresetn(rx_out.resetn),
.m_axis_aclk(rx_out.clk),
.m_axis_tvalid(rx_out.tvalid),
.m_axis_tready(rx_out.tready),
.m_axis_tdata(rx_out.tdata),
.m_axis_tlast(rx_out.tlast),
.m_axis_tuser(rx_out.tuser)
);
assign rx_out.tkeep = '1;
// assign rx_out.tuser = reg_num_samples;
assign rx_out.tdest = 1;
endmodule
`resetall

334
radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.v Executable file
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`resetall
`timescale 1ns / 1ps
`default_nettype none
module ethernet_top #
(
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
)
(
/*
* Clock: 125MHz LVDS
* Reset: active low
*/
input wire clk_freerun,
input wire reset,
output wire [3:0] eth_clk,
output wire [3:0] eth_resetn,
input wire [15:0] packet_size,
axi4s_intf.master rx_udp_0,
axi4s_intf.slave tx_udp_0,
axi4s_intf.master rx_udp_1,
axi4s_intf.slave tx_udp_1,
/*
* Ethernet: SFP+
*/
input wire sfp0_rx_p,
input wire sfp0_rx_n,
output wire sfp0_tx_p,
output wire sfp0_tx_n,
input wire sfp1_rx_p,
input wire sfp1_rx_n,
output wire sfp1_tx_p,
output wire sfp1_tx_n,
input wire sfp2_rx_p,
input wire sfp2_rx_n,
output wire sfp2_tx_p,
output wire sfp2_tx_n,
input wire sfp3_rx_p,
input wire sfp3_rx_n,
output wire sfp3_tx_p,
output wire sfp3_tx_n,
input wire sfp_mgt_refclk_0_p,
input wire sfp_mgt_refclk_0_n,
output wire sfp0_tx_disable_b,
output wire sfp1_tx_disable_b,
output wire sfp2_tx_disable_b,
output wire sfp3_tx_disable_b
);
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
// XGMII 10G PHY
assign sfp0_tx_disable_b = 1'b0;
assign sfp1_tx_disable_b = 1'b0;
assign sfp2_tx_disable_b = 1'b0;
assign sfp3_tx_disable_b = 1'b0;
wire sfp0_tx_clk_int;
wire sfp0_tx_rst_int;
wire [63:0] sfp0_txd_int;
wire [7:0] sfp0_txc_int;
wire sfp0_rx_clk_int;
wire sfp0_rx_rst_int;
wire [63:0] sfp0_rxd_int;
wire [7:0] sfp0_rxc_int;
wire sfp1_tx_clk_int;
wire sfp1_tx_rst_int;
wire [63:0] sfp1_txd_int;
wire [7:0] sfp1_txc_int;
wire sfp1_rx_clk_int;
wire sfp1_rx_rst_int;
wire [63:0] sfp1_rxd_int;
wire [7:0] sfp1_rxc_int;
wire sfp2_tx_clk_int;
wire sfp2_tx_rst_int;
wire [63:0] sfp2_txd_int;
wire [7:0] sfp2_txc_int;
wire sfp2_rx_clk_int;
wire sfp2_rx_rst_int;
wire [63:0] sfp2_rxd_int;
wire [7:0] sfp2_rxc_int;
wire sfp3_tx_clk_int;
wire sfp3_tx_rst_int;
wire [63:0] sfp3_txd_int;
wire [7:0] sfp3_txc_int;
wire sfp3_rx_clk_int;
wire sfp3_rx_rst_int;
wire [63:0] sfp3_rxd_int;
wire [7:0] sfp3_rxc_int;
assign clk_156mhz_int = sfp0_tx_clk_int;
assign rst_156mhz_int = sfp0_tx_rst_int;
// assign eth_resetn = !sfp0_tx_rst_int;
// assign eth_clk = sfp0_tx_clk_int;
assign eth_resetn[0] = !sfp0_tx_rst_int;
assign eth_clk[0] = sfp0_tx_clk_int;
assign eth_resetn[1] = !sfp1_tx_rst_int;
assign eth_clk[1] = sfp1_tx_clk_int;
assign eth_resetn[2] = !sfp2_tx_rst_int;
assign eth_clk[2] = sfp2_tx_clk_int;
assign eth_resetn[3] = !sfp3_tx_rst_int;
assign eth_clk[3] = sfp3_tx_clk_int;
wire sfp0_rx_block_lock;
wire sfp1_rx_block_lock;
wire sfp2_rx_block_lock;
wire sfp3_rx_block_lock;
wire sfp_mgt_refclk_0;
wire reset_freerun;
sync_reset #(
.N(4)
)
sync_reset_freerun_inst (
.clk(clk_freerun),
.rst(reset),
.out(reset_freerun)
);
IBUFDS_GTE3 ibufds_gte4_sfp_mgt_refclk_0_inst (
.I (sfp_mgt_refclk_0_p),
.IB (sfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (sfp_mgt_refclk_0),
.ODIV2 ()
);
eth_xcvr_phy_quad_wrapper
sfp_phy_inst (
.xcvr_ctrl_clk(clk_freerun),
.xcvr_ctrl_rst(reset_freerun),
/*
* Common
*/
.xcvr_gtpowergood_out(),
/*
* PLL
*/
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
/*
* Serial data
*/
.xcvr_txp({sfp3_tx_p, sfp2_tx_p, sfp1_tx_p, sfp0_tx_p}),
.xcvr_txn({sfp3_tx_n, sfp2_tx_n, sfp1_tx_n, sfp0_tx_n}),
.xcvr_rxp({sfp3_rx_p, sfp2_rx_p, sfp1_rx_p, sfp0_rx_p}),
.xcvr_rxn({sfp3_rx_n, sfp2_rx_n, sfp1_rx_n, sfp0_rx_n}),
/*
* PHY connections
*/
.phy_1_tx_clk(sfp0_tx_clk_int),
.phy_1_tx_rst(sfp0_tx_rst_int),
.phy_1_xgmii_txd(sfp0_txd_int),
.phy_1_xgmii_txc(sfp0_txc_int),
.phy_1_rx_clk(sfp0_rx_clk_int),
.phy_1_rx_rst(sfp0_rx_rst_int),
.phy_1_xgmii_rxd(sfp0_rxd_int),
.phy_1_xgmii_rxc(sfp0_rxc_int),
.phy_1_tx_bad_block(),
.phy_1_rx_error_count(),
.phy_1_rx_bad_block(),
.phy_1_rx_sequence_error(),
.phy_1_rx_block_lock(sfp0_rx_block_lock),
.phy_1_rx_status(),
.phy_1_cfg_tx_prbs31_enable(1'b0),
.phy_1_cfg_rx_prbs31_enable(1'b0),
.phy_2_tx_clk(sfp1_tx_clk_int),
.phy_2_tx_rst(sfp1_tx_rst_int),
.phy_2_xgmii_txd(sfp1_txd_int),
.phy_2_xgmii_txc(sfp1_txc_int),
.phy_2_rx_clk(sfp1_rx_clk_int),
.phy_2_rx_rst(sfp1_rx_rst_int),
.phy_2_xgmii_rxd(sfp1_rxd_int),
.phy_2_xgmii_rxc(sfp1_rxc_int),
.phy_2_tx_bad_block(),
.phy_2_rx_error_count(),
.phy_2_rx_bad_block(),
.phy_2_rx_sequence_error(),
.phy_2_rx_block_lock(sfp1_rx_block_lock),
.phy_2_rx_status(),
.phy_2_cfg_tx_prbs31_enable(1'b0),
.phy_2_cfg_rx_prbs31_enable(1'b0),
.phy_3_tx_clk(sfp2_tx_clk_int),
.phy_3_tx_rst(sfp2_tx_rst_int),
.phy_3_xgmii_txd(sfp2_txd_int),
.phy_3_xgmii_txc(sfp2_txc_int),
.phy_3_rx_clk(sfp2_rx_clk_int),
.phy_3_rx_rst(sfp2_rx_rst_int),
.phy_3_xgmii_rxd(sfp2_rxd_int),
.phy_3_xgmii_rxc(sfp2_rxc_int),
.phy_3_tx_bad_block(),
.phy_3_rx_error_count(),
.phy_3_rx_bad_block(),
.phy_3_rx_sequence_error(),
.phy_3_rx_block_lock(sfp2_rx_block_lock),
.phy_3_rx_status(),
.phy_3_cfg_tx_prbs31_enable(1'b0),
.phy_3_cfg_rx_prbs31_enable(1'b0),
.phy_4_tx_clk(sfp3_tx_clk_int),
.phy_4_tx_rst(sfp3_tx_rst_int),
.phy_4_xgmii_txd(sfp3_txd_int),
.phy_4_xgmii_txc(sfp3_txc_int),
.phy_4_rx_clk(sfp3_rx_clk_int),
.phy_4_rx_rst(sfp3_rx_rst_int),
.phy_4_xgmii_rxd(sfp3_rxd_int),
.phy_4_xgmii_rxc(sfp3_rxc_int),
.phy_4_tx_bad_block(),
.phy_4_rx_error_count(),
.phy_4_rx_bad_block(),
.phy_4_rx_sequence_error(),
.phy_4_rx_block_lock(sfp3_rx_block_lock),
.phy_4_rx_status(),
.phy_4_cfg_tx_prbs31_enable(1'b0),
.phy_4_cfg_rx_prbs31_enable(1'b0)
);
assign sfp2_txd_int = 64'h0707070707070707;
assign sfp2_txc_int = 8'hff;
assign sfp3_txd_int = 64'h0707070707070707;
assign sfp3_txc_int = 8'hff;
fpga_core # (
.IP_ADDR(2),
.PORT_IN(1234),
.MAC_ADDR(48'h02_00_00_00_00_00)
)
core_inst_0 (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
// .clk(clk_156mhz_int),
// .rst(rst_156mhz_int),
.clk(sfp0_tx_clk_int),
.rst(sfp0_tx_rst_int),
.packet_size(packet_size),
.rx_fifo_udp_payload_axis_tdata(rx_udp_0.tdata),
.rx_fifo_udp_payload_axis_tkeep(rx_udp_0.tkeep),
.rx_fifo_udp_payload_axis_tvalid(rx_udp_0.tvalid),
.rx_fifo_udp_payload_axis_tready(rx_udp_0.tready),
.rx_fifo_udp_payload_axis_tlast(rx_udp_0.tlast),
.rx_fifo_udp_payload_axis_tuser(rx_udp_0.tuser),
.tx_fifo_udp_payload_axis_tdata(tx_udp_0.tdata),
.tx_fifo_udp_payload_axis_tkeep(tx_udp_0.tkeep),
.tx_fifo_udp_payload_axis_tvalid(tx_udp_0.tvalid),
.tx_fifo_udp_payload_axis_tready(tx_udp_0.tready),
.tx_fifo_udp_payload_axis_tlast(tx_udp_0.tlast),
.tx_fifo_udp_payload_axis_tuser(tx_udp_0.tuser),
.tx_fifo_udp_payload_axis_tdest(tx_udp_0.tdest),
/*
* Ethernet: SFP+
*/
.sfp_tx_clk(sfp0_tx_clk_int),
.sfp_tx_rst(sfp0_tx_rst_int),
.sfp_txd(sfp0_txd_int),
.sfp_txc(sfp0_txc_int),
.sfp_rx_clk(sfp0_rx_clk_int),
.sfp_rx_rst(sfp0_rx_rst_int),
.sfp_rxd(sfp0_rxd_int),
.sfp_rxc(sfp0_rxc_int)
);
fpga_core # (
.IP_ADDR(3),
.PORT_IN(1235),
.MAC_ADDR(48'h03_00_00_00_00_00)
)
core_inst_1 (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
// .clk(clk_156mhz_int),
// .rst(rst_156mhz_int),
.clk(sfp1_tx_clk_int),
.rst(sfp1_tx_rst_int),
.packet_size(packet_size),
.rx_fifo_udp_payload_axis_tdata(rx_udp_1.tdata),
.rx_fifo_udp_payload_axis_tkeep(rx_udp_1.tkeep),
.rx_fifo_udp_payload_axis_tvalid(rx_udp_1.tvalid),
.rx_fifo_udp_payload_axis_tready(rx_udp_1.tready),
.rx_fifo_udp_payload_axis_tlast(rx_udp_1.tlast),
.rx_fifo_udp_payload_axis_tuser(rx_udp_1.tuser),
.tx_fifo_udp_payload_axis_tdata(tx_udp_1.tdata),
.tx_fifo_udp_payload_axis_tkeep(tx_udp_1.tkeep),
.tx_fifo_udp_payload_axis_tvalid(tx_udp_1.tvalid),
.tx_fifo_udp_payload_axis_tready(tx_udp_1.tready),
.tx_fifo_udp_payload_axis_tlast(tx_udp_1.tlast),
.tx_fifo_udp_payload_axis_tuser(tx_udp_1.tuser),
.tx_fifo_udp_payload_axis_tdest(tx_udp_1.tdest),
/*
* Ethernet: SFP+
*/
.sfp_tx_clk(sfp1_tx_clk_int),
.sfp_tx_rst(sfp1_tx_rst_int),
.sfp_txd(sfp1_txd_int),
.sfp_txc(sfp1_txc_int),
.sfp_rx_clk(sfp1_rx_clk_int),
.sfp_rx_rst(sfp1_rx_rst_int),
.sfp_rxd(sfp1_rxd_int),
.sfp_rxc(sfp1_rxc_int)
);
endmodule
`resetall

154
radar_alinx_kintex.srcs/sources_1/hdl/spi.v Executable file
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`resetall
`timescale 1ns / 1ps
`default_nettype none
module simple_spi #
(
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
)
(
input wire clk,
input wire reset,
// AXI4L Config Interface
axi4l_intf.slave ctrl_if,
output wire [31:0] ss,
inout wire mosi,
input wire miso,
output wire sck
);
// ------------------------------
// AXIL Decode
// ------------------------------
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
wire rden;
wire wren;
wire [AXI_DATA_WIDTH-1 : 0] wdata;
reg [AXI_DATA_WIDTH-1 : 0] rdata;
axil_slave
# (
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH)
) axil_slave_i
(
// AXIL Slave
.S_AXI_ACLK(ctrl_if.clk),
.S_AXI_ARESETN(ctrl_if.resetn),
.S_AXI_AWADDR(ctrl_if.awaddr),
.S_AXI_AWPROT(ctrl_if.awprot),
.S_AXI_AWVALID(ctrl_if.awvalid),
.S_AXI_AWREADY(ctrl_if.awready),
.S_AXI_WDATA(ctrl_if.wdata),
.S_AXI_WSTRB(ctrl_if.wstrb),
.S_AXI_WVALID(ctrl_if.wvalid),
.S_AXI_WREADY(ctrl_if.wready),
.S_AXI_BRESP(ctrl_if.bresp),
.S_AXI_BVALID(ctrl_if.bvalid),
.S_AXI_BREADY(ctrl_if.bready),
.S_AXI_ARADDR(ctrl_if.araddr),
.S_AXI_ARPROT(ctrl_if.arprot),
.S_AXI_ARVALID(ctrl_if.arvalid),
.S_AXI_ARREADY(ctrl_if.arready),
.S_AXI_RDATA(ctrl_if.rdata),
.S_AXI_RRESP(ctrl_if.rresp),
.S_AXI_RVALID(ctrl_if.rvalid),
.S_AXI_RREADY(ctrl_if.rready),
.raddr(raddr),
.waddr(waddr),
.wren(wren),
.rden(rden),
.wdata(wdata),
.rdata(rdata)
);
// ------------------------------
// Config Registers
// ------------------------------
reg [31:0] clk_div;
reg [7:0] data;
reg [31:0] ss;
reg [24:0] pwm_pulsewidth;
always @ (posedge clk) begin
if (reset) begin
scratch <= 0;
end else if (wren && waddr[11:0] == 'h004) begin
scratch <= wdata;
end
end
always @ (posedge clk) begin
if (reset) begin
gpo_reg <= 0;
end else if (wren && waddr[11:0] == 'h008) begin
gpo_reg <= wdata;
end
end
always @ (posedge clk) begin
if (reset) begin
pwm_period <= 1500000;
end else if (wren && waddr[11:0] == 'h010) begin
pwm_period <= wdata;
end
end
always @ (posedge clk) begin
if (reset) begin
pwm_pulsewidth <= 500000;
end else if (wren && waddr[11:0] == 'h014) begin
pwm_pulsewidth <= wdata;
end
end
always @ (posedge clk) begin
if (rden) begin
if (raddr[11:0] == 'h000)
rdata <= 'h12345678;
if (raddr[11:0] == 'h004)
rdata <= scratch;
if (raddr[11:0] == 'h008)
rdata <= gpo_reg;
if (raddr[11:0] == 'h00C)
rdata <= gpi;
end
end
assign gpo = gpo_reg;
// ------------------------------
// Fan PWM
// ------------------------------
reg [24:0] pwm_cnt;
reg pwm_out;
assign fan_pwm = pwm_out;
always @ (posedge clk) begin
if (pwm_cnt < pwm_period) begin
pwm_cnt <= pwm_cnt + 1;
end else begin
pwm_cnt <= 0;
end
if (pwm_cnt < pwm_pulsewidth) begin
pwm_out <= 1'bz;
end else begin
pwm_out <= 1'b0;
end
end
endmodule
`resetall

389
radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v Executable file
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`resetall
`timescale 1ns / 1ps
`default_nettype none
module timing_engine #
(
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32,
parameter NUM_RX = 2
)
(
input wire clk,
input wire pps,
// AXI4L Config Interface
axi4l_intf.slave ctrl_if,
output wire start_of_cpi,
output wire start_of_pulse,
axi4s_intf.master hdr_out[NUM_RX]
);
// ------------------------------
// AXIL Decode
// ------------------------------
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
wire rden;
wire wren;
wire [AXI_DATA_WIDTH-1 : 0] wdata;
reg [AXI_DATA_WIDTH-1 : 0] rdata;
axil_slave
# (
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH)
) axil_slave_i
(
// AXIL Slave
.S_AXI_ACLK(ctrl_if.clk),
.S_AXI_ARESETN(ctrl_if.resetn),
.S_AXI_AWADDR(ctrl_if.awaddr),
.S_AXI_AWPROT(ctrl_if.awprot),
.S_AXI_AWVALID(ctrl_if.awvalid),
.S_AXI_AWREADY(ctrl_if.awready),
.S_AXI_WDATA(ctrl_if.wdata),
.S_AXI_WSTRB(ctrl_if.wstrb),
.S_AXI_WVALID(ctrl_if.wvalid),
.S_AXI_WREADY(ctrl_if.wready),
.S_AXI_BRESP(ctrl_if.bresp),
.S_AXI_BVALID(ctrl_if.bvalid),
.S_AXI_BREADY(ctrl_if.bready),
.S_AXI_ARADDR(ctrl_if.araddr),
.S_AXI_ARPROT(ctrl_if.arprot),
.S_AXI_ARVALID(ctrl_if.arvalid),
.S_AXI_ARREADY(ctrl_if.arready),
.S_AXI_RDATA(ctrl_if.rdata),
.S_AXI_RRESP(ctrl_if.rresp),
.S_AXI_RVALID(ctrl_if.rvalid),
.S_AXI_RREADY(ctrl_if.rready),
.raddr(raddr),
.waddr(waddr),
.wren(wren),
.rden(rden),
.wdata(wdata),
.rdata(rdata)
);
// ------------------------------
// Config Registers
// ------------------------------
wire reset;
assign reset = ~ctrl_if.resetn;
reg [31:0] reg_ctrl;
reg [31:0] reg_pri;
reg [31:0] reg_num_pulses;
reg [31:0] reg_inter_cpi;
reg [64:0] system_time;
reg [64:0] pps_frac_sec;
reg [32:0] pps_sec;
reg [32:0] reg_pps_sec_set;
reg reg_pps_set;
reg hdr_bram_we;
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_ctrl <= 0;
end else if (wren && waddr[11:0] == 'h000) begin
reg_ctrl <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_pri <= 0;
end else if (wren && waddr[11:0] == 'h004) begin
reg_pri <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_num_pulses <= 0;
end else if (wren && waddr[11:0] == 'h008) begin
reg_num_pulses <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_inter_cpi <= 0;
end else if (wren && waddr[11:0] == 'h010) begin
reg_inter_cpi <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_pps_sec_set <= 0;
reg_pps_set <= 0;
end else if (wren && waddr[11:0] == 'h014) begin
reg_pps_sec_set <= wdata;
reg_pps_set <= 1;
end else begin
reg_pps_set <= 0;
end
end
always @ (posedge ctrl_if.clk) begin
if (wren && waddr[11:10] == 2'b11) begin
hdr_bram_we <= 1;
end else begin
hdr_bram_we <= 0;
end
end
always @ (posedge ctrl_if.clk) begin
if (rden) begin
if (raddr[11:0] == 'h000)
rdata <= reg_ctrl;
if (raddr[11:0] == 'h004)
rdata <= reg_pri;
if (raddr[11:0] == 'h008)
rdata <= reg_num_pulses;
if (raddr[11:0] == 'h00C)
rdata <= reg_inter_cpi;
end
end
// ------------------------------
// Timestamping
// ------------------------------
reg [64:0] system_time_start_of_cpi;
reg [64:0] pps_sec_start_of_cpi;
reg [64:0] pps_frac_sec_start_of_cpi;
reg [15:0] pps_pipe;
reg pps_debounce;
reg pps_q;
reg pps_q2;
reg pps_red;
always @ (posedge clk) begin
pps_pipe <= {pps_pipe[14:0], pps};
pps_debounce = |pps_pipe;
pps_q <= pps_debounce;
pps_q2 <= pps_q;
pps_red <= !pps_q2 & pps_q;
end
always @ (posedge clk) begin
system_time <= system_time + 1;
if (start_of_cpi) begin
system_time_start_of_cpi <= system_time;
pps_frac_sec_start_of_cpi <= pps_frac_sec;
pps_sec_start_of_cpi <= pps_sec;
end
// Fractional seconds rolls over every time PPS strobes
if (pps_red) begin
pps_frac_sec <= 0;
end else begin
pps_frac_sec <= pps_frac_sec + 1;
end
if (reg_pps_set) begin
pps_sec <= reg_pps_sec_set;
end else if (pps_red) begin
pps_sec <= pps_sec + 1;
end
end
// ------------------------------
// Header Generation
// ------------------------------
wire start_of_cpi_hdr_clk;
xpm_cdc_pulse #(
.RST_USED(0)
)
xpm_cdc_pulse_inst (
.src_clk(clk),
.src_pulse(start_of_cpi_stretch),
.dest_clk(hdr_out[0].clk),
.dest_pulse(start_of_cpi_hdr_clk)
);
reg [7:0] hdr_count;
reg hdr_active;
reg hdr_active_q;
reg hdr_active_q2;
reg hdr_active_q3;
reg [63:0] hdr_bram_out;
reg [63:0] hdr_data;
wire hdr_tlast;
reg hdr_tlast_q;
reg hdr_tlast_q2;
reg hdr_tlast_q3;
always @ (posedge hdr_out[0].clk) begin
if (rst == 1'b1) begin
hdr_count <= 0;
hdr_active <= 0;
end else begin
if (start_of_cpi_hdr_clk) begin
hdr_active <= 1;
hdr_count <= 0;
end
if (hdr_active) begin
hdr_count <= hdr_count + 1;
if (hdr_count == 127) begin
hdr_active <= 0;
end
end
hdr_active_q <= hdr_active;
hdr_active_q2 <= hdr_active_q;
hdr_active_q3 <= hdr_active_q2;
hdr_tlast_q <= hdr_tlast;
hdr_tlast_q2 <= hdr_tlast_q;
hdr_tlast_q3 <= hdr_tlast_q2;
if (hdr_count == 6) begin // index 3 of header after accounting for latency (64 bit words)
hdr_data <= {32'h00000000, pps_sec_start_of_cpi};
end else if (hdr_count == 7) begin
hdr_data <= pps_frac_sec_start_of_cpi;
end else if (hdr_count == 8) begin
hdr_data <= system_time_start_of_cpi;
end else begin
hdr_data <= hdr_bram_out;
end
end
end
assign hdr_tlast = (hdr_count == 127) ? 1 : 0;
hdr_mem hdr_mem_i (
.clka(ctrl_if.clk),
.ena(1'b1),
.wea(hdr_bram_we),
.addra(waddr[9:2]),
.dina(wdata),
.clkb(hdr_out[0].clk),
.enb(1'b1),
.addrb(hdr_count),
.doutb(hdr_bram_out)
);
genvar i;
generate
for (i = 0; i < NUM_RX; i = i + 1) begin
hdr_fifo hdr_fifo_i (
.s_axis_aresetn(rstn),
.s_axis_aclk(hdr_out[i].clk),
.s_axis_tvalid(hdr_active_q3),
.s_axis_tready(),
.s_axis_tdata(hdr_data),
.s_axis_tlast(hdr_tlast_q3),
.m_axis_tvalid(hdr_out[i].tvalid),
.m_axis_tready(hdr_out[i].tready),
.m_axis_tdata(hdr_out[i].tdata),
.m_axis_tlast(hdr_out[i].tlast)
);
assign hdr_out[i].tkeep = '1;
assign hdr_out[i].tuser = 64;
assign hdr_out[i].tdest = 0;
end
endgenerate
// hdr_fifo hdr_fifo_i (
// .s_axis_aresetn(rstn),
// .s_axis_aclk(hdr_out.clk),
// .s_axis_tvalid(hdr_active_q3),
// .s_axis_tready(),
// .s_axis_tdata(hdr_data),
// .s_axis_tlast(hdr_tlast_q3),
// .m_axis_tvalid(hdr_out.tvalid),
// .m_axis_tready(hdr_out.tready),
// .m_axis_tdata(hdr_out.tdata),
// .m_axis_tlast(hdr_out.tlast)
// );
// assign hdr_out.tkeep = '1;
// assign hdr_out.tuser = 64;
// assign hdr_out.tdest = 0;
// ------------------------------
// Timing
// ------------------------------
wire rst;
wire rstn;
reg [31:0] pri_cnt;
reg [31:0] pulse_cnt;
wire inter_cpi_active;
reg start_of_pulse_reg;
reg start_of_cpi_reg;
reg [3:0] start_of_cpi_pipe;
wire start_of_cpi_stretch;
assign rst = reg_ctrl[0];
assign rstn = ~rst;
assign start_of_cpi = start_of_cpi_reg;
assign start_of_pulse = start_of_pulse_reg;
assign inter_cpi_active = (pulse_cnt < reg_num_pulses) ? 0 : 1;
assign start_of_cpi_stretch = |start_of_cpi_pipe;
always @ (posedge clk) begin
if (rst == 1'b1) begin
pri_cnt <= 0;
pulse_cnt <= 0;
start_of_pulse_reg = 1'b0;
end else begin
start_of_cpi_pipe <= {start_of_cpi_pipe[2:0], start_of_cpi};
start_of_pulse_reg = 1'b0;
start_of_cpi_reg = 1'b0;
pri_cnt <= pri_cnt + 1;
if (inter_cpi_active == 0) begin
if (pri_cnt == 1) begin
start_of_pulse_reg = 1'b1;
if (pulse_cnt == 0) begin
start_of_cpi_reg = 1'b1;
end
end
if (pri_cnt == reg_pri) begin
pri_cnt <= 0;
pulse_cnt <= pulse_cnt + 1;
end
end else begin
if (pri_cnt == reg_inter_cpi) begin
pri_cnt <= 0;
pulse_cnt <= 0;
end
end
end
end
endmodule
`resetall

876
radar_alinx_kintex.srcs/sources_1/hdl/top.v Executable file
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`timescale 1 ps / 1 ps
module top #
(
parameter NUM_RX = 2
)
(
input wire clk_200_n,
input wire clk_200_p,
output wire ddr_act_n,
output wire [16:0] ddr_adr,
output wire [1:0] ddr_ba,
output wire [0:0] ddr_bg,
output wire [0:0] ddr_ck_c,
output wire [0:0] ddr_ck_t,
output wire [0:0] ddr_cke,
output wire [0:0] ddr_cs_n,
inout wire [7:0] ddr_dm_n,
inout wire [63:0] ddr_dq,
inout wire [7:0] ddr_dqs_c,
inout wire [7:0] ddr_dqs_t,
output wire [0:0] ddr_odt,
output wire ddr_reset_n,
output wire mdc,
inout wire mdio,
output wire phy_rst_n,
input wire [3:0] rgmii_rd,
input wire rgmii_rx_ctl,
input wire rgmii_rxc,
output wire [3:0] rgmii_td,
output wire rgmii_tx_ctl,
output wire rgmii_txc,
input wire uart_rxd,
output wire uart_txd,
output wire [3:0] leds,
output wire fan_pwm,
output wire fmc_power_en,
input wire pps,
// RF Control
output wire tx0_rf_attn_sin, //ADRF5730
output wire tx0_rf_attn_clk, //ADRF5730
output wire tx0_rf_attn_le, //ADRF5730
output wire tx1_rf_attn_sin, //ADRF5730
output wire tx1_rf_attn_clk, //ADRF5730
output wire tx1_rf_attn_le, //ADRF5730
output wire txlo_drv_en,
output wire rx0_rf_attn_sin, //ADRF5721
output wire rx0_rf_attn_clk, //ADRF5721
output wire rx0_rf_attn_le, //ADRF5721
output wire rx0_if_attn_sin, //HMC624
output wire rx0_if_attn_clk, //HMC624
output wire rx0_if_attn_le, //HMC624
output wire rx0_lna_en,
output wire rx1_rf_attn_sin, //ADRF5721
output wire rx1_rf_attn_clk, //ADRF5721
output wire rx1_rf_attn_le, //ADRF5721
output wire rx1_if_attn_sin, //HMC624
output wire rx1_if_attn_clk, //HMC624
output wire rx1_if_attn_le, //HMC624
output wire rx1_lna_en,
// Ethernet: SFP+
input wire sfp0_rx_p,
input wire sfp0_rx_n,
output wire sfp0_tx_p,
output wire sfp0_tx_n,
input wire sfp1_rx_p,
input wire sfp1_rx_n,
output wire sfp1_tx_p,
output wire sfp1_tx_n,
input wire sfp2_rx_p,
input wire sfp2_rx_n,
output wire sfp2_tx_p,
output wire sfp2_tx_n,
input wire sfp3_rx_p,
input wire sfp3_rx_n,
output wire sfp3_tx_p,
output wire sfp3_tx_n,
input wire sfp_mgt_refclk_0_p,
input wire sfp_mgt_refclk_0_n,
output wire sfp0_tx_disable_b,
output wire sfp1_tx_disable_b,
output wire sfp2_tx_disable_b,
output wire sfp3_tx_disable_b,
// FMC AD9081
// SPI0 - To AD9081
// SPI1 - To Clk Gen HMC7044LP10BE
inout wire fmc_spi0_mosi,
inout wire fmc_spi0_miso,
inout wire fmc_spi0_sck,
inout wire fmc_spi0_ss,
inout wire fmc_spi1_mosi,
inout wire fmc_spi1_sck,
inout wire fmc_spi1_ss,
input wire [7:0] jesd_rxn_in,
input wire [7:0] jesd_rxp_in,
output wire [7:0] jesd_txn_out,
output wire [7:0] jesd_txp_out,
input wire jesd_sysref_p,
input wire jesd_sysref_n,
input wire jesd_core_clk_p,
input wire jesd_core_clk_n,
input wire jesd_qpll0_refclk_p,
input wire jesd_qpll0_refclk_n,
output wire resetb
);
wire mdio_mdio_i;
wire mdio_mdio_o;
wire mdio_mdio_t;
wire fmc_spi0_io0_i;
wire fmc_spi0_io0_o;
wire fmc_spi0_io0_t;
wire fmc_spi0_io1_i;
wire fmc_spi0_io1_o;
wire fmc_spi0_io1_t;
wire fmc_spi0_sck_i;
wire fmc_spi0_sck_o;
wire fmc_spi0_sck_t;
wire fmc_spi0_ss_i;
wire fmc_spi0_ss_o;
wire fmc_spi0_ss_t;
wire fmc_spi1_io0_i;
wire fmc_spi1_io0_o;
wire fmc_spi1_io0_t;
wire fmc_spi1_io1_i;
wire fmc_spi1_io1_o;
wire fmc_spi1_io1_t;
wire fmc_spi1_sck_i;
wire fmc_spi1_sck_o;
wire fmc_spi1_sck_t;
wire [1:0]fmc_spi1_ss_i;
wire [1:0]fmc_spi1_ss_o;
wire fmc_spi1_ss_t;
wire ddr_init_calib_complete;
wire mb_axi_clk;
wire mb_axi_aresetn;
wire mb_axi_reset;
wire common0_qpll1_lock_out;
wire common1_qpll1_lock_out;
wire jesd_axis_tx_aresetn;
wire jesd_axis_rx_aresetn;
wire [255:0]jesd_axis_rx_cmd_tdata;
wire jesd_axis_rx_cmd_tready;
wire [7:0]jesd_axis_rx_cmd_tuser;
wire jesd_axis_rx_cmd_tvalid;
wire [511:0]jesd_axis_rx_tdata;
wire jesd_axis_rx_tvalid;
wire [255:0]jesd_axis_tx_cmd_tdata;
wire jesd_axis_tx_cmd_tready;
wire jesd_axis_tx_cmd_tvalid;
wire [511:0]jesd_axis_tx_tdata;
wire jesd_axis_tx_tready;
wire jesd_rx_core_reset;
wire jesd_rx_sys_reset;
wire jesd_tx_core_reset;
wire jesd_tx_sys_reset;
wire jesd_core_clk;
wire jesd_core_clk_in;
wire [14:0] dac0_wf_bram_addr;
wire dac0_wf_bram_clk;
wire [31:0] dac0_wf_bram_din;
wire [31:0] dac0_wf_bram_dout;
wire dac0_wf_bram_en;
wire dac0_wf_bram_rst;
wire [3:0] dac0_wf_bram_we;
wire [14:0] dac1_wf_bram_addr;
wire dac1_wf_bram_clk;
wire [31:0] dac1_wf_bram_din;
wire [31:0] dac1_wf_bram_dout;
wire dac1_wf_bram_en;
wire dac1_wf_bram_rst;
wire [3:0] dac1_wf_bram_we;
wire [14:0] dac2_wf_bram_addr;
wire dac2_wf_bram_clk;
wire [31:0] dac2_wf_bram_din;
wire [31:0] dac2_wf_bram_dout;
wire dac2_wf_bram_en;
wire dac2_wf_bram_rst;
wire [3:0] dac2_wf_bram_we;
wire [14:0] dac3_wf_bram_addr;
wire dac3_wf_bram_clk;
wire [31:0] dac3_wf_bram_din;
wire [31:0] dac3_wf_bram_dout;
wire dac3_wf_bram_en;
wire dac3_wf_bram_rst;
wire [3:0] dac3_wf_bram_we;
wire start_of_cpi;
wire start_of_pulse;
wire [3:0] eth_clk;
wire [3:0] eth_resetn;
wire ext_reset_in_200;
// ------------------------------
// Buffers
// ------------------------------
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS") // Specify the input I/O standard
) core_clk_ibufds_c (
.I (jesd_core_clk_p),
.IB (jesd_core_clk_n),
.O (jesd_core_clk_in)
);
BUFG BUFG_inst (
.O(jesd_core_clk),
.I(jesd_core_clk_in)
);
IOBUF mdio_mdio_iobuf
(.I(mdio_mdio_o),
.IO(mdio),
.O(mdio_mdio_i),
.T(mdio_mdio_t));
IOBUF fmc_spi0_io0_iobuf
(.I(fmc_spi0_io0_o),
.IO(fmc_spi0_mosi),
.O(fmc_spi0_io0_i),
.T(fmc_spi0_io0_t));
IOBUF fmc_spi0_io1_iobuf
(.I(fmc_spi0_io1_o),
.IO(fmc_spi0_miso),
.O(fmc_spi0_io1_i),
.T(fmc_spi0_io1_t));
IOBUF fmc_spi0_sck_iobuf
(.I(fmc_spi0_sck_o),
.IO(fmc_spi0_sck),
.O(fmc_spi0_sck_i),
.T(fmc_spi0_sck_t));
IOBUF fmc_spi0_ss_iobuf_0
(.I(fmc_spi0_ss_o),
.IO(fmc_spi0_ss),
.O(fmc_spi0_ss_i),
.T(fmc_spi0_ss_t));
// This is 3 Wire Interface, Don't need MISO
// Use extra slave select to manually control tristate pin
// of MOSI, Xilinx driver doesn't support swapping tristate in the middle of
// a transaction
IOBUF fmc_spi1_io0_iobuf
(.I(fmc_spi1_io0_o),
.IO(fmc_spi1_mosi),
.O(fmc_spi1_io0_i),
.T(fmc_spi1_ss_o[1]));
assign fmc_spi1_io1_i = fmc_spi1_io0_i;
IOBUF fmc_spi1_sck_iobuf
(.I(fmc_spi1_sck_o),
.IO(fmc_spi1_sck),
.O(fmc_spi1_sck_i),
.T(fmc_spi1_sck_t));
IOBUF fmc_spi1_ss_iobuf_0
(.I(fmc_spi1_ss_o[0]),
.IO(fmc_spi1_ss),
.O(fmc_spi1_ss_i[0]),
.T(fmc_spi1_ss_t));
// ------------------------------
// BD
// ------------------------------
axi4l_intf # (
.AXI_ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32)
)
util_reg_if (
.clk(mb_axi_clk),
.resetn(mb_axi_aresetn)
);
axi4l_intf # (
.AXI_ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32)
)
timing_engine_if (
.clk(mb_axi_clk),
.resetn(mb_axi_aresetn)
);
axi4l_intf # (
.AXI_ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32)
)
dig_rx_if[NUM_RX] (
.clk(mb_axi_clk),
.resetn(mb_axi_aresetn)
);
axi4l_intf # (
.AXI_ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32)
)
wf_gen_if (
.clk(mb_axi_clk),
.resetn(mb_axi_aresetn)
);
// axi4s_intf # (
// .AXI_DATA_WIDTH(64),
// .AXI_ID_WIDTH(1)
// )
// rx_udp_axis[NUM_RX] (
// .clk(eth_clk[0]),
// .resetn(eth_resetn[0])
// );
axi4s_intf # (
.AXI_DATA_WIDTH(64),
.AXI_ID_WIDTH(1)
)
rx_udp_axis[NUM_RX] ();
axi4s_intf # (
.AXI_DATA_WIDTH(64),
.AXI_ID_WIDTH(1)
)
tx_udp_0_axis (
.clk(eth_clk[0]),
.resetn(eth_resetn[0])
);
assign ext_reset_in_200 = 1;
assign mb_axi_reset = !mb_axi_aresetn;
wire qspi_flash_aresetn;
reg [15:0] pps_pipe;
reg pps_debounce;
reg pps_q;
reg pps_q2;
reg pps_red;
always @ (posedge mb_axi_clk) begin
pps_pipe <= {pps_pipe[14:0], pps};
pps_debounce = |pps_pipe;
pps_q <= pps_debounce;
pps_q2 <= pps_q;
pps_red <= !pps_q2 & pps_q;
end
microblaze_bd microblaze_bd_i
(
.STARTUP_IO_cfgclk(),
.STARTUP_IO_cfgmclk(),
.STARTUP_IO_eos(),
.STARTUP_IO_gsr(1'b0),
.STARTUP_IO_gts(1'b0),
.STARTUP_IO_keyclearb(1'b1),
.STARTUP_IO_preq(),
.STARTUP_IO_userdoneo(1'b1),
.STARTUP_IO_usrclkts(1'b0),
.STARTUP_IO_usrdonets(1'b1),
.qspi_flash_aresetn(qspi_flash_aresetn),
.pps(pps_red),
.clk_200_in_clk_n(clk_200_n),
.clk_200_in_clk_p(clk_200_p),
.ddr_act_n(ddr_act_n),
.ddr_adr(ddr_adr),
.ddr_ba(ddr_ba),
.ddr_bg(ddr_bg),
.ddr_ck_c(ddr_ck_c),
.ddr_ck_t(ddr_ck_t),
.ddr_cke(ddr_cke),
.ddr_cs_n(ddr_cs_n),
.ddr_dm_n(ddr_dm_n),
.ddr_dq(ddr_dq),
.ddr_dqs_c(ddr_dqs_c),
.ddr_dqs_t(ddr_dqs_t),
.ddr_odt(ddr_odt),
.ddr_reset_n(ddr_reset_n),
.ddr_init_calib_complete(ddr_init_calib_complete),
.ext_reset_in_200(ext_reset_in_200),
.mdio_mdc(mdc),
.mdio_mdio_i(mdio_mdio_i),
.mdio_mdio_o(mdio_mdio_o),
.mdio_mdio_t(mdio_mdio_t),
.phy_rst_n(phy_rst_n),
.rgmii_rd(rgmii_rd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_rxc(rgmii_rxc),
.rgmii_td(rgmii_td),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_txc(rgmii_txc),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.mb_axi_clk(mb_axi_clk),
.mb_axi_aresetn(mb_axi_aresetn),
.util_reg_axil_araddr(util_reg_if.araddr),
.util_reg_axil_arprot(util_reg_if.arprot),
.util_reg_axil_arready(util_reg_if.arready),
.util_reg_axil_arvalid(util_reg_if.arvalid),
.util_reg_axil_awaddr(util_reg_if.awaddr),
.util_reg_axil_awprot(util_reg_if.awprot),
.util_reg_axil_awready(util_reg_if.awready),
.util_reg_axil_awvalid(util_reg_if.awvalid),
.util_reg_axil_bready(util_reg_if.bready),
.util_reg_axil_bresp(util_reg_if.bresp),
.util_reg_axil_bvalid(util_reg_if.bvalid),
.util_reg_axil_rdata(util_reg_if.rdata),
.util_reg_axil_rready(util_reg_if.rready),
.util_reg_axil_rresp(util_reg_if.rresp),
.util_reg_axil_rvalid(util_reg_if.rvalid),
.util_reg_axil_wdata(util_reg_if.wdata),
.util_reg_axil_wready(util_reg_if.wready),
.util_reg_axil_wstrb(util_reg_if.wstrb),
.util_reg_axil_wvalid(util_reg_if.wvalid),
.timing_engine_axil_araddr(timing_engine_if.araddr),
.timing_engine_axil_arprot(timing_engine_if.arprot),
.timing_engine_axil_arready(timing_engine_if.arready),
.timing_engine_axil_arvalid(timing_engine_if.arvalid),
.timing_engine_axil_awaddr(timing_engine_if.awaddr),
.timing_engine_axil_awprot(timing_engine_if.awprot),
.timing_engine_axil_awready(timing_engine_if.awready),
.timing_engine_axil_awvalid(timing_engine_if.awvalid),
.timing_engine_axil_bready(timing_engine_if.bready),
.timing_engine_axil_bresp(timing_engine_if.bresp),
.timing_engine_axil_bvalid(timing_engine_if.bvalid),
.timing_engine_axil_rdata(timing_engine_if.rdata),
.timing_engine_axil_rready(timing_engine_if.rready),
.timing_engine_axil_rresp(timing_engine_if.rresp),
.timing_engine_axil_rvalid(timing_engine_if.rvalid),
.timing_engine_axil_wdata(timing_engine_if.wdata),
.timing_engine_axil_wready(timing_engine_if.wready),
.timing_engine_axil_wstrb(timing_engine_if.wstrb),
.timing_engine_axil_wvalid(timing_engine_if.wvalid),
.dig_rx0_axil_araddr(dig_rx_if[0].araddr),
.dig_rx0_axil_arprot(dig_rx_if[0].arprot),
.dig_rx0_axil_arready(dig_rx_if[0].arready),
.dig_rx0_axil_arvalid(dig_rx_if[0].arvalid),
.dig_rx0_axil_awaddr(dig_rx_if[0].awaddr),
.dig_rx0_axil_awprot(dig_rx_if[0].awprot),
.dig_rx0_axil_awready(dig_rx_if[0].awready),
.dig_rx0_axil_awvalid(dig_rx_if[0].awvalid),
.dig_rx0_axil_bready(dig_rx_if[0].bready),
.dig_rx0_axil_bresp(dig_rx_if[0].bresp),
.dig_rx0_axil_bvalid(dig_rx_if[0].bvalid),
.dig_rx0_axil_rdata(dig_rx_if[0].rdata),
.dig_rx0_axil_rready(dig_rx_if[0].rready),
.dig_rx0_axil_rresp(dig_rx_if[0].rresp),
.dig_rx0_axil_rvalid(dig_rx_if[0].rvalid),
.dig_rx0_axil_wdata(dig_rx_if[0].wdata),
.dig_rx0_axil_wready(dig_rx_if[0].wready),
.dig_rx0_axil_wstrb(dig_rx_if[0].wstrb),
.dig_rx0_axil_wvalid(dig_rx_if[0].wvalid),
.dig_rx1_axil_araddr(dig_rx_if[1].araddr),
.dig_rx1_axil_arprot(dig_rx_if[1].arprot),
.dig_rx1_axil_arready(dig_rx_if[1].arready),
.dig_rx1_axil_arvalid(dig_rx_if[1].arvalid),
.dig_rx1_axil_awaddr(dig_rx_if[1].awaddr),
.dig_rx1_axil_awprot(dig_rx_if[1].awprot),
.dig_rx1_axil_awready(dig_rx_if[1].awready),
.dig_rx1_axil_awvalid(dig_rx_if[1].awvalid),
.dig_rx1_axil_bready(dig_rx_if[1].bready),
.dig_rx1_axil_bresp(dig_rx_if[1].bresp),
.dig_rx1_axil_bvalid(dig_rx_if[1].bvalid),
.dig_rx1_axil_rdata(dig_rx_if[1].rdata),
.dig_rx1_axil_rready(dig_rx_if[1].rready),
.dig_rx1_axil_rresp(dig_rx_if[1].rresp),
.dig_rx1_axil_rvalid(dig_rx_if[1].rvalid),
.dig_rx1_axil_wdata(dig_rx_if[1].wdata),
.dig_rx1_axil_wready(dig_rx_if[1].wready),
.dig_rx1_axil_wstrb(dig_rx_if[1].wstrb),
.dig_rx1_axil_wvalid(dig_rx_if[1].wvalid),
.wf_gen_axil_araddr(wf_gen_if.araddr),
.wf_gen_axil_arprot(wf_gen_if.arprot),
.wf_gen_axil_arready(wf_gen_if.arready),
.wf_gen_axil_arvalid(wf_gen_if.arvalid),
.wf_gen_axil_awaddr(wf_gen_if.awaddr),
.wf_gen_axil_awprot(wf_gen_if.awprot),
.wf_gen_axil_awready(wf_gen_if.awready),
.wf_gen_axil_awvalid(wf_gen_if.awvalid),
.wf_gen_axil_bready(wf_gen_if.bready),
.wf_gen_axil_bresp(wf_gen_if.bresp),
.wf_gen_axil_bvalid(wf_gen_if.bvalid),
.wf_gen_axil_rdata(wf_gen_if.rdata),
.wf_gen_axil_rready(wf_gen_if.rready),
.wf_gen_axil_rresp(wf_gen_if.rresp),
.wf_gen_axil_rvalid(wf_gen_if.rvalid),
.wf_gen_axil_wdata(wf_gen_if.wdata),
.wf_gen_axil_wready(wf_gen_if.wready),
.wf_gen_axil_wstrb(wf_gen_if.wstrb),
.wf_gen_axil_wvalid(wf_gen_if.wvalid),
.fmc_spi0_io0_i(fmc_spi0_io0_i),
.fmc_spi0_io0_o(fmc_spi0_io0_o),
.fmc_spi0_io0_t(fmc_spi0_io0_t),
.fmc_spi0_io1_i(fmc_spi0_io1_i),
.fmc_spi0_io1_o(fmc_spi0_io1_o),
.fmc_spi0_io1_t(fmc_spi0_io1_t),
.fmc_spi0_sck_i(fmc_spi0_sck_i),
.fmc_spi0_sck_o(fmc_spi0_sck_o),
.fmc_spi0_sck_t(fmc_spi0_sck_t),
.fmc_spi0_ss_i(fmc_spi0_ss_i),
.fmc_spi0_ss_o(fmc_spi0_ss_o),
.fmc_spi0_ss_t(fmc_spi0_ss_t),
.fmc_spi1_io0_i(fmc_spi1_io0_i),
.fmc_spi1_io0_o(fmc_spi1_io0_o),
.fmc_spi1_io0_t(fmc_spi1_io0_t),
.fmc_spi1_io1_i(fmc_spi1_io1_i),
.fmc_spi1_io1_o(fmc_spi1_io1_o),
.fmc_spi1_io1_t(fmc_spi1_io1_t),
.fmc_spi1_sck_i(fmc_spi1_sck_i),
.fmc_spi1_sck_o(fmc_spi1_sck_o),
.fmc_spi1_sck_t(fmc_spi1_sck_t),
.fmc_spi1_ss_i(fmc_spi1_ss_i),
.fmc_spi1_ss_o(fmc_spi1_ss_o),
.fmc_spi1_ss_t(fmc_spi1_ss_t),
.common0_qpll1_lock_out(common0_qpll1_lock_out),
.common1_qpll1_lock_out(common1_qpll1_lock_out),
.jesd_axis_tx_aresetn(jesd_axis_tx_aresetn),
.jesd_axis_rx_aresetn(jesd_axis_rx_aresetn),
.jesd_axis_rx_cmd_tdata(jesd_axis_rx_cmd_tdata),
.jesd_axis_rx_cmd_tready(jesd_axis_rx_cmd_tready),
.jesd_axis_rx_cmd_tuser(jesd_axis_rx_cmd_tuser),
.jesd_axis_rx_cmd_tvalid(jesd_axis_rx_cmd_tvalid),
.jesd_axis_rx_tdata(jesd_axis_rx_tdata),
.jesd_axis_rx_tvalid(jesd_axis_rx_tvalid),
.jesd_axis_tx_cmd_tdata(jesd_axis_tx_cmd_tdata),
.jesd_axis_tx_cmd_tready(jesd_axis_tx_cmd_tready),
.jesd_axis_tx_cmd_tvalid(jesd_axis_tx_cmd_tvalid),
.jesd_axis_tx_tdata(jesd_axis_tx_tdata),
.jesd_axis_tx_tready(jesd_axis_tx_tready),
.jesd_qpll0_refclk_clk_n(jesd_qpll0_refclk_n),
.jesd_qpll0_refclk_clk_p(jesd_qpll0_refclk_p),
.jesd_sysref_clk_n(jesd_sysref_n),
.jesd_sysref_clk_p(jesd_sysref_p),
.jesd_rx_core_reset(jesd_rx_core_reset),
.jesd_rxn_in(jesd_rxn_in),
.jesd_rxp_in(jesd_rxp_in),
.jesd_tx_core_reset(jesd_tx_core_reset),
.jesd_txn_out(jesd_txn_out),
.jesd_txp_out(jesd_txp_out),
.jesd_tx_sys_reset(jesd_tx_sys_reset),
.jesd_rx_sys_reset(jesd_rx_sys_reset),
.jesd_core_clk(jesd_core_clk),
.eth_clk(eth_clk[0]),
.eth_resetn(eth_resetn[0]),
.udp_rx_tdata(rx_udp_axis[0].tdata),
.udp_rx_tready(rx_udp_axis[0].tready),
.udp_rx_tvalid(rx_udp_axis[0].tvalid),
.udp_rx_tlast(rx_udp_axis[0].tlast),
.udp_tx_tdata(tx_udp_0_axis.tdata),
.udp_tx_tkeep(tx_udp_0_axis.tkeep),
.udp_tx_tlast(tx_udp_0_axis.tlast),
.udp_tx_tready(tx_udp_0_axis.tready),
.udp_tx_tvalid(tx_udp_0_axis.tvalid),
.dac0_wf_bram_addr(dac0_wf_bram_addr),
.dac0_wf_bram_clk(dac0_wf_bram_clk),
.dac0_wf_bram_din(dac0_wf_bram_din),
.dac0_wf_bram_dout(dac0_wf_bram_dout),
.dac0_wf_bram_en(dac0_wf_bram_en),
.dac0_wf_bram_rst(dac0_wf_bram_rst),
.dac0_wf_bram_we(dac0_wf_bram_we),
.dac1_wf_bram_addr(dac1_wf_bram_addr),
.dac1_wf_bram_clk(dac1_wf_bram_clk),
.dac1_wf_bram_din(dac1_wf_bram_din),
.dac1_wf_bram_dout(dac1_wf_bram_dout),
.dac1_wf_bram_en(dac1_wf_bram_en),
.dac1_wf_bram_rst(dac1_wf_bram_rst),
.dac1_wf_bram_we(dac1_wf_bram_we),
.dac2_wf_bram_addr(dac2_wf_bram_addr),
.dac2_wf_bram_clk(dac2_wf_bram_clk),
.dac2_wf_bram_din(dac2_wf_bram_din),
.dac2_wf_bram_dout(dac2_wf_bram_dout),
.dac2_wf_bram_en(dac2_wf_bram_en),
.dac2_wf_bram_rst(dac2_wf_bram_rst),
.dac2_wf_bram_we(dac2_wf_bram_we),
.dac3_wf_bram_addr(dac3_wf_bram_addr),
.dac3_wf_bram_clk(dac3_wf_bram_clk),
.dac3_wf_bram_din(dac3_wf_bram_din),
.dac3_wf_bram_dout(dac3_wf_bram_dout),
.dac3_wf_bram_en(dac3_wf_bram_en),
.dac3_wf_bram_rst(dac3_wf_bram_rst),
.dac3_wf_bram_we(dac3_wf_bram_we)
);
// ------------------------------
// Utility Registers
// ------------------------------
wire [31:0] gpi;
wire [31:0] gpo;
wire [15:0] packet_size;
wire eth_reset;
assign leds = gpo[3:0];
assign fmc_power_en = gpo[4];
assign resetb = gpo[5];
assign jesd_rx_core_reset = gpo[6];
assign jesd_tx_core_reset = gpo[7];
assign jesd_rx_sys_reset = gpo[8];
assign jesd_tx_sys_reset = gpo[9];
assign qspi_flash_aresetn = ~gpo[10];
assign eth_reset = gpo[15];
assign gpi[31:3] = 0;
// assign gpi[31] = start_of_cpi;
// assign gpi[30] = start_of_pulse;
assign gpi[2] = common1_qpll1_lock_out;
assign gpi[1] = common0_qpll1_lock_out;
assign gpi[0] = ddr_init_calib_complete;
util_reg util_reg_i
(
.ctrl_if(util_reg_if),
.gpo(gpo),
.gpi(gpi),
.packet_size(packet_size),
.fan_pwm(fan_pwm),
.tx0_rf_attn_sin(tx0_rf_attn_sin),
.tx0_rf_attn_clk(tx0_rf_attn_clk),
.tx0_rf_attn_le(tx0_rf_attn_le),
.tx1_rf_attn_sin(tx1_rf_attn_sin),
.tx1_rf_attn_clk(tx1_rf_attn_clk),
.tx1_rf_attn_le(tx1_rf_attn_le),
.rx0_rf_attn_sin(rx0_rf_attn_sin),
.rx0_rf_attn_clk(rx0_rf_attn_clk),
.rx0_rf_attn_le(rx0_rf_attn_le),
.rx0_if_attn_sin(rx0_if_attn_sin),
.rx0_if_attn_clk(rx0_if_attn_clk),
.rx0_if_attn_le(rx0_if_attn_le),
.rx1_rf_attn_sin(rx1_rf_attn_sin),
.rx1_rf_attn_clk(rx1_rf_attn_clk),
.rx1_rf_attn_le(rx1_rf_attn_le),
.rx1_if_attn_sin(rx1_if_attn_sin),
.rx1_if_attn_clk(rx1_if_attn_clk),
.rx1_if_attn_le(rx1_if_attn_le)
);
// ------------------------------
// 10G Ethernet
// ------------------------------
axi4s_intf # (
.AXI_DATA_WIDTH(64),
.AXI_USER_WIDTH(16)
)
tx_udp_switch_out[NUM_RX] ();
axi4s_intf # (
.AXI_DATA_WIDTH(64),
.AXI_USER_WIDTH(16)
)
hdr_out[NUM_RX] ();
axi4s_intf # (
.AXI_DATA_WIDTH(64),
.AXI_USER_WIDTH(15)
)
rx_axis[NUM_RX] ();
// These are from the block design, not currently using this though
assign tx_udp_0_axis.tuser = 1'b0;
assign tx_udp_0_axis.tready = 1'b1;
// This one is not connected to block design
assign rx_udp_axis[1].tready = 1;
ethernet_top ethernet_top_i
(
.clk_freerun(mb_axi_clk),
.reset(eth_reset),
.eth_clk(eth_clk),
.eth_resetn(eth_resetn),
.packet_size(packet_size),
.rx_udp_0(rx_udp_axis[0]),
.tx_udp_0(tx_udp_switch_out[0]),
.rx_udp_1(rx_udp_axis[1]),
.tx_udp_1(tx_udp_switch_out[1]),
.sfp0_rx_p(sfp0_rx_p),
.sfp0_rx_n(sfp0_rx_n),
.sfp0_tx_p(sfp0_tx_p),
.sfp0_tx_n(sfp0_tx_n),
.sfp1_rx_p(sfp1_rx_p),
.sfp1_rx_n(sfp1_rx_n),
.sfp1_tx_p(sfp1_tx_p),
.sfp1_tx_n(sfp1_tx_n),
.sfp2_rx_p(sfp2_rx_p),
.sfp2_rx_n(sfp2_rx_n),
.sfp2_tx_p(sfp2_tx_p),
.sfp2_tx_n(sfp2_tx_n),
.sfp3_rx_p(sfp3_rx_p),
.sfp3_rx_n(sfp3_rx_n),
.sfp3_tx_p(sfp3_tx_p),
.sfp3_tx_n(sfp3_tx_n),
.sfp_mgt_refclk_0_p(sfp_mgt_refclk_0_p),
.sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n),
.sfp0_tx_disable_b(sfp0_tx_disable_b),
.sfp1_tx_disable_b(sfp1_tx_disable_b),
.sfp2_tx_disable_b(sfp2_tx_disable_b),
.sfp3_tx_disable_b(sfp3_tx_disable_b)
);
genvar i;
generate
for (i = 0; i < NUM_RX; i = i + 1) begin
assign tx_udp_switch_out[i].clk = eth_clk[i];
assign tx_udp_switch_out[i].resetn = eth_resetn[i];
assign rx_axis[i].clk = eth_clk[i];
assign rx_axis[i].resetn = eth_resetn[i];
assign hdr_out[i].clk = eth_clk[i];
assign hdr_out[i].resetn = eth_resetn[i];
assign rx_udp_axis[i].clk = eth_clk[i];
assign rx_udp_axis[i].resetn = eth_resetn[i];
// ------------------------------
// RX Chain
// ------------------------------
digital_rx_chain digital_rx_chain_i (
.clk(jesd_core_clk),
.ctrl_if(dig_rx_if[i]),
.start_of_pulse(start_of_pulse),
.in_tvalid(jesd_axis_rx_tvalid),
.in_tdata_i(jesd_axis_rx_tdata[i*128+63 :i*128+0]),
.in_tdata_q(jesd_axis_rx_tdata[i*128+127 :i*128+64]),
.rx_out(rx_axis[i])
);
axis_switch_0 axis_switch_i (
.aclk(eth_clk[i]),
.aresetn(eth_resetn[i]),
.s_axis_tvalid({hdr_out[i].tvalid, rx_axis[i].tvalid}),
.s_axis_tready({hdr_out[i].tready, rx_axis[i].tready}),
.s_axis_tdata({hdr_out[i].tdata, rx_axis[i].tdata}),
.s_axis_tlast({hdr_out[i].tlast, rx_axis[i].tlast}),
.s_axis_tuser({hdr_out[i].tuser, rx_axis[i].tuser}),
.s_axis_tdest({hdr_out[i].tdest, rx_axis[i].tdest}),
.m_axis_tvalid(tx_udp_switch_out[i].tvalid),
.m_axis_tready(tx_udp_switch_out[i].tready),
.m_axis_tdata(tx_udp_switch_out[i].tdata),
.m_axis_tlast(tx_udp_switch_out[i].tlast),
.m_axis_tuser(tx_udp_switch_out[i].tuser),
.m_axis_tdest(tx_udp_switch_out[i].tdest),
.s_req_suppress(2'b00),
.s_decode_err()
);
assign tx_udp_switch_out[i].tkeep = '1;
end
endgenerate
// ------------------------------
// Timing Engine
// ------------------------------
timing_engine timing_engine_i
(
.clk(jesd_core_clk),
.pps(pps),
.ctrl_if(timing_engine_if),
.start_of_cpi(start_of_cpi),
.start_of_pulse(start_of_pulse),
.hdr_out(hdr_out)
);
// ------------------------------
// TX Chain
// ------------------------------
assign jesd_axis_rx_cmd_tready = 1'b1;
assign jesd_axis_tx_cmd_tdata = 0;
assign jesd_axis_tx_cmd_tvalid = 1'b1;
waveform_gen waveform_gen_i (
.clk(jesd_core_clk),
.ctrl_if(wf_gen_if),
.start_of_pulse(start_of_pulse),
.dac0_wf_bram_addr(dac0_wf_bram_addr),
.dac0_wf_bram_clk(dac0_wf_bram_clk),
.dac0_wf_bram_din(dac0_wf_bram_din),
.dac0_wf_bram_dout(dac0_wf_bram_dout),
.dac0_wf_bram_en(dac0_wf_bram_en),
.dac0_wf_bram_rst(dac0_wf_bram_rst),
.dac0_wf_bram_we(dac0_wf_bram_we),
.dac1_wf_bram_addr(dac1_wf_bram_addr),
.dac1_wf_bram_clk(dac1_wf_bram_clk),
.dac1_wf_bram_din(dac1_wf_bram_din),
.dac1_wf_bram_dout(dac1_wf_bram_dout),
.dac1_wf_bram_en(dac1_wf_bram_en),
.dac1_wf_bram_rst(dac1_wf_bram_rst),
.dac1_wf_bram_we(dac1_wf_bram_we),
.dac2_wf_bram_addr(dac2_wf_bram_addr),
.dac2_wf_bram_clk(dac2_wf_bram_clk),
.dac2_wf_bram_din(dac2_wf_bram_din),
.dac2_wf_bram_dout(dac2_wf_bram_dout),
.dac2_wf_bram_en(dac2_wf_bram_en),
.dac2_wf_bram_rst(dac2_wf_bram_rst),
.dac2_wf_bram_we(dac2_wf_bram_we),
.dac3_wf_bram_addr(dac3_wf_bram_addr),
.dac3_wf_bram_clk(dac3_wf_bram_clk),
.dac3_wf_bram_din(dac3_wf_bram_din),
.dac3_wf_bram_dout(dac3_wf_bram_dout),
.dac3_wf_bram_en(dac3_wf_bram_en),
.dac3_wf_bram_rst(dac3_wf_bram_rst),
.dac3_wf_bram_we(dac3_wf_bram_we),
.jesd_tx(jesd_axis_tx_tdata)
);
endmodule

321
radar_alinx_kintex.srcs/sources_1/hdl/util_reg.v Executable file
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`resetall
`timescale 1ns / 1ps
`default_nettype none
module util_reg #
(
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
)
(
// AXI4L Config Interface
axi4l_intf.slave ctrl_if,
output wire [31:0] gpo,
input wire [31:0] gpi,
output wire [15:0] packet_size,
output wire fan_pwm,
output wire tx0_rf_attn_sin, //ADRF5730
output wire tx0_rf_attn_clk, //ADRF5730
output wire tx0_rf_attn_le, //ADRF5730
output wire tx1_rf_attn_sin, //ADRF5730
output wire tx1_rf_attn_clk, //ADRF5730
output wire tx1_rf_attn_le, //ADRF5730
output wire rx0_rf_attn_sin, //ADRF5721
output wire rx0_rf_attn_clk, //ADRF5721
output wire rx0_rf_attn_le, //ADRF5721
output wire rx0_if_attn_sin, //HMC624
output wire rx0_if_attn_clk, //HMC624
output wire rx0_if_attn_le, //HMC624
output wire rx1_rf_attn_sin, //ADRF5721
output wire rx1_rf_attn_clk, //ADRF5721
output wire rx1_rf_attn_le, //ADRF5721
output wire rx1_if_attn_sin, //HMC624
output wire rx1_if_attn_clk, //HMC624
output wire rx1_if_attn_le //HMC624
);
// ------------------------------
// AXIL Decode
// ------------------------------
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
wire rden;
wire wren;
wire [AXI_DATA_WIDTH-1 : 0] wdata;
reg [AXI_DATA_WIDTH-1 : 0] rdata;
axil_slave
# (
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH)
) axil_slave_i
(
// AXIL Slave
.S_AXI_ACLK(ctrl_if.clk),
.S_AXI_ARESETN(ctrl_if.resetn),
.S_AXI_AWADDR(ctrl_if.awaddr),
.S_AXI_AWPROT(ctrl_if.awprot),
.S_AXI_AWVALID(ctrl_if.awvalid),
.S_AXI_AWREADY(ctrl_if.awready),
.S_AXI_WDATA(ctrl_if.wdata),
.S_AXI_WSTRB(ctrl_if.wstrb),
.S_AXI_WVALID(ctrl_if.wvalid),
.S_AXI_WREADY(ctrl_if.wready),
.S_AXI_BRESP(ctrl_if.bresp),
.S_AXI_BVALID(ctrl_if.bvalid),
.S_AXI_BREADY(ctrl_if.bready),
.S_AXI_ARADDR(ctrl_if.araddr),
.S_AXI_ARPROT(ctrl_if.arprot),
.S_AXI_ARVALID(ctrl_if.arvalid),
.S_AXI_ARREADY(ctrl_if.arready),
.S_AXI_RDATA(ctrl_if.rdata),
.S_AXI_RRESP(ctrl_if.rresp),
.S_AXI_RVALID(ctrl_if.rvalid),
.S_AXI_RREADY(ctrl_if.rready),
.raddr(raddr),
.waddr(waddr),
.wren(wren),
.rden(rden),
.wdata(wdata),
.rdata(rdata)
);
// ------------------------------
// Config Registers
// ------------------------------
wire reset;
assign reset = ~ctrl_if.resetn;
reg [31:0] scratch;
reg [31:0] reg_gpo;
reg [24:0] pwm_period;
reg [24:0] pwm_pulsewidth;
reg [15:0] reg_packet_size;
reg [7:0] reg_num_bits;
reg [15:0] reg_dev_sel;
reg [31:0] reg_spi_data;
reg [7:0] reg_spi_clk_div;
reg start_spi_transaction;
always @ (posedge ctrl_if.clk) begin
if (reset) begin
scratch <= 0;
end else if (wren && waddr[11:0] == 'h004) begin
scratch <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_gpo <= 0;
end else if (wren && waddr[11:0] == 'h008) begin
reg_gpo <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
pwm_period <= 1500000;
end else if (wren && waddr[11:0] == 'h010) begin
pwm_period <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
pwm_pulsewidth <= 500000;
end else if (wren && waddr[11:0] == 'h014) begin
pwm_pulsewidth <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_packet_size <= 1024;
end else if (wren && waddr[11:0] == 'h01C) begin
reg_packet_size <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_num_bits <= 6;
start_spi_transaction <= 0;
end else if (wren && waddr[11:0] == 'h100) begin
reg_num_bits <= wdata;
start_spi_transaction <= 1;
end else begin
start_spi_transaction <= 0;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_dev_sel <= 0;
end else if (wren && waddr[11:0] == 'h104) begin
reg_dev_sel <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_spi_data <= 0;
end else if (wren && waddr[11:0] == 'h108) begin
reg_spi_data <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (reset) begin
reg_spi_clk_div <= 16;
end else if (wren && waddr[11:0] == 'h10C) begin
reg_spi_clk_div <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (rden) begin
if (raddr[11:0] == 'h000)
rdata <= 'h12345678;
if (raddr[11:0] == 'h004)
rdata <= scratch;
if (raddr[11:0] == 'h008)
rdata <= reg_gpo;
if (raddr[11:0] == 'h00C)
rdata <= gpi;
if (raddr[11:0] == 'h010)
rdata <= pwm_period;
if (raddr[11:0] == 'h014)
rdata <= pwm_pulsewidth;
if (raddr[11:0] == 'h01C)
rdata <= reg_packet_size;
if (raddr[11:0] == 'h100)
rdata <= reg_num_bits;
if (raddr[11:0] == 'h104)
rdata <= reg_dev_sel;
if (raddr[11:0] == 'h108)
rdata <= reg_spi_data;
if (raddr[11:0] == 'h10C)
rdata <= reg_spi_clk_div;
if (raddr[11:0] == 'h110)
rdata <= {28'b0000000, 2'b00, spi_active, le_active};
end
end
assign gpo = reg_gpo;
assign packet_size = reg_packet_size;
// ------------------------------
// Fan PWM
// ------------------------------
reg [24:0] pwm_cnt;
reg pwm_out;
assign fan_pwm = pwm_out;
always @ (posedge ctrl_if.clk) begin
if (pwm_cnt < pwm_period) begin
pwm_cnt <= pwm_cnt + 1;
end else begin
pwm_cnt <= 0;
end
if (pwm_cnt < pwm_pulsewidth) begin
pwm_out <= 1'bz;
end else begin
pwm_out <= 1'b0;
end
end
// ------------------------------
// Attenuator Serial Bus Control
// ------------------------------
reg [7:0] spi_clk_cnt;
reg [7:0] spi_bit_cnt;
reg spi_active;
reg le_active;
reg [31:0] spi_shift_data;
reg [7:0] le_count;
reg le;
always @ (posedge ctrl_if.clk) begin
if (start_spi_transaction) begin
spi_active <= 1;
end
if (spi_active) begin
spi_clk_cnt <= spi_clk_cnt + 1;
if (spi_clk_cnt == reg_spi_clk_div) begin
spi_clk_cnt <= 0;
spi_bit_cnt <= spi_bit_cnt + 1;
// Shift Data Down One Bit
spi_shift_data <= spi_shift_data >> 1;
if (spi_bit_cnt == reg_num_bits) begin
spi_active <= 0;
le_active <= 1;
end
end
end else begin
spi_clk_cnt <= 0;
spi_bit_cnt <= 0;
spi_shift_data <= reg_spi_data;
end
if (le_active) begin
le_count <= le_count + 1;
if (le_count == 10) begin
le = 1;
end else if (le_count == 20) begin
le = 0;
le_active <= 0;
end;
end else begin
le_count <= 0;
le = 0;
end
end
wire spi_data;
wire spi_clk;
wire spi_le;
assign spi_data = spi_active ? spi_shift_data[0] : 0;
assign spi_clk = (spi_clk_cnt > reg_spi_clk_div[7:1]) ? 1 : 0;
assign spi_le = le;
assign tx0_rf_attn_sin = reg_dev_sel[0] ? spi_data : 0;
assign tx0_rf_attn_clk = reg_dev_sel[0] ? spi_clk : 0;
assign tx0_rf_attn_le = reg_dev_sel[0] ? spi_le : 0;
assign tx1_rf_attn_sin = reg_dev_sel[1] ? spi_data : 0;
assign tx1_rf_attn_clk = reg_dev_sel[1] ? spi_clk : 0;
assign tx1_rf_attn_le = reg_dev_sel[1] ? spi_le : 0;
assign rx0_rf_attn_sin = reg_dev_sel[2] ? spi_data : 0;
assign rx0_rf_attn_clk = reg_dev_sel[2] ? spi_clk : 0;
assign rx0_rf_attn_le = reg_dev_sel[2] ? spi_le : 0;
assign rx0_if_attn_sin = reg_dev_sel[3] ? spi_data : 0;
assign rx0_if_attn_clk = reg_dev_sel[3] ? spi_clk : 0;
assign rx0_if_attn_le = reg_dev_sel[3] ? spi_le : 0;
assign rx1_rf_attn_sin = reg_dev_sel[4] ? spi_data : 0;
assign rx1_rf_attn_clk = reg_dev_sel[4] ? spi_clk : 0;
assign rx1_rf_attn_le = reg_dev_sel[4] ? spi_le : 0;
assign rx1_if_attn_sin = reg_dev_sel[5] ? spi_data : 0;
assign rx1_if_attn_clk = reg_dev_sel[5] ? spi_clk : 0;
assign rx1_if_attn_le = reg_dev_sel[5] ? spi_le : 0;
endmodule
`resetall

159
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/arbiter.v Executable file
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/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Arbiter module
*/
module arbiter #
(
parameter PORTS = 4,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// blocking arbiter enable
parameter ARB_BLOCK = 0,
// block on acknowledge assert when nonzero, request deassert when 0
parameter ARB_BLOCK_ACK = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 0
)
(
input wire clk,
input wire rst,
input wire [PORTS-1:0] request,
input wire [PORTS-1:0] acknowledge,
output wire [PORTS-1:0] grant,
output wire grant_valid,
output wire [$clog2(PORTS)-1:0] grant_encoded
);
reg [PORTS-1:0] grant_reg = 0, grant_next;
reg grant_valid_reg = 0, grant_valid_next;
reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
assign grant_valid = grant_valid_reg;
assign grant = grant_reg;
assign grant_encoded = grant_encoded_reg;
wire request_valid;
wire [$clog2(PORTS)-1:0] request_index;
wire [PORTS-1:0] request_mask;
priority_encoder #(
.WIDTH(PORTS),
.LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
priority_encoder_inst (
.input_unencoded(request),
.output_valid(request_valid),
.output_encoded(request_index),
.output_unencoded(request_mask)
);
reg [PORTS-1:0] mask_reg = 0, mask_next;
wire masked_request_valid;
wire [$clog2(PORTS)-1:0] masked_request_index;
wire [PORTS-1:0] masked_request_mask;
priority_encoder #(
.WIDTH(PORTS),
.LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
priority_encoder_masked (
.input_unencoded(request & mask_reg),
.output_valid(masked_request_valid),
.output_encoded(masked_request_index),
.output_unencoded(masked_request_mask)
);
always @* begin
grant_next = 0;
grant_valid_next = 0;
grant_encoded_next = 0;
mask_next = mask_reg;
if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin
// granted request still asserted; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin
// granted request not yet acknowledged; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (request_valid) begin
if (ARB_TYPE_ROUND_ROBIN) begin
if (masked_request_valid) begin
grant_valid_next = 1;
grant_next = masked_request_mask;
grant_encoded_next = masked_request_index;
if (ARB_LSB_HIGH_PRIORITY) begin
mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
end else begin
mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
end
end else begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
if (ARB_LSB_HIGH_PRIORITY) begin
mask_next = {PORTS{1'b1}} << (request_index + 1);
end else begin
mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
end
end
end else begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
end
end
end
always @(posedge clk) begin
grant_reg <= grant_next;
grant_valid_reg <= grant_valid_next;
grant_encoded_reg <= grant_encoded_next;
mask_reg <= mask_next;
if (rst) begin
grant_reg <= 0;
grant_valid_reg <= 0;
grant_encoded_reg <= 0;
mask_reg <= 0;
end
end
endmodule
`resetall

452
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/arp.v Executable file
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/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* ARP block for IPv4, ethernet frame interface
*/
module arp #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Log2 of ARP cache size
parameter CACHE_ADDR_WIDTH = 9,
// ARP request retry count
parameter REQUEST_RETRY_COUNT = 4,
// ARP request retry interval (in cycles)
parameter REQUEST_RETRY_INTERVAL = 125000000*2,
// ARP request timeout (in cycles)
parameter REQUEST_TIMEOUT = 125000000*30
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* ARP requests
*/
input wire arp_request_valid,
output wire arp_request_ready,
input wire [31:0] arp_request_ip,
output wire arp_response_valid,
input wire arp_response_ready,
output wire arp_response_error,
output wire [47:0] arp_response_mac,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_cache
);
localparam [15:0]
ARP_OPER_ARP_REQUEST = 16'h0001,
ARP_OPER_ARP_REPLY = 16'h0002,
ARP_OPER_INARP_REQUEST = 16'h0008,
ARP_OPER_INARP_REPLY = 16'h0009;
wire incoming_frame_valid;
reg incoming_frame_ready;
wire [47:0] incoming_eth_dest_mac;
wire [47:0] incoming_eth_src_mac;
wire [15:0] incoming_eth_type;
wire [15:0] incoming_arp_htype;
wire [15:0] incoming_arp_ptype;
wire [7:0] incoming_arp_hlen;
wire [7:0] incoming_arp_plen;
wire [15:0] incoming_arp_oper;
wire [47:0] incoming_arp_sha;
wire [31:0] incoming_arp_spa;
wire [47:0] incoming_arp_tha;
wire [31:0] incoming_arp_tpa;
/*
* ARP frame processing
*/
arp_eth_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
arp_eth_rx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// ARP frame output
.m_frame_valid(incoming_frame_valid),
.m_frame_ready(incoming_frame_ready),
.m_eth_dest_mac(incoming_eth_dest_mac),
.m_eth_src_mac(incoming_eth_src_mac),
.m_eth_type(incoming_eth_type),
.m_arp_htype(incoming_arp_htype),
.m_arp_ptype(incoming_arp_ptype),
.m_arp_hlen(incoming_arp_hlen),
.m_arp_plen(incoming_arp_plen),
.m_arp_oper(incoming_arp_oper),
.m_arp_sha(incoming_arp_sha),
.m_arp_spa(incoming_arp_spa),
.m_arp_tha(incoming_arp_tha),
.m_arp_tpa(incoming_arp_tpa),
// Status signals
.busy(),
.error_header_early_termination(),
.error_invalid_header()
);
reg outgoing_frame_valid_reg = 1'b0, outgoing_frame_valid_next;
wire outgoing_frame_ready;
reg [47:0] outgoing_eth_dest_mac_reg = 48'd0, outgoing_eth_dest_mac_next;
reg [15:0] outgoing_arp_oper_reg = 16'd0, outgoing_arp_oper_next;
reg [47:0] outgoing_arp_tha_reg = 48'd0, outgoing_arp_tha_next;
reg [31:0] outgoing_arp_tpa_reg = 32'd0, outgoing_arp_tpa_next;
arp_eth_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
arp_eth_tx_inst (
.clk(clk),
.rst(rst),
// ARP frame input
.s_frame_valid(outgoing_frame_valid_reg),
.s_frame_ready(outgoing_frame_ready),
.s_eth_dest_mac(outgoing_eth_dest_mac_reg),
.s_eth_src_mac(local_mac),
.s_eth_type(16'h0806),
.s_arp_htype(16'h0001),
.s_arp_ptype(16'h0800),
.s_arp_oper(outgoing_arp_oper_reg),
.s_arp_sha(local_mac),
.s_arp_spa(local_ip),
.s_arp_tha(outgoing_arp_tha_reg),
.s_arp_tpa(outgoing_arp_tpa_reg),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy()
);
reg cache_query_request_valid_reg = 1'b0, cache_query_request_valid_next;
reg [31:0] cache_query_request_ip_reg = 32'd0, cache_query_request_ip_next;
wire cache_query_response_valid;
wire cache_query_response_error;
wire [47:0] cache_query_response_mac;
reg cache_write_request_valid_reg = 1'b0, cache_write_request_valid_next;
reg [31:0] cache_write_request_ip_reg = 32'd0, cache_write_request_ip_next;
reg [47:0] cache_write_request_mac_reg = 48'd0, cache_write_request_mac_next;
/*
* ARP cache
*/
arp_cache #(
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH)
)
arp_cache_inst (
.clk(clk),
.rst(rst),
// Query cache
.query_request_valid(cache_query_request_valid_reg),
.query_request_ready(),
.query_request_ip(cache_query_request_ip_reg),
.query_response_valid(cache_query_response_valid),
.query_response_ready(1'b1),
.query_response_error(cache_query_response_error),
.query_response_mac(cache_query_response_mac),
// Write cache
.write_request_valid(cache_write_request_valid_reg),
.write_request_ready(),
.write_request_ip(cache_write_request_ip_reg),
.write_request_mac(cache_write_request_mac_reg),
// Configuration
.clear_cache(clear_cache)
);
reg arp_request_operation_reg = 1'b0, arp_request_operation_next;
reg arp_request_ready_reg = 1'b0, arp_request_ready_next;
reg [31:0] arp_request_ip_reg = 32'd0, arp_request_ip_next;
reg arp_response_valid_reg = 1'b0, arp_response_valid_next;
reg arp_response_error_reg = 1'b0, arp_response_error_next;
reg [47:0] arp_response_mac_reg = 48'd0, arp_response_mac_next;
reg [5:0] arp_request_retry_cnt_reg = 6'd0, arp_request_retry_cnt_next;
reg [35:0] arp_request_timer_reg = 36'd0, arp_request_timer_next;
assign arp_request_ready = arp_request_ready_reg;
assign arp_response_valid = arp_response_valid_reg;
assign arp_response_error = arp_response_error_reg;
assign arp_response_mac = arp_response_mac_reg;
always @* begin
incoming_frame_ready = 1'b0;
outgoing_frame_valid_next = outgoing_frame_valid_reg && !outgoing_frame_ready;
outgoing_eth_dest_mac_next = outgoing_eth_dest_mac_reg;
outgoing_arp_oper_next = outgoing_arp_oper_reg;
outgoing_arp_tha_next = outgoing_arp_tha_reg;
outgoing_arp_tpa_next = outgoing_arp_tpa_reg;
cache_query_request_valid_next = 1'b0;
cache_query_request_ip_next = cache_query_request_ip_reg;
cache_write_request_valid_next = 1'b0;
cache_write_request_mac_next = cache_write_request_mac_reg;
cache_write_request_ip_next = cache_write_request_ip_reg;
arp_request_ready_next = 1'b0;
arp_request_ip_next = arp_request_ip_reg;
arp_request_operation_next = arp_request_operation_reg;
arp_request_retry_cnt_next = arp_request_retry_cnt_reg;
arp_request_timer_next = arp_request_timer_reg;
arp_response_valid_next = arp_response_valid_reg && !arp_response_ready;
arp_response_error_next = 1'b0;
arp_response_mac_next = 48'd0;
// manage incoming frames
incoming_frame_ready = outgoing_frame_ready;
if (incoming_frame_valid && incoming_frame_ready) begin
if (incoming_eth_type == 16'h0806 && incoming_arp_htype == 16'h0001 && incoming_arp_ptype == 16'h0800) begin
// store sender addresses in cache
cache_write_request_valid_next = 1'b1;
cache_write_request_ip_next = incoming_arp_spa;
cache_write_request_mac_next = incoming_arp_sha;
if (incoming_arp_oper == ARP_OPER_ARP_REQUEST) begin
// ARP request
if (incoming_arp_tpa == local_ip) begin
// send reply frame to valid incoming request
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = incoming_eth_src_mac;
outgoing_arp_oper_next = ARP_OPER_ARP_REPLY;
outgoing_arp_tha_next = incoming_arp_sha;
outgoing_arp_tpa_next = incoming_arp_spa;
end
end else if (incoming_arp_oper == ARP_OPER_INARP_REQUEST) begin
// INARP request
if (incoming_arp_tha == local_mac) begin
// send reply frame to valid incoming request
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = incoming_eth_src_mac;
outgoing_arp_oper_next = ARP_OPER_INARP_REPLY;
outgoing_arp_tha_next = incoming_arp_sha;
outgoing_arp_tpa_next = incoming_arp_spa;
end
end
end
end
// manage ARP lookup requests
if (arp_request_operation_reg) begin
arp_request_ready_next = 1'b0;
cache_query_request_valid_next = 1'b1;
arp_request_timer_next = arp_request_timer_reg - 1;
// if we got a response, it will go in the cache, so when the query succeds, we're done
if (cache_query_response_valid && !cache_query_response_error) begin
arp_request_operation_next = 1'b0;
cache_query_request_valid_next = 1'b0;
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = cache_query_response_mac;
end
// timer timeout
if (arp_request_timer_reg == 0) begin
if (arp_request_retry_cnt_reg > 0) begin
// have more retries
// send ARP request frame
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = 48'hffffffffffff;
outgoing_arp_oper_next = ARP_OPER_ARP_REQUEST;
outgoing_arp_tha_next = 48'h000000000000;
outgoing_arp_tpa_next = arp_request_ip_reg;
arp_request_retry_cnt_next = arp_request_retry_cnt_reg - 1;
if (arp_request_retry_cnt_reg > 1) begin
arp_request_timer_next = REQUEST_RETRY_INTERVAL;
end else begin
arp_request_timer_next = REQUEST_TIMEOUT;
end
end else begin
// out of retries
arp_request_operation_next = 1'b0;
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b1;
cache_query_request_valid_next = 1'b0;
end
end
end else begin
arp_request_ready_next = !arp_response_valid_next;
if (cache_query_request_valid_reg) begin
cache_query_request_valid_next = 1'b1;
if (cache_query_response_valid) begin
if (cache_query_response_error) begin
arp_request_operation_next = 1'b1;
// send ARP request frame
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = 48'hffffffffffff;
outgoing_arp_oper_next = ARP_OPER_ARP_REQUEST;
outgoing_arp_tha_next = 48'h000000000000;
outgoing_arp_tpa_next = arp_request_ip_reg;
arp_request_retry_cnt_next = REQUEST_RETRY_COUNT-1;
arp_request_timer_next = REQUEST_RETRY_INTERVAL;
end else begin
cache_query_request_valid_next = 1'b0;
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = cache_query_response_mac;
end
end
end else if (arp_request_valid && arp_request_ready) begin
if (arp_request_ip == 32'hffffffff) begin
// broadcast address; use broadcast MAC address
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = 48'hffffffffffff;
end else if (((arp_request_ip ^ gateway_ip) & subnet_mask) == 0) begin
// within subnet
// (no bits differ between request IP and gateway IP where subnet mask is set)
if (~(arp_request_ip | subnet_mask) == 0) begin
// broadcast address; use broadcast MAC address
// (all bits in request IP set where subnet mask is clear)
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = 48'hffffffffffff;
end else begin
// unicast address; look up IP directly
cache_query_request_valid_next = 1'b1;
cache_query_request_ip_next = arp_request_ip;
arp_request_ip_next = arp_request_ip;
end
end else begin
// outside of subnet, so look up gateway address
cache_query_request_valid_next = 1'b1;
cache_query_request_ip_next = gateway_ip;
arp_request_ip_next = gateway_ip;
end
end
end
end
always @(posedge clk) begin
if (rst) begin
outgoing_frame_valid_reg <= 1'b0;
cache_query_request_valid_reg <= 1'b0;
cache_write_request_valid_reg <= 1'b0;
arp_request_ready_reg <= 1'b0;
arp_request_operation_reg <= 1'b0;
arp_request_retry_cnt_reg <= 6'd0;
arp_request_timer_reg <= 36'd0;
arp_response_valid_reg <= 1'b0;
end else begin
outgoing_frame_valid_reg <= outgoing_frame_valid_next;
cache_query_request_valid_reg <= cache_query_request_valid_next;
cache_write_request_valid_reg <= cache_write_request_valid_next;
arp_request_ready_reg <= arp_request_ready_next;
arp_request_operation_reg <= arp_request_operation_next;
arp_request_retry_cnt_reg <= arp_request_retry_cnt_next;
arp_request_timer_reg <= arp_request_timer_next;
arp_response_valid_reg <= arp_response_valid_next;
end
cache_query_request_ip_reg <= cache_query_request_ip_next;
outgoing_eth_dest_mac_reg <= outgoing_eth_dest_mac_next;
outgoing_arp_oper_reg <= outgoing_arp_oper_next;
outgoing_arp_tha_reg <= outgoing_arp_tha_next;
outgoing_arp_tpa_reg <= outgoing_arp_tpa_next;
cache_write_request_mac_reg <= cache_write_request_mac_next;
cache_write_request_ip_reg <= cache_write_request_ip_next;
arp_request_ip_reg <= arp_request_ip_next;
arp_response_error_reg <= arp_response_error_next;
arp_response_mac_reg <= arp_response_mac_next;
end
endmodule
`resetall

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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* ARP cache
*/
module arp_cache #(
parameter CACHE_ADDR_WIDTH = 9
)
(
input wire clk,
input wire rst,
/*
* Cache query
*/
input wire query_request_valid,
output wire query_request_ready,
input wire [31:0] query_request_ip,
output wire query_response_valid,
input wire query_response_ready,
output wire query_response_error,
output wire [47:0] query_response_mac,
/*
* Cache write
*/
input wire write_request_valid,
output wire write_request_ready,
input wire [31:0] write_request_ip,
input wire [47:0] write_request_mac,
/*
* Configuration
*/
input wire clear_cache
);
reg mem_write = 0;
reg store_query = 0;
reg store_write = 0;
reg query_ip_valid_reg = 0, query_ip_valid_next;
reg [31:0] query_ip_reg = 0;
reg write_ip_valid_reg = 0, write_ip_valid_next;
reg [31:0] write_ip_reg = 0;
reg [47:0] write_mac_reg = 0;
reg clear_cache_reg = 0, clear_cache_next;
reg [CACHE_ADDR_WIDTH-1:0] wr_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, wr_ptr_next;
reg [CACHE_ADDR_WIDTH-1:0] rd_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, rd_ptr_next;
reg valid_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [31:0] ip_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [47:0] mac_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg query_request_ready_reg = 0, query_request_ready_next;
reg query_response_valid_reg = 0, query_response_valid_next;
reg query_response_error_reg = 0, query_response_error_next;
reg [47:0] query_response_mac_reg = 0;
reg write_request_ready_reg = 0, write_request_ready_next;
wire [31:0] query_request_hash;
wire [31:0] write_request_hash;
assign query_request_ready = query_request_ready_reg;
assign query_response_valid = query_response_valid_reg;
assign query_response_error = query_response_error_reg;
assign query_response_mac = query_response_mac_reg;
assign write_request_ready = write_request_ready_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
rd_hash (
.data_in(query_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(query_request_hash)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
wr_hash (
.data_in(write_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(write_request_hash)
);
integer i;
initial begin
for (i = 0; i < 2**CACHE_ADDR_WIDTH; i = i + 1) begin
valid_mem[i] = 1'b0;
ip_addr_mem[i] = 32'd0;
mac_addr_mem[i] = 48'd0;
end
end
always @* begin
mem_write = 1'b0;
store_query = 1'b0;
store_write = 1'b0;
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
clear_cache_next = clear_cache_reg | clear_cache;
query_ip_valid_next = query_ip_valid_reg;
query_request_ready_next = (~query_ip_valid_reg || ~query_request_valid || query_response_ready) && !clear_cache_next;
query_response_valid_next = query_response_valid_reg & ~query_response_ready;
query_response_error_next = query_response_error_reg;
if (query_ip_valid_reg && (~query_request_valid || query_response_ready)) begin
query_response_valid_next = 1;
query_ip_valid_next = 0;
if (valid_mem[rd_ptr_reg] && ip_addr_mem[rd_ptr_reg] == query_ip_reg) begin
query_response_error_next = 0;
end else begin
query_response_error_next = 1;
end
end
if (query_request_valid && query_request_ready && (~query_ip_valid_reg || ~query_request_valid || query_response_ready)) begin
store_query = 1;
query_ip_valid_next = 1;
rd_ptr_next = query_request_hash[CACHE_ADDR_WIDTH-1:0];
end
write_ip_valid_next = write_ip_valid_reg;
write_request_ready_next = !clear_cache_next;
if (write_ip_valid_reg) begin
write_ip_valid_next = 0;
mem_write = 1;
end
if (write_request_valid && write_request_ready) begin
store_write = 1;
write_ip_valid_next = 1;
wr_ptr_next = write_request_hash[CACHE_ADDR_WIDTH-1:0];
end
if (clear_cache) begin
clear_cache_next = 1'b1;
wr_ptr_next = 0;
end else if (clear_cache_reg) begin
wr_ptr_next = wr_ptr_reg + 1;
clear_cache_next = wr_ptr_next != 0;
mem_write = 1;
end
end
always @(posedge clk) begin
if (rst) begin
query_ip_valid_reg <= 1'b0;
query_request_ready_reg <= 1'b0;
query_response_valid_reg <= 1'b0;
write_ip_valid_reg <= 1'b0;
write_request_ready_reg <= 1'b0;
clear_cache_reg <= 1'b1;
wr_ptr_reg <= 0;
end else begin
query_ip_valid_reg <= query_ip_valid_next;
query_request_ready_reg <= query_request_ready_next;
query_response_valid_reg <= query_response_valid_next;
write_ip_valid_reg <= write_ip_valid_next;
write_request_ready_reg <= write_request_ready_next;
clear_cache_reg <= clear_cache_next;
wr_ptr_reg <= wr_ptr_next;
end
query_response_error_reg <= query_response_error_next;
if (store_query) begin
query_ip_reg <= query_request_ip;
end
if (store_write) begin
write_ip_reg <= write_request_ip;
write_mac_reg <= write_request_mac;
end
rd_ptr_reg <= rd_ptr_next;
query_response_mac_reg <= mac_addr_mem[rd_ptr_reg];
if (mem_write) begin
valid_mem[wr_ptr_reg] <= !clear_cache_reg;
ip_addr_mem[wr_ptr_reg] <= write_ip_reg;
mac_addr_mem[wr_ptr_reg] <= write_mac_reg;
end
end
endmodule
`resetall

331
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/arp_eth_rx.v Executable file
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/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* ARP ethernet frame receiver (Ethernet frame in, ARP frame out)
*/
module arp_eth_rx #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* ARP frame output
*/
output wire m_frame_valid,
input wire m_frame_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [15:0] m_arp_htype,
output wire [15:0] m_arp_ptype,
output wire [7:0] m_arp_hlen,
output wire [7:0] m_arp_plen,
output wire [15:0] m_arp_oper,
output wire [47:0] m_arp_sha,
output wire [31:0] m_arp_spa,
output wire [47:0] m_arp_tha,
output wire [31:0] m_arp_tpa,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_invalid_header
);
parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
parameter HDR_SIZE = 28;
parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = HDR_SIZE % BYTE_LANES;
// bus width assertions
initial begin
if (BYTE_LANES * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
/*
ARP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0806) 2 octets
HTYPE (1) 2 octets
PTYPE (0x0800) 2 octets
HLEN (6) 1 octets
PLEN (4) 1 octets
OPER 2 octets
SHA Sender MAC 6 octets
SPA Sender IP 4 octets
THA Target MAC 6 octets
TPA Target IP 4 octets
This module receives an Ethernet frame with header fields in parallel and
payload on an AXI stream interface, decodes the ARP packet fields, and
produces the frame fields in parallel.
*/
// datapath control signals
reg store_eth_hdr;
reg read_eth_header_reg = 1'b1, read_eth_header_next;
reg read_arp_header_reg = 1'b0, read_arp_header_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg m_frame_valid_reg = 1'b0, m_frame_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [15:0] m_arp_htype_reg = 16'd0, m_arp_htype_next;
reg [15:0] m_arp_ptype_reg = 16'd0, m_arp_ptype_next;
reg [7:0] m_arp_hlen_reg = 8'd0, m_arp_hlen_next;
reg [7:0] m_arp_plen_reg = 8'd0, m_arp_plen_next;
reg [15:0] m_arp_oper_reg = 16'd0, m_arp_oper_next;
reg [47:0] m_arp_sha_reg = 48'd0, m_arp_sha_next;
reg [31:0] m_arp_spa_reg = 32'd0, m_arp_spa_next;
reg [47:0] m_arp_tha_reg = 48'd0, m_arp_tha_next;
reg [31:0] m_arp_tpa_reg = 32'd0, m_arp_tpa_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_invalid_header_reg = 1'b0, error_invalid_header_next;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_frame_valid = m_frame_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_arp_htype = m_arp_htype_reg;
assign m_arp_ptype = m_arp_ptype_reg;
assign m_arp_hlen = m_arp_hlen_reg;
assign m_arp_plen = m_arp_plen_reg;
assign m_arp_oper = m_arp_oper_reg;
assign m_arp_sha = m_arp_sha_reg;
assign m_arp_spa = m_arp_spa_reg;
assign m_arp_tha = m_arp_tha_reg;
assign m_arp_tpa = m_arp_tpa_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_invalid_header = error_invalid_header_reg;
always @* begin
read_eth_header_next = read_eth_header_reg;
read_arp_header_next = read_arp_header_reg;
ptr_next = ptr_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
m_frame_valid_next = m_frame_valid_reg && !m_frame_ready;
m_arp_htype_next = m_arp_htype_reg;
m_arp_ptype_next = m_arp_ptype_reg;
m_arp_hlen_next = m_arp_hlen_reg;
m_arp_plen_next = m_arp_plen_reg;
m_arp_oper_next = m_arp_oper_reg;
m_arp_sha_next = m_arp_sha_reg;
m_arp_spa_next = m_arp_spa_reg;
m_arp_tha_next = m_arp_tha_reg;
m_arp_tpa_next = m_arp_tpa_reg;
error_header_early_termination_next = 1'b0;
error_invalid_header_next = 1'b0;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
if (read_eth_header_reg) begin
store_eth_hdr = 1'b1;
ptr_next = 0;
read_eth_header_next = 1'b0;
read_arp_header_next = 1'b1;
end
end
if (s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) begin
if (read_arp_header_reg) begin
// word transfer in - store it
ptr_next = ptr_reg + 1;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/BYTE_LANES && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[offset%BYTE_LANES])) begin \
field = s_eth_payload_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \
end
`_HEADER_FIELD_(0, m_arp_htype_next[1*8 +: 8])
`_HEADER_FIELD_(1, m_arp_htype_next[0*8 +: 8])
`_HEADER_FIELD_(2, m_arp_ptype_next[1*8 +: 8])
`_HEADER_FIELD_(3, m_arp_ptype_next[0*8 +: 8])
`_HEADER_FIELD_(4, m_arp_hlen_next[0*8 +: 8])
`_HEADER_FIELD_(5, m_arp_plen_next[0*8 +: 8])
`_HEADER_FIELD_(6, m_arp_oper_next[1*8 +: 8])
`_HEADER_FIELD_(7, m_arp_oper_next[0*8 +: 8])
`_HEADER_FIELD_(8, m_arp_sha_next[5*8 +: 8])
`_HEADER_FIELD_(9, m_arp_sha_next[4*8 +: 8])
`_HEADER_FIELD_(10, m_arp_sha_next[3*8 +: 8])
`_HEADER_FIELD_(11, m_arp_sha_next[2*8 +: 8])
`_HEADER_FIELD_(12, m_arp_sha_next[1*8 +: 8])
`_HEADER_FIELD_(13, m_arp_sha_next[0*8 +: 8])
`_HEADER_FIELD_(14, m_arp_spa_next[3*8 +: 8])
`_HEADER_FIELD_(15, m_arp_spa_next[2*8 +: 8])
`_HEADER_FIELD_(16, m_arp_spa_next[1*8 +: 8])
`_HEADER_FIELD_(17, m_arp_spa_next[0*8 +: 8])
`_HEADER_FIELD_(18, m_arp_tha_next[5*8 +: 8])
`_HEADER_FIELD_(19, m_arp_tha_next[4*8 +: 8])
`_HEADER_FIELD_(20, m_arp_tha_next[3*8 +: 8])
`_HEADER_FIELD_(21, m_arp_tha_next[2*8 +: 8])
`_HEADER_FIELD_(22, m_arp_tha_next[1*8 +: 8])
`_HEADER_FIELD_(23, m_arp_tha_next[0*8 +: 8])
`_HEADER_FIELD_(24, m_arp_tpa_next[3*8 +: 8])
`_HEADER_FIELD_(25, m_arp_tpa_next[2*8 +: 8])
`_HEADER_FIELD_(26, m_arp_tpa_next[1*8 +: 8])
`_HEADER_FIELD_(27, m_arp_tpa_next[0*8 +: 8])
if (ptr_reg == 27/BYTE_LANES && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[27%BYTE_LANES])) begin
read_arp_header_next = 1'b0;
end
`undef _HEADER_FIELD_
end
if (s_eth_payload_axis_tlast) begin
if (read_arp_header_next) begin
// don't have the whole header
error_header_early_termination_next = 1'b1;
end else if (m_arp_hlen_next != 4'd6 || m_arp_plen_next != 4'd4) begin
// lengths not valid
error_invalid_header_next = 1'b1;
end else begin
// otherwise, transfer tuser
m_frame_valid_next = !s_eth_payload_axis_tuser;
end
ptr_next = 1'b0;
read_eth_header_next = 1'b1;
read_arp_header_next = 1'b0;
end
end
if (read_eth_header_next) begin
s_eth_hdr_ready_next = !m_frame_valid_next;
end else begin
s_eth_payload_axis_tready_next = 1'b1;
end
end
always @(posedge clk) begin
read_eth_header_reg <= read_eth_header_next;
read_arp_header_reg <= read_arp_header_next;
ptr_reg <= ptr_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_frame_valid_reg <= m_frame_valid_next;
m_arp_htype_reg <= m_arp_htype_next;
m_arp_ptype_reg <= m_arp_ptype_next;
m_arp_hlen_reg <= m_arp_hlen_next;
m_arp_plen_reg <= m_arp_plen_next;
m_arp_oper_reg <= m_arp_oper_next;
m_arp_sha_reg <= m_arp_sha_next;
m_arp_spa_reg <= m_arp_spa_next;
m_arp_tha_reg <= m_arp_tha_next;
m_arp_tpa_reg <= m_arp_tpa_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_invalid_header_reg <= error_invalid_header_next;
busy_reg <= read_arp_header_next;
// datapath
if (store_eth_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
end
if (rst) begin
read_eth_header_reg <= 1'b1;
read_arp_header_reg <= 1'b0;
ptr_reg <= 0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_frame_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_invalid_header_reg <= 1'b0;
end
end
endmodule
`resetall

368
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/arp_eth_tx.v Executable file
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@@ -0,0 +1,368 @@
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* ARP ethernet frame transmitter (ARP frame in, Ethernet frame out)
*/
module arp_eth_tx #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* ARP frame input
*/
input wire s_frame_valid,
output wire s_frame_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [15:0] s_arp_htype,
input wire [15:0] s_arp_ptype,
input wire [15:0] s_arp_oper,
input wire [47:0] s_arp_sha,
input wire [31:0] s_arp_spa,
input wire [47:0] s_arp_tha,
input wire [31:0] s_arp_tpa,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* Status signals
*/
output wire busy
);
parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
parameter HDR_SIZE = 28;
parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = HDR_SIZE % BYTE_LANES;
// bus width assertions
initial begin
if (BYTE_LANES * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
/*
ARP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0806) 2 octets
HTYPE (1) 2 octets
PTYPE (0x0800) 2 octets
HLEN (6) 1 octets
PLEN (4) 1 octets
OPER 2 octets
SHA Sender MAC 6 octets
SPA Sender IP 4 octets
THA Target MAC 6 octets
TPA Target IP 4 octets
This module receives an ARP frame with header fields in parallel and
transmits the complete Ethernet payload on an AXI interface.
*/
// datapath control signals
reg store_frame;
reg send_arp_header_reg = 1'b0, send_arp_header_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg [15:0] arp_htype_reg = 16'd0;
reg [15:0] arp_ptype_reg = 16'd0;
reg [15:0] arp_oper_reg = 16'd0;
reg [47:0] arp_sha_reg = 48'd0;
reg [31:0] arp_spa_reg = 32'd0;
reg [47:0] arp_tha_reg = 48'd0;
reg [31:0] arp_tpa_reg = 32'd0;
reg s_frame_ready_reg = 1'b0, s_frame_ready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg busy_reg = 1'b0;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_frame_ready = s_frame_ready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign busy = busy_reg;
always @* begin
send_arp_header_next = send_arp_header_reg;
ptr_next = ptr_reg;
s_frame_ready_next = 1'b0;
store_frame = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_payload_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_eth_payload_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
m_eth_payload_axis_tvalid_int = 1'b0;
m_eth_payload_axis_tlast_int = 1'b0;
m_eth_payload_axis_tuser_int = 1'b0;
if (s_frame_ready && s_frame_valid) begin
store_frame = 1'b1;
m_eth_hdr_valid_next = 1'b1;
ptr_next = 0;
send_arp_header_next = 1'b1;
end
if (m_eth_payload_axis_tready_int_reg) begin
if (send_arp_header_reg) begin
ptr_next = ptr_reg + 1;
m_eth_payload_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_eth_payload_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
m_eth_payload_axis_tvalid_int = 1'b1;
m_eth_payload_axis_tlast_int = 1'b0;
m_eth_payload_axis_tuser_int = 1'b0;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/BYTE_LANES) begin \
m_eth_payload_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \
m_eth_payload_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \
end
`_HEADER_FIELD_(0, arp_htype_reg[1*8 +: 8])
`_HEADER_FIELD_(1, arp_htype_reg[0*8 +: 8])
`_HEADER_FIELD_(2, arp_ptype_reg[1*8 +: 8])
`_HEADER_FIELD_(3, arp_ptype_reg[0*8 +: 8])
`_HEADER_FIELD_(4, 8'd6)
`_HEADER_FIELD_(5, 8'd4)
`_HEADER_FIELD_(6, arp_oper_reg[1*8 +: 8])
`_HEADER_FIELD_(7, arp_oper_reg[0*8 +: 8])
`_HEADER_FIELD_(8, arp_sha_reg[5*8 +: 8])
`_HEADER_FIELD_(9, arp_sha_reg[4*8 +: 8])
`_HEADER_FIELD_(10, arp_sha_reg[3*8 +: 8])
`_HEADER_FIELD_(11, arp_sha_reg[2*8 +: 8])
`_HEADER_FIELD_(12, arp_sha_reg[1*8 +: 8])
`_HEADER_FIELD_(13, arp_sha_reg[0*8 +: 8])
`_HEADER_FIELD_(14, arp_spa_reg[3*8 +: 8])
`_HEADER_FIELD_(15, arp_spa_reg[2*8 +: 8])
`_HEADER_FIELD_(16, arp_spa_reg[1*8 +: 8])
`_HEADER_FIELD_(17, arp_spa_reg[0*8 +: 8])
`_HEADER_FIELD_(18, arp_tha_reg[5*8 +: 8])
`_HEADER_FIELD_(19, arp_tha_reg[4*8 +: 8])
`_HEADER_FIELD_(20, arp_tha_reg[3*8 +: 8])
`_HEADER_FIELD_(21, arp_tha_reg[2*8 +: 8])
`_HEADER_FIELD_(22, arp_tha_reg[1*8 +: 8])
`_HEADER_FIELD_(23, arp_tha_reg[0*8 +: 8])
`_HEADER_FIELD_(24, arp_tpa_reg[3*8 +: 8])
`_HEADER_FIELD_(25, arp_tpa_reg[2*8 +: 8])
`_HEADER_FIELD_(26, arp_tpa_reg[1*8 +: 8])
`_HEADER_FIELD_(27, arp_tpa_reg[0*8 +: 8])
if (ptr_reg == 27/BYTE_LANES) begin
m_eth_payload_axis_tlast_int = 1'b1;
send_arp_header_next = 1'b0;
end
`undef _HEADER_FIELD_
end
end
s_frame_ready_next = !m_eth_hdr_valid_next && !send_arp_header_next;
end
always @(posedge clk) begin
send_arp_header_reg <= send_arp_header_next;
ptr_reg <= ptr_next;
s_frame_ready_reg <= s_frame_ready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
busy_reg <= send_arp_header_next;
if (store_frame) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
arp_htype_reg <= s_arp_htype;
arp_ptype_reg <= s_arp_ptype;
arp_oper_reg <= s_arp_oper;
arp_sha_reg <= s_arp_sha;
arp_spa_reg <= s_arp_spa;
arp_tha_reg <= s_arp_tha;
arp_tpa_reg <= s_arp_tpa;
end
if (rst) begin
send_arp_header_reg <= 1'b0;
ptr_reg <= 0;
s_frame_ready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
// datapath
if (store_eth_payload_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

325
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/axis_adapter.v Executable file
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/*
Copyright (c) 2014-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream bus width adapter
*/
module axis_adapter #
(
// Width of input AXI stream interface in bits
parameter S_DATA_WIDTH = 8,
// Propagate tkeep signal on input interface
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [S_DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [M_DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
);
// force keep width to 1 when disabled
localparam S_BYTE_LANES = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
localparam M_BYTE_LANES = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
// bus byte sizes (must be identical)
localparam S_BYTE_SIZE = S_DATA_WIDTH / S_BYTE_LANES;
localparam M_BYTE_SIZE = M_DATA_WIDTH / M_BYTE_LANES;
// bus width assertions
initial begin
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_WIDTH) begin
$error("Error: input data width not evenly divisible (instance %m)");
$finish;
end
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_WIDTH) begin
$error("Error: output data width not evenly divisible (instance %m)");
$finish;
end
if (S_BYTE_SIZE != M_BYTE_SIZE) begin
$error("Error: byte size mismatch (instance %m)");
$finish;
end
end
generate
if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
// same width; bypass
assign s_axis_tready = m_axis_tready;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = M_KEEP_ENABLE ? s_axis_tkeep : {M_KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tid = ID_ENABLE ? s_axis_tid : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? s_axis_tdest : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? s_axis_tuser : {USER_WIDTH{1'b0}};
end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
// output is wider; upsize
// required number of segments in wider bus
localparam SEG_COUNT = M_BYTE_LANES / S_BYTE_LANES;
// data width and keep width per segment
localparam SEG_DATA_WIDTH = M_DATA_WIDTH / SEG_COUNT;
localparam SEG_KEEP_WIDTH = M_BYTE_LANES / SEG_COUNT;
reg [$clog2(SEG_COUNT)-1:0] seg_reg = 0;
reg [S_DATA_WIDTH-1:0] s_axis_tdata_reg = {S_DATA_WIDTH{1'b0}};
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep_reg = {S_KEEP_WIDTH{1'b0}};
reg s_axis_tvalid_reg = 1'b0;
reg s_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] s_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] s_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] s_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [M_DATA_WIDTH-1:0] m_axis_tdata_reg = {M_DATA_WIDTH{1'b0}};
reg [M_KEEP_WIDTH-1:0] m_axis_tkeep_reg = {M_KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
assign s_axis_tready = !s_axis_tvalid_reg;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = M_KEEP_ENABLE ? m_axis_tkeep_reg : {M_KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready;
if (!m_axis_tvalid_reg || m_axis_tready) begin
// output register empty
if (seg_reg == 0) begin
m_axis_tdata_reg[seg_reg*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep;
end else begin
m_axis_tdata_reg[seg_reg*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] <= s_axis_tdata;
m_axis_tkeep_reg[seg_reg*SEG_KEEP_WIDTH +: SEG_KEEP_WIDTH] <= s_axis_tkeep;
end
m_axis_tlast_reg <= s_axis_tvalid_reg ? s_axis_tlast_reg : s_axis_tlast;
m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis_tid;
m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis_tdest;
m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis_tuser;
if (s_axis_tvalid_reg) begin
// consume data from buffer
s_axis_tvalid_reg <= 1'b0;
if (s_axis_tlast_reg || seg_reg == SEG_COUNT-1) begin
seg_reg <= 0;
m_axis_tvalid_reg <= 1'b1;
end else begin
seg_reg <= seg_reg + 1;
end
end else if (s_axis_tvalid) begin
// data direct from input
if (s_axis_tlast || seg_reg == SEG_COUNT-1) begin
seg_reg <= 0;
m_axis_tvalid_reg <= 1'b1;
end else begin
seg_reg <= seg_reg + 1;
end
end
end else if (s_axis_tvalid && s_axis_tready) begin
// store input data in skid buffer
s_axis_tdata_reg <= s_axis_tdata;
s_axis_tkeep_reg <= s_axis_tkeep;
s_axis_tvalid_reg <= 1'b1;
s_axis_tlast_reg <= s_axis_tlast;
s_axis_tid_reg <= s_axis_tid;
s_axis_tdest_reg <= s_axis_tdest;
s_axis_tuser_reg <= s_axis_tuser;
end
if (rst) begin
seg_reg <= 0;
s_axis_tvalid_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
end
end
end else begin : downsize
// output is narrower; downsize
// required number of segments in wider bus
localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES;
// data width and keep width per segment
localparam SEG_DATA_WIDTH = S_DATA_WIDTH / SEG_COUNT;
localparam SEG_KEEP_WIDTH = S_BYTE_LANES / SEG_COUNT;
reg [S_DATA_WIDTH-1:0] s_axis_tdata_reg = {S_DATA_WIDTH{1'b0}};
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep_reg = {S_KEEP_WIDTH{1'b0}};
reg s_axis_tvalid_reg = 1'b0;
reg s_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] s_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] s_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] s_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [M_DATA_WIDTH-1:0] m_axis_tdata_reg = {M_DATA_WIDTH{1'b0}};
reg [M_KEEP_WIDTH-1:0] m_axis_tkeep_reg = {M_KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
assign s_axis_tready = !s_axis_tvalid_reg;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = M_KEEP_ENABLE ? m_axis_tkeep_reg : {M_KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready;
if (!m_axis_tvalid_reg || m_axis_tready) begin
// output register empty
m_axis_tdata_reg <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep;
m_axis_tlast_reg <= 1'b0;
m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis_tid;
m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis_tdest;
m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis_tuser;
if (s_axis_tvalid_reg) begin
// buffer has data; shift out from buffer
s_axis_tdata_reg <= s_axis_tdata_reg >> SEG_DATA_WIDTH;
s_axis_tkeep_reg <= s_axis_tkeep_reg >> SEG_KEEP_WIDTH;
m_axis_tvalid_reg <= 1'b1;
if ((s_axis_tkeep_reg >> SEG_KEEP_WIDTH) == 0) begin
s_axis_tvalid_reg <= 1'b0;
m_axis_tlast_reg <= s_axis_tlast_reg;
end
end else if (s_axis_tvalid && s_axis_tready) begin
// buffer is empty; store from input
s_axis_tdata_reg <= s_axis_tdata >> SEG_DATA_WIDTH;
s_axis_tkeep_reg <= s_axis_tkeep >> SEG_KEEP_WIDTH;
s_axis_tlast_reg <= s_axis_tlast;
s_axis_tid_reg <= s_axis_tid;
s_axis_tdest_reg <= s_axis_tdest;
s_axis_tuser_reg <= s_axis_tuser;
m_axis_tvalid_reg <= 1'b1;
if ((s_axis_tkeep >> SEG_KEEP_WIDTH) == 0) begin
s_axis_tvalid_reg <= 1'b0;
m_axis_tlast_reg <= s_axis_tlast;
end else begin
s_axis_tvalid_reg <= 1'b1;
end
end
end else if (s_axis_tvalid && s_axis_tready) begin
// store input data
s_axis_tdata_reg <= s_axis_tdata;
s_axis_tkeep_reg <= s_axis_tkeep;
s_axis_tvalid_reg <= 1'b1;
s_axis_tlast_reg <= s_axis_tlast;
s_axis_tid_reg <= s_axis_tid;
s_axis_tdest_reg <= s_axis_tdest;
s_axis_tuser_reg <= s_axis_tuser;
end
if (rst) begin
s_axis_tvalid_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
endgenerate
endmodule
`resetall

910
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/axis_async_fifo.v Executable file
View File

@@ -0,0 +1,910 @@
/*
Copyright (c) 2014-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO
*/
module axis_async_fifo #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter OUTPUT_FIFO_ENABLE = 0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_WHEN_FULL = 0,
// Mark incoming frames as bad frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO to be clear
parameter MARK_WHEN_FULL = 0,
// Enable pause request input
parameter PAUSE_ENABLE = 0,
// Pause between frames
parameter FRAME_PAUSE = FRAME_FIFO
)
(
/*
* AXI input
*/
input wire s_clk,
input wire s_rst,
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
input wire m_clk,
input wire m_rst,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Pause
*/
input wire s_pause_req,
output wire s_pause_ack,
input wire m_pause_req,
output wire m_pause_ack,
/*
* Status
*/
output wire [$clog2(DEPTH):0] s_status_depth,
output wire [$clog2(DEPTH):0] s_status_depth_commit,
output wire s_status_overflow,
output wire s_status_bad_frame,
output wire s_status_good_frame,
output wire [$clog2(DEPTH):0] m_status_depth,
output wire [$clog2(DEPTH):0] m_status_depth_commit,
output wire m_status_overflow,
output wire m_status_bad_frame,
output wire m_status_good_frame
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
// check configuration
initial begin
if (FRAME_FIFO && !LAST_ENABLE) begin
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
$finish;
end
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin
$error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
$finish;
end
if (MARK_WHEN_FULL && FRAME_FIFO) begin
$error("Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
$finish;
end
if (MARK_WHEN_FULL && !LAST_ENABLE) begin
$error("Error: MARK_WHEN_FULL set requires LAST_ENABLE set (instance %m)");
$finish;
end
end
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
function [ADDR_WIDTH:0] bin2gray(input [ADDR_WIDTH:0] b);
bin2gray = b ^ (b >> 1);
endfunction
function [ADDR_WIDTH:0] gray2bin(input [ADDR_WIDTH:0] g);
integer i;
for (i = 0; i <= ADDR_WIDTH; i = i + 1) begin
gray2bin[i] = ^(g >> i);
end
endfunction
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_commit_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_sync_commit_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_conv_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_conv_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_temp;
reg [ADDR_WIDTH:0] rd_ptr_temp;
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] wr_ptr_commit_sync_reg = {ADDR_WIDTH+1{1'b0}};
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg wr_ptr_update_valid_reg = 1'b0;
reg wr_ptr_update_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_sync1_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_sync2_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_sync3_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_ack_sync1_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_ack_sync2_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg s_rst_sync1_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg s_rst_sync2_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg s_rst_sync3_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg m_rst_sync1_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg m_rst_sync2_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg m_rst_sync3_reg = 1'b1;
(* ramstyle = "no_rw_check" *)
reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg mem_read_data_valid_reg = 1'b0;
(* shreg_extract = "no" *)
reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0];
reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {ADDR_WIDTH-1{1'b0}}});
// empty when pointers match exactly
wire empty = FRAME_FIFO ? (rd_ptr_reg == wr_ptr_commit_sync_reg) : (rd_ptr_gray_reg == wr_ptr_gray_sync2_reg);
// overflow within packet
wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
// control signals
reg write;
reg read;
reg store_output;
reg s_frame_reg = 1'b0;
reg m_frame_reg = 1'b0;
reg drop_frame_reg = 1'b0;
reg mark_frame_reg = 1'b0;
reg send_frame_reg = 1'b0;
reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
reg m_drop_frame_reg = 1'b0;
reg m_terminate_frame_reg = 1'b0;
reg [ADDR_WIDTH:0] s_depth_reg = 0;
reg [ADDR_WIDTH:0] s_depth_commit_reg = 0;
reg [ADDR_WIDTH:0] m_depth_reg = 0;
reg [ADDR_WIDTH:0] m_depth_commit_reg = 0;
reg overflow_sync1_reg = 1'b0;
reg overflow_sync2_reg = 1'b0;
reg overflow_sync3_reg = 1'b0;
reg overflow_sync4_reg = 1'b0;
reg bad_frame_sync1_reg = 1'b0;
reg bad_frame_sync2_reg = 1'b0;
reg bad_frame_sync3_reg = 1'b0;
reg bad_frame_sync4_reg = 1'b0;
reg good_frame_sync1_reg = 1'b0;
reg good_frame_sync2_reg = 1'b0;
reg good_frame_sync3_reg = 1'b0;
reg good_frame_sync4_reg = 1'b0;
assign s_axis_tready = (FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL)) && !s_rst_sync3_reg;
wire [WIDTH-1:0] s_axis;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast | mark_frame_reg;
if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis_tuser;
endgenerate
wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1];
wire m_axis_tready_pipe;
wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1];
wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0];
wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] | m_terminate_frame_reg : 1'b1;
wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? (m_terminate_frame_reg ? USER_BAD_FRAME_VALUE : m_axis[USER_OFFSET +: USER_WIDTH]) : {USER_WIDTH{1'b0}};
wire m_axis_tready_out;
wire m_axis_tvalid_out;
wire [DATA_WIDTH-1:0] m_axis_tdata_out;
wire [KEEP_WIDTH-1:0] m_axis_tkeep_out;
wire m_axis_tlast_out;
wire [ID_WIDTH-1:0] m_axis_tid_out;
wire [DEST_WIDTH-1:0] m_axis_tdest_out;
wire [USER_WIDTH-1:0] m_axis_tuser_out;
wire pipe_ready;
assign s_status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {s_depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : s_depth_reg;
assign s_status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {s_depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : s_depth_commit_reg;
assign s_status_overflow = overflow_reg;
assign s_status_bad_frame = bad_frame_reg;
assign s_status_good_frame = good_frame_reg;
assign m_status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {m_depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : m_depth_reg;
assign m_status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {m_depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : m_depth_commit_reg;
assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg;
assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg;
assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg;
// reset synchronization
always @(posedge m_clk or posedge m_rst) begin
if (m_rst) begin
s_rst_sync1_reg <= 1'b1;
end else begin
s_rst_sync1_reg <= 1'b0;
end
end
always @(posedge s_clk) begin
s_rst_sync2_reg <= s_rst_sync1_reg;
s_rst_sync3_reg <= s_rst_sync2_reg;
end
always @(posedge s_clk or posedge s_rst) begin
if (s_rst) begin
m_rst_sync1_reg <= 1'b1;
end else begin
m_rst_sync1_reg <= 1'b0;
end
end
always @(posedge m_clk) begin
m_rst_sync2_reg <= m_rst_sync1_reg;
m_rst_sync3_reg <= m_rst_sync2_reg;
end
// Write logic
always @(posedge s_clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
// have updated pointer to sync
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_commit_reg <= wr_ptr_commit_reg;
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end
end
if (s_axis_tready && s_axis_tvalid && LAST_ENABLE) begin
// track input frame status
s_frame_reg <= !s_axis_tlast;
end
if (s_rst_sync3_reg && LAST_ENABLE) begin
// if sink side is reset during transfer, drop partial frame
if (s_frame_reg && !(s_axis_tready && s_axis_tvalid && s_axis_tlast)) begin
drop_frame_reg <= 1'b1;
end
if (s_axis_tready && s_axis_tvalid && !s_axis_tlast) begin
drop_frame_reg <= 1'b1;
end
end
if (FRAME_FIFO) begin
// frame FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_temp = wr_ptr_commit_reg;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
// end of frame or send frame
send_frame_reg <= !s_axis_tlast;
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer
wr_ptr_temp = wr_ptr_commit_reg;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
bad_frame_reg <= 1'b1;
end else begin
// good packet or packet overflow, update write pointer
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_commit_reg <= wr_ptr_temp;
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end else begin
// sync in progress; flag it for later
wr_ptr_update_valid_reg <= 1'b1;
end
good_frame_reg <= s_axis_tlast;
end
end
end
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_temp = wr_ptr_reg;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_commit_reg <= wr_ptr_temp;
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end else begin
// sync in progress; flag it for later
wr_ptr_update_valid_reg <= 1'b1;
end
end
end else begin
// normal FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
if (drop_frame_reg && LAST_ENABLE) begin
// currently dropping frame
if (s_axis_tlast) begin
// end of frame
if (!full && mark_frame_reg && MARK_WHEN_FULL) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
// end of frame, clear drop flag
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
// full or marking frame
// drop frame; mark if this isn't the first cycle
drop_frame_reg <= 1'b1;
mark_frame_reg <= mark_frame_reg || s_frame_reg;
if (s_axis_tlast) begin
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// transfer in
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
end
if (s_rst_sync3_reg) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_sync_commit_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_update_reg <= 1'b0;
end
if (s_rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_sync_commit_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_update_reg <= 1'b0;
s_frame_reg <= 1'b0;
drop_frame_reg <= 1'b0;
mark_frame_reg <= 1'b0;
send_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// Write-side status
always @(posedge s_clk) begin
rd_ptr_conv_reg <= gray2bin(rd_ptr_gray_sync2_reg);
s_depth_reg <= wr_ptr_reg - rd_ptr_conv_reg;
s_depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_conv_reg;
end
// pointer synchronization
always @(posedge s_clk) begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
if (s_rst) begin
rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_ack_sync1_reg <= 1'b0;
wr_ptr_update_ack_sync2_reg <= 1'b0;
end
end
always @(posedge m_clk) begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
if (FRAME_FIFO && wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
wr_ptr_commit_sync_reg <= wr_ptr_sync_commit_reg;
end
wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
if (FRAME_FIFO && m_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
end
if (m_rst) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_commit_sync_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_sync1_reg <= 1'b0;
wr_ptr_update_sync2_reg <= 1'b0;
wr_ptr_update_sync3_reg <= 1'b0;
end
end
// status synchronization
always @(posedge s_clk) begin
overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
if (s_rst) begin
overflow_sync1_reg <= 1'b0;
bad_frame_sync1_reg <= 1'b0;
good_frame_sync1_reg <= 1'b0;
end
end
always @(posedge m_clk) begin
overflow_sync2_reg <= overflow_sync1_reg;
overflow_sync3_reg <= overflow_sync2_reg;
overflow_sync4_reg <= overflow_sync3_reg;
bad_frame_sync2_reg <= bad_frame_sync1_reg;
bad_frame_sync3_reg <= bad_frame_sync2_reg;
bad_frame_sync4_reg <= bad_frame_sync3_reg;
good_frame_sync2_reg <= good_frame_sync1_reg;
good_frame_sync3_reg <= good_frame_sync2_reg;
good_frame_sync4_reg <= good_frame_sync3_reg;
if (m_rst) begin
overflow_sync2_reg <= 1'b0;
overflow_sync3_reg <= 1'b0;
overflow_sync4_reg <= 1'b0;
bad_frame_sync2_reg <= 1'b0;
bad_frame_sync3_reg <= 1'b0;
bad_frame_sync4_reg <= 1'b0;
good_frame_sync2_reg <= 1'b0;
good_frame_sync3_reg <= 1'b0;
good_frame_sync4_reg <= 1'b0;
end
end
// Read logic
integer j;
always @(posedge m_clk) begin
if (m_axis_tready_pipe) begin
// output ready; invalidate stage
m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
m_terminate_frame_reg <= 1'b0;
end
for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
if (m_axis_tready_pipe || ((~m_axis_tvalid_pipe_reg) >> j)) begin
// output ready or bubble in pipeline; transfer down pipeline
m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
end
end
if (m_axis_tready_pipe || ~m_axis_tvalid_pipe_reg) begin
// output ready or bubble in pipeline; read new data from FIFO
m_axis_tvalid_pipe_reg[0] <= 1'b0;
m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
if (!empty && !m_rst_sync3_reg && !m_drop_frame_reg && pipe_ready) begin
// not empty, increment pointer
m_axis_tvalid_pipe_reg[0] <= 1'b1;
rd_ptr_temp = rd_ptr_reg + 1;
rd_ptr_reg <= rd_ptr_temp;
rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
end
end
if (m_axis_tvalid_pipe && LAST_ENABLE) begin
// track output frame status
if (m_axis_tlast_pipe && m_axis_tready_pipe) begin
m_frame_reg <= 1'b0;
end else begin
m_frame_reg <= 1'b1;
end
end
if (m_drop_frame_reg && (OUTPUT_FIFO_ENABLE ? pipe_ready : m_axis_tready_pipe || !m_axis_tvalid_pipe) && LAST_ENABLE) begin
// terminate frame
// (only for frame transfers interrupted by source reset)
m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b1;
m_terminate_frame_reg <= 1'b1;
m_drop_frame_reg <= 1'b0;
end
if (m_rst_sync3_reg && LAST_ENABLE) begin
// if source side is reset during transfer, drop partial frame
// empty output pipeline, except for last stage
if (RAM_PIPELINE > 0) begin
m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-2:0] <= 0;
end
if (m_frame_reg && (!m_axis_tvalid_pipe || (m_axis_tvalid_pipe && !m_axis_tlast_pipe)) &&
!(m_drop_frame_reg || m_terminate_frame_reg)) begin
// terminate frame
m_drop_frame_reg <= 1'b1;
end
end
if (m_rst_sync3_reg) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
end
if (m_rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
m_axis_tvalid_pipe_reg <= 0;
m_frame_reg <= 1'b0;
m_drop_frame_reg <= 1'b0;
m_terminate_frame_reg <= 1'b0;
end
end
// Read-side status
always @(posedge m_clk) begin
wr_ptr_conv_reg <= gray2bin(wr_ptr_gray_sync2_reg);
m_depth_reg <= wr_ptr_conv_reg - rd_ptr_reg;
m_depth_commit_reg <= FRAME_FIFO ? wr_ptr_commit_sync_reg - rd_ptr_reg : wr_ptr_conv_reg - rd_ptr_reg;
end
generate
if (!OUTPUT_FIFO_ENABLE) begin
assign pipe_ready = 1'b1;
assign m_axis_tready_pipe = m_axis_tready_out;
assign m_axis_tvalid_out = m_axis_tvalid_pipe;
assign m_axis_tdata_out = m_axis_tdata_pipe;
assign m_axis_tkeep_out = m_axis_tkeep_pipe;
assign m_axis_tlast_out = m_axis_tlast_pipe;
assign m_axis_tid_out = m_axis_tid_pipe;
assign m_axis_tdest_out = m_axis_tdest_pipe;
assign m_axis_tuser_out = m_axis_tuser_pipe;
end else begin : output_fifo
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign pipe_ready = !out_fifo_half_full_reg;
assign m_axis_tready_pipe = 1'b1;
assign m_axis_tdata_out = m_axis_tdata_reg;
assign m_axis_tkeep_out = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid_out = m_axis_tvalid_reg;
assign m_axis_tlast_out = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid_out = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest_out = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser_out = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
always @(posedge m_clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
if (!out_fifo_full && m_axis_tvalid_pipe) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe;
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe;
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tvalid_reg <= 1'b1;
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (m_rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
if (PAUSE_ENABLE) begin : pause
// Pause logic
reg pause_reg = 1'b0;
reg pause_frame_reg = 1'b0;
reg s_pause_req_sync1_reg;
reg s_pause_req_sync2_reg;
reg s_pause_req_sync3_reg;
reg s_pause_ack_sync1_reg;
reg s_pause_ack_sync2_reg;
reg s_pause_ack_sync3_reg;
always @(posedge s_clk) begin
s_pause_req_sync1_reg <= s_pause_req;
s_pause_ack_sync2_reg <= s_pause_ack_sync1_reg;
s_pause_ack_sync3_reg <= s_pause_ack_sync2_reg;
end
always @(posedge m_clk) begin
s_pause_req_sync2_reg <= s_pause_req_sync1_reg;
s_pause_req_sync3_reg <= s_pause_req_sync2_reg;
s_pause_ack_sync1_reg <= pause_reg;
end
assign m_axis_tready_out = m_axis_tready && !pause_reg;
assign m_axis_tvalid = m_axis_tvalid_out && !pause_reg;
assign m_axis_tdata = m_axis_tdata_out;
assign m_axis_tkeep = m_axis_tkeep_out;
assign m_axis_tlast = m_axis_tlast_out;
assign m_axis_tid = m_axis_tid_out;
assign m_axis_tdest = m_axis_tdest_out;
assign m_axis_tuser = m_axis_tuser_out;
assign s_pause_ack = s_pause_ack_sync3_reg;
assign m_pause_ack = pause_reg;
always @(posedge m_clk) begin
if (FRAME_PAUSE) begin
if (pause_reg) begin
// paused; update pause status
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end else if (m_axis_tvalid_out) begin
// frame transfer; set frame bit
pause_frame_reg <= 1'b1;
if (m_axis_tready && m_axis_tlast) begin
// end of frame; clear frame bit and update pause status
pause_frame_reg <= 1'b0;
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end
end else if (!pause_frame_reg) begin
// idle; update pause status
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end
end else begin
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
end
if (m_rst) begin
pause_frame_reg <= 1'b0;
pause_reg <= 1'b0;
end
end
end else begin
assign m_axis_tready_out = m_axis_tready;
assign m_axis_tvalid = m_axis_tvalid_out;
assign m_axis_tdata = m_axis_tdata_out;
assign m_axis_tkeep = m_axis_tkeep_out;
assign m_axis_tlast = m_axis_tlast_out;
assign m_axis_tid = m_axis_tid_out;
assign m_axis_tdest = m_axis_tdest_out;
assign m_axis_tuser = m_axis_tuser_out;
assign s_pause_ack = 1'b0;
assign m_pause_ack = 1'b0;
end
endgenerate
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/axis_async_fifo_adapter.v Executable file
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/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO with width converter
*/
module axis_async_fifo_adapter #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of input AXI stream interface in bits
parameter S_DATA_WIDTH = 8,
// Propagate tkeep signal on input interface
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of RAM pipeline registers in FIFO
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter OUTPUT_FIFO_ENABLE = 0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_WHEN_FULL = 0,
// Mark incoming frames as bad frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO to be clear
parameter MARK_WHEN_FULL = 0,
// Enable pause request input
parameter PAUSE_ENABLE = 0,
// Pause between frames
parameter FRAME_PAUSE = FRAME_FIFO
)
(
/*
* AXI input
*/
input wire s_clk,
input wire s_rst,
input wire [S_DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
input wire m_clk,
input wire m_rst,
output wire [M_DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Pause
*/
input wire s_pause_req,
output wire s_pause_ack,
input wire m_pause_req,
output wire m_pause_ack,
/*
* Status
*/
output wire [$clog2(DEPTH):0] s_status_depth,
output wire [$clog2(DEPTH):0] s_status_depth_commit,
output wire s_status_overflow,
output wire s_status_bad_frame,
output wire s_status_good_frame,
output wire [$clog2(DEPTH):0] m_status_depth,
output wire [$clog2(DEPTH):0] m_status_depth_commit,
output wire m_status_overflow,
output wire m_status_bad_frame,
output wire m_status_good_frame
);
// force keep width to 1 when disabled
localparam S_BYTE_LANES = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
localparam M_BYTE_LANES = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
// bus byte sizes (must be identical)
localparam S_BYTE_SIZE = S_DATA_WIDTH / S_BYTE_LANES;
localparam M_BYTE_SIZE = M_DATA_WIDTH / M_BYTE_LANES;
// output bus is wider
localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES;
// total data and keep widths
localparam DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH;
localparam KEEP_WIDTH = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES;
// bus width assertions
initial begin
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_WIDTH) begin
$error("Error: input data width not evenly divisible (instance %m)");
$finish;
end
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_WIDTH) begin
$error("Error: output data width not evenly divisible (instance %m)");
$finish;
end
if (S_BYTE_SIZE != M_BYTE_SIZE) begin
$error("Error: byte size mismatch (instance %m)");
$finish;
end
end
wire [DATA_WIDTH-1:0] pre_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] pre_fifo_axis_tkeep;
wire pre_fifo_axis_tvalid;
wire pre_fifo_axis_tready;
wire pre_fifo_axis_tlast;
wire [ID_WIDTH-1:0] pre_fifo_axis_tid;
wire [DEST_WIDTH-1:0] pre_fifo_axis_tdest;
wire [USER_WIDTH-1:0] pre_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] post_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] post_fifo_axis_tkeep;
wire post_fifo_axis_tvalid;
wire post_fifo_axis_tready;
wire post_fifo_axis_tlast;
wire [ID_WIDTH-1:0] post_fifo_axis_tid;
wire [DEST_WIDTH-1:0] post_fifo_axis_tdest;
wire [USER_WIDTH-1:0] post_fifo_axis_tuser;
generate
if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize_pre
// output wider, adapt width before FIFO
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(s_clk),
.rst(s_rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(pre_fifo_axis_tdata),
.m_axis_tkeep(pre_fifo_axis_tkeep),
.m_axis_tvalid(pre_fifo_axis_tvalid),
.m_axis_tready(pre_fifo_axis_tready),
.m_axis_tlast(pre_fifo_axis_tlast),
.m_axis_tid(pre_fifo_axis_tid),
.m_axis_tdest(pre_fifo_axis_tdest),
.m_axis_tuser(pre_fifo_axis_tuser)
);
end else begin : bypass_pre
assign pre_fifo_axis_tdata = s_axis_tdata;
assign pre_fifo_axis_tkeep = s_axis_tkeep;
assign pre_fifo_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = pre_fifo_axis_tready;
assign pre_fifo_axis_tlast = s_axis_tlast;
assign pre_fifo_axis_tid = s_axis_tid;
assign pre_fifo_axis_tdest = s_axis_tdest;
assign pre_fifo_axis_tuser = s_axis_tuser;
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_ENABLE(OUTPUT_FIFO_ENABLE),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_ENABLE(PAUSE_ENABLE),
.FRAME_PAUSE(FRAME_PAUSE)
)
fifo_inst (
// AXI input
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis_tdata(pre_fifo_axis_tdata),
.s_axis_tkeep(pre_fifo_axis_tkeep),
.s_axis_tvalid(pre_fifo_axis_tvalid),
.s_axis_tready(pre_fifo_axis_tready),
.s_axis_tlast(pre_fifo_axis_tlast),
.s_axis_tid(pre_fifo_axis_tid),
.s_axis_tdest(pre_fifo_axis_tdest),
.s_axis_tuser(pre_fifo_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis_tdata(post_fifo_axis_tdata),
.m_axis_tkeep(post_fifo_axis_tkeep),
.m_axis_tvalid(post_fifo_axis_tvalid),
.m_axis_tready(post_fifo_axis_tready),
.m_axis_tlast(post_fifo_axis_tlast),
.m_axis_tid(post_fifo_axis_tid),
.m_axis_tdest(post_fifo_axis_tdest),
.m_axis_tuser(post_fifo_axis_tuser),
// Pause
.s_pause_req(s_pause_req),
.s_pause_ack(s_pause_ack),
.m_pause_req(m_pause_req),
.m_pause_ack(m_pause_ack),
// Status
.s_status_depth(s_status_depth),
.s_status_depth_commit(s_status_depth_commit),
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_depth(m_status_depth),
.m_status_depth_commit(m_status_depth_commit),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
if (M_BYTE_LANES < S_BYTE_LANES) begin : downsize_post
// input wider, adapt width after FIFO
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(m_clk),
.rst(m_rst),
// AXI input
.s_axis_tdata(post_fifo_axis_tdata),
.s_axis_tkeep(post_fifo_axis_tkeep),
.s_axis_tvalid(post_fifo_axis_tvalid),
.s_axis_tready(post_fifo_axis_tready),
.s_axis_tlast(post_fifo_axis_tlast),
.s_axis_tid(post_fifo_axis_tid),
.s_axis_tdest(post_fifo_axis_tdest),
.s_axis_tuser(post_fifo_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
end else begin : bypass_post
assign m_axis_tdata = post_fifo_axis_tdata;
assign m_axis_tkeep = post_fifo_axis_tkeep;
assign m_axis_tvalid = post_fifo_axis_tvalid;
assign post_fifo_axis_tready = m_axis_tready;
assign m_axis_tlast = post_fifo_axis_tlast;
assign m_axis_tid = post_fifo_axis_tid;
assign m_axis_tdest = post_fifo_axis_tdest;
assign m_axis_tuser = post_fifo_axis_tuser;
end
endgenerate
endmodule
`resetall

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/*
Copyright (c) 2013-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO
*/
module axis_fifo #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter OUTPUT_FIFO_ENABLE = 0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_WHEN_FULL = 0,
// Mark incoming frames as bad frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO to be clear
parameter MARK_WHEN_FULL = 0,
// Enable pause request input
parameter PAUSE_ENABLE = 0,
// Pause between frames
parameter FRAME_PAUSE = FRAME_FIFO
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Pause
*/
input wire pause_req,
output wire pause_ack,
/*
* Status
*/
output wire [$clog2(DEPTH):0] status_depth,
output wire [$clog2(DEPTH):0] status_depth_commit,
output wire status_overflow,
output wire status_bad_frame,
output wire status_good_frame
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
// check configuration
initial begin
if (FRAME_FIFO && !LAST_ENABLE) begin
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
$finish;
end
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin
$error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
$finish;
end
if (MARK_WHEN_FULL && FRAME_FIFO) begin
$error("Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
$finish;
end
if (MARK_WHEN_FULL && !LAST_ENABLE) begin
$error("Error: MARK_WHEN_FULL set requires LAST_ENABLE set (instance %m)");
$finish;
end
end
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_commit_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
(* ramstyle = "no_rw_check" *)
reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg mem_read_data_valid_reg = 1'b0;
(* shreg_extract = "no" *)
reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0];
reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0;
// full when first MSB different but rest same
wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
// empty when pointers match exactly
wire empty = wr_ptr_commit_reg == rd_ptr_reg;
// overflow within packet
wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
reg s_frame_reg = 1'b0;
reg drop_frame_reg = 1'b0;
reg mark_frame_reg = 1'b0;
reg send_frame_reg = 1'b0;
reg [ADDR_WIDTH:0] depth_reg = 0;
reg [ADDR_WIDTH:0] depth_commit_reg = 0;
reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
assign s_axis_tready = FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL);
wire [WIDTH-1:0] s_axis;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast | mark_frame_reg;
if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis_tuser;
endgenerate
wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1];
wire m_axis_tready_pipe;
wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1];
wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0];
wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
wire m_axis_tready_out;
wire m_axis_tvalid_out;
wire [DATA_WIDTH-1:0] m_axis_tdata_out;
wire [KEEP_WIDTH-1:0] m_axis_tkeep_out;
wire m_axis_tlast_out;
wire [ID_WIDTH-1:0] m_axis_tid_out;
wire [DEST_WIDTH-1:0] m_axis_tdest_out;
wire [USER_WIDTH-1:0] m_axis_tuser_out;
wire pipe_ready;
assign status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_reg;
assign status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_commit_reg;
assign status_overflow = overflow_reg;
assign status_bad_frame = bad_frame_reg;
assign status_good_frame = good_frame_reg;
// Write logic
always @(posedge clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (s_axis_tready && s_axis_tvalid && LAST_ENABLE) begin
// track input frame status
s_frame_reg <= !s_axis_tlast;
end
if (FRAME_FIFO) begin
// frame FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_reg <= wr_ptr_commit_reg;
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// store it
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
// end of frame or send frame
send_frame_reg <= !s_axis_tlast;
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer
wr_ptr_reg <= wr_ptr_commit_reg;
bad_frame_reg <= 1'b1;
end else begin
// good packet or packet overflow, update write pointer
wr_ptr_commit_reg <= wr_ptr_reg + 1;
good_frame_reg <= s_axis_tlast;
end
end
end
end else if (s_axis_tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_commit_reg <= wr_ptr_reg;
end
end else begin
// normal FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
if (drop_frame_reg && MARK_WHEN_FULL) begin
// currently dropping frame
if (s_axis_tlast) begin
// end of frame
if (!full && mark_frame_reg) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end
// end of frame, clear drop flag
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
// full or marking frame
// drop frame; mark if this isn't the first cycle
drop_frame_reg <= 1'b1;
mark_frame_reg <= mark_frame_reg || s_frame_reg;
if (s_axis_tlast) begin
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// transfer in
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end
end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end
end
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}};
s_frame_reg <= 1'b0;
drop_frame_reg <= 1'b0;
mark_frame_reg <= 1'b0;
send_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// Status
always @(posedge clk) begin
depth_reg <= wr_ptr_reg - rd_ptr_reg;
depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_reg;
end
// Read logic
integer j;
always @(posedge clk) begin
if (m_axis_tready_pipe) begin
// output ready; invalidate stage
m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
end
for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
if (m_axis_tready_pipe || ((~m_axis_tvalid_pipe_reg) >> j)) begin
// output ready or bubble in pipeline; transfer down pipeline
m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
end
end
if (m_axis_tready_pipe || ~m_axis_tvalid_pipe_reg) begin
// output ready or bubble in pipeline; read new data from FIFO
m_axis_tvalid_pipe_reg[0] <= 1'b0;
m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
if (!empty && pipe_ready) begin
// not empty, increment pointer
m_axis_tvalid_pipe_reg[0] <= 1'b1;
rd_ptr_reg <= rd_ptr_reg + 1;
end
end
if (rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
m_axis_tvalid_pipe_reg <= 0;
end
end
generate
if (!OUTPUT_FIFO_ENABLE) begin
assign pipe_ready = 1'b1;
assign m_axis_tready_pipe = m_axis_tready_out;
assign m_axis_tvalid_out = m_axis_tvalid_pipe;
assign m_axis_tdata_out = m_axis_tdata_pipe;
assign m_axis_tkeep_out = m_axis_tkeep_pipe;
assign m_axis_tlast_out = m_axis_tlast_pipe;
assign m_axis_tid_out = m_axis_tid_pipe;
assign m_axis_tdest_out = m_axis_tdest_pipe;
assign m_axis_tuser_out = m_axis_tuser_pipe;
end else begin : output_fifo
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign pipe_ready = !out_fifo_half_full_reg;
assign m_axis_tready_pipe = 1'b1;
assign m_axis_tdata_out = m_axis_tdata_reg;
assign m_axis_tkeep_out = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid_out = m_axis_tvalid_reg;
assign m_axis_tlast_out = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid_out = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest_out = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser_out = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
if (!out_fifo_full && m_axis_tvalid_pipe) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe;
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe;
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tvalid_reg <= 1'b1;
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
if (PAUSE_ENABLE) begin : pause
// Pause logic
reg pause_reg = 1'b0;
reg pause_frame_reg = 1'b0;
assign m_axis_tready_out = m_axis_tready && !pause_reg;
assign m_axis_tvalid = m_axis_tvalid_out && !pause_reg;
assign m_axis_tdata = m_axis_tdata_out;
assign m_axis_tkeep = m_axis_tkeep_out;
assign m_axis_tlast = m_axis_tlast_out;
assign m_axis_tid = m_axis_tid_out;
assign m_axis_tdest = m_axis_tdest_out;
assign m_axis_tuser = m_axis_tuser_out;
assign pause_ack = pause_reg;
always @(posedge clk) begin
if (FRAME_PAUSE) begin
if (pause_reg) begin
// paused; update pause status
pause_reg <= pause_req;
end else if (m_axis_tvalid_out) begin
// frame transfer; set frame bit
pause_frame_reg <= 1'b1;
if (m_axis_tready && m_axis_tlast) begin
// end of frame; clear frame bit and update pause status
pause_frame_reg <= 1'b0;
pause_reg <= pause_req;
end
end else if (!pause_frame_reg) begin
// idle; update pause status
pause_reg <= pause_req;
end
end else begin
pause_reg <= pause_req;
end
if (rst) begin
pause_frame_reg <= 1'b0;
pause_reg <= 1'b0;
end
end
end else begin
assign m_axis_tready_out = m_axis_tready;
assign m_axis_tvalid = m_axis_tvalid_out;
assign m_axis_tdata = m_axis_tdata_out;
assign m_axis_tkeep = m_axis_tkeep_out;
assign m_axis_tlast = m_axis_tlast_out;
assign m_axis_tid = m_axis_tid_out;
assign m_axis_tdest = m_axis_tdest_out;
assign m_axis_tuser = m_axis_tuser_out;
assign pause_ack = 1'b0;
end
endgenerate
endmodule
`resetall

355
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/axis_xgmii_rx_32.v Executable file
View File

@@ -0,0 +1,355 @@
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream XGMII frame receiver (XGMII in, AXI out)
*/
module axis_xgmii_rx_32 #
(
parameter DATA_WIDTH = 32,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* XGMII input
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Configuration
*/
input wire cfg_rx_enable,
/*
* Status
*/
output wire start_packet,
output wire error_bad_frame,
output wire error_bad_fcs
);
// bus width assertions
initial begin
if (DATA_WIDTH != 32) begin
$error("Error: Interface width must be 32");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PREAMBLE = 2'd1,
STATE_PAYLOAD = 2'd2,
STATE_LAST = 2'd3;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg [1:0] term_lane_reg = 0, term_lane_d0_reg = 0;
reg term_present_reg = 1'b0;
reg framing_error_reg = 1'b0;
reg [DATA_WIDTH-1:0] xgmii_rxd_d0 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] xgmii_rxd_d1 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] xgmii_rxd_d2 = {DATA_WIDTH{1'b0}};
reg [CTRL_WIDTH-1:0] xgmii_rxc_d0 = {CTRL_WIDTH{1'b0}};
reg xgmii_start_d0 = 1'b0;
reg xgmii_start_d1 = 1'b0;
reg xgmii_start_d2 = 1'b0;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, m_axis_tkeep_next;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}, m_axis_tuser_next;
reg start_packet_reg = 1'b0, start_packet_next;
reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
wire [3:0] crc_valid;
reg [3:0] crc_valid_save;
assign crc_valid[3] = crc_next == ~32'h2144df1c;
assign crc_valid[2] = crc_next == ~32'hc622f71d;
assign crc_valid[1] = crc_next == ~32'hb1c2a1a3;
assign crc_valid[0] = crc_next == ~32'h9d6cdf7e;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
assign start_packet = start_packet_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
wire last_cycle = state_reg == STATE_LAST;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc (
.data_in(xgmii_rxd_d0),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
m_axis_tdata_next = xgmii_rxd_d2;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b0;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = m_axis_tuser_reg;
m_axis_tuser_next[0] = 1'b0;
start_packet_next = 1'b0;
error_bad_frame_next = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
if (xgmii_start_d2 && cfg_rx_enable) begin
// start condition
if (framing_error_reg) begin
// control or error characters in first data word
m_axis_tdata_next = xgmii_rxd_d2;
m_axis_tkeep_next = 4'h1;
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b1;
m_axis_tuser_next[0] = 1'b1;
error_bad_frame_next = 1'b1;
state_next = STATE_IDLE;
end else begin
reset_crc = 1'b0;
state_next = STATE_PREAMBLE;
end
end else begin
if (PTP_TS_ENABLE) begin
m_axis_tuser_next[1 +: PTP_TS_WIDTH] = ptp_ts;
end
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
// drop preamble
start_packet_next = 1'b1;
state_next = STATE_PAYLOAD;
end
STATE_PAYLOAD: begin
// read payload
m_axis_tdata_next = xgmii_rxd_d2;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next[0] = 1'b0;
if (framing_error_reg) begin
// control or error characters in packet
m_axis_tlast_next = 1'b1;
m_axis_tuser_next[0] = 1'b1;
error_bad_frame_next = 1'b1;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else if (term_present_reg) begin
reset_crc = 1'b1;
if (term_lane_reg == 0) begin
// end this cycle
m_axis_tkeep_next = 4'b1111;
m_axis_tlast_next = 1'b1;
if (term_lane_reg == 0 && crc_valid_save[3]) begin
// CRC valid
end else begin
m_axis_tuser_next[0] = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
state_next = STATE_IDLE;
end else begin
// need extra cycle
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_LAST: begin
// last cycle of packet
m_axis_tdata_next = xgmii_rxd_d2;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}} >> (CTRL_WIDTH-term_lane_d0_reg);
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b1;
m_axis_tuser_next[0] = 1'b0;
reset_crc = 1'b1;
if ((term_lane_d0_reg == 1 && crc_valid_save[0]) ||
(term_lane_d0_reg == 2 && crc_valid_save[1]) ||
(term_lane_d0_reg == 3 && crc_valid_save[2])) begin
// CRC valid
end else begin
m_axis_tuser_next[0] = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
state_next = STATE_IDLE;
end
endcase
end
integer i;
always @(posedge clk) begin
state_reg <= state_next;
m_axis_tdata_reg <= m_axis_tdata_next;
m_axis_tkeep_reg <= m_axis_tkeep_next;
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tlast_reg <= m_axis_tlast_next;
m_axis_tuser_reg <= m_axis_tuser_next;
start_packet_reg <= start_packet_next;
error_bad_frame_reg <= error_bad_frame_next;
error_bad_fcs_reg <= error_bad_fcs_next;
term_lane_reg <= 0;
term_present_reg <= 1'b0;
framing_error_reg <= xgmii_rxc != 0;
for (i = CTRL_WIDTH-1; i >= 0; i = i - 1) begin
if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin
term_lane_reg <= i;
term_present_reg <= 1'b1;
framing_error_reg <= (xgmii_rxc & ({CTRL_WIDTH{1'b1}} >> (CTRL_WIDTH-i))) != 0;
end
end
term_lane_d0_reg <= term_lane_reg;
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else begin
crc_state <= crc_next;
end
crc_valid_save <= crc_valid;
for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
xgmii_rxd_d0[i*8 +: 8] <= xgmii_rxc[i] ? 8'd0 : xgmii_rxd[i*8 +: 8];
end
xgmii_rxc_d0 <= xgmii_rxc;
xgmii_rxd_d1 <= xgmii_rxd_d0;
xgmii_rxd_d2 <= xgmii_rxd_d1;
xgmii_start_d0 <= xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START;
xgmii_start_d1 <= xgmii_start_d0;
xgmii_start_d2 <= xgmii_start_d1;
if (rst) begin
state_reg <= STATE_IDLE;
m_axis_tvalid_reg <= 1'b0;
start_packet_reg <= 1'b0;
error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}};
xgmii_start_d0 <= 1'b0;
xgmii_start_d1 <= 1'b0;
xgmii_start_d2 <= 1'b0;
end
end
endmodule
`resetall

449
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/axis_xgmii_rx_64.v Executable file
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@@ -0,0 +1,449 @@
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream XGMII frame receiver (XGMII in, AXI out)
*/
module axis_xgmii_rx_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* XGMII input
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Configuration
*/
input wire cfg_rx_enable,
/*
* Status
*/
output wire [1:0] start_packet,
output wire error_bad_frame,
output wire error_bad_fcs
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg lanes_swapped = 1'b0;
reg [31:0] swap_rxd = 32'd0;
reg [3:0] swap_rxc = 4'd0;
reg [3:0] swap_rxc_term = 4'd0;
reg [DATA_WIDTH-1:0] xgmii_rxd_masked = {DATA_WIDTH{1'b0}};
reg [CTRL_WIDTH-1:0] xgmii_term = {CTRL_WIDTH{1'b0}};
reg [2:0] term_lane_reg = 0, term_lane_d0_reg = 0;
reg term_present_reg = 1'b0;
reg framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0;
reg [DATA_WIDTH-1:0] xgmii_rxd_d0 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] xgmii_rxd_d1 = {DATA_WIDTH{1'b0}};
reg [CTRL_WIDTH-1:0] xgmii_rxc_d0 = {CTRL_WIDTH{1'b0}};
reg xgmii_start_swap = 1'b0;
reg xgmii_start_d0 = 1'b0;
reg xgmii_start_d1 = 1'b0;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, m_axis_tkeep_next;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}, m_axis_tuser_next;
reg [1:0] start_packet_reg = 2'b00;
reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts_adj_reg = 0;
reg ptp_ts_borrow_reg = 0;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
wire [7:0] crc_valid;
reg [7:0] crc_valid_save;
assign crc_valid[7] = crc_next == ~32'h2144df1c;
assign crc_valid[6] = crc_next == ~32'hc622f71d;
assign crc_valid[5] = crc_next == ~32'hb1c2a1a3;
assign crc_valid[4] = crc_next == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_next == ~32'h6522df69;
assign crc_valid[2] = crc_next == ~32'he60914ae;
assign crc_valid[1] = crc_next == ~32'he38a6876;
assign crc_valid[0] = crc_next == ~32'h6b87b1ec;
reg [4+16-1:0] last_ts_reg = 0;
reg [4+16-1:0] ts_inc_reg = 0;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
assign start_packet = start_packet_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc (
.data_in(xgmii_rxd_d0),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
// Mask input data
integer j;
always @* begin
for (j = 0; j < 8; j = j + 1) begin
xgmii_rxd_masked[j*8 +: 8] = xgmii_rxc[j] ? 8'd0 : xgmii_rxd[j*8 +: 8];
xgmii_term[j] = xgmii_rxc[j] && (xgmii_rxd[j*8 +: 8] == XGMII_TERM);
end
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
m_axis_tdata_next = xgmii_rxd_d1;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b0;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = m_axis_tuser_reg;
m_axis_tuser_next[0] = 1'b0;
error_bad_frame_next = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
if (xgmii_start_d1 && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// read payload
m_axis_tdata_next = xgmii_rxd_d1;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next[0] = 1'b0;
if (PTP_TS_ENABLE) begin
m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
end
if (framing_error_reg || framing_error_d0_reg) begin
// control or error characters in packet
m_axis_tlast_next = 1'b1;
m_axis_tuser_next[0] = 1'b1;
error_bad_frame_next = 1'b1;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else if (term_present_reg) begin
reset_crc = 1'b1;
if (term_lane_reg <= 4) begin
// end this cycle
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}} >> (CTRL_WIDTH-4-term_lane_reg);
m_axis_tlast_next = 1'b1;
if ((term_lane_reg == 0 && crc_valid_save[7]) ||
(term_lane_reg == 1 && crc_valid[0]) ||
(term_lane_reg == 2 && crc_valid[1]) ||
(term_lane_reg == 3 && crc_valid[2]) ||
(term_lane_reg == 4 && crc_valid[3])) begin
// CRC valid
end else begin
m_axis_tuser_next[0] = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
state_next = STATE_IDLE;
end else begin
// need extra cycle
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_LAST: begin
// last cycle of packet
m_axis_tdata_next = xgmii_rxd_d1;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}} >> (CTRL_WIDTH+4-term_lane_d0_reg);
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b1;
m_axis_tuser_next[0] = 1'b0;
reset_crc = 1'b1;
if ((term_lane_d0_reg == 5 && crc_valid_save[4]) ||
(term_lane_d0_reg == 6 && crc_valid_save[5]) ||
(term_lane_d0_reg == 7 && crc_valid_save[6])) begin
// CRC valid
end else begin
m_axis_tuser_next[0] = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
if (xgmii_start_d1 && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
end
end
endcase
end
integer i;
always @(posedge clk) begin
state_reg <= state_next;
m_axis_tdata_reg <= m_axis_tdata_next;
m_axis_tkeep_reg <= m_axis_tkeep_next;
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tlast_reg <= m_axis_tlast_next;
m_axis_tuser_reg <= m_axis_tuser_next;
start_packet_reg <= 2'b00;
error_bad_frame_reg <= error_bad_frame_next;
error_bad_fcs_reg <= error_bad_fcs_next;
swap_rxd <= xgmii_rxd_masked[63:32];
swap_rxc <= xgmii_rxc[7:4];
swap_rxc_term <= xgmii_term[7:4];
xgmii_start_swap <= 1'b0;
xgmii_start_d0 <= xgmii_start_swap;
if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin
// ns field rollover
ptp_ts_adj_reg[15:0] <= ptp_ts_reg[15:0];
{ptp_ts_borrow_reg, ptp_ts_adj_reg[45:16]} <= $signed({1'b0, ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
ptp_ts_adj_reg[47:46] <= 0;
ptp_ts_adj_reg[95:48] <= ptp_ts_reg[95:48] + 1;
end
// lane swapping and termination character detection
if (lanes_swapped) begin
xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd};
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
term_lane_reg <= 0;
term_present_reg <= 1'b0;
framing_error_reg <= {xgmii_rxc[3:0], swap_rxc} != 0;
for (i = CTRL_WIDTH-1; i >= 0; i = i - 1) begin
if ({xgmii_term[3:0], swap_rxc_term} & (1 << i)) begin
term_lane_reg <= i;
term_present_reg <= 1'b1;
framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc} & ({CTRL_WIDTH{1'b1}} >> (CTRL_WIDTH-i))) != 0;
lanes_swapped <= 1'b0;
end
end
end else begin
xgmii_rxd_d0 <= xgmii_rxd_masked;
xgmii_rxc_d0 <= xgmii_rxc;
term_lane_reg <= 0;
term_present_reg <= 1'b0;
framing_error_reg <= xgmii_rxc != 0;
for (i = CTRL_WIDTH-1; i >= 0; i = i - 1) begin
if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin
term_lane_reg <= i;
term_present_reg <= 1'b1;
framing_error_reg <= (xgmii_rxc & ({CTRL_WIDTH{1'b1}} >> (CTRL_WIDTH-i))) != 0;
lanes_swapped <= 1'b0;
end
end
end
// start control character detection
if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin
lanes_swapped <= 1'b0;
xgmii_start_d0 <= 1'b1;
term_lane_reg <= 0;
term_present_reg <= 1'b0;
framing_error_reg <= xgmii_rxc[7:1] != 0;
end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin
lanes_swapped <= 1'b1;
xgmii_start_swap <= 1'b1;
term_lane_reg <= 0;
term_present_reg <= 1'b0;
framing_error_reg <= xgmii_rxc[7:5] != 0;
end
// capture timestamps
if (xgmii_start_swap) begin
start_packet_reg <= 2'b10;
if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1);
end
end
if (xgmii_start_d0) begin
if (!lanes_swapped) begin
start_packet_reg <= 2'b01;
ptp_ts_reg <= ptp_ts;
end
end
term_lane_d0_reg <= term_lane_reg;
framing_error_d0_reg <= framing_error_reg;
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else begin
crc_state <= crc_next;
end
crc_valid_save <= crc_valid;
xgmii_rxd_d1 <= xgmii_rxd_d0;
xgmii_start_d1 <= xgmii_start_d0;
last_ts_reg <= ptp_ts;
ts_inc_reg <= ptp_ts - last_ts_reg;
if (rst) begin
state_reg <= STATE_IDLE;
m_axis_tvalid_reg <= 1'b0;
start_packet_reg <= 2'b00;
error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}};
xgmii_start_swap <= 1'b0;
xgmii_start_d0 <= 1'b0;
xgmii_start_d1 <= 1'b0;
lanes_swapped <= 1'b0;
end
end
endmodule
`resetall

563
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/axis_xgmii_tx_32.v Executable file
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/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream XGMII frame transmitter (AXI in, XGMII out)
*/
module axis_xgmii_tx_32 #
(
parameter DATA_WIDTH = 32,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TS_CTRL_IN_TUSER = 0,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TS_ENABLE ? (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* XGMII output
*/
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
/*
* Status
*/
output wire start_packet,
output wire error_underflow
);
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
// bus width assertions
initial begin
if (DATA_WIDTH != 32) begin
$error("Error: Interface width must be 32");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_PREAMBLE = 4'd1,
STATE_PAYLOAD = 4'd2,
STATE_PAD = 4'd3,
STATE_FCS_1 = 4'd4,
STATE_FCS_2 = 4'd5,
STATE_FCS_3 = 4'd6,
STATE_ERR = 4'd7,
STATE_IFG = 4'd8;
reg [3:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
reg [DATA_WIDTH-1:0] s_tdata_reg = 0, s_tdata_next;
reg [EMPTY_WIDTH-1:0] s_empty_reg = 0, s_empty_next;
reg [DATA_WIDTH-1:0] fcs_output_txd_0;
reg [DATA_WIDTH-1:0] fcs_output_txd_1;
reg [CTRL_WIDTH-1:0] fcs_output_txc_0;
reg [CTRL_WIDTH-1:0] fcs_output_txc_1;
reg [7:0] ifg_offset;
reg extra_cycle;
reg frame_reg = 1'b0, frame_next;
reg frame_error_reg = 1'b0, frame_error_next;
reg [MIN_LEN_WIDTH-1:0] frame_min_count_reg = 0, frame_min_count_next;
reg [7:0] ifg_count_reg = 8'd0, ifg_count_next;
reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
reg [31:0] crc_state_reg[3:0];
wire [31:0] crc_state_next[3:0];
reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next;
reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next;
reg start_packet_reg = 1'b0, start_packet_next;
reg error_underflow_reg = 1'b0, error_underflow_next;
assign s_axis_tready = s_axis_tready_reg;
assign xgmii_txd = xgmii_txd_reg;
assign xgmii_txc = xgmii_txc_reg;
assign m_axis_ptp_ts = PTP_TS_ENABLE ? m_axis_ptp_ts_reg : 0;
assign m_axis_ptp_ts_tag = PTP_TAG_ENABLE ? m_axis_ptp_ts_tag_reg : 0;
assign m_axis_ptp_ts_valid = PTP_TS_ENABLE || PTP_TAG_ENABLE ? m_axis_ptp_ts_valid_reg : 1'b0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
generate
genvar n;
for (n = 0; n < 4; n = n + 1) begin : crc
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8*(n+1)),
.STYLE("AUTO")
)
eth_crc (
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[3]),
.data_out(),
.state_out(crc_state_next[n])
);
end
endgenerate
function [1:0] keep2empty;
input [3:0] k;
casez (k)
4'bzzz0: keep2empty = 2'd3;
4'bzz01: keep2empty = 2'd3;
4'bz011: keep2empty = 2'd2;
4'b0111: keep2empty = 2'd1;
4'b1111: keep2empty = 2'd0;
endcase
endfunction
// Mask input data
integer j;
always @* begin
for (j = 0; j < 4; j = j + 1) begin
s_axis_tdata_masked[j*8 +: 8] = s_axis_tkeep[j] ? s_axis_tdata[j*8 +: 8] : 8'd0;
end
end
// FCS cycle calculation
always @* begin
casez (s_empty_reg)
2'd3: begin
fcs_output_txd_0 = {~crc_state_next[0][23:0], s_tdata_reg[7:0]};
fcs_output_txd_1 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[0][31:24]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1110;
ifg_offset = 8'd3;
extra_cycle = 1'b0;
end
2'd2: begin
fcs_output_txd_0 = {~crc_state_next[1][15:0], s_tdata_reg[15:0]};
fcs_output_txd_1 = {XGMII_IDLE, XGMII_TERM, ~crc_state_reg[1][31:16]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1100;
ifg_offset = 8'd2;
extra_cycle = 1'b0;
end
2'd1: begin
fcs_output_txd_0 = {~crc_state_next[2][7:0], s_tdata_reg[23:0]};
fcs_output_txd_1 = {XGMII_TERM, ~crc_state_reg[2][31:8]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1000;
ifg_offset = 8'd1;
extra_cycle = 1'b0;
end
2'd0: begin
fcs_output_txd_0 = s_tdata_reg;
fcs_output_txd_1 = ~crc_state_reg[3];
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b0000;
ifg_offset = 8'd4;
extra_cycle = 1'b1;
end
endcase
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
frame_next = frame_reg;
frame_error_next = frame_error_reg;
frame_min_count_next = frame_min_count_reg;
ifg_count_next = ifg_count_reg;
deficit_idle_count_next = deficit_idle_count_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
s_empty_next = s_empty_reg;
m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
m_axis_ptp_ts_valid_next = 1'b0;
if (start_packet_reg && PTP_TS_ENABLE) begin
m_axis_ptp_ts_next = ptp_ts;
if (PTP_TS_CTRL_IN_TUSER) begin
m_axis_ptp_ts_tag_next = s_axis_tuser >> 2;
m_axis_ptp_ts_valid_next = s_axis_tuser[1];
end else begin
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_next = 1'b1;
end
end
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
start_packet_next = 1'b0;
error_underflow_next = 1'b0;
if (s_axis_tvalid && s_axis_tready) begin
frame_next = !s_axis_tlast;
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_error_next = 1'b0;
frame_min_count_next = MIN_FRAME_LENGTH-4-CTRL_WIDTH;
reset_crc = 1'b1;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
if (s_axis_tvalid && cfg_tx_enable) begin
// XGMII start and preamble
xgmii_txd_next = {{3{ETH_PRE}}, XGMII_START};
xgmii_txc_next = 4'b0001;
s_axis_tready_next = 1'b1;
state_next = STATE_PREAMBLE;
end else begin
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
// send preamble
reset_crc = 1'b1;
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
xgmii_txd_next = {ETH_SFD, {3{ETH_PRE}}};
xgmii_txc_next = {CTRL_WIDTH{1'b0}};
s_axis_tready_next = 1'b1;
start_packet_next = 1'b1;
state_next = STATE_PAYLOAD;
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
if (frame_min_count_reg > CTRL_WIDTH) begin
frame_min_count_next = frame_min_count_reg - CTRL_WIDTH;
end else begin
frame_min_count_next = 0;
end
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = {CTRL_WIDTH{1'b0}};
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
if (!s_axis_tvalid || s_axis_tlast) begin
s_axis_tready_next = frame_next; // drop frame
frame_error_next = !s_axis_tvalid || s_axis_tuser[0];
error_underflow_next = !s_axis_tvalid;
if (ENABLE_PADDING && frame_min_count_reg) begin
if (frame_min_count_reg > CTRL_WIDTH) begin
s_empty_next = 0;
state_next = STATE_PAD;
end else begin
if (keep2empty(s_axis_tkeep) > CTRL_WIDTH-frame_min_count_reg) begin
s_empty_next = CTRL_WIDTH-frame_min_count_reg;
end
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LENGTH
s_axis_tready_next = frame_next; // drop frame
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = {CTRL_WIDTH{1'b0}};
s_tdata_next = 32'd0;
s_empty_next = 0;
update_crc = 1'b1;
if (frame_min_count_reg > CTRL_WIDTH) begin
frame_min_count_next = frame_min_count_reg - CTRL_WIDTH;
state_next = STATE_PAD;
end else begin
frame_min_count_next = 0;
s_empty_next = CTRL_WIDTH-frame_min_count_reg;
state_next = STATE_FCS_1;
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tready_next = frame_next; // drop frame
xgmii_txd_next = fcs_output_txd_0;
xgmii_txc_next = fcs_output_txc_0;
update_crc = 1'b1;
ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + deficit_idle_count_reg;
if (frame_error_reg) begin
state_next = STATE_ERR;
end else begin
state_next = STATE_FCS_2;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tready_next = frame_next; // drop frame
xgmii_txd_next = fcs_output_txd_1;
xgmii_txc_next = fcs_output_txc_1;
if (extra_cycle) begin
state_next = STATE_FCS_3;
end else begin
state_next = STATE_IFG;
end
end
STATE_FCS_3: begin
// last cycle
s_axis_tready_next = frame_next; // drop frame
xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd3) begin
state_next = STATE_IFG;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd0) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end
end
STATE_ERR: begin
// terminate packet with error
s_axis_tready_next = frame_next; // drop frame
// XGMII error
xgmii_txd_next = {XGMII_TERM, {3{XGMII_ERROR}}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
ifg_count_next = 8'd12;
state_next = STATE_IFG;
end
STATE_IFG: begin
// send IFG
s_axis_tready_next = frame_next; // drop frame
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
if (ifg_count_reg > 8'd4) begin
ifg_count_next = ifg_count_reg - 8'd4;
end else begin
ifg_count_next = 8'd0;
end
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd3 || frame_reg) begin
state_next = STATE_IFG;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd0 || frame_reg) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end
end
endcase
end
always @(posedge clk) begin
state_reg <= state_next;
frame_reg <= frame_next;
frame_error_reg <= frame_error_next;
frame_min_count_reg <= frame_min_count_next;
ifg_count_reg <= ifg_count_next;
deficit_idle_count_reg <= deficit_idle_count_next;
s_tdata_reg <= s_tdata_next;
s_empty_reg <= s_empty_next;
s_axis_tready_reg <= s_axis_tready_next;
m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
crc_state_reg[0] <= crc_state_next[0];
crc_state_reg[1] <= crc_state_next[1];
crc_state_reg[2] <= crc_state_next[2];
if (update_crc) begin
crc_state_reg[3] <= crc_state_next[3];
end
if (reset_crc) begin
crc_state_reg[3] <= 32'hFFFFFFFF;
end
xgmii_txd_reg <= xgmii_txd_next;
xgmii_txc_reg <= xgmii_txc_next;
start_packet_reg <= start_packet_next;
error_underflow_reg <= error_underflow_next;
if (rst) begin
state_reg <= STATE_IDLE;
frame_reg <= 1'b0;
ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0;
s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0;
xgmii_txd_reg <= {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_reg <= {CTRL_WIDTH{1'b1}};
start_packet_reg <= 1'b0;
error_underflow_reg <= 1'b0;
end
end
endmodule
`resetall

656
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/axis_xgmii_tx_64.v Executable file
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@@ -0,0 +1,656 @@
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream XGMII frame transmitter (AXI in, XGMII out)
*/
module axis_xgmii_tx_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
parameter PTP_TS_CTRL_IN_TUSER = 0,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TS_ENABLE ? (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* XGMII output
*/
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
/*
* Status
*/
output wire [1:0] start_packet,
output wire error_underflow
);
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_PAD = 3'd2,
STATE_FCS_1 = 3'd3,
STATE_FCS_2 = 3'd4,
STATE_ERR = 3'd5,
STATE_IFG = 3'd6;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg swap_lanes_reg = 1'b0, swap_lanes_next;
reg [31:0] swap_txd = 32'd0;
reg [3:0] swap_txc = 4'd0;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
reg [DATA_WIDTH-1:0] s_tdata_reg = 0, s_tdata_next;
reg [EMPTY_WIDTH-1:0] s_empty_reg = 0, s_empty_next;
reg [DATA_WIDTH-1:0] fcs_output_txd_0;
reg [DATA_WIDTH-1:0] fcs_output_txd_1;
reg [CTRL_WIDTH-1:0] fcs_output_txc_0;
reg [CTRL_WIDTH-1:0] fcs_output_txc_1;
reg [7:0] ifg_offset;
reg frame_start_reg = 1'b0, frame_start_next;
reg frame_reg = 1'b0, frame_next;
reg frame_error_reg = 1'b0, frame_error_next;
reg [MIN_LEN_WIDTH-1:0] frame_min_count_reg = 0, frame_min_count_next;
reg [7:0] ifg_count_reg = 8'd0, ifg_count_next;
reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0;
reg m_axis_ptp_ts_valid_reg = 1'b0;
reg m_axis_ptp_ts_valid_int_reg = 1'b0;
reg m_axis_ptp_ts_borrow_reg = 1'b0;
reg [31:0] crc_state_reg[7:0];
wire [31:0] crc_state_next[7:0];
reg [4+16-1:0] last_ts_reg = 0;
reg [4+16-1:0] ts_inc_reg = 0;
reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next;
reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next;
reg start_packet_reg = 2'b00;
reg error_underflow_reg = 1'b0, error_underflow_next;
assign s_axis_tready = s_axis_tready_reg;
assign xgmii_txd = xgmii_txd_reg;
assign xgmii_txc = xgmii_txc_reg;
assign m_axis_ptp_ts = PTP_TS_ENABLE ? ((!PTP_TS_FMT_TOD || m_axis_ptp_ts_borrow_reg) ? m_axis_ptp_ts_reg : m_axis_ptp_ts_adj_reg) : 0;
assign m_axis_ptp_ts_tag = PTP_TAG_ENABLE ? m_axis_ptp_ts_tag_reg : 0;
assign m_axis_ptp_ts_valid = PTP_TS_ENABLE || PTP_TAG_ENABLE ? m_axis_ptp_ts_valid_reg : 1'b0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
generate
genvar n;
for (n = 0; n < 8; n = n + 1) begin : crc
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8*(n+1)),
.STYLE("AUTO")
)
eth_crc (
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[7]),
.data_out(),
.state_out(crc_state_next[n])
);
end
endgenerate
function [2:0] keep2empty;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2empty = 3'd7;
8'bzzzzzz01: keep2empty = 3'd7;
8'bzzzzz011: keep2empty = 3'd6;
8'bzzzz0111: keep2empty = 3'd5;
8'bzzz01111: keep2empty = 3'd4;
8'bzz011111: keep2empty = 3'd3;
8'bz0111111: keep2empty = 3'd2;
8'b01111111: keep2empty = 3'd1;
8'b11111111: keep2empty = 3'd0;
endcase
endfunction
// Mask input data
integer j;
always @* begin
for (j = 0; j < 8; j = j + 1) begin
s_axis_tdata_masked[j*8 +: 8] = s_axis_tkeep[j] ? s_axis_tdata[j*8 +: 8] : 8'd0;
end
end
// FCS cycle calculation
always @* begin
casez (s_empty_reg)
3'd7: begin
fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_next[0][31:0], s_tdata_reg[7:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11100000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd3;
end
3'd6: begin
fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_state_next[1][31:0], s_tdata_reg[15:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd2;
end
3'd5: begin
fcs_output_txd_0 = {XGMII_TERM, ~crc_state_next[2][31:0], s_tdata_reg[23:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b10000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd1;
end
3'd4: begin
fcs_output_txd_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]};
fcs_output_txd_1 = {{7{XGMII_IDLE}}, XGMII_TERM};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd8;
end
3'd3: begin
fcs_output_txd_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]};
fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[4][31:24]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111110;
ifg_offset = 8'd7;
end
3'd2: begin
fcs_output_txd_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]};
fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[5][31:16]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111100;
ifg_offset = 8'd6;
end
3'd1: begin
fcs_output_txd_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]};
fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[6][31:8]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111000;
ifg_offset = 8'd5;
end
3'd0: begin
fcs_output_txd_0 = s_tdata_reg;
fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[7][31:0]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11110000;
ifg_offset = 8'd4;
end
endcase
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
swap_lanes_next = swap_lanes_reg;
frame_start_next = 1'b0;
frame_next = frame_reg;
frame_error_next = frame_error_reg;
frame_min_count_next = frame_min_count_reg;
ifg_count_next = ifg_count_reg;
deficit_idle_count_next = deficit_idle_count_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
s_empty_next = s_empty_reg;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
error_underflow_next = 1'b0;
if (s_axis_tvalid && s_axis_tready) begin
frame_next = !s_axis_tlast;
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_error_next = 1'b0;
frame_min_count_next = MIN_FRAME_LENGTH-4-CTRL_WIDTH;
reset_crc = 1'b1;
s_axis_tready_next = cfg_tx_enable;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
if (s_axis_tvalid && s_axis_tready) begin
// XGMII start, preamble, and SFD
xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START};
xgmii_txc_next = 8'b00000001;
frame_start_next = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
swap_lanes_next = 1'b0;
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
if (frame_min_count_reg > CTRL_WIDTH) begin
frame_min_count_next = frame_min_count_reg - CTRL_WIDTH;
end else begin
frame_min_count_next = 0;
end
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = {CTRL_WIDTH{1'b0}};
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
if (!s_axis_tvalid || s_axis_tlast) begin
s_axis_tready_next = frame_next; // drop frame
frame_error_next = !s_axis_tvalid || s_axis_tuser[0];
error_underflow_next = !s_axis_tvalid;
if (ENABLE_PADDING && frame_min_count_reg) begin
if (frame_min_count_reg > CTRL_WIDTH) begin
s_empty_next = 0;
state_next = STATE_PAD;
end else begin
if (keep2empty(s_axis_tkeep) > CTRL_WIDTH-frame_min_count_reg) begin
s_empty_next = CTRL_WIDTH-frame_min_count_reg;
end
if (frame_error_next) begin
state_next = STATE_ERR;
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
if (frame_error_next) begin
state_next = STATE_ERR;
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LENGTH
s_axis_tready_next = frame_next; // drop frame
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = {CTRL_WIDTH{1'b0}};
s_tdata_next = 64'd0;
s_empty_next = 0;
update_crc = 1'b1;
if (frame_min_count_reg > CTRL_WIDTH) begin
frame_min_count_next = frame_min_count_reg - CTRL_WIDTH;
state_next = STATE_PAD;
end else begin
frame_min_count_next = 0;
s_empty_next = CTRL_WIDTH-frame_min_count_reg;
if (frame_error_reg) begin
state_next = STATE_ERR;
end else begin
state_next = STATE_FCS_1;
end
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tready_next = frame_next; // drop frame
xgmii_txd_next = fcs_output_txd_0;
xgmii_txc_next = fcs_output_txc_0;
update_crc = 1'b1;
ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg;
if (s_empty_reg <= 4) begin
state_next = STATE_FCS_2;
end else begin
state_next = STATE_IFG;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tready_next = frame_next; // drop frame
xgmii_txd_next = fcs_output_txd_1;
xgmii_txc_next = fcs_output_txc_1;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
swap_lanes_next = 1'b1;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
end
s_axis_tready_next = cfg_tx_enable;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = cfg_tx_enable;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
end
end
STATE_ERR: begin
// terminate packet with error
s_axis_tready_next = frame_next; // drop frame
// XGMII error
xgmii_txd_next = {XGMII_TERM, {7{XGMII_ERROR}}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
ifg_count_next = 8'd12;
state_next = STATE_IFG;
end
STATE_IFG: begin
// send IFG
s_axis_tready_next = frame_next; // drop frame
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7 || frame_reg) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
swap_lanes_next = 1'b1;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
end
s_axis_tready_next = cfg_tx_enable;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4 || frame_reg) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = cfg_tx_enable;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
end
end
endcase
end
always @(posedge clk) begin
state_reg <= state_next;
swap_lanes_reg <= swap_lanes_next;
frame_start_reg <= frame_start_next;
frame_reg <= frame_next;
frame_error_reg <= frame_error_next;
frame_min_count_reg <= frame_min_count_next;
ifg_count_reg <= ifg_count_next;
deficit_idle_count_reg <= deficit_idle_count_next;
s_tdata_reg <= s_tdata_next;
s_empty_reg <= s_empty_next;
s_axis_tready_reg <= s_axis_tready_next;
m_axis_ptp_ts_valid_reg <= 1'b0;
m_axis_ptp_ts_valid_int_reg <= 1'b0;
start_packet_reg <= 2'b00;
error_underflow_reg <= error_underflow_next;
if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_int_reg;
m_axis_ptp_ts_adj_reg[15:0] <= m_axis_ptp_ts_reg[15:0];
{m_axis_ptp_ts_borrow_reg, m_axis_ptp_ts_adj_reg[45:16]} <= $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
m_axis_ptp_ts_adj_reg[47:46] <= 0;
m_axis_ptp_ts_adj_reg[95:48] <= m_axis_ptp_ts_reg[95:48] + 1;
end
if (frame_start_reg) begin
if (swap_lanes_reg) begin
if (PTP_TS_ENABLE) begin
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1);
m_axis_ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
m_axis_ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1);
end
end
start_packet_reg <= 2'b10;
end else begin
if (PTP_TS_ENABLE) begin
m_axis_ptp_ts_reg <= ptp_ts;
end
start_packet_reg <= 2'b01;
end
if (PTP_TS_ENABLE) begin
if (PTP_TS_CTRL_IN_TUSER) begin
m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 2;
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_int_reg <= s_axis_tuser[1];
end else begin
m_axis_ptp_ts_valid_reg <= s_axis_tuser[1];
end
end else begin
m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 1;
if (PTP_TS_FMT_TOD) begin
m_axis_ptp_ts_valid_int_reg <= 1'b1;
end else begin
m_axis_ptp_ts_valid_reg <= 1'b1;
end
end
end
end
crc_state_reg[0] <= crc_state_next[0];
crc_state_reg[1] <= crc_state_next[1];
crc_state_reg[2] <= crc_state_next[2];
crc_state_reg[3] <= crc_state_next[3];
crc_state_reg[4] <= crc_state_next[4];
crc_state_reg[5] <= crc_state_next[5];
crc_state_reg[6] <= crc_state_next[6];
if (update_crc) begin
crc_state_reg[7] <= crc_state_next[7];
end
if (reset_crc) begin
crc_state_reg[7] <= 32'hFFFFFFFF;
end
swap_txd <= xgmii_txd_next[63:32];
swap_txc <= xgmii_txc_next[7:4];
if (swap_lanes_reg) begin
xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd};
xgmii_txc_reg <= {xgmii_txc_next[3:0], swap_txc};
end else begin
xgmii_txd_reg <= xgmii_txd_next;
xgmii_txc_reg <= xgmii_txc_next;
end
last_ts_reg <= ptp_ts;
ts_inc_reg <= ptp_ts - last_ts_reg;
if (rst) begin
state_reg <= STATE_IDLE;
frame_start_reg <= 1'b0;
frame_reg <= 1'b0;
swap_lanes_reg <= 1'b0;
ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0;
s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0;
m_axis_ptp_ts_valid_int_reg <= 1'b0;
xgmii_txd_reg <= {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_reg <= {CTRL_WIDTH{1'b1}};
start_packet_reg <= 2'b00;
error_underflow_reg <= 1'b0;
end
end
endmodule
`resetall

315
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_arb_mux.v Executable file
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@@ -0,0 +1,315 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Ethernet arbitrated multiplexer
*/
module eth_arb_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame inputs
*/
input wire [S_COUNT-1:0] s_eth_hdr_valid,
output wire [S_COUNT-1:0] s_eth_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_eth_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_eth_payload_axis_tready,
input wire [S_COUNT-1:0] s_eth_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_eth_hdr_ready_reg = {S_COUNT{1'b0}}, s_eth_hdr_ready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = (m_eth_payload_axis_tready_int_reg && grant_valid) << grant_encoded;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_eth_payload_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_eth_payload_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_eth_payload_axis_tvalid[grant_encoded];
wire current_s_tready = s_eth_payload_axis_tready[grant_encoded];
wire current_s_tlast = s_eth_payload_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] current_s_tid = s_eth_payload_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_eth_payload_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_eth_hdr_valid & ~grant;
assign acknowledge = grant & s_eth_payload_axis_tvalid & s_eth_payload_axis_tready & s_eth_payload_axis_tlast;
always @* begin
frame_next = frame_reg;
s_eth_hdr_ready_next = {S_COUNT{1'b0}};
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (s_eth_payload_axis_tvalid[grant_encoded] && s_eth_payload_axis_tready[grant_encoded]) begin
// end of frame detection
if (s_eth_payload_axis_tlast[grant_encoded]) begin
frame_next = 1'b0;
end
end
if (!frame_reg && grant_valid && (m_eth_hdr_ready || !m_eth_hdr_valid)) begin
// start of frame
frame_next = 1'b1;
s_eth_hdr_ready_next = grant;
m_eth_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[grant_encoded*48 +: 48];
m_eth_type_next = s_eth_type[grant_encoded*16 +: 16];
end
// pass through selected packet data
m_eth_payload_axis_tdata_int = current_s_tdata;
m_eth_payload_axis_tkeep_int = current_s_tkeep;
m_eth_payload_axis_tvalid_int = current_s_tvalid && m_eth_payload_axis_tready_int_reg && grant_valid;
m_eth_payload_axis_tlast_int = current_s_tlast;
m_eth_payload_axis_tid_int = current_s_tid;
m_eth_payload_axis_tdest_int = current_s_tdest;
m_eth_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
if (rst) begin
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= {S_COUNT{1'b0}};
m_eth_hdr_valid_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tid = ID_ENABLE ? m_eth_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

405
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_axis_rx.v Executable file
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@@ -0,0 +1,405 @@
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream ethernet frame receiver (AXI in, Ethernet frame out)
*/
module eth_axis_rx #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination
);
parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
parameter HDR_SIZE = 14;
parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = HDR_SIZE % BYTE_LANES;
// bus width assertions
initial begin
if (BYTE_LANES * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame on an AXI stream interface, decodes
and strips the headers, then produces the header fields in parallel along
with the payload in a separate AXI stream.
*/
reg read_eth_header_reg = 1'b1, read_eth_header_next;
reg read_eth_payload_reg = 1'b0, read_eth_payload_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg flush_save;
reg transfer_in_save;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg [DATA_WIDTH-1:0] save_axis_tdata_reg = 64'd0;
reg [KEEP_WIDTH-1:0] save_axis_tkeep_reg = 8'd0;
reg save_axis_tlast_reg = 1'b0;
reg save_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] shift_axis_tdata;
reg [KEEP_WIDTH-1:0] shift_axis_tkeep;
reg shift_axis_tvalid;
reg shift_axis_tlast;
reg shift_axis_tuser;
reg shift_axis_input_tready;
reg shift_axis_extra_cycle_reg = 1'b0;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
always @* begin
if (OFFSET == 0) begin
// passthrough if no overlap
shift_axis_tdata = s_axis_tdata;
shift_axis_tkeep = s_axis_tkeep;
shift_axis_tvalid = s_axis_tvalid;
shift_axis_tlast = s_axis_tlast;
shift_axis_tuser = s_axis_tuser;
shift_axis_input_tready = 1'b1;
end else if (shift_axis_extra_cycle_reg) begin
shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8);
shift_axis_tkeep = {{KEEP_WIDTH{1'b0}}, save_axis_tkeep_reg} >> OFFSET;
shift_axis_tvalid = 1'b1;
shift_axis_tlast = save_axis_tlast_reg;
shift_axis_tuser = save_axis_tuser_reg;
shift_axis_input_tready = flush_save;
end else begin
shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8);
shift_axis_tkeep = {s_axis_tkeep, save_axis_tkeep_reg} >> OFFSET;
shift_axis_tvalid = s_axis_tvalid;
shift_axis_tlast = (s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0));
shift_axis_tuser = (s_axis_tuser && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0));
shift_axis_input_tready = !(s_axis_tlast && s_axis_tready && s_axis_tvalid);
end
end
always @* begin
read_eth_header_next = read_eth_header_reg;
read_eth_payload_next = read_eth_payload_reg;
ptr_next = ptr_reg;
s_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_axis_input_tready && (!m_eth_hdr_valid || m_eth_hdr_ready);
flush_save = 1'b0;
transfer_in_save = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
error_header_early_termination_next = 1'b0;
m_eth_payload_axis_tdata_int = shift_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_axis_tkeep;
m_eth_payload_axis_tvalid_int = 1'b0;
m_eth_payload_axis_tlast_int = shift_axis_tlast;
m_eth_payload_axis_tuser_int = shift_axis_tuser;
if ((s_axis_tready && s_axis_tvalid) || (m_eth_payload_axis_tready_int_reg && shift_axis_extra_cycle_reg)) begin
transfer_in_save = 1'b1;
if (read_eth_header_reg) begin
// word transfer in - store it
ptr_next = ptr_reg + 1;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[offset%BYTE_LANES])) begin \
field = s_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \
end
`_HEADER_FIELD_(0, m_eth_dest_mac_next[5*8 +: 8])
`_HEADER_FIELD_(1, m_eth_dest_mac_next[4*8 +: 8])
`_HEADER_FIELD_(2, m_eth_dest_mac_next[3*8 +: 8])
`_HEADER_FIELD_(3, m_eth_dest_mac_next[2*8 +: 8])
`_HEADER_FIELD_(4, m_eth_dest_mac_next[1*8 +: 8])
`_HEADER_FIELD_(5, m_eth_dest_mac_next[0*8 +: 8])
`_HEADER_FIELD_(6, m_eth_src_mac_next[5*8 +: 8])
`_HEADER_FIELD_(7, m_eth_src_mac_next[4*8 +: 8])
`_HEADER_FIELD_(8, m_eth_src_mac_next[3*8 +: 8])
`_HEADER_FIELD_(9, m_eth_src_mac_next[2*8 +: 8])
`_HEADER_FIELD_(10, m_eth_src_mac_next[1*8 +: 8])
`_HEADER_FIELD_(11, m_eth_src_mac_next[0*8 +: 8])
`_HEADER_FIELD_(12, m_eth_type_next[1*8 +: 8])
`_HEADER_FIELD_(13, m_eth_type_next[0*8 +: 8])
if (ptr_reg == 13/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[13%BYTE_LANES])) begin
if (!shift_axis_tlast) begin
m_eth_hdr_valid_next = 1'b1;
read_eth_header_next = 1'b0;
read_eth_payload_next = 1'b1;
end
end
`undef _HEADER_FIELD_
end
if (read_eth_payload_reg) begin
// transfer payload
m_eth_payload_axis_tdata_int = shift_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_axis_tkeep;
m_eth_payload_axis_tvalid_int = 1'b1;
m_eth_payload_axis_tlast_int = shift_axis_tlast;
m_eth_payload_axis_tuser_int = shift_axis_tuser;
end
if (shift_axis_tlast) begin
if (read_eth_header_next) begin
// don't have the whole header
error_header_early_termination_next = 1'b1;
end
flush_save = 1'b1;
ptr_next = 1'b0;
read_eth_header_next = 1'b1;
read_eth_payload_next = 1'b0;
end
end
end
always @(posedge clk) begin
read_eth_header_reg <= read_eth_header_next;
read_eth_payload_reg <= read_eth_payload_next;
ptr_reg <= ptr_next;
s_axis_tready_reg <= s_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
error_header_early_termination_reg <= error_header_early_termination_next;
busy_reg <= (read_eth_payload_next || ptr_next != 0);
if (transfer_in_save) begin
save_axis_tdata_reg <= s_axis_tdata;
save_axis_tkeep_reg <= s_axis_tkeep;
save_axis_tuser_reg <= s_axis_tuser;
end
if (flush_save) begin
save_axis_tlast_reg <= 1'b0;
shift_axis_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_axis_tlast_reg <= s_axis_tlast;
shift_axis_extra_cycle_reg <= OFFSET ? s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) != 0) : 1'b0;
end
if (rst) begin
read_eth_header_reg <= 1'b1;
read_eth_payload_reg <= 1'b0;
ptr_reg <= 0;
s_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 1'b0;
save_axis_tlast_reg <= 1'b0;
shift_axis_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
// datapath
if (store_eth_payload_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

409
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_axis_tx.v Executable file
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@@ -0,0 +1,409 @@
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream ethernet frame transmitter (Ethernet frame in, AXI out)
*/
module eth_axis_tx #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status signals
*/
output wire busy
);
parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
parameter HDR_SIZE = 14;
parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = HDR_SIZE % BYTE_LANES;
// bus width assertions
initial begin
if (BYTE_LANES * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame with header fields in parallel along
with the payload in an AXI stream, combines the header with the payload, and
transmits the complete Ethernet frame on the output AXI stream interface.
*/
// datapath control signals
reg store_eth_hdr;
reg send_eth_header_reg = 1'b0, send_eth_header_next;
reg send_eth_payload_reg = 1'b0, send_eth_payload_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg flush_save;
reg transfer_in_save;
reg [47:0] eth_dest_mac_reg = 48'd0;
reg [47:0] eth_src_mac_reg = 48'd0;
reg [15:0] eth_type_reg = 16'd0;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg busy_reg = 1'b0;
reg [DATA_WIDTH-1:0] save_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] save_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg save_eth_payload_axis_tlast_reg = 1'b0;
reg save_eth_payload_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] shift_eth_payload_axis_tdata;
reg [KEEP_WIDTH-1:0] shift_eth_payload_axis_tkeep;
reg shift_eth_payload_axis_tvalid;
reg shift_eth_payload_axis_tlast;
reg shift_eth_payload_axis_tuser;
reg shift_eth_payload_axis_input_tready;
reg shift_eth_payload_axis_extra_cycle_reg = 1'b0;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign busy = busy_reg;
always @* begin
if (OFFSET == 0) begin
// passthrough if no overlap
shift_eth_payload_axis_tdata = s_eth_payload_axis_tdata;
shift_eth_payload_axis_tkeep = s_eth_payload_axis_tkeep;
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = s_eth_payload_axis_tlast;
shift_eth_payload_axis_tuser = s_eth_payload_axis_tuser;
shift_eth_payload_axis_input_tready = 1'b1;
end else if (shift_eth_payload_axis_extra_cycle_reg) begin
shift_eth_payload_axis_tdata = {s_eth_payload_axis_tdata, save_eth_payload_axis_tdata_reg} >> ((KEEP_WIDTH-OFFSET)*8);
shift_eth_payload_axis_tkeep = {{KEEP_WIDTH{1'b0}}, save_eth_payload_axis_tkeep_reg} >> (KEEP_WIDTH-OFFSET);
shift_eth_payload_axis_tvalid = 1'b1;
shift_eth_payload_axis_tlast = save_eth_payload_axis_tlast_reg;
shift_eth_payload_axis_tuser = save_eth_payload_axis_tuser_reg;
shift_eth_payload_axis_input_tready = flush_save;
end else begin
shift_eth_payload_axis_tdata = {s_eth_payload_axis_tdata, save_eth_payload_axis_tdata_reg} >> ((KEEP_WIDTH-OFFSET)*8);
shift_eth_payload_axis_tkeep = {s_eth_payload_axis_tkeep, save_eth_payload_axis_tkeep_reg} >> (KEEP_WIDTH-OFFSET);
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = (s_eth_payload_axis_tlast && ((s_eth_payload_axis_tkeep & ({KEEP_WIDTH{1'b1}} << (KEEP_WIDTH-OFFSET))) == 0));
shift_eth_payload_axis_tuser = (s_eth_payload_axis_tuser && ((s_eth_payload_axis_tkeep & ({KEEP_WIDTH{1'b1}} << (KEEP_WIDTH-OFFSET))) == 0));
shift_eth_payload_axis_input_tready = !(s_eth_payload_axis_tlast && s_eth_payload_axis_tready && s_eth_payload_axis_tvalid);
end
end
always @* begin
send_eth_header_next = send_eth_header_reg;
send_eth_payload_next = send_eth_payload_reg;
ptr_next = ptr_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
flush_save = 1'b0;
transfer_in_save = 1'b0;
m_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
store_eth_hdr = 1'b1;
ptr_next = 0;
send_eth_header_next = 1'b1;
send_eth_payload_next = (OFFSET != 0) && (CYCLE_COUNT == 1);
s_eth_payload_axis_tready_next = send_eth_payload_next && m_axis_tready_int_early;
end
if (send_eth_payload_reg) begin
s_eth_payload_axis_tready_next = m_axis_tready_int_early && shift_eth_payload_axis_input_tready;
m_axis_tdata_int = shift_eth_payload_axis_tdata;
m_axis_tkeep_int = shift_eth_payload_axis_tkeep;
m_axis_tlast_int = shift_eth_payload_axis_tlast;
m_axis_tuser_int = shift_eth_payload_axis_tuser;
if ((s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) || (m_axis_tready_int_reg && shift_eth_payload_axis_extra_cycle_reg)) begin
transfer_in_save = 1'b1;
m_axis_tvalid_int = 1'b1;
if (shift_eth_payload_axis_tlast) begin
flush_save = 1'b1;
s_eth_payload_axis_tready_next = 1'b0;
ptr_next = 0;
send_eth_payload_next = 1'b0;
end
end
end
if (m_axis_tready_int_reg && (!OFFSET || !send_eth_payload_reg || m_axis_tvalid_int)) begin
if (send_eth_header_reg) begin
ptr_next = ptr_reg + 1;
if ((OFFSET != 0) && (CYCLE_COUNT == 1 || ptr_next == CYCLE_COUNT-1) && !send_eth_payload_reg) begin
send_eth_payload_next = 1'b1;
s_eth_payload_axis_tready_next = m_axis_tready_int_early && shift_eth_payload_axis_input_tready;
end
m_axis_tvalid_int = 1'b1;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/BYTE_LANES) begin \
m_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \
m_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \
end
`_HEADER_FIELD_(0, eth_dest_mac_reg[5*8 +: 8])
`_HEADER_FIELD_(1, eth_dest_mac_reg[4*8 +: 8])
`_HEADER_FIELD_(2, eth_dest_mac_reg[3*8 +: 8])
`_HEADER_FIELD_(3, eth_dest_mac_reg[2*8 +: 8])
`_HEADER_FIELD_(4, eth_dest_mac_reg[1*8 +: 8])
`_HEADER_FIELD_(5, eth_dest_mac_reg[0*8 +: 8])
`_HEADER_FIELD_(6, eth_src_mac_reg[5*8 +: 8])
`_HEADER_FIELD_(7, eth_src_mac_reg[4*8 +: 8])
`_HEADER_FIELD_(8, eth_src_mac_reg[3*8 +: 8])
`_HEADER_FIELD_(9, eth_src_mac_reg[2*8 +: 8])
`_HEADER_FIELD_(10, eth_src_mac_reg[1*8 +: 8])
`_HEADER_FIELD_(11, eth_src_mac_reg[0*8 +: 8])
`_HEADER_FIELD_(12, eth_type_reg[1*8 +: 8])
`_HEADER_FIELD_(13, eth_type_reg[0*8 +: 8])
if (ptr_reg == 13/BYTE_LANES) begin
if (!send_eth_payload_reg) begin
s_eth_payload_axis_tready_next = m_axis_tready_int_early;
send_eth_payload_next = 1'b1;
end
send_eth_header_next = 1'b0;
end
`undef _HEADER_FIELD_
end
end
s_eth_hdr_ready_next = !(send_eth_header_next || send_eth_payload_next);
end
always @(posedge clk) begin
send_eth_header_reg <= send_eth_header_next;
send_eth_payload_reg <= send_eth_payload_next;
ptr_reg <= ptr_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
busy_reg <= send_eth_header_next || send_eth_payload_next;
if (store_eth_hdr) begin
eth_dest_mac_reg <= s_eth_dest_mac;
eth_src_mac_reg <= s_eth_src_mac;
eth_type_reg <= s_eth_type;
end
if (transfer_in_save) begin
save_eth_payload_axis_tdata_reg <= s_eth_payload_axis_tdata;
save_eth_payload_axis_tkeep_reg <= s_eth_payload_axis_tkeep;
save_eth_payload_axis_tuser_reg <= s_eth_payload_axis_tuser;
end
if (flush_save) begin
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_axis_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_eth_payload_axis_tlast_reg <= s_eth_payload_axis_tlast;
shift_eth_payload_axis_extra_cycle_reg <= OFFSET ? s_eth_payload_axis_tlast && ((s_eth_payload_axis_tkeep & ({KEEP_WIDTH{1'b1}} << (KEEP_WIDTH-OFFSET))) != 0) : 1'b0;
end
if (rst) begin
send_eth_header_reg <= 1'b0;
send_eth_payload_reg <= 1'b0;
ptr_reg <= 0;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

731
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_mac_10g.v Executable file
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@@ -0,0 +1,731 @@
/*
Copyright (c) 2015-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC
*/
module eth_mac_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_PTP_TS_CTRL_IN_TUSER = 0,
parameter TX_PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter TX_USER_WIDTH = (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1,
parameter RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter PFC_ENABLE = 0,
parameter PAUSE_ENABLE = PFC_ENABLE
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
input wire tx_lfc_req,
input wire tx_lfc_resend,
input wire rx_lfc_en,
output wire rx_lfc_req,
input wire rx_lfc_ack,
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
input wire [7:0] tx_pfc_req,
input wire tx_pfc_resend,
input wire [7:0] rx_pfc_en,
output wire [7:0] rx_pfc_req,
input wire [7:0] rx_pfc_ack,
/*
* Pause interface
*/
input wire tx_lfc_pause_en,
input wire tx_pause_req,
output wire tx_pause_ack,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire stat_tx_mcf,
output wire stat_rx_mcf,
output wire stat_tx_lfc_pkt,
output wire stat_tx_lfc_xon,
output wire stat_tx_lfc_xoff,
output wire stat_tx_lfc_paused,
output wire stat_tx_pfc_pkt,
output wire [7:0] stat_tx_pfc_xon,
output wire [7:0] stat_tx_pfc_xoff,
output wire [7:0] stat_tx_pfc_paused,
output wire stat_rx_lfc_pkt,
output wire stat_rx_lfc_xon,
output wire stat_rx_lfc_xoff,
output wire stat_rx_lfc_paused,
output wire stat_rx_pfc_pkt,
output wire [7:0] stat_rx_pfc_xon,
output wire [7:0] stat_rx_pfc_xoff,
output wire [7:0] stat_rx_pfc_paused,
/*
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable,
input wire [47:0] cfg_mcf_rx_eth_dst_mcast,
input wire cfg_mcf_rx_check_eth_dst_mcast,
input wire [47:0] cfg_mcf_rx_eth_dst_ucast,
input wire cfg_mcf_rx_check_eth_dst_ucast,
input wire [47:0] cfg_mcf_rx_eth_src,
input wire cfg_mcf_rx_check_eth_src,
input wire [15:0] cfg_mcf_rx_eth_type,
input wire [15:0] cfg_mcf_rx_opcode_lfc,
input wire cfg_mcf_rx_check_opcode_lfc,
input wire [15:0] cfg_mcf_rx_opcode_pfc,
input wire cfg_mcf_rx_check_opcode_pfc,
input wire cfg_mcf_rx_forward,
input wire cfg_mcf_rx_enable,
input wire [47:0] cfg_tx_lfc_eth_dst,
input wire [47:0] cfg_tx_lfc_eth_src,
input wire [15:0] cfg_tx_lfc_eth_type,
input wire [15:0] cfg_tx_lfc_opcode,
input wire cfg_tx_lfc_en,
input wire [15:0] cfg_tx_lfc_quanta,
input wire [15:0] cfg_tx_lfc_refresh,
input wire [47:0] cfg_tx_pfc_eth_dst,
input wire [47:0] cfg_tx_pfc_eth_src,
input wire [15:0] cfg_tx_pfc_eth_type,
input wire [15:0] cfg_tx_pfc_opcode,
input wire cfg_tx_pfc_en,
input wire [8*16-1:0] cfg_tx_pfc_quanta,
input wire [8*16-1:0] cfg_tx_pfc_refresh,
input wire [15:0] cfg_rx_lfc_opcode,
input wire cfg_rx_lfc_en,
input wire [15:0] cfg_rx_pfc_opcode,
input wire cfg_rx_pfc_en
);
parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE;
parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH;
// bus width assertions
initial begin
if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin
$error("Error: Interface width must be 32 or 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
wire [DATA_WIDTH-1:0] tx_axis_tdata_int;
wire [KEEP_WIDTH-1:0] tx_axis_tkeep_int;
wire tx_axis_tvalid_int;
wire tx_axis_tready_int;
wire tx_axis_tlast_int;
wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_int;
wire [DATA_WIDTH-1:0] rx_axis_tdata_int;
wire [KEEP_WIDTH-1:0] rx_axis_tkeep_int;
wire rx_axis_tvalid_int;
wire rx_axis_tlast_int;
wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int;
generate
if (DATA_WIDTH == 64) begin
axis_xgmii_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata_int),
.m_axis_tkeep(rx_axis_tkeep_int),
.m_axis_tvalid(rx_axis_tvalid_int),
.m_axis_tlast(rx_axis_tlast_int),
.m_axis_tuser(rx_axis_tuser_int),
.ptp_ts(rx_ptp_ts),
.cfg_rx_enable(cfg_rx_enable),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_xgmii_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH_INT)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata_int),
.s_axis_tkeep(tx_axis_tkeep_int),
.s_axis_tvalid(tx_axis_tvalid_int),
.s_axis_tready(tx_axis_tready_int),
.s_axis_tlast(tx_axis_tlast_int),
.s_axis_tuser(tx_axis_tuser_int),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
end else begin
axis_xgmii_rx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata_int),
.m_axis_tkeep(rx_axis_tkeep_int),
.m_axis_tvalid(rx_axis_tvalid_int),
.m_axis_tlast(rx_axis_tlast_int),
.m_axis_tuser(rx_axis_tuser_int),
.ptp_ts(rx_ptp_ts),
.cfg_rx_enable(cfg_rx_enable),
.start_packet(rx_start_packet[0]),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
assign rx_start_packet[1] = 1'b0;
axis_xgmii_tx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH_INT)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata_int),
.s_axis_tkeep(tx_axis_tkeep_int),
.s_axis_tvalid(tx_axis_tvalid_int),
.s_axis_tready(tx_axis_tready_int),
.s_axis_tlast(tx_axis_tlast_int),
.s_axis_tuser(tx_axis_tuser_int),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.start_packet(tx_start_packet[0]),
.error_underflow(tx_error_underflow)
);
assign tx_start_packet[1] = 1'b0;
end
if (MAC_CTRL_ENABLE) begin : mac_ctrl
localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2;
wire tx_mcf_valid;
wire tx_mcf_ready;
wire [47:0] tx_mcf_eth_dst;
wire [47:0] tx_mcf_eth_src;
wire [15:0] tx_mcf_eth_type;
wire [15:0] tx_mcf_opcode;
wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params;
wire rx_mcf_valid;
wire [47:0] rx_mcf_eth_dst;
wire [47:0] rx_mcf_eth_src;
wire [15:0] rx_mcf_eth_type;
wire [15:0] rx_mcf_opcode;
wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params;
// terminate LFC pause requests from RX internally on TX side
wire tx_pause_req_int;
wire rx_lfc_ack_int;
reg tx_lfc_req_sync_reg_1 = 1'b0;
reg tx_lfc_req_sync_reg_2 = 1'b0;
reg tx_lfc_req_sync_reg_3 = 1'b0;
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
tx_lfc_req_sync_reg_1 <= 1'b0;
end else begin
tx_lfc_req_sync_reg_1 <= rx_lfc_req;
end
end
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_lfc_req_sync_reg_2 <= 1'b0;
tx_lfc_req_sync_reg_3 <= 1'b0;
end else begin
tx_lfc_req_sync_reg_2 <= tx_lfc_req_sync_reg_1;
tx_lfc_req_sync_reg_3 <= tx_lfc_req_sync_reg_2;
end
end
reg rx_lfc_ack_sync_reg_1 = 1'b0;
reg rx_lfc_ack_sync_reg_2 = 1'b0;
reg rx_lfc_ack_sync_reg_3 = 1'b0;
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
rx_lfc_ack_sync_reg_1 <= 1'b0;
end else begin
rx_lfc_ack_sync_reg_1 <= tx_lfc_pause_en ? tx_pause_ack : 0;
end
end
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_lfc_ack_sync_reg_2 <= 1'b0;
rx_lfc_ack_sync_reg_3 <= 1'b0;
end else begin
rx_lfc_ack_sync_reg_2 <= rx_lfc_ack_sync_reg_1;
rx_lfc_ack_sync_reg_3 <= rx_lfc_ack_sync_reg_2;
end
end
assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en ? tx_lfc_req_sync_reg_3 : 0);
assign rx_lfc_ack_int = rx_lfc_ack || rx_lfc_ack_sync_reg_3;
// handle PTP TS enable bit in tuser
wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_in;
if (PTP_TS_ENABLE && !TX_PTP_TS_CTRL_IN_TUSER) begin
assign tx_axis_tuser_in = {tx_axis_tuser[TX_USER_WIDTH-1:1], 1'b1, tx_axis_tuser[0]};
end else begin
assign tx_axis_tuser_in = tx_axis_tuser;
end
mac_ctrl_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH_INT),
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
)
mac_ctrl_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
/*
* AXI stream input
*/
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser_in),
/*
* AXI stream output
*/
.m_axis_tdata(tx_axis_tdata_int),
.m_axis_tkeep(tx_axis_tkeep_int),
.m_axis_tvalid(tx_axis_tvalid_int),
.m_axis_tready(tx_axis_tready_int),
.m_axis_tlast(tx_axis_tlast_int),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_axis_tuser_int),
/*
* MAC control frame interface
*/
.mcf_valid(tx_mcf_valid),
.mcf_ready(tx_mcf_ready),
.mcf_eth_dst(tx_mcf_eth_dst),
.mcf_eth_src(tx_mcf_eth_src),
.mcf_eth_type(tx_mcf_eth_type),
.mcf_opcode(tx_mcf_opcode),
.mcf_params(tx_mcf_params),
.mcf_id(0),
.mcf_dest(0),
.mcf_user(0),
/*
* Pause interface
*/
.tx_pause_req(tx_pause_req_int),
.tx_pause_ack(tx_pause_ack),
/*
* Status
*/
.stat_tx_mcf(stat_tx_mcf)
);
mac_ctrl_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.USE_READY(0),
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
)
mac_ctrl_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
/*
* AXI stream input
*/
.s_axis_tdata(rx_axis_tdata_int),
.s_axis_tkeep(rx_axis_tkeep_int),
.s_axis_tvalid(rx_axis_tvalid_int),
.s_axis_tready(),
.s_axis_tlast(rx_axis_tlast_int),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_axis_tuser_int),
/*
* AXI stream output
*/
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(1'b1),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
/*
* MAC control frame interface
*/
.mcf_valid(rx_mcf_valid),
.mcf_eth_dst(rx_mcf_eth_dst),
.mcf_eth_src(rx_mcf_eth_src),
.mcf_eth_type(rx_mcf_eth_type),
.mcf_opcode(rx_mcf_opcode),
.mcf_params(rx_mcf_params),
.mcf_id(),
.mcf_dest(),
.mcf_user(),
/*
* Configuration
*/
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc && PFC_ENABLE),
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
/*
* Status
*/
.stat_rx_mcf(stat_rx_mcf)
);
mac_pause_ctrl_tx #(
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE),
.PFC_ENABLE(PFC_ENABLE)
)
mac_pause_ctrl_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
/*
* MAC control frame interface
*/
.mcf_valid(tx_mcf_valid),
.mcf_ready(tx_mcf_ready),
.mcf_eth_dst(tx_mcf_eth_dst),
.mcf_eth_src(tx_mcf_eth_src),
.mcf_eth_type(tx_mcf_eth_type),
.mcf_opcode(tx_mcf_opcode),
.mcf_params(tx_mcf_params),
/*
* Pause (IEEE 802.3 annex 31B)
*/
.tx_lfc_req(tx_lfc_req),
.tx_lfc_resend(tx_lfc_resend),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
*/
.tx_pfc_req(tx_pfc_req),
.tx_pfc_resend(tx_pfc_resend),
/*
* Configuration
*/
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
.cfg_tx_lfc_en(cfg_tx_lfc_en),
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
.cfg_tx_pfc_en(cfg_tx_pfc_en),
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
.cfg_quanta_step((DATA_WIDTH*256)/512),
.cfg_quanta_clk_en(1'b1),
/*
* Status
*/
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
.stat_tx_lfc_xon(stat_tx_lfc_xon),
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
.stat_tx_lfc_paused(stat_tx_lfc_paused),
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
.stat_tx_pfc_xon(stat_tx_pfc_xon),
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
.stat_tx_pfc_paused(stat_tx_pfc_paused)
);
mac_pause_ctrl_rx #(
.MCF_PARAMS_SIZE(18),
.PFC_ENABLE(PFC_ENABLE)
)
mac_pause_ctrl_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
/*
* MAC control frame interface
*/
.mcf_valid(rx_mcf_valid),
.mcf_eth_dst(rx_mcf_eth_dst),
.mcf_eth_src(rx_mcf_eth_src),
.mcf_eth_type(rx_mcf_eth_type),
.mcf_opcode(rx_mcf_opcode),
.mcf_params(rx_mcf_params),
/*
* Pause (IEEE 802.3 annex 31B)
*/
.rx_lfc_en(rx_lfc_en),
.rx_lfc_req(rx_lfc_req),
.rx_lfc_ack(rx_lfc_ack_int),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
*/
.rx_pfc_en(rx_pfc_en),
.rx_pfc_req(rx_pfc_req),
.rx_pfc_ack(rx_pfc_ack),
/*
* Configuration
*/
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
.cfg_rx_lfc_en(cfg_rx_lfc_en),
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
.cfg_rx_pfc_en(cfg_rx_pfc_en),
.cfg_quanta_step((DATA_WIDTH*256)/512),
.cfg_quanta_clk_en(1'b1),
/*
* Status
*/
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
.stat_rx_lfc_xon(stat_rx_lfc_xon),
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
.stat_rx_lfc_paused(stat_rx_lfc_paused),
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
.stat_rx_pfc_xon(stat_rx_pfc_xon),
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
.stat_rx_pfc_paused(stat_rx_pfc_paused)
);
end else begin
assign tx_axis_tdata_int = tx_axis_tdata;
assign tx_axis_tkeep_int = tx_axis_tkeep;
assign tx_axis_tvalid_int = tx_axis_tvalid;
assign tx_axis_tready = tx_axis_tready_int;
assign tx_axis_tlast_int = tx_axis_tlast;
assign tx_axis_tuser_int = tx_axis_tuser;
assign rx_axis_tdata = rx_axis_tdata_int;
assign rx_axis_tkeep = rx_axis_tkeep_int;
assign rx_axis_tvalid = rx_axis_tvalid_int;
assign rx_axis_tlast = rx_axis_tlast_int;
assign rx_axis_tuser = rx_axis_tuser_int;
assign rx_lfc_req = 0;
assign rx_pfc_req = 0;
assign tx_pause_ack = 0;
assign stat_tx_mcf = 0;
assign stat_rx_mcf = 0;
assign stat_tx_lfc_pkt = 0;
assign stat_tx_lfc_xon = 0;
assign stat_tx_lfc_xoff = 0;
assign stat_tx_lfc_paused = 0;
assign stat_tx_pfc_pkt = 0;
assign stat_tx_pfc_xon = 0;
assign stat_tx_pfc_xoff = 0;
assign stat_tx_pfc_paused = 0;
assign stat_rx_lfc_pkt = 0;
assign stat_rx_lfc_xon = 0;
assign stat_rx_lfc_xoff = 0;
assign stat_rx_lfc_paused = 0;
assign stat_rx_pfc_pkt = 0;
assign stat_rx_pfc_xon = 0;
assign stat_rx_pfc_xoff = 0;
assign stat_rx_pfc_paused = 0;
end
endgenerate
endmodule
`resetall

488
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_mac_10g_fifo.v Executable file
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/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC with TX and RX FIFOs
*/
module eth_mac_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_RAM_PIPELINE = 1,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_PTP_TS_CTRL_IN_TUSER = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter TX_PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter TX_USER_WIDTH = (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1,
parameter RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (PTP_TS_ENABLE) begin : tx_ptp
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(6)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(TX_PTP_TAG_ENABLE),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
// AXI input
.s_clk(tx_clk),
.s_rst(tx_rst),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(tx_axis_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(m_axis_tx_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
if (PTP_TS_ENABLE) begin : rx_ptp
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(6)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
end else begin
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
endgenerate
eth_mac_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TS_CTRL_IN_TUSER(TX_PTP_TS_CTRL_IN_TUSER),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH)
)
eth_mac_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
`resetall

142
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY
*/
module eth_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* Status
*/
output wire tx_bad_block,
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_sequence_error,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_status,
/*
* Configuration
*/
input wire cfg_tx_prbs31_enable,
input wire cfg_rx_prbs31_enable
);
eth_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
eth_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_bad_block(tx_bad_block),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule
`resetall

149
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g_rx.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY RX
*/
module eth_phy_10g_rx #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_sequence_error,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_status,
/*
* Configuration
*/
input wire cfg_rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
xgmii_baser_dec_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
xgmii_baser_dec_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error)
);
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g_rx_ber_mon.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY BER monitor
*/
module eth_phy_10g_rx_ber_mon #
(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
/*
* Status
*/
output wire rx_high_ber
);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
parameter COUNT_WIDTH = $clog2($rtoi(COUNT_125US));
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [COUNT_WIDTH-1:0] time_count_reg = COUNT_125US, time_count_next;
reg [3:0] ber_count_reg = 4'd0, ber_count_next;
reg rx_high_ber_reg = 1'b0, rx_high_ber_next;
assign rx_high_ber = rx_high_ber_reg;
always @* begin
if (time_count_reg > 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = time_count_reg;
end
ber_count_next = ber_count_reg;
rx_high_ber_next = rx_high_ber_reg;
if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
if (ber_count_reg != 4'd15) begin
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end else begin
// invalid header
if (ber_count_reg == 4'd15) begin
rx_high_ber_next = 1'b1;
end else begin
ber_count_next = ber_count_reg + 1;
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end
if (time_count_reg == 0) begin
// 125 us timer expired
ber_count_next = 4'd0;
time_count_next = COUNT_125US;
end
end
always @(posedge clk) begin
time_count_reg <= time_count_next;
ber_count_reg <= ber_count_next;
rx_high_ber_reg <= rx_high_ber_next;
if (rst) begin
time_count_reg <= COUNT_125US;
ber_count_reg <= 4'd0;
rx_high_ber_reg <= 1'b0;
end
end
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g_rx_frame_sync.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY frame sync
*/
module eth_phy_10g_rx_frame_sync #
(
parameter HDR_WIDTH = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire rx_block_lock
);
parameter BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
parameter BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [5:0] sh_count_reg = 6'd0, sh_count_next;
reg [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
reg [BITSLIP_COUNT_WIDTH-1:0] bitslip_count_reg = 0, bitslip_count_next;
reg serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
reg rx_block_lock_reg = 1'b0, rx_block_lock_next;
assign serdes_rx_bitslip = serdes_rx_bitslip_reg;
assign rx_block_lock = rx_block_lock_reg;
always @* begin
sh_count_next = sh_count_reg;
sh_invalid_count_next = sh_invalid_count_reg;
bitslip_count_next = bitslip_count_reg;
serdes_rx_bitslip_next = serdes_rx_bitslip_reg;
rx_block_lock_next = rx_block_lock_reg;
if (bitslip_count_reg) begin
bitslip_count_next = bitslip_count_reg-1;
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_LOW_CYCLES > 0 ? BITSLIP_LOW_CYCLES-1 : 0;
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;
if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
if (!sh_invalid_count_reg) begin
rx_block_lock_next = 1'b1;
end
end
end else begin
// invalid header
sh_count_next = sh_count_reg + 1;
sh_invalid_count_next = sh_invalid_count_reg + 1;
if (!rx_block_lock_reg || &sh_invalid_count_reg) begin
// invalid count overflow, lost block lock
sh_count_next = 0;
sh_invalid_count_next = 0;
rx_block_lock_next = 1'b0;
// slip one bit
serdes_rx_bitslip_next = 1'b1;
bitslip_count_next = BITSLIP_HIGH_CYCLES > 0 ? BITSLIP_HIGH_CYCLES-1 : 0;
end else if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
end
end
end
always @(posedge clk) begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
bitslip_count_reg <= bitslip_count_next;
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
rx_block_lock_reg <= rx_block_lock_next;
if (rst) begin
sh_count_reg <= 6'd0;
sh_invalid_count_reg <= 4'd0;
bitslip_count_reg <= 0;
serdes_rx_bitslip_reg <= 1'b0;
rx_block_lock_reg <= 1'b0;
end
end
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g_rx_if.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY RX IF
*/
module eth_phy_10g_rx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_rx_data,
output wire [HDR_WIDTH-1:0] encoded_rx_hdr,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* Status
*/
input wire rx_bad_block,
input wire rx_sequence_error,
output wire [6:0] rx_error_count,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_status,
/*
* Configuration
*/
input wire cfg_rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] serdes_rx_data_rev, serdes_rx_data_int;
wire [HDR_WIDTH-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_rx_hdr_rev[n] = serdes_rx_hdr[HDR_WIDTH-n-1];
end
end else begin
assign serdes_rx_data_rev = serdes_rx_data;
assign serdes_rx_hdr_rev = serdes_rx_hdr;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_WIDTH-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_WIDTH-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_rx_data_pipe_reg[n] <= {DATA_WIDTH{1'b0}};
serdes_rx_hdr_pipe_reg[n] <= {HDR_WIDTH{1'b0}};
end
always @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];
end
end
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_rx_data_int = serdes_rx_data_rev;
assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
end
endgenerate
wire [DATA_WIDTH-1:0] descrambled_rx_data;
reg [DATA_WIDTH-1:0] encoded_rx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] encoded_rx_hdr_reg = {HDR_WIDTH{1'b0}};
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
reg [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data;
reg [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data_reg = 0;
reg [6:0] rx_error_count_reg = 0;
reg [5:0] rx_error_count_1_reg = 0;
reg [5:0] rx_error_count_2_reg = 0;
reg [5:0] rx_error_count_1_temp = 0;
reg [5:0] rx_error_count_2_temp = 0;
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
);
lfsr #(
.LFSR_WIDTH(31),
.LFSR_POLY(31'h10000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH+HDR_WIDTH),
.STYLE("AUTO")
)
prbs31_check_inst (
.data_in(~{serdes_rx_data_int, serdes_rx_hdr_int}),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
integer i;
always @* begin
rx_error_count_1_temp = 0;
rx_error_count_2_temp = 0;
for (i = 0; i < DATA_WIDTH+HDR_WIDTH; i = i + 1) begin
if (i & 1) begin
rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data_reg[i];
end else begin
rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data_reg[i];
end
end
end
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
if (PRBS31_ENABLE) begin
if (cfg_rx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
prbs31_data_reg <= prbs31_data;
end else begin
prbs31_data_reg <= 0;
end
rx_error_count_1_reg <= rx_error_count_1_temp;
rx_error_count_2_reg <= rx_error_count_2_temp;
rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
end else begin
rx_error_count_reg <= 0;
end
end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
assign rx_error_count = rx_error_count_reg;
wire serdes_rx_bitslip_int;
wire serdes_rx_reset_req_int;
assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable);
assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && cfg_rx_prbs31_enable);
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip_int),
.rx_block_lock(rx_block_lock)
);
eth_phy_10g_rx_ber_mon #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
eth_phy_10g_rx_watchdog #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_watchdog_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_reset_req(serdes_rx_reset_req_int),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status)
);
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g_rx_watchdog.v Executable file
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/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY serdes watchdog
*/
module eth_phy_10g_rx_watchdog #
(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_reset_req,
/*
* Monitor inputs
*/
input wire rx_bad_block,
input wire rx_sequence_error,
input wire rx_block_lock,
input wire rx_high_ber,
/*
* Status
*/
output wire rx_status
);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
parameter COUNT_WIDTH = $clog2($rtoi(COUNT_125US));
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [COUNT_WIDTH-1:0] time_count_reg = 0, time_count_next;
reg [3:0] error_count_reg = 0, error_count_next;
reg [3:0] status_count_reg = 0, status_count_next;
reg saw_ctrl_sh_reg = 1'b0, saw_ctrl_sh_next;
reg [9:0] block_error_count_reg = 0, block_error_count_next;
reg serdes_rx_reset_req_reg = 1'b0, serdes_rx_reset_req_next;
reg rx_status_reg = 1'b0, rx_status_next;
assign serdes_rx_reset_req = serdes_rx_reset_req_reg;
assign rx_status = rx_status_reg;
always @* begin
error_count_next = error_count_reg;
status_count_next = status_count_reg;
saw_ctrl_sh_next = saw_ctrl_sh_reg;
block_error_count_next = block_error_count_reg;
serdes_rx_reset_req_next = 1'b0;
rx_status_next = rx_status_reg;
if (rx_block_lock) begin
if (serdes_rx_hdr == SYNC_CTRL) begin
saw_ctrl_sh_next = 1'b1;
end
if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin
block_error_count_next = block_error_count_reg + 1;
end
end else begin
rx_status_next = 1'b0;
status_count_next = 0;
end
if (time_count_reg != 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = COUNT_125US;
if (!saw_ctrl_sh_reg || &block_error_count_reg) begin
error_count_next = error_count_reg + 1;
status_count_next = 0;
end else begin
error_count_next = 0;
if (!(&status_count_reg)) begin
status_count_next = status_count_reg + 1;
end
end
if (&error_count_reg) begin
error_count_next = 0;
serdes_rx_reset_req_next = 1'b1;
end
if (&status_count_reg) begin
rx_status_next = 1'b1;
end
saw_ctrl_sh_next = 1'b0;
block_error_count_next = 0;
end
end
always @(posedge clk) begin
time_count_reg <= time_count_next;
error_count_reg <= error_count_next;
status_count_reg <= status_count_next;
saw_ctrl_sh_reg <= saw_ctrl_sh_next;
block_error_count_reg <= block_error_count_next;
rx_status_reg <= rx_status_next;
if (rst) begin
time_count_reg <= COUNT_125US;
error_count_reg <= 0;
status_count_reg <= 0;
saw_ctrl_sh_reg <= 1'b0;
block_error_count_reg <= 0;
rx_status_reg <= 1'b0;
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
serdes_rx_reset_req_reg <= 1'b0;
end else begin
serdes_rx_reset_req_reg <= serdes_rx_reset_req_next;
end
end
endmodule
`resetall

127
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g_tx.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY TX
*/
module eth_phy_10g_tx #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* Status
*/
output wire tx_bad_block,
/*
* Configuration
*/
input wire cfg_tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
xgmii_baser_enc_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
xgmii_baser_enc_inst (
.clk(clk),
.rst(rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.tx_bad_block(tx_bad_block)
);
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule
`resetall

183
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_phy_10g_tx_if.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY TX IF
*/
module eth_phy_10g_tx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
input wire [DATA_WIDTH-1:0] encoded_tx_data,
input wire [HDR_WIDTH-1:0] encoded_tx_hdr,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* Configuration
*/
input wire cfg_tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
wire [DATA_WIDTH-1:0] scrambled_data;
reg [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data;
reg [DATA_WIDTH-1:0] serdes_tx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] serdes_tx_hdr_reg = {HDR_WIDTH{1'b0}};
wire [DATA_WIDTH-1:0] serdes_tx_data_int;
wire [HDR_WIDTH-1:0] serdes_tx_hdr_int;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_tx_data_int[n] = serdes_tx_data_reg[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_tx_hdr_int[n] = serdes_tx_hdr_reg[HDR_WIDTH-n-1];
end
end else begin
assign serdes_tx_data_int = serdes_tx_data_reg;
assign serdes_tx_hdr_int = serdes_tx_hdr_reg;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_WIDTH-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_WIDTH-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_tx_data_pipe_reg[n] <= {DATA_WIDTH{1'b0}};
serdes_tx_hdr_pipe_reg[n] <= {HDR_WIDTH{1'b0}};
end
always @(posedge clk) begin
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1];
end
end
assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_tx_data = serdes_tx_data_int;
assign serdes_tx_hdr = serdes_tx_hdr_int;
end
endgenerate
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
scrambler_inst (
.data_in(encoded_tx_data),
.state_in(scrambler_state_reg),
.data_out(scrambled_data),
.state_out(scrambler_state)
);
lfsr #(
.LFSR_WIDTH(31),
.LFSR_POLY(31'h10000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH+HDR_WIDTH),
.STYLE("AUTO")
)
prbs31_gen_inst (
.data_in({DATA_WIDTH+HDR_WIDTH{1'b0}}),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
if (PRBS31_ENABLE && cfg_tx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
serdes_tx_data_reg <= ~prbs31_data[DATA_WIDTH+HDR_WIDTH-1:HDR_WIDTH];
serdes_tx_hdr_reg <= ~prbs31_data[HDR_WIDTH-1:0];
end else begin
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
end
endmodule
`resetall

395
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_xcvr_phy_quad_wrapper.v Executable file
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/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver and PHY quad wrapper
*/
module eth_xcvr_phy_quad_wrapper #
(
parameter COUNT = 4,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Common
*/
output wire xcvr_gtpowergood_out,
/*
* PLL
*/
input wire xcvr_gtrefclk00_in,
/*
* Serial data
*/
output wire [COUNT-1:0] xcvr_txp,
output wire [COUNT-1:0] xcvr_txn,
input wire [COUNT-1:0] xcvr_rxp,
input wire [COUNT-1:0] xcvr_rxn,
/*
* PHY connections
*/
output wire phy_1_tx_clk,
output wire phy_1_tx_rst,
input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc,
output wire phy_1_rx_clk,
output wire phy_1_rx_rst,
output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc,
output wire phy_1_tx_bad_block,
output wire [6:0] phy_1_rx_error_count,
output wire phy_1_rx_bad_block,
output wire phy_1_rx_sequence_error,
output wire phy_1_rx_block_lock,
output wire phy_1_rx_high_ber,
output wire phy_1_rx_status,
input wire phy_1_cfg_tx_prbs31_enable,
input wire phy_1_cfg_rx_prbs31_enable,
output wire phy_2_tx_clk,
output wire phy_2_tx_rst,
input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc,
output wire phy_2_rx_clk,
output wire phy_2_rx_rst,
output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc,
output wire phy_2_tx_bad_block,
output wire [6:0] phy_2_rx_error_count,
output wire phy_2_rx_bad_block,
output wire phy_2_rx_sequence_error,
output wire phy_2_rx_block_lock,
output wire phy_2_rx_high_ber,
output wire phy_2_rx_status,
input wire phy_2_cfg_tx_prbs31_enable,
input wire phy_2_cfg_rx_prbs31_enable,
output wire phy_3_tx_clk,
output wire phy_3_tx_rst,
input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc,
output wire phy_3_rx_clk,
output wire phy_3_rx_rst,
output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc,
output wire phy_3_tx_bad_block,
output wire [6:0] phy_3_rx_error_count,
output wire phy_3_rx_bad_block,
output wire phy_3_rx_sequence_error,
output wire phy_3_rx_block_lock,
output wire phy_3_rx_high_ber,
output wire phy_3_rx_status,
input wire phy_3_cfg_tx_prbs31_enable,
input wire phy_3_cfg_rx_prbs31_enable,
output wire phy_4_tx_clk,
output wire phy_4_tx_rst,
input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc,
output wire phy_4_rx_clk,
output wire phy_4_rx_rst,
output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc,
output wire phy_4_tx_bad_block,
output wire [6:0] phy_4_rx_error_count,
output wire phy_4_rx_bad_block,
output wire phy_4_rx_sequence_error,
output wire phy_4_rx_block_lock,
output wire phy_4_rx_high_ber,
output wire phy_4_rx_status,
input wire phy_4_cfg_tx_prbs31_enable,
input wire phy_4_cfg_rx_prbs31_enable
);
generate
wire xcvr_qpll0lock;
wire xcvr_qpll0clk;
wire xcvr_qpll0refclk;
if (COUNT > 0) begin : phy1
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_1 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
// PLL out
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock),
.xcvr_qpll0clk_out(xcvr_qpll0clk),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(xcvr_txp[0]),
.xcvr_txn(xcvr_txn[0]),
.xcvr_rxp(xcvr_rxp[0]),
.xcvr_rxn(xcvr_rxn[0]),
// PHY connections
.phy_tx_clk(phy_1_tx_clk),
.phy_tx_rst(phy_1_tx_rst),
.phy_xgmii_txd(phy_1_xgmii_txd),
.phy_xgmii_txc(phy_1_xgmii_txc),
.phy_rx_clk(phy_1_rx_clk),
.phy_rx_rst(phy_1_rx_rst),
.phy_xgmii_rxd(phy_1_xgmii_rxd),
.phy_xgmii_rxc(phy_1_xgmii_rxc),
.phy_tx_bad_block(phy_1_tx_bad_block),
.phy_rx_error_count(phy_1_rx_error_count),
.phy_rx_bad_block(phy_1_rx_bad_block),
.phy_rx_sequence_error(phy_1_rx_sequence_error),
.phy_rx_block_lock(phy_1_rx_block_lock),
.phy_rx_high_ber(phy_1_rx_high_ber),
.phy_rx_status(phy_1_rx_status),
.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
);
end
if (COUNT > 1) begin : phy2
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_2 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
// Serial data
.xcvr_txp(xcvr_txp[1]),
.xcvr_txn(xcvr_txn[1]),
.xcvr_rxp(xcvr_rxp[1]),
.xcvr_rxn(xcvr_rxn[1]),
// PHY connections
.phy_tx_clk(phy_2_tx_clk),
.phy_tx_rst(phy_2_tx_rst),
.phy_xgmii_txd(phy_2_xgmii_txd),
.phy_xgmii_txc(phy_2_xgmii_txc),
.phy_rx_clk(phy_2_rx_clk),
.phy_rx_rst(phy_2_rx_rst),
.phy_xgmii_rxd(phy_2_xgmii_rxd),
.phy_xgmii_rxc(phy_2_xgmii_rxc),
.phy_tx_bad_block(phy_2_tx_bad_block),
.phy_rx_error_count(phy_2_rx_error_count),
.phy_rx_bad_block(phy_2_rx_bad_block),
.phy_rx_sequence_error(phy_2_rx_sequence_error),
.phy_rx_block_lock(phy_2_rx_block_lock),
.phy_rx_high_ber(phy_2_rx_high_ber),
.phy_rx_status(phy_2_rx_status),
.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
);
end
if (COUNT > 2) begin : phy3
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_3 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
// Serial data
.xcvr_txp(xcvr_txp[2]),
.xcvr_txn(xcvr_txn[2]),
.xcvr_rxp(xcvr_rxp[2]),
.xcvr_rxn(xcvr_rxn[2]),
// PHY connections
.phy_tx_clk(phy_3_tx_clk),
.phy_tx_rst(phy_3_tx_rst),
.phy_xgmii_txd(phy_3_xgmii_txd),
.phy_xgmii_txc(phy_3_xgmii_txc),
.phy_rx_clk(phy_3_rx_clk),
.phy_rx_rst(phy_3_rx_rst),
.phy_xgmii_rxd(phy_3_xgmii_rxd),
.phy_xgmii_rxc(phy_3_xgmii_rxc),
.phy_tx_bad_block(phy_3_tx_bad_block),
.phy_rx_error_count(phy_3_rx_error_count),
.phy_rx_bad_block(phy_3_rx_bad_block),
.phy_rx_sequence_error(phy_3_rx_sequence_error),
.phy_rx_block_lock(phy_3_rx_block_lock),
.phy_rx_high_ber(phy_3_rx_high_ber),
.phy_rx_status(phy_3_rx_status),
.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
);
end
if (COUNT > 3) begin : phy4
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_4 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
// Serial data
.xcvr_txp(xcvr_txp[3]),
.xcvr_txn(xcvr_txn[3]),
.xcvr_rxp(xcvr_rxp[3]),
.xcvr_rxn(xcvr_rxn[3]),
// PHY connections
.phy_tx_clk(phy_4_tx_clk),
.phy_tx_rst(phy_4_tx_rst),
.phy_xgmii_txd(phy_4_xgmii_txd),
.phy_xgmii_txc(phy_4_xgmii_txc),
.phy_rx_clk(phy_4_rx_clk),
.phy_rx_rst(phy_4_rx_rst),
.phy_xgmii_rxd(phy_4_xgmii_rxd),
.phy_xgmii_rxc(phy_4_xgmii_rxc),
.phy_tx_bad_block(phy_4_tx_bad_block),
.phy_rx_error_count(phy_4_rx_error_count),
.phy_rx_bad_block(phy_4_rx_bad_block),
.phy_rx_sequence_error(phy_4_rx_sequence_error),
.phy_rx_block_lock(phy_4_rx_block_lock),
.phy_rx_high_ber(phy_4_rx_high_ber),
.phy_rx_status(phy_4_rx_status),
.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
);
end
endgenerate
endmodule
`resetall

307
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/eth_xcvr_phy_wrapper.v Executable file
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/*
Copyright (c) 2021-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver and PHY wrapper
*/
module eth_xcvr_phy_wrapper #
(
parameter HAS_COMMON = 1,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Common
*/
output wire xcvr_gtpowergood_out,
/*
* PLL out
*/
input wire xcvr_gtrefclk00_in,
output wire xcvr_qpll0lock_out,
output wire xcvr_qpll0clk_out,
output wire xcvr_qpll0refclk_out,
/*
* PLL in
*/
input wire xcvr_qpll0lock_in,
output wire xcvr_qpll0reset_out,
input wire xcvr_qpll0clk_in,
input wire xcvr_qpll0refclk_in,
/*
* Serial data
*/
output wire xcvr_txp,
output wire xcvr_txn,
input wire xcvr_rxp,
input wire xcvr_rxn,
/*
* PHY connections
*/
output wire phy_tx_clk,
output wire phy_tx_rst,
input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
output wire phy_rx_clk,
output wire phy_rx_rst,
output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
output wire phy_tx_bad_block,
output wire [6:0] phy_rx_error_count,
output wire phy_rx_bad_block,
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
output wire phy_rx_status,
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire phy_rx_reset_req;
wire gt_reset_tx_datapath = 1'b0;
wire gt_reset_rx_datapath = phy_rx_reset_req;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
generate
if (HAS_COMMON) begin : xcvr
eth_xcvr_gt_full
eth_xcvr_gt_full_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtrefclk00_in(xcvr_gtrefclk00_in),
.qpll0lock_out(xcvr_qpll0lock_out),
.qpll0outclk_out(xcvr_qpll0clk_out),
.qpll0outrefclk_out(xcvr_qpll0refclk_out),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
assign xcvr_qpll0reset_out = 1'b0;
end else begin : xcvr
eth_xcvr_gt_channel
eth_xcvr_gt_channel_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
.qpll0clk_in(xcvr_qpll0clk_in),
.qpll0refclk_in(xcvr_qpll0refclk_in),
.qpll1clk_in(1'b0),
.qpll1refclk_in(1'b0),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
assign xcvr_qpll0lock_out = 1'b0;
assign xcvr_qpll0clk_out = 1'b0;
assign xcvr_qpll0refclk_out = 1'b0;
end
endgenerate
sync_reset #(
.N(4)
)
tx_reset_sync_inst (
.clk(phy_tx_clk),
.rst(!gt_reset_tx_done),
.out(phy_tx_rst)
);
sync_reset #(
.N(4)
)
rx_reset_sync_inst (
.clk(phy_rx_clk),
.rst(!gt_reset_rx_done),
.out(phy_rx_rst)
);
eth_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(1),
.SCRAMBLER_DISABLE(0),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
phy_inst (
.tx_clk(phy_tx_clk),
.tx_rst(phy_tx_rst),
.rx_clk(phy_rx_clk),
.rx_rst(phy_rx_rst),
.xgmii_txd(phy_xgmii_txd),
.xgmii_txc(phy_xgmii_txc),
.xgmii_rxd(phy_xgmii_rxd),
.xgmii_rxc(phy_xgmii_rxc),
.serdes_tx_data(gt_txdata),
.serdes_tx_hdr(gt_txheader),
.serdes_rx_data(gt_rxdata),
.serdes_rx_hdr(gt_rxheader),
.serdes_rx_bitslip(gt_rxgearboxslip),
.serdes_rx_reset_req(phy_rx_reset_req),
.tx_bad_block(phy_tx_bad_block),
.rx_error_count(phy_rx_error_count),
.rx_bad_block(phy_rx_bad_block),
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.rx_status(phy_rx_status),
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule
`resetall

602
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/fpga_core.v Executable file
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/*
Copyright (c) 2020-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter integer IP_ADDR = 128,
parameter integer PORT_IN = 1234,
parameter [47:0] MAC_ADDR = 48'h02_00_00_00_00_00
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
input wire [15:0] packet_size,
output wire [63:0] rx_fifo_udp_payload_axis_tdata,
output wire [7:0] rx_fifo_udp_payload_axis_tkeep,
output wire rx_fifo_udp_payload_axis_tvalid,
input wire rx_fifo_udp_payload_axis_tready,
output wire rx_fifo_udp_payload_axis_tlast,
output wire rx_fifo_udp_payload_axis_tuser,
input wire [63:0] tx_fifo_udp_payload_axis_tdata,
input wire [7:0] tx_fifo_udp_payload_axis_tkeep,
input wire tx_fifo_udp_payload_axis_tvalid,
output wire tx_fifo_udp_payload_axis_tready,
input wire tx_fifo_udp_payload_axis_tlast,
input wire tx_fifo_udp_payload_axis_tuser,
input wire [3:0] tx_fifo_udp_payload_axis_tdest,
/*
* Ethernet: SFP+
*/
input wire sfp_tx_clk,
input wire sfp_tx_rst,
output wire [63:0] sfp_txd,
output wire [7:0] sfp_txc,
input wire sfp_rx_clk,
input wire sfp_rx_rst,
input wire [63:0] sfp_rxd,
input wire [7:0] sfp_rxc
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
reg tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
reg [15:0] tx_udp_dest_port;
reg [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
// Configuration
// wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [47:0] local_mac = MAC_ADDR;
// wire [31:0] local_ip = {8'd192, 8'd168, 8'd2, 8'd128};
// wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd2, 8'd1};
wire [31:0] local_ip = {8'd192, 8'd168, IP_ADDR[7:0], 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, IP_ADDR[7:0], 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// wire [15:0] port = 16'd1234;
wire [15:0] port = PORT_IN;
wire [15:0] control_port = 16'd1235;
wire [15:0] control_packet_size = 16'd512;
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == PORT_IN;
wire no_match = ~match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((~match_cond_reg & ~no_match_reg) |
(rx_udp_payload_axis_tvalid & rx_udp_payload_axis_tready & rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign rx_udp_hdr_ready = (tx_eth_hdr_ready & match_cond) | no_match;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid & match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready & match_cond_reg) | no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
// assign tx_udp_source_port = 16'd1234;
assign tx_udp_source_port = PORT_IN;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast || tlast_udp; // what happens if tlast comes before payload length ends
// assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign tx_udp_payload_axis_tuser = 0;
reg [12:0] packet_size_div_8;
// assign packet_size_div_8 = packet_size[15:3];
// Need to inject additional TLAST signals on UDP packet boundaries, incoming data from
// DMA will only have TLAST at very end
reg [15:0] tlast_cnt;
reg tlast_udp;
always @(posedge clk) begin
if (rst) begin
tlast_cnt <= 0;
tlast_udp <= 0;
tx_udp_hdr_valid <= 0;
// next_packet_ready <= 1;
tx_udp_length <= 1024;
packet_size_div_8 <= 128;
end else begin
if (tx_fifo_udp_payload_axis_tready && tx_fifo_udp_payload_axis_tvalid) begin
if (tlast_cnt == (packet_size_div_8-2)) begin
tlast_udp <= 1;
tlast_cnt <= tlast_cnt + 1;
end else if (tlast_cnt == (packet_size_div_8-1)) begin
tlast_udp <= 0;
tlast_cnt <= 0;
// next_packet_ready <= 1;
end else begin
tlast_cnt <= tlast_cnt + 1;
tlast_udp <= 0;
end
end else if (tx_fifo_udp_payload_axis_tready && tx_fifo_udp_payload_axis_tlast) begin
tlast_cnt <= 0;
end
if (tx_udp_hdr_ready) begin
if (tx_fifo_udp_payload_axis_tvalid) begin
tx_udp_hdr_valid <= 1;
// next_packet_ready <= 0;
if (tx_fifo_udp_payload_axis_tdest == 15) begin
// Control Traffic
tx_udp_dest_port <= control_port;
tx_udp_length <= control_packet_size+8;
packet_size_div_8 <= (control_packet_size >> 3);
end else if (tx_fifo_udp_payload_axis_tdest == 0) begin
// Header Packet
tx_udp_dest_port <= port;
tx_udp_length <= 1024+8;
packet_size_div_8 <= (1024 >> 3);
end else begin
// Data Traffic
tx_udp_dest_port <= port;
tx_udp_length <= packet_size+8;
packet_size_div_8 <= (packet_size >> 3);
end
end
end else begin
tx_udp_hdr_valid = 0;
end
end
end
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(8192),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(8192),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(sfp_rx_clk),
.rx_rst(sfp_rx_rst),
.tx_clk(sfp_tx_clk),
.tx_rst(sfp_tx_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(sfp_rxd),
.xgmii_rxc(sfp_rxc),
.xgmii_txd(sfp_txd),
.xgmii_txc(sfp_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64 #(
.UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH(4096)
)
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
endmodule
`resetall

353
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/ip_64.v Executable file
View File

@@ -0,0 +1,353 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IPv4 block, ethernet frame interface (64 bit datapath)
*/
module ip_64
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* ARP requests
*/
output wire arp_request_valid,
input wire arp_request_ready,
output wire [31:0] arp_request_ip,
input wire arp_response_valid,
output wire arp_response_ready,
input wire arp_response_error,
input wire [47:0] arp_response_mac,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status
*/
output wire rx_busy,
output wire tx_busy,
output wire rx_error_header_early_termination,
output wire rx_error_payload_early_termination,
output wire rx_error_invalid_header,
output wire rx_error_invalid_checksum,
output wire tx_error_payload_early_termination,
output wire tx_error_arp_failed,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_ARP_QUERY = 2'd1,
STATE_WAIT_PACKET = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg outgoing_ip_hdr_valid_reg = 1'b0, outgoing_ip_hdr_valid_next;
wire outgoing_ip_hdr_ready;
reg [47:0] outgoing_eth_dest_mac_reg = 48'h000000000000, outgoing_eth_dest_mac_next;
wire outgoing_ip_payload_axis_tready;
/*
* IP frame processing
*/
ip_eth_rx_64
ip_eth_rx_64_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_eth_dest_mac(m_ip_eth_dest_mac),
.m_eth_src_mac(m_ip_eth_src_mac),
.m_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// Status signals
.busy(rx_busy),
.error_header_early_termination(rx_error_header_early_termination),
.error_payload_early_termination(rx_error_payload_early_termination),
.error_invalid_header(rx_error_invalid_header),
.error_invalid_checksum(rx_error_invalid_checksum)
);
ip_eth_tx_64
ip_eth_tx_64_inst (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(outgoing_ip_hdr_valid_reg),
.s_ip_hdr_ready(outgoing_ip_hdr_ready),
.s_eth_dest_mac(outgoing_eth_dest_mac_reg),
.s_eth_src_mac(local_mac),
.s_eth_type(16'h0800),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(16'd0),
.s_ip_flags(3'b010),
.s_ip_fragment_offset(13'd0),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(outgoing_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(tx_busy),
.error_payload_early_termination(tx_error_payload_early_termination)
);
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg arp_request_valid_reg = 1'b0, arp_request_valid_next;
reg arp_response_ready_reg = 1'b0, arp_response_ready_next;
reg drop_packet_reg = 1'b0, drop_packet_next;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = outgoing_ip_payload_axis_tready || drop_packet_reg;
assign arp_request_valid = arp_request_valid_reg;
assign arp_request_ip = s_ip_dest_ip;
assign arp_response_ready = arp_response_ready_reg;
assign tx_error_arp_failed = arp_response_error;
always @* begin
state_next = STATE_IDLE;
arp_request_valid_next = arp_request_valid_reg && !arp_request_ready;
arp_response_ready_next = 1'b0;
drop_packet_next = 1'b0;
s_ip_hdr_ready_next = 1'b0;
outgoing_ip_hdr_valid_next = outgoing_ip_hdr_valid_reg && !outgoing_ip_hdr_ready;
outgoing_eth_dest_mac_next = outgoing_eth_dest_mac_reg;
case (state_reg)
STATE_IDLE: begin
// wait for outgoing packet
if (s_ip_hdr_valid) begin
// initiate ARP request
arp_request_valid_next = 1'b1;
arp_response_ready_next = 1'b1;
state_next = STATE_ARP_QUERY;
end else begin
state_next = STATE_IDLE;
end
end
STATE_ARP_QUERY: begin
arp_response_ready_next = 1'b1;
if (arp_response_valid) begin
// wait for ARP reponse
if (arp_response_error) begin
// did not get MAC address; drop packet
s_ip_hdr_ready_next = 1'b1;
drop_packet_next = 1'b1;
state_next = STATE_WAIT_PACKET;
end else begin
// got MAC address; send packet
s_ip_hdr_ready_next = 1'b1;
outgoing_ip_hdr_valid_next = 1'b1;
outgoing_eth_dest_mac_next = arp_response_mac;
state_next = STATE_WAIT_PACKET;
end
end else begin
state_next = STATE_ARP_QUERY;
end
end
STATE_WAIT_PACKET: begin
drop_packet_next = drop_packet_reg;
// wait for packet transfer to complete
if (s_ip_payload_axis_tlast && s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_PACKET;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
arp_request_valid_reg <= 1'b0;
arp_response_ready_reg <= 1'b0;
drop_packet_reg <= 1'b0;
s_ip_hdr_ready_reg <= 1'b0;
outgoing_ip_hdr_valid_reg <= 1'b0;
end else begin
state_reg <= state_next;
arp_request_valid_reg <= arp_request_valid_next;
arp_response_ready_reg <= arp_response_ready_next;
drop_packet_reg <= drop_packet_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
outgoing_ip_hdr_valid_reg <= outgoing_ip_hdr_valid_next;
end
outgoing_eth_dest_mac_reg <= outgoing_eth_dest_mac_next;
end
endmodule
`resetall

406
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/ip_arb_mux.v Executable file
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@@ -0,0 +1,406 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IP arbitrated multiplexer
*/
module ip_arb_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* IP frame inputs
*/
input wire [S_COUNT-1:0] s_ip_hdr_valid,
output wire [S_COUNT-1:0] s_ip_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*4-1:0] s_ip_version,
input wire [S_COUNT*4-1:0] s_ip_ihl,
input wire [S_COUNT*6-1:0] s_ip_dscp,
input wire [S_COUNT*2-1:0] s_ip_ecn,
input wire [S_COUNT*16-1:0] s_ip_length,
input wire [S_COUNT*16-1:0] s_ip_identification,
input wire [S_COUNT*3-1:0] s_ip_flags,
input wire [S_COUNT*13-1:0] s_ip_fragment_offset,
input wire [S_COUNT*8-1:0] s_ip_ttl,
input wire [S_COUNT*8-1:0] s_ip_protocol,
input wire [S_COUNT*16-1:0] s_ip_header_checksum,
input wire [S_COUNT*32-1:0] s_ip_source_ip,
input wire [S_COUNT*32-1:0] s_ip_dest_ip,
input wire [S_COUNT*DATA_WIDTH-1:0] s_ip_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_ip_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_ip_payload_axis_tready,
input wire [S_COUNT-1:0] s_ip_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_ip_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_ip_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_ip_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [DATA_WIDTH-1:0] m_ip_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_ip_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_ip_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_ip_payload_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_ip_hdr_ready_reg = {S_COUNT{1'b0}}, s_ip_hdr_ready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
// internal datapath
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = (m_ip_payload_axis_tready_int_reg && grant_valid) << grant_encoded;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_ip_payload_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_ip_payload_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_ip_payload_axis_tvalid[grant_encoded];
wire current_s_tready = s_ip_payload_axis_tready[grant_encoded];
wire current_s_tlast = s_ip_payload_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] current_s_tid = s_ip_payload_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_ip_payload_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_ip_payload_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_ip_hdr_valid & ~grant;
assign acknowledge = grant & s_ip_payload_axis_tvalid & s_ip_payload_axis_tready & s_ip_payload_axis_tlast;
always @* begin
frame_next = frame_reg;
s_ip_hdr_ready_next = {S_COUNT{1'b0}};
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
if (s_ip_payload_axis_tvalid[grant_encoded] && s_ip_payload_axis_tready[grant_encoded]) begin
// end of frame detection
if (s_ip_payload_axis_tlast[grant_encoded]) begin
frame_next = 1'b0;
end
end
if (!frame_reg && grant_valid && (m_ip_hdr_ready || !m_ip_hdr_valid)) begin
// start of frame
frame_next = 1'b1;
s_ip_hdr_ready_next = grant;
m_ip_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[grant_encoded*48 +: 48];
m_eth_type_next = s_eth_type[grant_encoded*16 +: 16];
m_ip_version_next = s_ip_version[grant_encoded*4 +: 4];
m_ip_ihl_next = s_ip_ihl[grant_encoded*4 +: 4];
m_ip_dscp_next = s_ip_dscp[grant_encoded*6 +: 6];
m_ip_ecn_next = s_ip_ecn[grant_encoded*2 +: 2];
m_ip_length_next = s_ip_length[grant_encoded*16 +: 16];
m_ip_identification_next = s_ip_identification[grant_encoded*16 +: 16];
m_ip_flags_next = s_ip_flags[grant_encoded*3 +: 3];
m_ip_fragment_offset_next = s_ip_fragment_offset[grant_encoded*13 +: 13];
m_ip_ttl_next = s_ip_ttl[grant_encoded*8 +: 8];
m_ip_protocol_next = s_ip_protocol[grant_encoded*8 +: 8];
m_ip_header_checksum_next = s_ip_header_checksum[grant_encoded*16 +: 16];
m_ip_source_ip_next = s_ip_source_ip[grant_encoded*32 +: 32];
m_ip_dest_ip_next = s_ip_dest_ip[grant_encoded*32 +: 32];
end
// pass through selected packet data
m_ip_payload_axis_tdata_int = current_s_tdata;
m_ip_payload_axis_tkeep_int = current_s_tkeep;
m_ip_payload_axis_tvalid_int = current_s_tvalid && m_ip_payload_axis_tready_int_reg && grant_valid;
m_ip_payload_axis_tlast_int = current_s_tlast;
m_ip_payload_axis_tid_int = current_s_tid;
m_ip_payload_axis_tdest_int = current_s_tdest;
m_ip_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
frame_reg <= frame_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
if (rst) begin
frame_reg <= 1'b0;
s_ip_hdr_ready_reg <= {S_COUNT{1'b0}};
m_ip_hdr_valid_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tkeep = KEEP_ENABLE ? m_ip_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tid = ID_ENABLE ? m_ip_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_ip_payload_axis_tdest = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_ip_payload_axis_tuser = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tid_reg <= temp_m_ip_payload_axis_tid_reg;
m_ip_payload_axis_tdest_reg <= temp_m_ip_payload_axis_tdest_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

463
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/ip_complete_64.v Executable file
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@@ -0,0 +1,463 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IPv4 and ARP block, ethernet frame interface (64 bit datapath)
*/
module ip_complete_64 #(
parameter ARP_CACHE_ADDR_WIDTH = 9,
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 156250000*2,
parameter ARP_REQUEST_TIMEOUT = 156250000*30
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status
*/
output wire rx_busy,
output wire tx_busy,
output wire rx_error_header_early_termination,
output wire rx_error_payload_early_termination,
output wire rx_error_invalid_header,
output wire rx_error_invalid_checksum,
output wire tx_error_payload_early_termination,
output wire tx_error_arp_failed,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_arp_cache
);
/*
This module integrates the IP and ARP modules for a complete IP stack
*/
wire arp_request_valid;
wire arp_request_ready;
wire [31:0] arp_request_ip;
wire arp_response_valid;
wire arp_response_ready;
wire arp_response_error;
wire [47:0] arp_response_mac;
wire ip_rx_eth_hdr_valid;
wire ip_rx_eth_hdr_ready;
wire [47:0] ip_rx_eth_dest_mac;
wire [47:0] ip_rx_eth_src_mac;
wire [15:0] ip_rx_eth_type;
wire [63:0] ip_rx_eth_payload_axis_tdata;
wire [7:0] ip_rx_eth_payload_axis_tkeep;
wire ip_rx_eth_payload_axis_tvalid;
wire ip_rx_eth_payload_axis_tready;
wire ip_rx_eth_payload_axis_tlast;
wire ip_rx_eth_payload_axis_tuser;
wire ip_tx_eth_hdr_valid;
wire ip_tx_eth_hdr_ready;
wire [47:0] ip_tx_eth_dest_mac;
wire [47:0] ip_tx_eth_src_mac;
wire [15:0] ip_tx_eth_type;
wire [63:0] ip_tx_eth_payload_axis_tdata;
wire [7:0] ip_tx_eth_payload_axis_tkeep;
wire ip_tx_eth_payload_axis_tvalid;
wire ip_tx_eth_payload_axis_tready;
wire ip_tx_eth_payload_axis_tlast;
wire ip_tx_eth_payload_axis_tuser;
wire arp_rx_eth_hdr_valid;
wire arp_rx_eth_hdr_ready;
wire [47:0] arp_rx_eth_dest_mac;
wire [47:0] arp_rx_eth_src_mac;
wire [15:0] arp_rx_eth_type;
wire [63:0] arp_rx_eth_payload_axis_tdata;
wire [7:0] arp_rx_eth_payload_axis_tkeep;
wire arp_rx_eth_payload_axis_tvalid;
wire arp_rx_eth_payload_axis_tready;
wire arp_rx_eth_payload_axis_tlast;
wire arp_rx_eth_payload_axis_tuser;
wire arp_tx_eth_hdr_valid;
wire arp_tx_eth_hdr_ready;
wire [47:0] arp_tx_eth_dest_mac;
wire [47:0] arp_tx_eth_src_mac;
wire [15:0] arp_tx_eth_type;
wire [63:0] arp_tx_eth_payload_axis_tdata;
wire [7:0] arp_tx_eth_payload_axis_tkeep;
wire arp_tx_eth_payload_axis_tvalid;
wire arp_tx_eth_payload_axis_tready;
wire arp_tx_eth_payload_axis_tlast;
wire arp_tx_eth_payload_axis_tuser;
/*
* Input classifier (eth_type)
*/
wire s_select_ip = (s_eth_type == 16'h0800);
wire s_select_arp = (s_eth_type == 16'h0806);
wire s_select_none = !(s_select_ip || s_select_arp);
reg s_select_ip_reg = 1'b0;
reg s_select_arp_reg = 1'b0;
reg s_select_none_reg = 1'b0;
always @(posedge clk) begin
if (rst) begin
s_select_ip_reg <= 1'b0;
s_select_arp_reg <= 1'b0;
s_select_none_reg <= 1'b0;
end else begin
if (s_eth_payload_axis_tvalid) begin
if ((!s_select_ip_reg && !s_select_arp_reg && !s_select_none_reg) ||
(s_eth_payload_axis_tvalid && s_eth_payload_axis_tready && s_eth_payload_axis_tlast)) begin
s_select_ip_reg <= s_select_ip;
s_select_arp_reg <= s_select_arp;
s_select_none_reg <= s_select_none;
end
end else begin
s_select_ip_reg <= 1'b0;
s_select_arp_reg <= 1'b0;
s_select_none_reg <= 1'b0;
end
end
end
assign ip_rx_eth_hdr_valid = s_select_ip && s_eth_hdr_valid;
assign ip_rx_eth_dest_mac = s_eth_dest_mac;
assign ip_rx_eth_src_mac = s_eth_src_mac;
assign ip_rx_eth_type = 16'h0800;
assign ip_rx_eth_payload_axis_tdata = s_eth_payload_axis_tdata;
assign ip_rx_eth_payload_axis_tkeep = s_eth_payload_axis_tkeep;
assign ip_rx_eth_payload_axis_tvalid = s_select_ip_reg && s_eth_payload_axis_tvalid;
assign ip_rx_eth_payload_axis_tlast = s_eth_payload_axis_tlast;
assign ip_rx_eth_payload_axis_tuser = s_eth_payload_axis_tuser;
assign arp_rx_eth_hdr_valid = s_select_arp && s_eth_hdr_valid;
assign arp_rx_eth_dest_mac = s_eth_dest_mac;
assign arp_rx_eth_src_mac = s_eth_src_mac;
assign arp_rx_eth_type = 16'h0806;
assign arp_rx_eth_payload_axis_tdata = s_eth_payload_axis_tdata;
assign arp_rx_eth_payload_axis_tkeep = s_eth_payload_axis_tkeep;
assign arp_rx_eth_payload_axis_tvalid = s_select_arp_reg && s_eth_payload_axis_tvalid;
assign arp_rx_eth_payload_axis_tlast = s_eth_payload_axis_tlast;
assign arp_rx_eth_payload_axis_tuser = s_eth_payload_axis_tuser;
assign s_eth_hdr_ready = (s_select_ip && ip_rx_eth_hdr_ready) ||
(s_select_arp && arp_rx_eth_hdr_ready) ||
(s_select_none);
assign s_eth_payload_axis_tready = (s_select_ip_reg && ip_rx_eth_payload_axis_tready) ||
(s_select_arp_reg && arp_rx_eth_payload_axis_tready) ||
s_select_none_reg;
/*
* Output arbiter
*/
eth_arb_mux #(
.S_COUNT(2),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.ARB_TYPE_ROUND_ROBIN(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
eth_arb_mux_inst (
.clk(clk),
.rst(rst),
// Ethernet frame inputs
.s_eth_hdr_valid({ip_tx_eth_hdr_valid, arp_tx_eth_hdr_valid}),
.s_eth_hdr_ready({ip_tx_eth_hdr_ready, arp_tx_eth_hdr_ready}),
.s_eth_dest_mac({ip_tx_eth_dest_mac, arp_tx_eth_dest_mac}),
.s_eth_src_mac({ip_tx_eth_src_mac, arp_tx_eth_src_mac}),
.s_eth_type({ip_tx_eth_type, arp_tx_eth_type}),
.s_eth_payload_axis_tdata({ip_tx_eth_payload_axis_tdata, arp_tx_eth_payload_axis_tdata}),
.s_eth_payload_axis_tkeep({ip_tx_eth_payload_axis_tkeep, arp_tx_eth_payload_axis_tkeep}),
.s_eth_payload_axis_tvalid({ip_tx_eth_payload_axis_tvalid, arp_tx_eth_payload_axis_tvalid}),
.s_eth_payload_axis_tready({ip_tx_eth_payload_axis_tready, arp_tx_eth_payload_axis_tready}),
.s_eth_payload_axis_tlast({ip_tx_eth_payload_axis_tlast, arp_tx_eth_payload_axis_tlast}),
.s_eth_payload_axis_tid(0),
.s_eth_payload_axis_tdest(0),
.s_eth_payload_axis_tuser({ip_tx_eth_payload_axis_tuser, arp_tx_eth_payload_axis_tuser}),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tid(),
.m_eth_payload_axis_tdest(),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser)
);
/*
* IP module
*/
ip_64
ip_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(ip_rx_eth_hdr_valid),
.s_eth_hdr_ready(ip_rx_eth_hdr_ready),
.s_eth_dest_mac(ip_rx_eth_dest_mac),
.s_eth_src_mac(ip_rx_eth_src_mac),
.s_eth_type(ip_rx_eth_type),
.s_eth_payload_axis_tdata(ip_rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(ip_rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(ip_rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(ip_rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(ip_rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(ip_rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(ip_tx_eth_hdr_valid),
.m_eth_hdr_ready(ip_tx_eth_hdr_ready),
.m_eth_dest_mac(ip_tx_eth_dest_mac),
.m_eth_src_mac(ip_tx_eth_src_mac),
.m_eth_type(ip_tx_eth_type),
.m_eth_payload_axis_tdata(ip_tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(ip_tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(ip_tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(ip_tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(ip_tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(ip_tx_eth_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_ip_eth_dest_mac(m_ip_eth_dest_mac),
.m_ip_eth_src_mac(m_ip_eth_src_mac),
.m_ip_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// ARP requests
.arp_request_valid(arp_request_valid),
.arp_request_ready(arp_request_ready),
.arp_request_ip(arp_request_ip),
.arp_response_valid(arp_response_valid),
.arp_response_ready(arp_response_ready),
.arp_response_error(arp_response_error),
.arp_response_mac(arp_response_mac),
// Status
.rx_busy(rx_busy),
.tx_busy(tx_busy),
.rx_error_header_early_termination(rx_error_header_early_termination),
.rx_error_payload_early_termination(rx_error_payload_early_termination),
.rx_error_invalid_header(rx_error_invalid_header),
.rx_error_invalid_checksum(rx_error_invalid_checksum),
.tx_error_payload_early_termination(tx_error_payload_early_termination),
.tx_error_arp_failed(tx_error_arp_failed),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip)
);
/*
* ARP module
*/
arp #(
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT)
)
arp_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(arp_rx_eth_hdr_valid),
.s_eth_hdr_ready(arp_rx_eth_hdr_ready),
.s_eth_dest_mac(arp_rx_eth_dest_mac),
.s_eth_src_mac(arp_rx_eth_src_mac),
.s_eth_type(arp_rx_eth_type),
.s_eth_payload_axis_tdata(arp_rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(arp_rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(arp_rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(arp_rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(arp_rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(arp_rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(arp_tx_eth_hdr_valid),
.m_eth_hdr_ready(arp_tx_eth_hdr_ready),
.m_eth_dest_mac(arp_tx_eth_dest_mac),
.m_eth_src_mac(arp_tx_eth_src_mac),
.m_eth_type(arp_tx_eth_type),
.m_eth_payload_axis_tdata(arp_tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(arp_tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(arp_tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(arp_tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(arp_tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(arp_tx_eth_payload_axis_tuser),
// ARP requests
.arp_request_valid(arp_request_valid),
.arp_request_ready(arp_request_ready),
.arp_request_ip(arp_request_ip),
.arp_response_valid(arp_response_valid),
.arp_response_ready(arp_response_ready),
.arp_response_error(arp_response_error),
.arp_response_mac(arp_response_mac),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_cache(clear_arp_cache)
);
endmodule
`resetall

690
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/ip_eth_rx_64.v Executable file
View File

@@ -0,0 +1,690 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IP ethernet frame receiver (Ethernet frame in, IP frame out, 64 bit datapath)
*/
module ip_eth_rx_64
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_payload_early_termination,
output wire error_invalid_header,
output wire error_invalid_checksum
);
/*
IP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
payload length octets
This module receives an Ethernet frame with header fields in parallel and
payload on an AXI stream interface, decodes and strips the IP header fields,
then produces the header fields in parallel along with the IP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg store_hdr_word_0;
reg store_hdr_word_1;
reg store_hdr_word_2;
reg store_last_word;
reg flush_save;
reg transfer_in_save;
reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [16:0] hdr_sum_high_reg = 17'd0;
reg [16:0] hdr_sum_low_reg = 17'd0;
reg [19:0] hdr_sum_temp;
reg [19:0] hdr_sum_reg = 20'd0, hdr_sum_next;
reg check_hdr_reg = 1'b0, check_hdr_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
reg error_invalid_header_reg = 1'b0, error_invalid_header_next;
reg error_invalid_checksum_reg = 1'b0, error_invalid_checksum_next;
reg [63:0] save_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] save_eth_payload_axis_tkeep_reg = 8'd0;
reg save_eth_payload_axis_tlast_reg = 1'b0;
reg save_eth_payload_axis_tuser_reg = 1'b0;
reg [63:0] shift_eth_payload_axis_tdata;
reg [7:0] shift_eth_payload_axis_tkeep;
reg shift_eth_payload_axis_tvalid;
reg shift_eth_payload_axis_tlast;
reg shift_eth_payload_axis_tuser;
reg shift_eth_payload_s_tready;
reg shift_eth_payload_extra_cycle_reg = 1'b0;
// internal datapath
reg [63:0] m_ip_payload_axis_tdata_int;
reg [7:0] m_ip_payload_axis_tkeep_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
assign error_invalid_header = error_invalid_header_reg;
assign error_invalid_checksum = error_invalid_checksum_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
shift_eth_payload_axis_tdata[31:0] = save_eth_payload_axis_tdata_reg[63:32];
shift_eth_payload_axis_tkeep[3:0] = save_eth_payload_axis_tkeep_reg[7:4];
if (shift_eth_payload_extra_cycle_reg) begin
shift_eth_payload_axis_tdata[63:32] = 32'd0;
shift_eth_payload_axis_tkeep[7:4] = 4'd0;
shift_eth_payload_axis_tvalid = 1'b1;
shift_eth_payload_axis_tlast = save_eth_payload_axis_tlast_reg;
shift_eth_payload_axis_tuser = save_eth_payload_axis_tuser_reg;
shift_eth_payload_s_tready = flush_save;
end else begin
shift_eth_payload_axis_tdata[63:32] = s_eth_payload_axis_tdata[31:0];
shift_eth_payload_axis_tkeep[7:4] = s_eth_payload_axis_tkeep[3:0];
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = (s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_axis_tuser = (s_eth_payload_axis_tuser && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_s_tready = !(s_eth_payload_axis_tlast && s_eth_payload_axis_tvalid && transfer_in_save);
end
end
always @* begin
state_next = STATE_IDLE;
flush_save = 1'b0;
transfer_in_save = 1'b0;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
store_hdr_word_0 = 1'b0;
store_hdr_word_1 = 1'b0;
store_hdr_word_2 = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
hdr_sum_temp = 32'd0;
hdr_sum_next = hdr_sum_reg;
check_hdr_next = check_hdr_reg;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_payload_axis_tdata_int = 64'd0;
m_ip_payload_axis_tkeep_int = 8'd0;
m_ip_payload_axis_tvalid_int = 1'b0;
m_ip_payload_axis_tlast_int = 1'b0;
m_ip_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
hdr_ptr_next = 6'd0;
hdr_sum_next = 32'd0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b1;
store_eth_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
word_count_next = m_ip_length_reg - 5*4;
if (s_eth_payload_axis_tvalid) begin
// word transfer in - store it
hdr_ptr_next = hdr_ptr_reg + 6'd8;
transfer_in_save = 1'b1;
state_next = STATE_READ_HEADER;
case (hdr_ptr_reg)
6'h00: begin
store_hdr_word_0 = 1'b1;
end
6'h08: begin
store_hdr_word_1 = 1'b1;
hdr_sum_next = hdr_sum_high_reg + hdr_sum_low_reg;
end
6'h10: begin
store_hdr_word_2 = 1'b1;
hdr_sum_next = hdr_sum_reg + hdr_sum_high_reg + hdr_sum_low_reg;
// check header checksum on next cycle for improved timing
check_hdr_next = 1'b1;
if (m_ip_version_reg != 4'd4 || m_ip_ihl_reg != 4'd5) begin
error_invalid_header_next = 1'b1;
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end else begin
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
state_next = STATE_READ_PAYLOAD;
end
end
endcase
if (shift_eth_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_hdr_valid_next = 1'b0;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = shift_eth_payload_axis_tdata;
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
store_last_word = 1'b1;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
transfer_in_save = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep & count2keep(word_count_reg);
if (shift_eth_payload_axis_tlast) begin
if (keep2count(shift_eth_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
end
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
m_ip_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
if (shift_eth_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
if (check_hdr_reg) begin
check_hdr_next = 1'b0;
hdr_sum_temp = hdr_sum_reg[15:0] + hdr_sum_reg[19:16] + hdr_sum_low_reg;
if (hdr_sum_temp != 19'h0ffff && hdr_sum_temp != 19'h1fffe) begin
// bad checksum
error_invalid_checksum_next = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b0;
if (shift_eth_payload_axis_tlast && shift_eth_payload_axis_tvalid) begin
// only one payload cycle; return to idle now
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
// drop payload
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end
end else begin
// good checksum; transfer header
m_ip_hdr_valid_next = 1'b1;
end
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = last_word_data_reg;
m_ip_payload_axis_tkeep_int = last_word_keep_reg;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
m_ip_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
if (shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 1'b0;
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
error_invalid_header_reg <= 1'b0;
error_invalid_checksum_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
error_invalid_header_reg <= error_invalid_header_next;
error_invalid_checksum_reg <= error_invalid_checksum_next;
busy_reg <= state_next != STATE_IDLE;
// datapath
if (flush_save) begin
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_eth_payload_axis_tlast_reg <= s_eth_payload_axis_tlast;
shift_eth_payload_extra_cycle_reg <= s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] != 0);
end
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
hdr_sum_reg <= hdr_sum_next;
check_hdr_reg <= check_hdr_next;
if (s_eth_payload_axis_tvalid) begin
hdr_sum_low_reg <= s_eth_payload_axis_tdata[15:0] + s_eth_payload_axis_tdata[31:16];
hdr_sum_high_reg <= s_eth_payload_axis_tdata[47:32] + s_eth_payload_axis_tdata[63:48];
end
// datapath
if (store_eth_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
end
if (store_last_word) begin
last_word_data_reg <= m_ip_payload_axis_tdata_int;
last_word_keep_reg <= m_ip_payload_axis_tkeep_int;
end
if (store_hdr_word_0) begin
{m_ip_version_reg, m_ip_ihl_reg} <= s_eth_payload_axis_tdata[ 7: 0];
{m_ip_dscp_reg, m_ip_ecn_reg} <= s_eth_payload_axis_tdata[15: 8];
m_ip_length_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_length_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_identification_reg[15: 8] <= s_eth_payload_axis_tdata[39:32];
m_ip_identification_reg[ 7: 0] <= s_eth_payload_axis_tdata[47:40];
{m_ip_flags_reg, m_ip_fragment_offset_reg[12:8]} <= s_eth_payload_axis_tdata[55:48];
m_ip_fragment_offset_reg[ 7:0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_1) begin
m_ip_ttl_reg <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_protocol_reg <= s_eth_payload_axis_tdata[15: 8];
m_ip_header_checksum_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_header_checksum_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_source_ip_reg[31:24] <= s_eth_payload_axis_tdata[39:32];
m_ip_source_ip_reg[23:16] <= s_eth_payload_axis_tdata[47:40];
m_ip_source_ip_reg[15: 8] <= s_eth_payload_axis_tdata[55:48];
m_ip_source_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_2) begin
m_ip_dest_ip_reg[31:24] <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_dest_ip_reg[23:16] <= s_eth_payload_axis_tdata[15: 8];
m_ip_dest_ip_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_dest_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
end
if (transfer_in_save) begin
save_eth_payload_axis_tdata_reg <= s_eth_payload_axis_tdata;
save_eth_payload_axis_tkeep_reg <= s_eth_payload_axis_tkeep;
save_eth_payload_axis_tuser_reg <= s_eth_payload_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_ip_payload_axis_tkeep_reg = 8'd0;
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg m_ip_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_ip_payload_axis_tkeep_reg = 8'd0;
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg temp_m_ip_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_ip_payload_int_to_output;
reg store_ip_payload_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tkeep = m_ip_payload_axis_tkeep_reg;
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_ip_payload_int_to_output = 1'b0;
store_ip_payload_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
// datapath
if (store_ip_payload_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_ip_payload_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

652
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/ip_eth_tx_64.v Executable file
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@@ -0,0 +1,652 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IP ethernet frame transmitter (IP frame in, Ethernet frame out, 64 bit datapath)
*/
module ip_eth_tx_64
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_payload_early_termination
);
/*
IP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
payload length octets
This module receives an IP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the Ethernet headers, and transmits the complete Ethernet payload on an AXI
interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_HEADER_LAST = 3'd2,
STATE_WRITE_PAYLOAD = 3'd3,
STATE_WRITE_PAYLOAD_LAST = 3'd4,
STATE_WAIT_LAST = 3'd5;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_last_word;
reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg flush_save;
reg transfer_in_save;
reg [19:0] hdr_sum_temp;
reg [19:0] hdr_sum_reg = 20'd0, hdr_sum_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg [5:0] ip_dscp_reg = 6'd0;
reg [1:0] ip_ecn_reg = 2'd0;
reg [15:0] ip_length_reg = 16'd0;
reg [15:0] ip_identification_reg = 16'd0;
reg [2:0] ip_flags_reg = 3'd0;
reg [12:0] ip_fragment_offset_reg = 13'd0;
reg [7:0] ip_ttl_reg = 8'd0;
reg [7:0] ip_protocol_reg = 8'd0;
reg [31:0] ip_source_ip_reg = 32'd0;
reg [31:0] ip_dest_ip_reg = 32'd0;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg busy_reg = 1'b0;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
reg [63:0] save_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] save_ip_payload_axis_tkeep_reg = 8'd0;
reg save_ip_payload_axis_tlast_reg = 1'b0;
reg save_ip_payload_axis_tuser_reg = 1'b0;
reg [63:0] shift_ip_payload_axis_tdata;
reg [7:0] shift_ip_payload_axis_tkeep;
reg shift_ip_payload_axis_tvalid;
reg shift_ip_payload_axis_tlast;
reg shift_ip_payload_axis_tuser;
reg shift_ip_payload_s_tready;
reg shift_ip_payload_extra_cycle_reg = 1'b0;
// internal datapath
reg [63:0] m_eth_payload_axis_tdata_int;
reg [7:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
shift_ip_payload_axis_tdata[31:0] = save_ip_payload_axis_tdata_reg[63:32];
shift_ip_payload_axis_tkeep[3:0] = save_ip_payload_axis_tkeep_reg[7:4];
if (shift_ip_payload_extra_cycle_reg) begin
shift_ip_payload_axis_tdata[63:32] = 32'd0;
shift_ip_payload_axis_tkeep[7:4] = 4'd0;
shift_ip_payload_axis_tvalid = 1'b1;
shift_ip_payload_axis_tlast = save_ip_payload_axis_tlast_reg;
shift_ip_payload_axis_tuser = save_ip_payload_axis_tuser_reg;
shift_ip_payload_s_tready = flush_save;
end else begin
shift_ip_payload_axis_tdata[63:32] = s_ip_payload_axis_tdata[31:0];
shift_ip_payload_axis_tkeep[7:4] = s_ip_payload_axis_tkeep[3:0];
shift_ip_payload_axis_tvalid = s_ip_payload_axis_tvalid;
shift_ip_payload_axis_tlast = (s_ip_payload_axis_tlast && (s_ip_payload_axis_tkeep[7:4] == 0));
shift_ip_payload_axis_tuser = (s_ip_payload_axis_tuser && (s_ip_payload_axis_tkeep[7:4] == 0));
shift_ip_payload_s_tready = !(s_ip_payload_axis_tlast && s_ip_payload_axis_tvalid && transfer_in_save) && !save_ip_payload_axis_tlast_reg;
end
end
always @* begin
state_next = STATE_IDLE;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
store_ip_hdr = 1'b0;
store_last_word = 1'b0;
flush_save = 1'b0;
transfer_in_save = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
hdr_sum_temp = 20'd0;
hdr_sum_next = hdr_sum_reg;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
error_payload_early_termination_next = 1'b0;
m_eth_payload_axis_tdata_int = 1'b0;
m_eth_payload_axis_tkeep_int = 1'b0;
m_eth_payload_axis_tvalid_int = 1'b0;
m_eth_payload_axis_tlast_int = 1'b0;
m_eth_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
hdr_ptr_next = 6'd0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
store_ip_hdr = 1'b1;
hdr_sum_next = {4'd4, 4'd5, s_ip_dscp, s_ip_ecn} +
s_ip_length +
s_ip_identification +
{s_ip_flags, s_ip_fragment_offset} +
{s_ip_ttl, s_ip_protocol} +
s_ip_source_ip[31:16] +
s_ip_source_ip[15: 0] +
s_ip_dest_ip[31:16] +
s_ip_dest_ip[15: 0];
s_ip_hdr_ready_next = 1'b0;
m_eth_hdr_valid_next = 1'b1;
if (m_eth_payload_axis_tready_int_reg) begin
m_eth_payload_axis_tvalid_int = 1'b1;
m_eth_payload_axis_tdata_int[ 7: 0] = {4'd4, 4'd5}; // ip_version, ip_ihl
m_eth_payload_axis_tdata_int[15: 8] = {s_ip_dscp, s_ip_ecn};
m_eth_payload_axis_tdata_int[23:16] = s_ip_length[15: 8];
m_eth_payload_axis_tdata_int[31:24] = s_ip_length[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = s_ip_identification[15: 8];
m_eth_payload_axis_tdata_int[47:40] = s_ip_identification[ 7: 0];
m_eth_payload_axis_tdata_int[55:48] = {s_ip_flags, s_ip_fragment_offset[12: 8]};
m_eth_payload_axis_tdata_int[63:56] = s_ip_fragment_offset[ 7: 0];
m_eth_payload_axis_tkeep_int = 8'hff;
hdr_ptr_next = 6'd8;
end
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// write header
word_count_next = ip_length_reg - 5*4 + 4;
if (m_eth_payload_axis_tready_int_reg) begin
hdr_ptr_next = hdr_ptr_reg + 6'd8;
m_eth_payload_axis_tvalid_int = 1'b1;
state_next = STATE_WRITE_HEADER;
case (hdr_ptr_reg)
6'h00: begin
m_eth_payload_axis_tdata_int[ 7: 0] = {4'd4, 4'd5}; // ip_version, ip_ihl
m_eth_payload_axis_tdata_int[15: 8] = {ip_dscp_reg, ip_ecn_reg};
m_eth_payload_axis_tdata_int[23:16] = ip_length_reg[15: 8];
m_eth_payload_axis_tdata_int[31:24] = ip_length_reg[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = ip_identification_reg[15: 8];
m_eth_payload_axis_tdata_int[47:40] = ip_identification_reg[ 7: 0];
m_eth_payload_axis_tdata_int[55:48] = {ip_flags_reg, ip_fragment_offset_reg[12: 8]};
m_eth_payload_axis_tdata_int[63:56] = ip_fragment_offset_reg[ 7: 0];
m_eth_payload_axis_tkeep_int = 8'hff;
end
6'h08: begin
hdr_sum_temp = hdr_sum_reg[15:0] + hdr_sum_reg[19:16];
hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[16];
m_eth_payload_axis_tdata_int[ 7: 0] = ip_ttl_reg;
m_eth_payload_axis_tdata_int[15: 8] = ip_protocol_reg;
m_eth_payload_axis_tdata_int[23:16] = ~hdr_sum_temp[15: 8];
m_eth_payload_axis_tdata_int[31:24] = ~hdr_sum_temp[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = ip_source_ip_reg[31:24];
m_eth_payload_axis_tdata_int[47:40] = ip_source_ip_reg[23:16];
m_eth_payload_axis_tdata_int[55:48] = ip_source_ip_reg[15: 8];
m_eth_payload_axis_tdata_int[63:56] = ip_source_ip_reg[ 7: 0];
m_eth_payload_axis_tkeep_int = 8'hff;
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early;
state_next = STATE_WRITE_HEADER_LAST;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_HEADER_LAST: begin
// last header word requires first payload word; process accordingly
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_ip_payload_s_tready;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
m_eth_payload_axis_tvalid_int = 1'b1;
transfer_in_save = 1'b1;
m_eth_payload_axis_tdata_int[ 7: 0] = ip_dest_ip_reg[31:24];
m_eth_payload_axis_tdata_int[15: 8] = ip_dest_ip_reg[23:16];
m_eth_payload_axis_tdata_int[23:16] = ip_dest_ip_reg[15: 8];
m_eth_payload_axis_tdata_int[31:24] = ip_dest_ip_reg[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = shift_ip_payload_axis_tdata[39:32];
m_eth_payload_axis_tdata_int[47:40] = shift_ip_payload_axis_tdata[47:40];
m_eth_payload_axis_tdata_int[55:48] = shift_ip_payload_axis_tdata[55:48];
m_eth_payload_axis_tdata_int[63:56] = shift_ip_payload_axis_tdata[63:56];
m_eth_payload_axis_tkeep_int = {shift_ip_payload_axis_tkeep[7:4], 4'hF};
m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser;
word_count_next = word_count_reg - 16'd8;
if (keep2count(m_eth_payload_axis_tkeep_int) >= word_count_reg) begin
// have entire payload
m_eth_payload_axis_tkeep_int = count2keep(word_count_reg);
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
store_last_word = 1'b1;
s_ip_payload_axis_tready_next = shift_ip_payload_s_tready;
m_eth_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
if (shift_ip_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
s_ip_payload_axis_tready_next = shift_ip_payload_s_tready;
m_eth_payload_axis_tuser_int = 1'b1;
state_next = STATE_WAIT_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_HEADER_LAST;
end
end
STATE_WRITE_PAYLOAD: begin
// write payload
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_ip_payload_s_tready;
m_eth_payload_axis_tdata_int = shift_ip_payload_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_ip_payload_axis_tkeep;
m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser;
store_last_word = 1'b1;
if (m_eth_payload_axis_tready_int_reg && shift_ip_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
transfer_in_save = 1'b1;
m_eth_payload_axis_tvalid_int = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_eth_payload_axis_tkeep_int = count2keep(word_count_reg);
if (shift_ip_payload_axis_tlast) begin
if (keep2count(shift_ip_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_eth_payload_axis_tuser_int = 1'b1;
end
s_ip_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
m_eth_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
if (shift_ip_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_eth_payload_axis_tuser_int = 1'b1;
s_ip_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_ip_payload_s_tready;
m_eth_payload_axis_tdata_int = last_word_data_reg;
m_eth_payload_axis_tkeep_int = last_word_keep_reg;
m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser;
if (m_eth_payload_axis_tready_int_reg && shift_ip_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
m_eth_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = shift_ip_payload_s_tready;
if (shift_ip_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 1'b0;
save_ip_payload_axis_tlast_reg <= 1'b0;
shift_ip_payload_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
error_payload_early_termination_reg <= error_payload_early_termination_next;
if (flush_save) begin
save_ip_payload_axis_tlast_reg <= 1'b0;
shift_ip_payload_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_ip_payload_axis_tlast_reg <= s_ip_payload_axis_tlast;
shift_ip_payload_extra_cycle_reg <= s_ip_payload_axis_tlast && (s_ip_payload_axis_tkeep[7:4] != 0);
end
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
hdr_sum_reg <= hdr_sum_next;
// datapath
if (store_ip_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
ip_dscp_reg <= s_ip_dscp;
ip_ecn_reg <= s_ip_ecn;
ip_length_reg <= s_ip_length;
ip_identification_reg <= s_ip_identification;
ip_flags_reg <= s_ip_flags;
ip_fragment_offset_reg <= s_ip_fragment_offset;
ip_ttl_reg <= s_ip_ttl;
ip_protocol_reg <= s_ip_protocol;
ip_source_ip_reg <= s_ip_source_ip;
ip_dest_ip_reg <= s_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= m_eth_payload_axis_tdata_int;
last_word_keep_reg <= m_eth_payload_axis_tkeep_int;
end
if (transfer_in_save) begin
save_ip_payload_axis_tdata_reg <= s_ip_payload_axis_tdata;
save_ip_payload_axis_tkeep_reg <= s_ip_payload_axis_tkeep;
save_ip_payload_axis_tuser_reg <= s_ip_payload_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_eth_payload_axis_tkeep_reg = 8'd0;
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready | !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
// datapath
if (store_eth_payload_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/lfsr.v Executable file
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/*
Copyright (c) 2016-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Parametrizable combinatorial parallel LFSR/CRC
*/
module lfsr #
(
// width of LFSR
parameter LFSR_WIDTH = 31,
// LFSR polynomial
parameter LFSR_POLY = 31'h10000001,
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// LFSR feed forward enable
parameter LFSR_FEED_FORWARD = 0,
// bit-reverse input and output
parameter REVERSE = 0,
// width of data input
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire [DATA_WIDTH-1:0] data_in,
input wire [LFSR_WIDTH-1:0] state_in,
output wire [DATA_WIDTH-1:0] data_out,
output wire [LFSR_WIDTH-1:0] state_out
);
/*
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR
next state computation, shifting DATA_WIDTH bits per pass through the module. Input data
is XORed with LFSR feedback path, tie data_in to zero if this is not required.
Works in two parts: statically computes a set of bit masks, then uses these bit masks to
select bits for XORing to compute the next state.
Ports:
data_in
Data bits to be shifted through the LFSR (DATA_WIDTH bits)
state_in
LFSR/CRC current state input (LFSR_WIDTH bits)
data_out
Data bits shifted out of LFSR (DATA_WIDTH bits)
state_out
LFSR/CRC next state output (LFSR_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
LFSR_FEED_FORWARD
Generate feed forward instead of feed back LFSR. Enable this for PRBS checking and self-
synchronous descrambling.
Fibonacci feed-forward style (example for 64b66b descrambler, 0x8000000001)
DIN (LSB first)
|
| .----. .----. .----. .----. .----. .----.
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--.
| '----' '----' '----' | '----' '----' '----' |
| V |
(+)<---------------------------(+)------------------------------'
|
V
DOUT
Galois feed-forward style
,-------------------+-------------------------+------------+--- DIN (MSB first)
| | | |
| .----. .----. V .----. .----. V .----. V
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |->(+)-> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
DATA_WIDTH
Specify width of input and output data bus. The module will perform one shift per input
data bit, so if the input data bus is not required tie data_in to zero and set DATA_WIDTH
to the required number of shifts per clock cycle.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
CRC16-CCITT Galois 16 16'h1021 16'h1d0f
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
CRC32C Galois, bit-reverse 32 32'h1edc6f41 32'hffffffff iSCSI, Intel CRC32 instruction; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
function [LFSR_WIDTH+DATA_WIDTH-1:0] lfsr_mask(input [31:0] index);
reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] state_val;
reg [DATA_WIDTH-1:0] data_val;
reg [DATA_WIDTH-1:0] data_mask;
integer i, j;
begin
// init bit masks
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
lfsr_mask_state[i] = 0;
lfsr_mask_state[i][i] = 1'b1;
lfsr_mask_data[i] = 0;
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
output_mask_state[i] = 0;
if (i < LFSR_WIDTH) begin
output_mask_state[i][i] = 1'b1;
end
output_mask_data[i] = 0;
end
// simulate shift register
if (LFSR_CONFIG == "FIBONACCI") begin
// Fibonacci configuration
for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ data_mask;
// add XOR inputs from correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if ((LFSR_POLY >> j) & 1) begin
state_val = lfsr_mask_state[j-1] ^ state_val;
data_val = lfsr_mask_data[j-1] ^ data_val;
end
end
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = data_mask;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
end
end else if (LFSR_CONFIG == "GALOIS") begin
// Galois configuration
for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ data_mask;
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = data_mask;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
// add XOR inputs at correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if ((LFSR_POLY >> j) & 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
end
end
end
end else begin
$error("Error: unknown configuration setting!");
$finish;
end
// reverse bits if selected
if (REVERSE) begin
if (index < LFSR_WIDTH) begin
state_val = 0;
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val[i] = lfsr_mask_state[LFSR_WIDTH-index-1][LFSR_WIDTH-i-1];
end
data_val = 0;
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_val[i] = lfsr_mask_data[LFSR_WIDTH-index-1][DATA_WIDTH-i-1];
end
end else begin
state_val = 0;
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val[i] = output_mask_state[DATA_WIDTH-(index-LFSR_WIDTH)-1][LFSR_WIDTH-i-1];
end
data_val = 0;
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_val[i] = output_mask_data[DATA_WIDTH-(index-LFSR_WIDTH)-1][DATA_WIDTH-i-1];
end
end
end else begin
if (index < LFSR_WIDTH) begin
state_val = lfsr_mask_state[index];
data_val = lfsr_mask_data[index];
end else begin
state_val = output_mask_state[index-LFSR_WIDTH];
data_val = output_mask_data[index-LFSR_WIDTH];
end
end
lfsr_mask = {data_val, state_val};
end
endfunction
// synthesis translate_off
`define SIMULATION
// synthesis translate_on
`ifdef SIMULATION
// "AUTO" style is "REDUCTION" for faster simulation
parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else
// "AUTO" style is "LOOP" for better synthesis result
parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif
genvar n;
generate
if (STYLE_INT == "REDUCTION") begin
// use Verilog reduction operator
// fast in iverilog
// significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer)
// slightly smaller than generated code with Quartus
// --> better for simulation
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state
wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n);
assign state_out[n] = ^({data_in, state_in} & mask);
end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data
wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH);
assign data_out[n] = ^({data_in, state_in} & mask);
end
end else if (STYLE_INT == "LOOP") begin
// use nested loops
// very slow in iverilog
// slightly smaller than generated code with ISE
// same size as generated code with Quartus
// --> better for synthesis
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state
wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n);
reg state_reg;
assign state_out[n] = state_reg;
integer i;
always @* begin
state_reg = 1'b0;
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
if (mask[i]) begin
state_reg = state_reg ^ state_in[i];
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
if (mask[i+LFSR_WIDTH]) begin
state_reg = state_reg ^ data_in[i];
end
end
end
end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data
wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH);
reg data_reg;
assign data_out[n] = data_reg;
integer i;
always @* begin
data_reg = 1'b0;
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
if (mask[i]) begin
data_reg = data_reg ^ state_in[i];
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
if (mask[i+LFSR_WIDTH]) begin
data_reg = data_reg ^ data_in[i];
end
end
end
end
end else begin
initial begin
$error("Error: unknown style setting!");
$finish;
end
end
endgenerate
endmodule
`resetall

448
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/mac_ctrl_rx.v Executable file
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@@ -0,0 +1,448 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* MAC control receive
*/
module mac_ctrl_rx #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = DATA_WIDTH>8,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter USE_READY = 0,
parameter MCF_PARAMS_SIZE = 18
)
(
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI stream output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* MAC control frame interface
*/
output wire mcf_valid,
output wire [47:0] mcf_eth_dst,
output wire [47:0] mcf_eth_src,
output wire [15:0] mcf_eth_type,
output wire [15:0] mcf_opcode,
output wire [MCF_PARAMS_SIZE*8-1:0] mcf_params,
output wire [ID_WIDTH-1:0] mcf_id,
output wire [DEST_WIDTH-1:0] mcf_dest,
output wire [USER_WIDTH-1:0] mcf_user,
/*
* Configuration
*/
input wire [47:0] cfg_mcf_rx_eth_dst_mcast,
input wire cfg_mcf_rx_check_eth_dst_mcast,
input wire [47:0] cfg_mcf_rx_eth_dst_ucast,
input wire cfg_mcf_rx_check_eth_dst_ucast,
input wire [47:0] cfg_mcf_rx_eth_src,
input wire cfg_mcf_rx_check_eth_src,
input wire [15:0] cfg_mcf_rx_eth_type,
input wire [15:0] cfg_mcf_rx_opcode_lfc,
input wire cfg_mcf_rx_check_opcode_lfc,
input wire [15:0] cfg_mcf_rx_opcode_pfc,
input wire cfg_mcf_rx_check_opcode_pfc,
input wire cfg_mcf_rx_forward,
input wire cfg_mcf_rx_enable,
/*
* Status
*/
output wire stat_rx_mcf
);
parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
parameter HDR_SIZE = 60;
parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = HDR_SIZE % BYTE_LANES;
// check configuration
initial begin
if (BYTE_LANES * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (MCF_PARAMS_SIZE > 44) begin
$error("Error: Maximum MCF_PARAMS_SIZE is 44 bytes (instance %m)");
$finish;
end
end
/*
MAC control frame
Field Length
Destination MAC address 6 octets [01:80:C2:00:00:01]
Source MAC address 6 octets
Ethertype 2 octets [0x8808]
Opcode 2 octets
Parameters 0-44 octets
This module manages the reception of MAC control frames. Incoming frames are
checked based on the ethertype and (optionally) MAC addresses. Matching control
frames are marked by setting tuser[0] on the data output and forwarded through
a separate interface for processing.
*/
reg read_mcf_reg = 1'b1, read_mcf_next;
reg mcf_frame_reg = 1'b0, mcf_frame_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
reg mcf_valid_reg = 0, mcf_valid_next;
reg [47:0] mcf_eth_dst_reg = 0, mcf_eth_dst_next;
reg [47:0] mcf_eth_src_reg = 0, mcf_eth_src_next;
reg [15:0] mcf_eth_type_reg = 0, mcf_eth_type_next;
reg [15:0] mcf_opcode_reg = 0, mcf_opcode_next;
reg [MCF_PARAMS_SIZE*8-1:0] mcf_params_reg = 0, mcf_params_next;
reg [ID_WIDTH-1:0] mcf_id_reg = 0, mcf_id_next;
reg [DEST_WIDTH-1:0] mcf_dest_reg = 0, mcf_dest_next;
reg [USER_WIDTH-1:0] mcf_user_reg = 0, mcf_user_next;
reg stat_rx_mcf_reg = 1'b0, stat_rx_mcf_next;
assign s_axis_tready = s_axis_tready_reg;
assign mcf_valid = mcf_valid_reg;
assign mcf_eth_dst = mcf_eth_dst_reg;
assign mcf_eth_src = mcf_eth_src_reg;
assign mcf_eth_type = mcf_eth_type_reg;
assign mcf_opcode = mcf_opcode_reg;
assign mcf_params = mcf_params_reg;
assign mcf_id = mcf_id_reg;
assign mcf_dest = mcf_dest_reg;
assign mcf_user = mcf_user_reg;
assign stat_rx_mcf = stat_rx_mcf_reg;
wire mcf_eth_dst_mcast_match = mcf_eth_dst_next == cfg_mcf_rx_eth_dst_mcast;
wire mcf_eth_dst_ucast_match = mcf_eth_dst_next == cfg_mcf_rx_eth_dst_ucast;
wire mcf_eth_src_match = mcf_eth_src_next == cfg_mcf_rx_eth_src;
wire mcf_eth_type_match = mcf_eth_type_next == cfg_mcf_rx_eth_type;
wire mcf_opcode_lfc_match = mcf_opcode_next == cfg_mcf_rx_opcode_lfc;
wire mcf_opcode_pfc_match = mcf_opcode_next == cfg_mcf_rx_opcode_pfc;
wire mcf_eth_dst_match = ((mcf_eth_dst_mcast_match && cfg_mcf_rx_check_eth_dst_mcast) ||
(mcf_eth_dst_ucast_match && cfg_mcf_rx_check_eth_dst_ucast) ||
(!cfg_mcf_rx_check_eth_dst_mcast && !cfg_mcf_rx_check_eth_dst_ucast));
wire mcf_opcode_match = ((mcf_opcode_lfc_match && cfg_mcf_rx_check_opcode_lfc) ||
(mcf_opcode_pfc_match && cfg_mcf_rx_check_opcode_pfc) ||
(!cfg_mcf_rx_check_opcode_lfc && !cfg_mcf_rx_check_opcode_pfc));
wire mcf_match = (mcf_eth_dst_match &&
(mcf_eth_src_match || !cfg_mcf_rx_check_eth_src) &&
mcf_eth_type_match && mcf_opcode_match);
integer k;
always @* begin
read_mcf_next = read_mcf_reg;
mcf_frame_next = mcf_frame_reg;
ptr_next = ptr_reg;
// pass through data
m_axis_tdata_int = s_axis_tdata;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = s_axis_tvalid;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
s_axis_tready_next = m_axis_tready_int_early || !USE_READY;
mcf_valid_next = 1'b0;
mcf_eth_dst_next = mcf_eth_dst_reg;
mcf_eth_src_next = mcf_eth_src_reg;
mcf_eth_type_next = mcf_eth_type_reg;
mcf_opcode_next = mcf_opcode_reg;
mcf_params_next = mcf_params_reg;
mcf_id_next = mcf_id_reg;
mcf_dest_next = mcf_dest_reg;
mcf_user_next = mcf_user_reg;
stat_rx_mcf_next = 1'b0;
if ((s_axis_tready || !USE_READY) && s_axis_tvalid) begin
if (read_mcf_reg) begin
ptr_next = ptr_reg + 1;
mcf_id_next = s_axis_tid;
mcf_dest_next = s_axis_tdest;
mcf_user_next = s_axis_tuser;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/BYTE_LANES) begin \
field = s_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \
end
`_HEADER_FIELD_(0, mcf_eth_dst_next[5*8 +: 8])
`_HEADER_FIELD_(1, mcf_eth_dst_next[4*8 +: 8])
`_HEADER_FIELD_(2, mcf_eth_dst_next[3*8 +: 8])
`_HEADER_FIELD_(3, mcf_eth_dst_next[2*8 +: 8])
`_HEADER_FIELD_(4, mcf_eth_dst_next[1*8 +: 8])
`_HEADER_FIELD_(5, mcf_eth_dst_next[0*8 +: 8])
`_HEADER_FIELD_(6, mcf_eth_src_next[5*8 +: 8])
`_HEADER_FIELD_(7, mcf_eth_src_next[4*8 +: 8])
`_HEADER_FIELD_(8, mcf_eth_src_next[3*8 +: 8])
`_HEADER_FIELD_(9, mcf_eth_src_next[2*8 +: 8])
`_HEADER_FIELD_(10, mcf_eth_src_next[1*8 +: 8])
`_HEADER_FIELD_(11, mcf_eth_src_next[0*8 +: 8])
`_HEADER_FIELD_(12, mcf_eth_type_next[1*8 +: 8])
`_HEADER_FIELD_(13, mcf_eth_type_next[0*8 +: 8])
`_HEADER_FIELD_(14, mcf_opcode_next[1*8 +: 8])
`_HEADER_FIELD_(15, mcf_opcode_next[0*8 +: 8])
if (ptr_reg == 0/BYTE_LANES) begin
// ensure params field gets cleared
mcf_params_next = 0;
end
for (k = 0; k < MCF_PARAMS_SIZE; k = k + 1) begin
if (ptr_reg == (16+k)/BYTE_LANES) begin
mcf_params_next[k*8 +: 8] = s_axis_tdata[((16+k)%BYTE_LANES)*8 +: 8];
end
end
if (ptr_reg == 15/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[13%BYTE_LANES])) begin
// record match at end of opcode field
mcf_frame_next = mcf_match && cfg_mcf_rx_enable;
end
if (ptr_reg == (HDR_SIZE-1)/BYTE_LANES) begin
read_mcf_next = 1'b0;
end
`undef _HEADER_FIELD_
end
if (s_axis_tlast) begin
if (s_axis_tuser[0]) begin
// frame marked invalid
end else if (mcf_frame_next) begin
if (!cfg_mcf_rx_forward) begin
// mark frame invalid
m_axis_tuser_int[0] = 1'b1;
end
// transfer out MAC control frame
mcf_valid_next = 1'b1;
stat_rx_mcf_next = 1'b1;
end
read_mcf_next = 1'b1;
mcf_frame_next = 1'b0;
ptr_next = 0;
end
end
end
always @(posedge clk) begin
read_mcf_reg <= read_mcf_next;
mcf_frame_reg <= mcf_frame_next;
ptr_reg <= ptr_next;
s_axis_tready_reg <= s_axis_tready_next;
mcf_valid_reg <= mcf_valid_next;
mcf_eth_dst_reg <= mcf_eth_dst_next;
mcf_eth_src_reg <= mcf_eth_src_next;
mcf_eth_type_reg <= mcf_eth_type_next;
mcf_opcode_reg <= mcf_opcode_next;
mcf_params_reg <= mcf_params_next;
mcf_id_reg <= mcf_id_next;
mcf_dest_reg <= mcf_dest_next;
mcf_user_reg <= mcf_user_next;
stat_rx_mcf_reg <= stat_rx_mcf_next;
if (rst) begin
read_mcf_reg <= 1'b1;
mcf_frame_reg <= 1'b0;
ptr_reg <= 0;
s_axis_tready_reg <= 1'b0;
mcf_valid_reg <= 1'b0;
stat_rx_mcf_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || !USE_READY || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !USE_READY || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready || !USE_READY) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

421
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/mac_ctrl_tx.v Executable file
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@@ -0,0 +1,421 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* MAC control transmit
*/
module mac_ctrl_tx #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = DATA_WIDTH>8,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter MCF_PARAMS_SIZE = 18
)
(
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI stream output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* MAC control frame interface
*/
input wire mcf_valid,
output wire mcf_ready,
input wire [47:0] mcf_eth_dst,
input wire [47:0] mcf_eth_src,
input wire [15:0] mcf_eth_type,
input wire [15:0] mcf_opcode,
input wire [MCF_PARAMS_SIZE*8-1:0] mcf_params,
input wire [ID_WIDTH-1:0] mcf_id,
input wire [DEST_WIDTH-1:0] mcf_dest,
input wire [USER_WIDTH-1:0] mcf_user,
/*
* Pause interface
*/
input wire tx_pause_req,
output wire tx_pause_ack,
/*
* Status
*/
output wire stat_tx_mcf
);
parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
parameter HDR_SIZE = 60;
parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = HDR_SIZE % BYTE_LANES;
// check configuration
initial begin
if (BYTE_LANES * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (MCF_PARAMS_SIZE > 44) begin
$error("Error: Maximum MCF_PARAMS_SIZE is 44 bytes (instance %m)");
$finish;
end
end
/*
MAC control frame
Field Length
Destination MAC address 6 octets [01:80:C2:00:00:01]
Source MAC address 6 octets
Ethertype 2 octets [0x8808]
Opcode 2 octets
Parameters 0-44 octets
This module manages the transmission of MAC control frames. Control frames
are accepted in parallel, serialized, and merged at a higher priority with
data traffic.
*/
reg send_data_reg = 1'b0, send_data_next;
reg send_mcf_reg = 1'b0, send_mcf_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg mcf_ready_reg = 1'b0, mcf_ready_next;
reg tx_pause_ack_reg = 1'b0, tx_pause_ack_next;
reg stat_tx_mcf_reg = 1'b0, stat_tx_mcf_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign mcf_ready = mcf_ready_reg;
assign tx_pause_ack = tx_pause_ack_reg;
assign stat_tx_mcf = stat_tx_mcf_reg;
integer k;
always @* begin
send_data_next = send_data_reg;
send_mcf_next = send_mcf_reg;
ptr_next = ptr_reg;
s_axis_tready_next = 1'b0;
mcf_ready_next = 1'b0;
tx_pause_ack_next = tx_pause_ack_reg;
stat_tx_mcf_next = 1'b0;
m_axis_tdata_int = 0;
m_axis_tkeep_int = 0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tid_int = 0;
m_axis_tdest_int = 0;
m_axis_tuser_int = 0;
if (!send_data_reg && !send_mcf_reg) begin
m_axis_tdata_int = s_axis_tdata;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req;
tx_pause_ack_next = tx_pause_req;
if (s_axis_tvalid && s_axis_tready) begin
s_axis_tready_next = m_axis_tready_int_early;
tx_pause_ack_next = 1'b0;
m_axis_tvalid_int = 1'b1;
if (s_axis_tlast) begin
s_axis_tready_next = m_axis_tready_int_early && !mcf_valid && !mcf_ready;
send_data_next = 1'b0;
end else begin
send_data_next = 1'b1;
end
end else if (mcf_valid) begin
s_axis_tready_next = 1'b0;
ptr_next = 0;
send_mcf_next = 1'b1;
mcf_ready_next = (CYCLE_COUNT == 1) && m_axis_tready_int_early;
end
end
if (send_data_reg) begin
m_axis_tdata_int = s_axis_tdata;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis_tvalid && s_axis_tready) begin
m_axis_tvalid_int = 1'b1;
if (s_axis_tlast) begin
s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req;
send_data_next = 1'b0;
if (mcf_valid) begin
s_axis_tready_next = 1'b0;
ptr_next = 0;
send_mcf_next = 1'b1;
mcf_ready_next = (CYCLE_COUNT == 1) && m_axis_tready_int_early;
end
end else begin
send_data_next = 1'b1;
end
end
end
if (send_mcf_reg) begin
mcf_ready_next = (CYCLE_COUNT == 1 || ptr_reg == CYCLE_COUNT-1) && m_axis_tready_int_early;
if (m_axis_tready_int_reg) begin
ptr_next = ptr_reg + 1;
m_axis_tvalid_int = 1'b1;
m_axis_tid_int = mcf_id;
m_axis_tdest_int = mcf_dest;
m_axis_tuser_int = mcf_user;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/BYTE_LANES) begin \
m_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \
m_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \
end
`_HEADER_FIELD_(0, mcf_eth_dst[5*8 +: 8])
`_HEADER_FIELD_(1, mcf_eth_dst[4*8 +: 8])
`_HEADER_FIELD_(2, mcf_eth_dst[3*8 +: 8])
`_HEADER_FIELD_(3, mcf_eth_dst[2*8 +: 8])
`_HEADER_FIELD_(4, mcf_eth_dst[1*8 +: 8])
`_HEADER_FIELD_(5, mcf_eth_dst[0*8 +: 8])
`_HEADER_FIELD_(6, mcf_eth_src[5*8 +: 8])
`_HEADER_FIELD_(7, mcf_eth_src[4*8 +: 8])
`_HEADER_FIELD_(8, mcf_eth_src[3*8 +: 8])
`_HEADER_FIELD_(9, mcf_eth_src[2*8 +: 8])
`_HEADER_FIELD_(10, mcf_eth_src[1*8 +: 8])
`_HEADER_FIELD_(11, mcf_eth_src[0*8 +: 8])
`_HEADER_FIELD_(12, mcf_eth_type[1*8 +: 8])
`_HEADER_FIELD_(13, mcf_eth_type[0*8 +: 8])
`_HEADER_FIELD_(14, mcf_opcode[1*8 +: 8])
`_HEADER_FIELD_(15, mcf_opcode[0*8 +: 8])
for (k = 0; k < HDR_SIZE-16; k = k + 1) begin
if (ptr_reg == (16+k)/BYTE_LANES) begin
if (k < MCF_PARAMS_SIZE) begin
m_axis_tdata_int[((16+k)%BYTE_LANES)*8 +: 8] = mcf_params[k*8 +: 8];
end else begin
m_axis_tdata_int[((16+k)%BYTE_LANES)*8 +: 8] = 0;
end
m_axis_tkeep_int[(16+k)%BYTE_LANES] = 1'b1;
end
end
if (ptr_reg == (HDR_SIZE-1)/BYTE_LANES) begin
s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req;
mcf_ready_next = 1'b0;
m_axis_tlast_int = 1'b1;
send_mcf_next = 1'b0;
stat_tx_mcf_next = 1'b1;
end else begin
mcf_ready_next = (ptr_next == CYCLE_COUNT-1) && m_axis_tready_int_early;
end
`undef _HEADER_FIELD_
end
end
end
always @(posedge clk) begin
send_data_reg <= send_data_next;
send_mcf_reg <= send_mcf_next;
ptr_reg <= ptr_next;
s_axis_tready_reg <= s_axis_tready_next;
mcf_ready_reg <= mcf_ready_next;
tx_pause_ack_reg <= tx_pause_ack_next;
stat_tx_mcf_reg <= stat_tx_mcf_next;
if (rst) begin
send_data_reg <= 1'b0;
send_mcf_reg <= 1'b0;
ptr_reg <= 0;
s_axis_tready_reg <= 1'b0;
mcf_ready_reg <= 1'b0;
tx_pause_ack_reg <= 1'b0;
stat_tx_mcf_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

221
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/mac_pause_ctrl_rx.v Executable file
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@@ -0,0 +1,221 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* PFC and pause frame receive handling
*/
module mac_pause_ctrl_rx #
(
parameter MCF_PARAMS_SIZE = 18,
parameter PFC_ENABLE = 1
)
(
input wire clk,
input wire rst,
/*
* MAC control frame interface
*/
input wire mcf_valid,
input wire [47:0] mcf_eth_dst,
input wire [47:0] mcf_eth_src,
input wire [15:0] mcf_eth_type,
input wire [15:0] mcf_opcode,
input wire [MCF_PARAMS_SIZE*8-1:0] mcf_params,
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
input wire rx_lfc_en,
output wire rx_lfc_req,
input wire rx_lfc_ack,
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
input wire [7:0] rx_pfc_en,
output wire [7:0] rx_pfc_req,
input wire [7:0] rx_pfc_ack,
/*
* Configuration
*/
input wire [15:0] cfg_rx_lfc_opcode,
input wire cfg_rx_lfc_en,
input wire [15:0] cfg_rx_pfc_opcode,
input wire cfg_rx_pfc_en,
input wire [9:0] cfg_quanta_step,
input wire cfg_quanta_clk_en,
/*
* Status
*/
output wire stat_rx_lfc_pkt,
output wire stat_rx_lfc_xon,
output wire stat_rx_lfc_xoff,
output wire stat_rx_lfc_paused,
output wire stat_rx_pfc_pkt,
output wire [7:0] stat_rx_pfc_xon,
output wire [7:0] stat_rx_pfc_xoff,
output wire [7:0] stat_rx_pfc_paused
);
localparam QFB = 8;
// check configuration
initial begin
if (MCF_PARAMS_SIZE < (PFC_ENABLE ? 18 : 2)) begin
$error("Error: MCF_PARAMS_SIZE too small for requested configuration (instance %m)");
$finish;
end
end
reg lfc_req_reg = 1'b0, lfc_req_next;
reg [7:0] pfc_req_reg = 8'd0, pfc_req_next;
reg [16+QFB-1:0] lfc_quanta_reg = 0, lfc_quanta_next;
reg [16+QFB-1:0] pfc_quanta_reg[0:7], pfc_quanta_next[0:7];
reg stat_rx_lfc_pkt_reg = 1'b0, stat_rx_lfc_pkt_next;
reg stat_rx_lfc_xon_reg = 1'b0, stat_rx_lfc_xon_next;
reg stat_rx_lfc_xoff_reg = 1'b0, stat_rx_lfc_xoff_next;
reg stat_rx_pfc_pkt_reg = 1'b0, stat_rx_pfc_pkt_next;
reg [7:0] stat_rx_pfc_xon_reg = 0, stat_rx_pfc_xon_next;
reg [7:0] stat_rx_pfc_xoff_reg = 0, stat_rx_pfc_xoff_next;
assign rx_lfc_req = lfc_req_reg;
assign rx_pfc_req = pfc_req_reg;
assign stat_rx_lfc_pkt = stat_rx_lfc_pkt_reg;
assign stat_rx_lfc_xon = stat_rx_lfc_xon_reg;
assign stat_rx_lfc_xoff = stat_rx_lfc_xoff_reg;
assign stat_rx_lfc_paused = lfc_req_reg;
assign stat_rx_pfc_pkt = stat_rx_pfc_pkt_reg;
assign stat_rx_pfc_xon = stat_rx_pfc_xon_reg;
assign stat_rx_pfc_xoff = stat_rx_pfc_xoff_reg;
assign stat_rx_pfc_paused = pfc_req_reg;
integer k;
initial begin
for (k = 0; k < 8; k = k + 1) begin
pfc_quanta_reg[k] = 0;
end
end
always @* begin
stat_rx_lfc_pkt_next = 1'b0;
stat_rx_lfc_xon_next = 1'b0;
stat_rx_lfc_xoff_next = 1'b0;
stat_rx_pfc_pkt_next = 1'b0;
stat_rx_pfc_xon_next = 0;
stat_rx_pfc_xoff_next = 0;
if (cfg_quanta_clk_en && rx_lfc_ack) begin
if (lfc_quanta_reg > cfg_quanta_step) begin
lfc_quanta_next = lfc_quanta_reg - cfg_quanta_step;
end else begin
lfc_quanta_next = 0;
end
end else begin
lfc_quanta_next = lfc_quanta_reg;
end
lfc_req_next = (lfc_quanta_reg != 0) && rx_lfc_en && cfg_rx_lfc_en;
for (k = 0; k < 8; k = k + 1) begin
if (cfg_quanta_clk_en && rx_pfc_ack[k]) begin
if (pfc_quanta_reg[k] > cfg_quanta_step) begin
pfc_quanta_next[k] = pfc_quanta_reg[k] - cfg_quanta_step;
end else begin
pfc_quanta_next[k] = 0;
end
end else begin
pfc_quanta_next[k] = pfc_quanta_reg[k];
end
pfc_req_next[k] = (pfc_quanta_reg[k] != 0) && rx_pfc_en[k] && cfg_rx_pfc_en;
end
if (mcf_valid) begin
if (mcf_opcode == cfg_rx_lfc_opcode && cfg_rx_lfc_en) begin
stat_rx_lfc_pkt_next = 1'b1;
stat_rx_lfc_xon_next = {mcf_params[7:0], mcf_params[15:8]} == 0;
stat_rx_lfc_xoff_next = {mcf_params[7:0], mcf_params[15:8]} != 0;
lfc_quanta_next = {mcf_params[7:0], mcf_params[15:8], {QFB{1'b0}}};
end else if (PFC_ENABLE && mcf_opcode == cfg_rx_pfc_opcode && cfg_rx_pfc_en) begin
stat_rx_pfc_pkt_next = 1'b1;
for (k = 0; k < 8; k = k + 1) begin
if (mcf_params[k+8]) begin
stat_rx_pfc_xon_next[k] = {mcf_params[16+(k*16)+0 +: 8], mcf_params[16+(k*16)+8 +: 8]} == 0;
stat_rx_pfc_xoff_next[k] = {mcf_params[16+(k*16)+0 +: 8], mcf_params[16+(k*16)+8 +: 8]} != 0;
pfc_quanta_next[k] = {mcf_params[16+(k*16)+0 +: 8], mcf_params[16+(k*16)+8 +: 8], {QFB{1'b0}}};
end
end
end
end
end
always @(posedge clk) begin
lfc_req_reg <= lfc_req_next;
pfc_req_reg <= pfc_req_next;
lfc_quanta_reg <= lfc_quanta_next;
for (k = 0; k < 8; k = k + 1) begin
pfc_quanta_reg[k] <= pfc_quanta_next[k];
end
stat_rx_lfc_pkt_reg <= stat_rx_lfc_pkt_next;
stat_rx_lfc_xon_reg <= stat_rx_lfc_xon_next;
stat_rx_lfc_xoff_reg <= stat_rx_lfc_xoff_next;
stat_rx_pfc_pkt_reg <= stat_rx_pfc_pkt_next;
stat_rx_pfc_xon_reg <= stat_rx_pfc_xon_next;
stat_rx_pfc_xoff_reg <= stat_rx_pfc_xoff_next;
if (rst) begin
lfc_req_reg <= 1'b0;
pfc_req_reg <= 8'd0;
lfc_quanta_reg <= 0;
for (k = 0; k < 8; k = k + 1) begin
pfc_quanta_reg[k] <= 0;
end
stat_rx_lfc_pkt_reg <= 1'b0;
stat_rx_lfc_xon_reg <= 1'b0;
stat_rx_lfc_xoff_reg <= 1'b0;
stat_rx_pfc_pkt_reg <= 1'b0;
stat_rx_pfc_xon_reg <= 0;
stat_rx_pfc_xoff_reg <= 0;
end
end
endmodule
`resetall

313
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/mac_pause_ctrl_tx.v Executable file
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@@ -0,0 +1,313 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* PFC and pause frame transmit handling
*/
module mac_pause_ctrl_tx #
(
parameter MCF_PARAMS_SIZE = 18,
parameter PFC_ENABLE = 1
)
(
input wire clk,
input wire rst,
/*
* MAC control frame interface
*/
output wire mcf_valid,
input wire mcf_ready,
output wire [47:0] mcf_eth_dst,
output wire [47:0] mcf_eth_src,
output wire [15:0] mcf_eth_type,
output wire [15:0] mcf_opcode,
output wire [MCF_PARAMS_SIZE*8-1:0] mcf_params,
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
input wire tx_lfc_req,
input wire tx_lfc_resend,
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
*/
input wire [7:0] tx_pfc_req,
input wire tx_pfc_resend,
/*
* Configuration
*/
input wire [47:0] cfg_tx_lfc_eth_dst,
input wire [47:0] cfg_tx_lfc_eth_src,
input wire [15:0] cfg_tx_lfc_eth_type,
input wire [15:0] cfg_tx_lfc_opcode,
input wire cfg_tx_lfc_en,
input wire [15:0] cfg_tx_lfc_quanta,
input wire [15:0] cfg_tx_lfc_refresh,
input wire [47:0] cfg_tx_pfc_eth_dst,
input wire [47:0] cfg_tx_pfc_eth_src,
input wire [15:0] cfg_tx_pfc_eth_type,
input wire [15:0] cfg_tx_pfc_opcode,
input wire cfg_tx_pfc_en,
input wire [8*16-1:0] cfg_tx_pfc_quanta,
input wire [8*16-1:0] cfg_tx_pfc_refresh,
input wire [9:0] cfg_quanta_step,
input wire cfg_quanta_clk_en,
/*
* Status
*/
output wire stat_tx_lfc_pkt,
output wire stat_tx_lfc_xon,
output wire stat_tx_lfc_xoff,
output wire stat_tx_lfc_paused,
output wire stat_tx_pfc_pkt,
output wire [7:0] stat_tx_pfc_xon,
output wire [7:0] stat_tx_pfc_xoff,
output wire [7:0] stat_tx_pfc_paused
);
localparam QFB = 8;
// check configuration
initial begin
if (MCF_PARAMS_SIZE < (PFC_ENABLE ? 18 : 2)) begin
$error("Error: MCF_PARAMS_SIZE too small for requested configuration (instance %m)");
$finish;
end
end
reg lfc_req_reg = 1'b0, lfc_req_next;
reg lfc_act_reg = 1'b0, lfc_act_next;
reg lfc_send_reg = 1'b0, lfc_send_next;
reg [7:0] pfc_req_reg = 8'd0, pfc_req_next;
reg [7:0] pfc_act_reg = 8'd0, pfc_act_next;
reg [7:0] pfc_en_reg = 8'd0, pfc_en_next;
reg pfc_send_reg = 1'b0, pfc_send_next;
reg [16+QFB-1:0] lfc_refresh_reg = 0, lfc_refresh_next;
reg [16+QFB-1:0] pfc_refresh_reg[0:7], pfc_refresh_next[0:7];
reg stat_tx_lfc_pkt_reg = 1'b0, stat_tx_lfc_pkt_next;
reg stat_tx_lfc_xon_reg = 1'b0, stat_tx_lfc_xon_next;
reg stat_tx_lfc_xoff_reg = 1'b0, stat_tx_lfc_xoff_next;
reg stat_tx_pfc_pkt_reg = 1'b0, stat_tx_pfc_pkt_next;
reg [7:0] stat_tx_pfc_xon_reg = 0, stat_tx_pfc_xon_next;
reg [7:0] stat_tx_pfc_xoff_reg = 0, stat_tx_pfc_xoff_next;
// MAC control interface
reg mcf_pfc_sel_reg = PFC_ENABLE != 0, mcf_pfc_sel_next;
reg mcf_valid_reg = 1'b0, mcf_valid_next;
wire [2*8-1:0] mcf_lfc_params;
assign mcf_lfc_params[16*0 +: 16] = lfc_req_reg ? {cfg_tx_lfc_quanta[0 +: 8], cfg_tx_lfc_quanta[8 +: 8]} : 0;
wire [18*8-1:0] mcf_pfc_params;
assign mcf_pfc_params[16*0 +: 16] = {pfc_en_reg, 8'd0};
assign mcf_pfc_params[16*1 +: 16] = pfc_req_reg[0] ? {cfg_tx_pfc_quanta[16*0+0 +: 8], cfg_tx_pfc_quanta[16*0+8 +: 8]} : 0;
assign mcf_pfc_params[16*2 +: 16] = pfc_req_reg[1] ? {cfg_tx_pfc_quanta[16*1+0 +: 8], cfg_tx_pfc_quanta[16*1+8 +: 8]} : 0;
assign mcf_pfc_params[16*3 +: 16] = pfc_req_reg[2] ? {cfg_tx_pfc_quanta[16*2+0 +: 8], cfg_tx_pfc_quanta[16*2+8 +: 8]} : 0;
assign mcf_pfc_params[16*4 +: 16] = pfc_req_reg[3] ? {cfg_tx_pfc_quanta[16*3+0 +: 8], cfg_tx_pfc_quanta[16*3+8 +: 8]} : 0;
assign mcf_pfc_params[16*5 +: 16] = pfc_req_reg[4] ? {cfg_tx_pfc_quanta[16*4+0 +: 8], cfg_tx_pfc_quanta[16*4+8 +: 8]} : 0;
assign mcf_pfc_params[16*6 +: 16] = pfc_req_reg[5] ? {cfg_tx_pfc_quanta[16*5+0 +: 8], cfg_tx_pfc_quanta[16*5+8 +: 8]} : 0;
assign mcf_pfc_params[16*7 +: 16] = pfc_req_reg[6] ? {cfg_tx_pfc_quanta[16*6+0 +: 8], cfg_tx_pfc_quanta[16*6+8 +: 8]} : 0;
assign mcf_pfc_params[16*8 +: 16] = pfc_req_reg[7] ? {cfg_tx_pfc_quanta[16*7+0 +: 8], cfg_tx_pfc_quanta[16*7+8 +: 8]} : 0;
assign mcf_valid = mcf_valid_reg;
assign mcf_eth_dst = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_eth_dst : cfg_tx_lfc_eth_dst;
assign mcf_eth_src = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_eth_src : cfg_tx_lfc_eth_src;
assign mcf_eth_type = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_eth_type : cfg_tx_lfc_eth_type;
assign mcf_opcode = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_opcode : cfg_tx_lfc_opcode;
assign mcf_params = (PFC_ENABLE && mcf_pfc_sel_reg) ? mcf_pfc_params : mcf_lfc_params;
assign stat_tx_lfc_pkt = stat_tx_lfc_pkt_reg;
assign stat_tx_lfc_xon = stat_tx_lfc_xon_reg;
assign stat_tx_lfc_xoff = stat_tx_lfc_xoff_reg;
assign stat_tx_lfc_paused = lfc_req_reg;
assign stat_tx_pfc_pkt = stat_tx_pfc_pkt_reg;
assign stat_tx_pfc_xon = stat_tx_pfc_xon_reg;
assign stat_tx_pfc_xoff = stat_tx_pfc_xoff_reg;
assign stat_tx_pfc_paused = pfc_req_reg;
integer k;
initial begin
for (k = 0; k < 8; k = k + 1) begin
pfc_refresh_reg[k] = 0;
end
end
always @* begin
lfc_req_next = lfc_req_reg;
lfc_act_next = lfc_act_reg;
lfc_send_next = lfc_send_reg | tx_lfc_resend;
pfc_req_next = pfc_req_reg;
pfc_act_next = pfc_act_reg;
pfc_en_next = pfc_en_reg;
pfc_send_next = pfc_send_reg | tx_pfc_resend;
mcf_pfc_sel_next = mcf_pfc_sel_reg;
mcf_valid_next = mcf_valid_reg && !mcf_ready;
stat_tx_lfc_pkt_next = 1'b0;
stat_tx_lfc_xon_next = 1'b0;
stat_tx_lfc_xoff_next = 1'b0;
stat_tx_pfc_pkt_next = 1'b0;
stat_tx_pfc_xon_next = 0;
stat_tx_pfc_xoff_next = 0;
if (cfg_quanta_clk_en) begin
if (lfc_refresh_reg > cfg_quanta_step) begin
lfc_refresh_next = lfc_refresh_reg - cfg_quanta_step;
end else begin
lfc_refresh_next = 0;
if (lfc_req_reg) begin
lfc_send_next = 1'b1;
end
end
end else begin
lfc_refresh_next = lfc_refresh_reg;
end
for (k = 0; k < 8; k = k + 1) begin
if (cfg_quanta_clk_en) begin
if (pfc_refresh_reg[k] > cfg_quanta_step) begin
pfc_refresh_next[k] = pfc_refresh_reg[k] - cfg_quanta_step;
end else begin
pfc_refresh_next[k] = 0;
if (pfc_req_reg[k]) begin
pfc_send_next = 1'b1;
end
end
end else begin
pfc_refresh_next[k] = pfc_refresh_reg[k];
end
end
if (cfg_tx_lfc_en) begin
if (!mcf_valid_reg) begin
if (lfc_req_reg != tx_lfc_req) begin
lfc_req_next = tx_lfc_req;
lfc_act_next = lfc_act_reg | tx_lfc_req;
lfc_send_next = 1'b1;
end
if (lfc_send_reg && !(PFC_ENABLE && cfg_tx_pfc_en && pfc_send_reg)) begin
mcf_pfc_sel_next = 1'b0;
mcf_valid_next = lfc_act_reg;
lfc_act_next = lfc_req_reg;
lfc_refresh_next = lfc_req_reg ? {cfg_tx_lfc_refresh, {QFB{1'b0}}} : 0;
lfc_send_next = 1'b0;
stat_tx_lfc_pkt_next = lfc_act_reg;
stat_tx_lfc_xon_next = lfc_act_reg && !lfc_req_reg;
stat_tx_lfc_xoff_next = lfc_act_reg && lfc_req_reg;
end
end
end
if (PFC_ENABLE && cfg_tx_pfc_en) begin
if (!mcf_valid_reg) begin
if (pfc_req_reg != tx_pfc_req) begin
pfc_req_next = tx_pfc_req;
pfc_act_next = pfc_act_reg | tx_pfc_req;
pfc_send_next = 1'b1;
end
if (pfc_send_reg) begin
mcf_pfc_sel_next = 1'b1;
mcf_valid_next = pfc_act_reg != 0;
pfc_en_next = pfc_act_reg;
pfc_act_next = pfc_req_reg;
for (k = 0; k < 8; k = k + 1) begin
pfc_refresh_next[k] = pfc_req_reg[k] ? {cfg_tx_pfc_refresh[16*k +: 16], {QFB{1'b0}}} : 0;
end
pfc_send_next = 1'b0;
stat_tx_pfc_pkt_next = pfc_act_reg != 0;
stat_tx_pfc_xon_next = pfc_act_reg & ~pfc_req_reg;
stat_tx_pfc_xoff_next = pfc_act_reg & pfc_req_reg;
end
end
end
end
always @(posedge clk) begin
lfc_req_reg <= lfc_req_next;
lfc_act_reg <= lfc_act_next;
lfc_send_reg <= lfc_send_next;
pfc_req_reg <= pfc_req_next;
pfc_act_reg <= pfc_act_next;
pfc_en_reg <= pfc_en_next;
pfc_send_reg <= pfc_send_next;
mcf_pfc_sel_reg <= mcf_pfc_sel_next;
mcf_valid_reg <= mcf_valid_next;
lfc_refresh_reg <= lfc_refresh_next;
for (k = 0; k < 8; k = k + 1) begin
pfc_refresh_reg[k] <= pfc_refresh_next[k];
end
stat_tx_lfc_pkt_reg <= stat_tx_lfc_pkt_next;
stat_tx_lfc_xon_reg <= stat_tx_lfc_xon_next;
stat_tx_lfc_xoff_reg <= stat_tx_lfc_xoff_next;
stat_tx_pfc_pkt_reg <= stat_tx_pfc_pkt_next;
stat_tx_pfc_xon_reg <= stat_tx_pfc_xon_next;
stat_tx_pfc_xoff_reg <= stat_tx_pfc_xoff_next;
if (rst) begin
lfc_req_reg <= 1'b0;
lfc_act_reg <= 1'b0;
lfc_send_reg <= 1'b0;
pfc_req_reg <= 0;
pfc_act_reg <= 0;
pfc_send_reg <= 0;
mcf_pfc_sel_reg <= PFC_ENABLE != 0;
mcf_valid_reg <= 1'b0;
lfc_refresh_reg <= 0;
for (k = 0; k < 8; k = k + 1) begin
pfc_refresh_reg[k] <= 0;
end
stat_tx_lfc_pkt_reg <= 1'b0;
stat_tx_lfc_xon_reg <= 1'b0;
stat_tx_lfc_xoff_reg <= 1'b0;
stat_tx_pfc_pkt_reg <= 1'b0;
stat_tx_pfc_xon_reg <= 0;
stat_tx_pfc_xoff_reg <= 0;
end
end
endmodule
`resetall

92
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/priority_encoder.v Executable file
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/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Priority encoder module
*/
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority selection
parameter LSB_HIGH_PRIORITY = 0
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1;
parameter W = 2**LEVELS;
// pad input to even power of two
wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded};
wire [W/2-1:0] stage_valid[LEVELS-1:0];
wire [W/2-1:0] stage_enc[LEVELS-1:0];
generate
genvar l, n;
// process input bits; generate valid bit and encoded bit for each pair
for (n = 0; n < W/2; n = n + 1) begin : loop_in
assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
if (LSB_HIGH_PRIORITY) begin
// bit 0 is highest priority
assign stage_enc[0][n] = !input_padded[n*2+0];
end else begin
// bit 0 is lowest priority
assign stage_enc[0][n] = input_padded[n*2+1];
end
end
// compress down to single valid bit and encoded bus
for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
if (LSB_HIGH_PRIORITY) begin
// bit 0 is highest priority
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
end else begin
// bit 0 is lowest priority
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
end
end
end
endgenerate
assign output_valid = stage_valid[LEVELS-1];
assign output_encoded = stage_enc[LEVELS-1];
assign output_unencoded = 1 << output_encoded;
endmodule
`resetall

830
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/ptp_clock_cdc.v Executable file
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/*
Copyright (c) 2019-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1fs
`default_nettype none
/*
* PTP clock CDC (clock domain crossing) module
*/
module ptp_clock_cdc #
(
parameter TS_WIDTH = 96,
parameter NS_WIDTH = 4,
parameter LOG_RATE = 3,
parameter PIPELINE_OUTPUT = 0
)
(
input wire input_clk,
input wire input_rst,
input wire output_clk,
input wire output_rst,
input wire sample_clk,
/*
* Timestamp inputs from source PTP clock
*/
input wire [TS_WIDTH-1:0] input_ts,
input wire input_ts_step,
/*
* Timestamp outputs
*/
output wire [TS_WIDTH-1:0] output_ts,
output wire output_ts_step,
/*
* PPS output
*/
output wire output_pps,
/*
* Status
*/
output wire locked
);
// bus width assertions
initial begin
if (TS_WIDTH != 64 && TS_WIDTH != 96) begin
$error("Error: Timestamp width must be 64 or 96");
$finish;
end
end
localparam FNS_WIDTH = 16;
localparam TS_NS_WIDTH = TS_WIDTH == 96 ? 30 : 48;
localparam TS_FNS_WIDTH = FNS_WIDTH > 16 ? 16 : FNS_WIDTH;
localparam CMP_FNS_WIDTH = 4;
localparam PHASE_CNT_WIDTH = LOG_RATE;
localparam PHASE_ACC_WIDTH = PHASE_CNT_WIDTH+16;
localparam LOG_SAMPLE_SYNC_RATE = LOG_RATE;
localparam SAMPLE_ACC_WIDTH = LOG_SAMPLE_SYNC_RATE+2;
localparam LOG_PHASE_ERR_RATE = 4;
localparam PHASE_ERR_ACC_WIDTH = LOG_PHASE_ERR_RATE+2;
localparam DEST_SYNC_LOCK_WIDTH = 7;
localparam FREQ_LOCK_WIDTH = 8;
localparam PTP_LOCK_WIDTH = 8;
localparam TIME_ERR_INT_WIDTH = NS_WIDTH+FNS_WIDTH;
localparam [30:0] NS_PER_S = 31'd1_000_000_000;
reg [NS_WIDTH+FNS_WIDTH-1:0] period_ns_reg = 0, period_ns_next = 0;
reg [NS_WIDTH+FNS_WIDTH-1:0] period_ns_delay_reg = 0, period_ns_delay_next = 0;
reg [31+FNS_WIDTH-1:0] period_ns_ovf_reg = 0, period_ns_ovf_next = 0;
reg [47:0] src_ts_s_capt_reg = 0;
reg [TS_NS_WIDTH+CMP_FNS_WIDTH-1:0] src_ts_ns_capt_reg = 0;
reg src_ts_step_capt_reg = 0;
reg [47:0] dest_ts_s_capt_reg = 0;
reg [TS_NS_WIDTH+CMP_FNS_WIDTH-1:0] dest_ts_ns_capt_reg = 0;
reg [47:0] src_ts_s_sync_reg = 0;
reg [TS_NS_WIDTH+CMP_FNS_WIDTH-1:0] src_ts_ns_sync_reg = 0;
reg src_ts_step_sync_reg = 0;
reg [47:0] ts_s_reg = 0, ts_s_next = 0;
reg [TS_NS_WIDTH+FNS_WIDTH-1:0] ts_ns_reg = 0, ts_ns_next = 0;
reg [TS_NS_WIDTH+FNS_WIDTH-1:0] ts_ns_inc_reg = 0, ts_ns_inc_next = 0;
reg [TS_NS_WIDTH+FNS_WIDTH+1-1:0] ts_ns_ovf_reg = {TS_NS_WIDTH+FNS_WIDTH+1{1'b1}}, ts_ns_ovf_next = 0;
reg ts_step_reg = 1'b0, ts_step_next;
reg pps_reg = 1'b0;
reg [47:0] ts_s_pipe_reg[0:PIPELINE_OUTPUT-1];
reg [TS_NS_WIDTH+CMP_FNS_WIDTH-1:0] ts_ns_pipe_reg[0:PIPELINE_OUTPUT-1];
reg ts_step_pipe_reg[0:PIPELINE_OUTPUT-1];
reg pps_pipe_reg[0:PIPELINE_OUTPUT-1];
reg [PHASE_CNT_WIDTH-1:0] src_phase_reg = {PHASE_CNT_WIDTH{1'b0}};
reg [PHASE_ACC_WIDTH-1:0] dest_phase_reg = {PHASE_ACC_WIDTH{1'b0}}, dest_phase_next;
reg [PHASE_ACC_WIDTH-1:0] dest_phase_inc_reg = {PHASE_ACC_WIDTH{1'b0}}, dest_phase_inc_next;
reg src_sync_reg = 1'b0;
reg src_update_reg = 1'b0;
reg src_phase_sync_reg = 1'b0;
reg dest_sync_reg = 1'b0;
reg dest_update_reg = 1'b0, dest_update_next = 1'b0;
reg dest_phase_sync_reg = 1'b0;
reg src_sync_sync1_reg = 1'b0;
reg src_sync_sync2_reg = 1'b0;
reg src_sync_sync3_reg = 1'b0;
reg src_phase_sync_sync1_reg = 1'b0;
reg src_phase_sync_sync2_reg = 1'b0;
reg src_phase_sync_sync3_reg = 1'b0;
reg dest_phase_sync_sync1_reg = 1'b0;
reg dest_phase_sync_sync2_reg = 1'b0;
reg dest_phase_sync_sync3_reg = 1'b0;
reg src_sync_sample_sync1_reg = 1'b0;
reg src_sync_sample_sync2_reg = 1'b0;
reg src_sync_sample_sync3_reg = 1'b0;
reg dest_sync_sample_sync1_reg = 1'b0;
reg dest_sync_sample_sync2_reg = 1'b0;
reg dest_sync_sample_sync3_reg = 1'b0;
reg [SAMPLE_ACC_WIDTH-1:0] sample_acc_reg = 0;
reg [SAMPLE_ACC_WIDTH-1:0] sample_acc_out_reg = 0;
reg [LOG_SAMPLE_SYNC_RATE-1:0] sample_cnt_reg = 0;
reg sample_update_reg = 1'b0;
reg sample_update_sync1_reg = 1'b0;
reg sample_update_sync2_reg = 1'b0;
reg sample_update_sync3_reg = 1'b0;
generate
if (PIPELINE_OUTPUT > 0) begin
// pipeline
(* shreg_extract = "no" *)
reg [TS_WIDTH-1:0] output_ts_reg[0:PIPELINE_OUTPUT-1];
(* shreg_extract = "no" *)
reg output_ts_step_reg[0:PIPELINE_OUTPUT-1];
(* shreg_extract = "no" *)
reg output_pps_reg[0:PIPELINE_OUTPUT-1];
assign output_ts = output_ts_reg[PIPELINE_OUTPUT-1];
assign output_ts_step = output_ts_step_reg[PIPELINE_OUTPUT-1];
assign output_pps = output_pps_reg[PIPELINE_OUTPUT-1];
integer i;
initial begin
for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
output_ts_reg[i] = 0;
output_ts_step_reg[i] = 1'b0;
output_pps_reg[i] = 1'b0;
end
end
always @(posedge output_clk) begin
if (TS_WIDTH == 96) begin
output_ts_reg[0][95:48] <= ts_s_reg;
output_ts_reg[0][47:46] <= 2'b00;
output_ts_reg[0][45:0] <= {ts_ns_reg, 16'd0} >> FNS_WIDTH;
end else if (TS_WIDTH == 64) begin
output_ts_reg[0] <= {ts_ns_reg, 16'd0} >> FNS_WIDTH;
end
output_ts_step_reg[0] <= ts_step_reg;
output_pps_reg[0] <= pps_reg;
for (i = 0; i < PIPELINE_OUTPUT-1; i = i + 1) begin
output_ts_reg[i+1] <= output_ts_reg[i];
output_ts_step_reg[i+1] <= output_ts_step_reg[i];
output_pps_reg[i+1] <= output_pps_reg[i];
end
if (output_rst) begin
for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
output_ts_reg[i] <= 0;
output_ts_step_reg[i] <= 1'b0;
output_pps_reg[i] <= 1'b0;
end
end
end
end else begin
if (TS_WIDTH == 96) begin
assign output_ts[95:48] = ts_s_reg;
assign output_ts[47:46] = 2'b00;
assign output_ts[45:0] = {ts_ns_reg, 16'd0} >> FNS_WIDTH;
end else if (TS_WIDTH == 64) begin
assign output_ts = {ts_ns_reg, 16'd0} >> FNS_WIDTH;
end
assign output_ts_step = ts_step_reg;
assign output_pps = pps_reg;
end
endgenerate
integer i;
initial begin
for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
ts_s_pipe_reg[i] = 0;
ts_ns_pipe_reg[i] = 0;
ts_step_pipe_reg[i] = 1'b0;
pps_pipe_reg[i] = 1'b0;
end
end
// source PTP clock capture and sync logic
reg input_ts_step_reg = 1'b0;
always @(posedge input_clk) begin
input_ts_step_reg <= input_ts_step || input_ts_step_reg;
src_phase_sync_reg <= input_ts[16+8];
{src_update_reg, src_phase_reg} <= src_phase_reg+1;
if (src_update_reg) begin
// capture source TS
if (TS_WIDTH == 96) begin
src_ts_s_capt_reg <= input_ts[95:48];
src_ts_ns_capt_reg <= input_ts[45:0] >> (16-CMP_FNS_WIDTH);
end else begin
src_ts_ns_capt_reg <= input_ts >> (16-CMP_FNS_WIDTH);
end
src_ts_step_capt_reg <= input_ts_step || input_ts_step_reg;
input_ts_step_reg <= 1'b0;
src_sync_reg <= !src_sync_reg;
end
if (input_rst) begin
input_ts_step_reg <= 1'b0;
src_phase_reg <= {PHASE_CNT_WIDTH{1'b0}};
src_sync_reg <= 1'b0;
src_update_reg <= 1'b0;
end
end
// CDC logic
always @(posedge output_clk) begin
src_sync_sync1_reg <= src_sync_reg;
src_sync_sync2_reg <= src_sync_sync1_reg;
src_sync_sync3_reg <= src_sync_sync2_reg;
src_phase_sync_sync1_reg <= src_phase_sync_reg;
src_phase_sync_sync2_reg <= src_phase_sync_sync1_reg;
src_phase_sync_sync3_reg <= src_phase_sync_sync2_reg;
dest_phase_sync_sync1_reg <= dest_phase_sync_reg;
dest_phase_sync_sync2_reg <= dest_phase_sync_sync1_reg;
dest_phase_sync_sync3_reg <= dest_phase_sync_sync2_reg;
end
always @(posedge sample_clk) begin
src_sync_sample_sync1_reg <= src_sync_reg;
src_sync_sample_sync2_reg <= src_sync_sample_sync1_reg;
src_sync_sample_sync3_reg <= src_sync_sample_sync2_reg;
dest_sync_sample_sync1_reg <= dest_sync_reg;
dest_sync_sample_sync2_reg <= dest_sync_sample_sync1_reg;
dest_sync_sample_sync3_reg <= dest_sync_sample_sync2_reg;
end
reg edge_1_reg = 1'b0;
reg edge_2_reg = 1'b0;
reg [3:0] active_reg = 0;
always @(posedge sample_clk) begin
// phase and frequency detector
if (dest_sync_sample_sync2_reg && !dest_sync_sample_sync3_reg) begin
if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin
edge_1_reg <= 1'b0;
edge_2_reg <= 1'b0;
end else begin
edge_1_reg <= !edge_2_reg;
edge_2_reg <= 1'b0;
end
end else if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin
edge_1_reg <= 1'b0;
edge_2_reg <= !edge_1_reg;
end
// accumulator
sample_acc_reg <= $signed(sample_acc_reg) + $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg});
sample_cnt_reg <= sample_cnt_reg + 1;
if (src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg) begin
active_reg[0] <= 1'b1;
end
if (sample_cnt_reg == 0) begin
active_reg <= {active_reg, src_sync_sample_sync2_reg && !src_sync_sample_sync3_reg};
sample_acc_reg <= $signed({1'b0, edge_2_reg}) - $signed({1'b0, edge_1_reg});
sample_acc_out_reg <= sample_acc_reg;
if (active_reg != 0) begin
sample_update_reg <= !sample_update_reg;
end
end
end
always @(posedge output_clk) begin
sample_update_sync1_reg <= sample_update_reg;
sample_update_sync2_reg <= sample_update_sync1_reg;
sample_update_sync3_reg <= sample_update_sync2_reg;
end
reg [SAMPLE_ACC_WIDTH-1:0] sample_acc_sync_reg = 0;
reg sample_acc_sync_valid_reg = 0;
reg [PHASE_ACC_WIDTH-1:0] dest_err_int_reg = 0, dest_err_int_next = 0;
reg [1:0] dest_ovf;
reg [DEST_SYNC_LOCK_WIDTH-1:0] dest_sync_lock_count_reg = 0, dest_sync_lock_count_next;
reg dest_sync_locked_reg = 1'b0, dest_sync_locked_next;
always @* begin
{dest_update_next, dest_phase_next} = dest_phase_reg + dest_phase_inc_reg;
dest_phase_inc_next = dest_phase_inc_reg;
dest_err_int_next = dest_err_int_reg;
dest_sync_lock_count_next = dest_sync_lock_count_reg;
dest_sync_locked_next = dest_sync_locked_reg;
if (sample_acc_sync_valid_reg) begin
// updated sampled dest_phase error
// time integral of error
if (dest_sync_locked_reg) begin
{dest_ovf, dest_err_int_next} = $signed({1'b0, dest_err_int_reg}) + $signed(sample_acc_sync_reg);
end else begin
{dest_ovf, dest_err_int_next} = $signed({1'b0, dest_err_int_reg}) + ($signed(sample_acc_sync_reg) * 2**6);
end
// saturate
if (dest_ovf[1]) begin
// sign bit set indicating underflow across zero; saturate to zero
dest_err_int_next = {PHASE_ACC_WIDTH{1'b0}};
end else if (dest_ovf[0]) begin
// sign bit clear but carry bit set indicating overflow; saturate to all 1
dest_err_int_next = {PHASE_ACC_WIDTH{1'b1}};
end
// compute output
if (dest_sync_locked_reg) begin
{dest_ovf, dest_phase_inc_next} = $signed({1'b0, dest_err_int_reg}) + ($signed(sample_acc_sync_reg) * 2**4);
end else begin
{dest_ovf, dest_phase_inc_next} = $signed({1'b0, dest_err_int_reg}) + ($signed(sample_acc_sync_reg) * 2**10);
end
// saturate
if (dest_ovf[1]) begin
// sign bit set indicating underflow across zero; saturate to zero
dest_phase_inc_next = {PHASE_ACC_WIDTH{1'b0}};
end else if (dest_ovf[0]) begin
// sign bit clear but carry bit set indicating overflow; saturate to all 1
dest_phase_inc_next = {PHASE_ACC_WIDTH{1'b1}};
end
// locked status
if ($signed(sample_acc_sync_reg[SAMPLE_ACC_WIDTH-1:2]) == 0 || $signed(sample_acc_sync_reg[SAMPLE_ACC_WIDTH-1:1]) == -1) begin
if (dest_sync_lock_count_reg == {DEST_SYNC_LOCK_WIDTH{1'b1}}) begin
dest_sync_locked_next = 1'b1;
end else begin
dest_sync_lock_count_next = dest_sync_lock_count_reg + 1;
end
end else begin
dest_sync_lock_count_next = 0;
dest_sync_locked_next = 1'b0;
end
end
end
reg [PHASE_ERR_ACC_WIDTH-1:0] phase_err_acc_reg = 0;
reg [PHASE_ERR_ACC_WIDTH-1:0] phase_err_out_reg = 0;
reg [LOG_PHASE_ERR_RATE-1:0] phase_err_cnt_reg = 0;
reg phase_err_out_valid_reg = 0;
reg phase_edge_1_reg = 1'b0;
reg phase_edge_2_reg = 1'b0;
reg [5:0] phase_active_reg = 0;
reg ts_sync_valid_reg = 1'b0;
reg ts_capt_valid_reg = 1'b0;
always @(posedge output_clk) begin
dest_phase_reg <= dest_phase_next;
dest_phase_inc_reg <= dest_phase_inc_next;
dest_update_reg <= dest_update_next;
sample_acc_sync_valid_reg <= 1'b0;
if (sample_update_sync2_reg ^ sample_update_sync3_reg) begin
// latch in synchronized counts from phase detector
sample_acc_sync_reg <= sample_acc_out_reg;
sample_acc_sync_valid_reg <= 1'b1;
end
if (PIPELINE_OUTPUT > 0) begin
dest_phase_sync_reg <= ts_ns_pipe_reg[PIPELINE_OUTPUT-1][8+FNS_WIDTH];
end else begin
dest_phase_sync_reg <= ts_ns_reg[8+FNS_WIDTH];
end
// phase and frequency detector
if (dest_phase_sync_sync2_reg && !dest_phase_sync_sync3_reg) begin
if (src_phase_sync_sync2_reg && !src_phase_sync_sync3_reg) begin
phase_edge_1_reg <= 1'b0;
phase_edge_2_reg <= 1'b0;
end else begin
phase_edge_1_reg <= !phase_edge_2_reg;
phase_edge_2_reg <= 1'b0;
end
end else if (src_phase_sync_sync2_reg && !src_phase_sync_sync3_reg) begin
phase_edge_1_reg <= 1'b0;
phase_edge_2_reg <= !phase_edge_1_reg;
end
// accumulator
phase_err_acc_reg <= $signed(phase_err_acc_reg) + $signed({1'b0, phase_edge_2_reg}) - $signed({1'b0, phase_edge_1_reg});
phase_err_cnt_reg <= phase_err_cnt_reg + 1;
if (src_phase_sync_sync2_reg && !src_phase_sync_sync3_reg) begin
phase_active_reg[0] <= 1'b1;
end
phase_err_out_valid_reg <= 1'b0;
if (phase_err_cnt_reg == 0) begin
phase_active_reg <= {phase_active_reg, src_phase_sync_sync2_reg && !src_phase_sync_sync3_reg};
phase_err_acc_reg <= $signed({1'b0, phase_edge_2_reg}) - $signed({1'b0, phase_edge_1_reg});
phase_err_out_reg <= phase_err_acc_reg;
if (phase_active_reg != 0) begin
phase_err_out_valid_reg <= 1'b1;
end
end
if (dest_update_reg) begin
// capture local TS
if (PIPELINE_OUTPUT > 0) begin
dest_ts_s_capt_reg <= ts_s_pipe_reg[PIPELINE_OUTPUT-1];
dest_ts_ns_capt_reg <= ts_ns_pipe_reg[PIPELINE_OUTPUT-1];
end else begin
dest_ts_s_capt_reg <= ts_s_reg;
dest_ts_ns_capt_reg <= ts_ns_reg >> FNS_WIDTH-CMP_FNS_WIDTH;
end
dest_sync_reg <= !dest_sync_reg;
ts_capt_valid_reg <= 1'b1;
end
if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin
// store captured source TS
if (TS_WIDTH == 96) begin
src_ts_s_sync_reg <= src_ts_s_capt_reg;
end
src_ts_ns_sync_reg <= src_ts_ns_capt_reg;
src_ts_step_sync_reg <= src_ts_step_capt_reg;
ts_sync_valid_reg <= 1'b1;
end
if (ts_sync_valid_reg && ts_capt_valid_reg) begin
ts_sync_valid_reg <= 1'b0;
ts_capt_valid_reg <= 1'b0;
end
dest_err_int_reg <= dest_err_int_next;
dest_sync_lock_count_reg <= dest_sync_lock_count_next;
dest_sync_locked_reg <= dest_sync_locked_next;
if (output_rst) begin
dest_phase_reg <= {PHASE_ACC_WIDTH{1'b0}};
dest_phase_inc_reg <= {PHASE_ACC_WIDTH{1'b0}};
dest_sync_reg <= 1'b0;
dest_update_reg <= 1'b0;
dest_err_int_reg <= 0;
dest_sync_lock_count_reg <= 0;
dest_sync_locked_reg <= 1'b0;
ts_sync_valid_reg <= 1'b0;
ts_capt_valid_reg <= 1'b0;
end
end
reg ts_diff_reg = 1'b0, ts_diff_next;
reg ts_diff_valid_reg = 1'b0, ts_diff_valid_next;
reg [3:0] mismatch_cnt_reg = 0, mismatch_cnt_next;
reg load_ts_reg = 1'b0, load_ts_next;
reg [9+CMP_FNS_WIDTH-1:0] ts_ns_diff_reg = 0, ts_ns_diff_next;
reg [TIME_ERR_INT_WIDTH-1:0] time_err_int_reg = 0, time_err_int_next;
reg [1:0] ptp_ovf;
reg [FREQ_LOCK_WIDTH-1:0] freq_lock_count_reg = 0, freq_lock_count_next;
reg freq_locked_reg = 1'b0, freq_locked_next;
reg [PTP_LOCK_WIDTH-1:0] ptp_lock_count_reg = 0, ptp_lock_count_next;
reg ptp_locked_reg = 1'b0, ptp_locked_next;
reg gain_sel_reg = 0, gain_sel_next;
assign locked = ptp_locked_reg && freq_locked_reg && dest_sync_locked_reg;
always @* begin
period_ns_next = period_ns_reg;
ts_s_next = ts_s_reg;
ts_ns_next = ts_ns_reg;
ts_ns_inc_next = ts_ns_inc_reg;
ts_ns_ovf_next = ts_ns_ovf_reg;
ts_step_next = 0;
ts_diff_next = 1'b0;
ts_diff_valid_next = 1'b0;
mismatch_cnt_next = mismatch_cnt_reg;
load_ts_next = load_ts_reg;
ts_ns_diff_next = ts_ns_diff_reg;
time_err_int_next = time_err_int_reg;
freq_lock_count_next = freq_lock_count_reg;
freq_locked_next = freq_locked_reg;
ptp_lock_count_next = ptp_lock_count_reg;
ptp_locked_next = ptp_locked_reg;
gain_sel_next = gain_sel_reg;
// PTP clock
period_ns_delay_next = period_ns_reg;
period_ns_ovf_next = {NS_PER_S, {FNS_WIDTH{1'b0}}} - period_ns_reg;
if (TS_WIDTH == 96) begin
// 96 bit timestamp
ts_ns_inc_next = ts_ns_inc_reg + period_ns_delay_reg;
ts_ns_ovf_next = ts_ns_inc_reg - period_ns_ovf_reg;
ts_ns_next = ts_ns_inc_reg;
if (!ts_ns_ovf_reg[30+FNS_WIDTH]) begin
// if the overflow lookahead did not borrow, one second has elapsed
// increment seconds field, pre-compute normal increment, force overflow lookahead borrow bit set
ts_ns_inc_next = ts_ns_ovf_reg + period_ns_delay_reg;
ts_ns_ovf_next[30+FNS_WIDTH] = 1'b1;
ts_ns_next = ts_ns_ovf_reg;
ts_s_next = ts_s_reg + 1;
end
end else if (TS_WIDTH == 64) begin
// 64 bit timestamp
ts_ns_next = ts_ns_reg + period_ns_reg;
end
if (ts_sync_valid_reg && ts_capt_valid_reg) begin
// Read new value
if (TS_WIDTH == 96) begin
if (src_ts_step_sync_reg || load_ts_reg) begin
// input stepped
load_ts_next = 1'b0;
ts_s_next = src_ts_s_sync_reg;
ts_ns_next[TS_NS_WIDTH+FNS_WIDTH-1:9+FNS_WIDTH] = src_ts_ns_sync_reg[TS_NS_WIDTH+CMP_FNS_WIDTH-1:9+CMP_FNS_WIDTH];
ts_ns_inc_next[TS_NS_WIDTH+FNS_WIDTH-1:9+FNS_WIDTH] = src_ts_ns_sync_reg[TS_NS_WIDTH+CMP_FNS_WIDTH-1:9+CMP_FNS_WIDTH];
ts_ns_ovf_next[30+FNS_WIDTH] = 1'b1;
ts_step_next = 1;
end else begin
// input did not step
load_ts_next = 1'b0;
ts_diff_valid_next = freq_locked_reg;
end
// compute difference
ts_ns_diff_next = src_ts_ns_sync_reg - dest_ts_ns_capt_reg;
ts_diff_next = src_ts_s_sync_reg != dest_ts_s_capt_reg || src_ts_ns_sync_reg[TS_NS_WIDTH+CMP_FNS_WIDTH-1:9+CMP_FNS_WIDTH] != dest_ts_ns_capt_reg[TS_NS_WIDTH+CMP_FNS_WIDTH-1:9+CMP_FNS_WIDTH];
end else if (TS_WIDTH == 64) begin
if (src_ts_step_sync_reg || load_ts_reg) begin
// input stepped
load_ts_next = 1'b0;
ts_ns_next[TS_NS_WIDTH+FNS_WIDTH-1:9+FNS_WIDTH] = src_ts_ns_sync_reg[TS_NS_WIDTH+CMP_FNS_WIDTH-1:9+CMP_FNS_WIDTH];
ts_step_next = 1;
end else begin
// input did not step
load_ts_next = 1'b0;
ts_diff_valid_next = freq_locked_reg;
end
// compute difference
ts_ns_diff_next = src_ts_ns_sync_reg - dest_ts_ns_capt_reg;
ts_diff_next = src_ts_ns_sync_reg[TS_NS_WIDTH+CMP_FNS_WIDTH-1:9+CMP_FNS_WIDTH] != dest_ts_ns_capt_reg[TS_NS_WIDTH+CMP_FNS_WIDTH-1:9+CMP_FNS_WIDTH];
end
end
if (ts_diff_valid_reg) begin
if (ts_diff_reg) begin
if (&mismatch_cnt_reg) begin
load_ts_next = 1'b1;
mismatch_cnt_next = 0;
end else begin
mismatch_cnt_next = mismatch_cnt_reg + 1;
end
end else begin
mismatch_cnt_next = 0;
end
end
if (phase_err_out_valid_reg) begin
// coarse phase/frequency lock of PTP clock
if ($signed(phase_err_out_reg) > 4 || $signed(phase_err_out_reg) < -4) begin
if (freq_lock_count_reg) begin
freq_lock_count_next = freq_lock_count_reg - 1;
end else begin
freq_locked_next = 1'b0;
end
end else begin
if (&freq_lock_count_reg) begin
freq_locked_next = 1'b1;
end else begin
freq_lock_count_next = freq_lock_count_reg + 1;
end
end
if (!freq_locked_reg) begin
ts_ns_diff_next = $signed(phase_err_out_reg) * 8 * 2**CMP_FNS_WIDTH;
ts_diff_valid_next = 1'b1;
end
end
if (ts_diff_valid_reg) begin
// PI control
// gain scheduling
casez (ts_ns_diff_reg[9+CMP_FNS_WIDTH-5 +: 5])
5'b01zzz: gain_sel_next = 1'b1;
5'b001zz: gain_sel_next = 1'b1;
5'b0001z: gain_sel_next = 1'b1;
5'b00001: gain_sel_next = 1'b1;
5'b00000: gain_sel_next = 1'b0;
5'b11111: gain_sel_next = 1'b0;
5'b11110: gain_sel_next = 1'b1;
5'b1110z: gain_sel_next = 1'b1;
5'b110zz: gain_sel_next = 1'b1;
5'b10zzz: gain_sel_next = 1'b1;
default: gain_sel_next = 1'b0;
endcase
// time integral of error
case (gain_sel_reg)
1'b0: {ptp_ovf, time_err_int_next} = $signed({1'b0, time_err_int_reg}) + ($signed(ts_ns_diff_reg) / 2**4);
1'b1: {ptp_ovf, time_err_int_next} = $signed({1'b0, time_err_int_reg}) + ($signed(ts_ns_diff_reg) * 2**2);
endcase
// saturate
if (ptp_ovf[1]) begin
// sign bit set indicating underflow across zero; saturate to zero
time_err_int_next = {TIME_ERR_INT_WIDTH{1'b0}};
end else if (ptp_ovf[0]) begin
// sign bit clear but carry bit set indicating overflow; saturate to all 1
time_err_int_next = {TIME_ERR_INT_WIDTH{1'b1}};
end
// compute output
case (gain_sel_reg)
1'b0: {ptp_ovf, period_ns_next} = $signed({1'b0, time_err_int_reg}) + ($signed(ts_ns_diff_reg) * 2**2);
1'b1: {ptp_ovf, period_ns_next} = $signed({1'b0, time_err_int_reg}) + ($signed(ts_ns_diff_reg) * 2**6);
endcase
// saturate
if (ptp_ovf[1]) begin
// sign bit set indicating underflow across zero; saturate to zero
period_ns_next = {NS_WIDTH+FNS_WIDTH{1'b0}};
end else if (ptp_ovf[0]) begin
// sign bit clear but carry bit set indicating overflow; saturate to all 1
period_ns_next = {NS_WIDTH+FNS_WIDTH{1'b1}};
end
// adjust period if integrator is saturated
if (time_err_int_reg == 0) begin
period_ns_next = {NS_WIDTH+FNS_WIDTH{1'b0}};
end else if (~time_err_int_reg == 0) begin
period_ns_next = {NS_WIDTH+FNS_WIDTH{1'b1}};
end
// locked status
if (!freq_locked_reg) begin
ptp_lock_count_next = 0;
ptp_locked_next = 1'b0;
end else if (gain_sel_reg == 1'b0) begin
if (&ptp_lock_count_reg) begin
ptp_locked_next = 1'b1;
end else begin
ptp_lock_count_next = ptp_lock_count_reg + 1;
end
end else begin
if (ptp_lock_count_reg) begin
ptp_lock_count_next = ptp_lock_count_reg - 1;
end else begin
ptp_locked_next = 1'b0;
end
end
end
end
always @(posedge output_clk) begin
period_ns_reg <= period_ns_next;
period_ns_delay_reg <= period_ns_delay_next;
period_ns_ovf_reg <= period_ns_ovf_next;
ts_s_reg <= ts_s_next;
ts_ns_reg <= ts_ns_next;
ts_ns_inc_reg <= ts_ns_inc_next;
ts_ns_ovf_reg <= ts_ns_ovf_next;
ts_step_reg <= ts_step_next;
ts_diff_reg <= ts_diff_next;
ts_diff_valid_reg <= ts_diff_valid_next;
mismatch_cnt_reg <= mismatch_cnt_next;
load_ts_reg <= load_ts_next;
ts_ns_diff_reg <= ts_ns_diff_next;
time_err_int_reg <= time_err_int_next;
freq_lock_count_reg <= freq_lock_count_next;
freq_locked_reg <= freq_locked_next;
ptp_lock_count_reg <= ptp_lock_count_next;
ptp_locked_reg <= ptp_locked_next;
gain_sel_reg <= gain_sel_next;
// PPS output
if (TS_WIDTH == 96) begin
pps_reg <= !ts_ns_ovf_reg[30+FNS_WIDTH];
end else if (TS_WIDTH == 64) begin
pps_reg <= 1'b0; // not currently implemented for 64 bit timestamp format
end
// pipeline
if (PIPELINE_OUTPUT > 0) begin
ts_s_pipe_reg[0] <= ts_s_reg;
ts_ns_pipe_reg[0] <= ts_ns_reg >> FNS_WIDTH-TS_FNS_WIDTH;
ts_step_pipe_reg[0] <= ts_step_reg;
pps_pipe_reg[0] <= pps_reg;
for (i = 0; i < PIPELINE_OUTPUT-1; i = i + 1) begin
ts_s_pipe_reg[i+1] <= ts_s_pipe_reg[i];
ts_ns_pipe_reg[i+1] <= ts_ns_pipe_reg[i];
ts_step_pipe_reg[i+1] <= ts_step_pipe_reg[i];
pps_pipe_reg[i+1] <= pps_pipe_reg[i];
end
end
if (output_rst) begin
period_ns_reg <= 0;
ts_s_reg <= 0;
ts_ns_reg <= 0;
ts_ns_inc_reg <= 0;
ts_ns_ovf_reg[30+FNS_WIDTH] <= 1'b1;
ts_step_reg <= 0;
pps_reg <= 0;
ts_diff_reg <= 1'b0;
ts_diff_valid_reg <= 1'b0;
mismatch_cnt_reg <= 0;
load_ts_reg <= 0;
time_err_int_reg <= 0;
freq_lock_count_reg <= 0;
freq_locked_reg <= 1'b0;
ptp_lock_count_reg <= 0;
ptp_locked_reg <= 1'b0;
for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
ts_s_pipe_reg[i] <= 0;
ts_ns_pipe_reg[i] <= 0;
ts_step_pipe_reg[i] <= 1'b0;
pps_pipe_reg[i] <= 1'b0;
end
end
end
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/sync_reset.v Executable file
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/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #
(
// depth of synchronizer
parameter N = 2
)
(
input wire clk,
input wire rst,
output wire out
);
(* srl_style = "register" *)
reg [N-1:0] sync_reg = {N{1'b1}};
assign out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst) begin
sync_reg <= {N{1'b1}};
end else begin
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
end
endmodule
`resetall

428
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/udp_64.v Executable file
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* UDP block, IP interface (64 bit datapath)
*/
module udp_64 #
(
parameter CHECKSUM_GEN_ENABLE = 1,
parameter CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048,
parameter CHECKSUM_HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_ip_eth_dest_mac,
input wire [47:0] s_ip_eth_src_mac,
input wire [15:0] s_ip_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* UDP frame input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [47:0] s_udp_eth_dest_mac,
input wire [47:0] s_udp_eth_src_mac,
input wire [15:0] s_udp_eth_type,
input wire [3:0] s_udp_ip_version,
input wire [3:0] s_udp_ip_ihl,
input wire [5:0] s_udp_ip_dscp,
input wire [1:0] s_udp_ip_ecn,
input wire [15:0] s_udp_ip_identification,
input wire [2:0] s_udp_ip_flags,
input wire [12:0] s_udp_ip_fragment_offset,
input wire [7:0] s_udp_ip_ttl,
input wire [15:0] s_udp_ip_header_checksum,
input wire [31:0] s_udp_ip_source_ip,
input wire [31:0] s_udp_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [63:0] s_udp_payload_axis_tdata,
input wire [7:0] s_udp_payload_axis_tkeep,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_udp_eth_dest_mac,
output wire [47:0] m_udp_eth_src_mac,
output wire [15:0] m_udp_eth_type,
output wire [3:0] m_udp_ip_version,
output wire [3:0] m_udp_ip_ihl,
output wire [5:0] m_udp_ip_dscp,
output wire [1:0] m_udp_ip_ecn,
output wire [15:0] m_udp_ip_length,
output wire [15:0] m_udp_ip_identification,
output wire [2:0] m_udp_ip_flags,
output wire [12:0] m_udp_ip_fragment_offset,
output wire [7:0] m_udp_ip_ttl,
output wire [7:0] m_udp_ip_protocol,
output wire [15:0] m_udp_ip_header_checksum,
output wire [31:0] m_udp_ip_source_ip,
output wire [31:0] m_udp_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status signals
*/
output wire rx_busy,
output wire tx_busy,
output wire rx_error_header_early_termination,
output wire rx_error_payload_early_termination,
output wire tx_error_payload_early_termination
);
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [47:0] tx_udp_eth_dest_mac;
wire [47:0] tx_udp_eth_src_mac;
wire [15:0] tx_udp_eth_type;
wire [3:0] tx_udp_ip_version;
wire [3:0] tx_udp_ip_ihl;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [15:0] tx_udp_ip_identification;
wire [2:0] tx_udp_ip_flags;
wire [12:0] tx_udp_ip_fragment_offset;
wire [7:0] tx_udp_ip_ttl;
wire [15:0] tx_udp_ip_header_checksum;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
udp_ip_rx_64
udp_ip_rx_64_inst (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_ip_eth_dest_mac),
.s_eth_src_mac(s_ip_eth_src_mac),
.s_eth_type(s_ip_eth_type),
.s_ip_version(s_ip_version),
.s_ip_ihl(s_ip_ihl),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_header_checksum(s_ip_header_checksum),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_eth_dest_mac(m_udp_eth_dest_mac),
.m_eth_src_mac(m_udp_eth_src_mac),
.m_eth_type(m_udp_eth_type),
.m_ip_version(m_udp_ip_version),
.m_ip_ihl(m_udp_ip_ihl),
.m_ip_dscp(m_udp_ip_dscp),
.m_ip_ecn(m_udp_ip_ecn),
.m_ip_length(m_udp_ip_length),
.m_ip_identification(m_udp_ip_identification),
.m_ip_flags(m_udp_ip_flags),
.m_ip_fragment_offset(m_udp_ip_fragment_offset),
.m_ip_ttl(m_udp_ip_ttl),
.m_ip_protocol(m_udp_ip_protocol),
.m_ip_header_checksum(m_udp_ip_header_checksum),
.m_ip_source_ip(m_udp_ip_source_ip),
.m_ip_dest_ip(m_udp_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
// Status signals
.busy(rx_busy),
.error_header_early_termination(rx_error_header_early_termination),
.error_payload_early_termination(rx_error_payload_early_termination)
);
generate
if (CHECKSUM_GEN_ENABLE) begin
udp_checksum_gen_64 #(
.PAYLOAD_FIFO_DEPTH(CHECKSUM_PAYLOAD_FIFO_DEPTH),
.HEADER_FIFO_DEPTH(CHECKSUM_HEADER_FIFO_DEPTH)
)
udp_checksum_gen_64_inst (
.clk(clk),
.rst(rst),
// UDP frame input
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_eth_dest_mac(s_udp_eth_dest_mac),
.s_eth_src_mac(s_udp_eth_src_mac),
.s_eth_type(s_udp_eth_type),
.s_ip_version(s_udp_ip_version),
.s_ip_ihl(s_udp_ip_ihl),
.s_ip_dscp(s_udp_ip_dscp),
.s_ip_ecn(s_udp_ip_ecn),
.s_ip_identification(s_udp_ip_identification),
.s_ip_flags(s_udp_ip_flags),
.s_ip_fragment_offset(s_udp_ip_fragment_offset),
.s_ip_ttl(s_udp_ip_ttl),
.s_ip_header_checksum(s_udp_ip_header_checksum),
.s_ip_source_ip(s_udp_ip_source_ip),
.s_ip_dest_ip(s_udp_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(tx_udp_hdr_valid),
.m_udp_hdr_ready(tx_udp_hdr_ready),
.m_eth_dest_mac(tx_udp_eth_dest_mac),
.m_eth_src_mac(tx_udp_eth_src_mac),
.m_eth_type(tx_udp_eth_type),
.m_ip_version(tx_udp_ip_version),
.m_ip_ihl(tx_udp_ip_ihl),
.m_ip_dscp(tx_udp_ip_dscp),
.m_ip_ecn(tx_udp_ip_ecn),
.m_ip_length(),
.m_ip_identification(tx_udp_ip_identification),
.m_ip_flags(tx_udp_ip_flags),
.m_ip_fragment_offset(tx_udp_ip_fragment_offset),
.m_ip_ttl(tx_udp_ip_ttl),
.m_ip_header_checksum(tx_udp_ip_header_checksum),
.m_ip_source_ip(tx_udp_ip_source_ip),
.m_ip_dest_ip(tx_udp_ip_dest_ip),
.m_udp_source_port(tx_udp_source_port),
.m_udp_dest_port(tx_udp_dest_port),
.m_udp_length(tx_udp_length),
.m_udp_checksum(tx_udp_checksum),
.m_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// Status signals
.busy()
);
end else begin
assign tx_udp_hdr_valid = s_udp_hdr_valid;
assign s_udp_hdr_ready = tx_udp_hdr_ready;
assign tx_udp_eth_dest_mac = s_udp_eth_dest_mac;
assign tx_udp_eth_src_mac = s_udp_eth_src_mac;
assign tx_udp_eth_type = s_udp_eth_type;
assign tx_udp_ip_version = s_udp_ip_version;
assign tx_udp_ip_ihl = s_udp_ip_ihl;
assign tx_udp_ip_dscp = s_udp_ip_dscp;
assign tx_udp_ip_ecn = s_udp_ip_ecn;
assign tx_udp_ip_identification = s_udp_ip_identification;
assign tx_udp_ip_flags = s_udp_ip_flags;
assign tx_udp_ip_fragment_offset = s_udp_ip_fragment_offset;
assign tx_udp_ip_ttl = s_udp_ip_ttl;
assign tx_udp_ip_header_checksum = s_udp_ip_header_checksum;
assign tx_udp_ip_source_ip = s_udp_ip_source_ip;
assign tx_udp_ip_dest_ip = s_udp_ip_dest_ip;
assign tx_udp_source_port = s_udp_source_port;
assign tx_udp_dest_port = s_udp_dest_port;
assign tx_udp_length = s_udp_length;
assign tx_udp_checksum = s_udp_checksum;
assign tx_udp_payload_axis_tdata = s_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = s_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = s_udp_payload_axis_tvalid;
assign s_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = s_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = s_udp_payload_axis_tuser;
end
endgenerate
udp_ip_tx_64
udp_ip_tx_64_inst (
.clk(clk),
.rst(rst),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_eth_dest_mac(tx_udp_eth_dest_mac),
.s_eth_src_mac(tx_udp_eth_src_mac),
.s_eth_type(tx_udp_eth_type),
.s_ip_version(tx_udp_ip_version),
.s_ip_ihl(tx_udp_ip_ihl),
.s_ip_dscp(tx_udp_ip_dscp),
.s_ip_ecn(tx_udp_ip_ecn),
.s_ip_identification(tx_udp_ip_identification),
.s_ip_flags(tx_udp_ip_flags),
.s_ip_fragment_offset(tx_udp_ip_fragment_offset),
.s_ip_ttl(tx_udp_ip_ttl),
.s_ip_protocol(8'h11),
.s_ip_header_checksum(tx_udp_ip_header_checksum),
.s_ip_source_ip(tx_udp_ip_source_ip),
.s_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_eth_dest_mac(m_ip_eth_dest_mac),
.m_eth_src_mac(m_ip_eth_src_mac),
.m_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// Status signals
.busy(tx_busy),
.error_payload_early_termination(tx_error_payload_early_termination)
);
endmodule
`resetall

597
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/udp_checksum_gen_64.v Executable file
View File

@@ -0,0 +1,597 @@
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* UDP checksum calculation module (64 bit datapath)
*/
module udp_checksum_gen_64 #
(
parameter PAYLOAD_FIFO_DEPTH = 2048,
parameter HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
input wire rst,
/*
* UDP frame input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [63:0] s_udp_payload_axis_tdata,
input wire [7:0] s_udp_payload_axis_tkeep,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status signals
*/
output wire busy
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives a UDP frame with header fields in parallel and payload on
an AXI stream interface, calculates the length and checksum, then produces the
header fields in parallel along with the UDP payload in a separate AXI stream.
*/
parameter HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH);
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_SUM_HEADER = 3'd1,
STATE_SUM_PAYLOAD = 3'd2,
STATE_FINISH_SUM_1 = 3'd3,
STATE_FINISH_SUM_2 = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_udp_hdr;
reg shift_payload_in;
reg [31:0] checksum_part;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [31:0] checksum_reg = 32'd0, checksum_next;
reg [16:0] checksum_temp1_reg = 17'd0, checksum_temp1_next;
reg [16:0] checksum_temp2_reg = 17'd0, checksum_temp2_next;
reg [47:0] eth_dest_mac_reg = 48'd0;
reg [47:0] eth_src_mac_reg = 48'd0;
reg [15:0] eth_type_reg = 16'd0;
reg [3:0] ip_version_reg = 4'd0;
reg [3:0] ip_ihl_reg = 4'd0;
reg [5:0] ip_dscp_reg = 6'd0;
reg [1:0] ip_ecn_reg = 2'd0;
reg [15:0] ip_identification_reg = 16'd0;
reg [2:0] ip_flags_reg = 3'd0;
reg [12:0] ip_fragment_offset_reg = 13'd0;
reg [7:0] ip_ttl_reg = 8'd0;
reg [15:0] ip_header_checksum_reg = 16'd0;
reg [31:0] ip_source_ip_reg = 32'd0;
reg [31:0] ip_dest_ip_reg = 32'd0;
reg [15:0] udp_source_port_reg = 16'd0;
reg [15:0] udp_dest_port_reg = 16'd0;
reg hdr_valid_reg = 0, hdr_valid_next;
reg s_udp_hdr_ready_reg = 1'b0, s_udp_hdr_ready_next;
reg s_udp_payload_axis_tready_reg = 1'b0, s_udp_payload_axis_tready_next;
reg busy_reg = 1'b0;
/*
* UDP Payload FIFO
*/
wire [63:0] s_udp_payload_fifo_tdata;
wire [7:0] s_udp_payload_fifo_tkeep;
wire s_udp_payload_fifo_tvalid;
wire s_udp_payload_fifo_tready;
wire s_udp_payload_fifo_tlast;
wire s_udp_payload_fifo_tuser;
wire [63:0] m_udp_payload_fifo_tdata;
wire [7:0] m_udp_payload_fifo_tkeep;
wire m_udp_payload_fifo_tvalid;
wire m_udp_payload_fifo_tready;
wire m_udp_payload_fifo_tlast;
wire m_udp_payload_fifo_tuser;
axis_fifo #(
.DEPTH(PAYLOAD_FIFO_DEPTH),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_udp_payload_fifo_tdata),
.s_axis_tkeep(s_udp_payload_fifo_tkeep),
.s_axis_tvalid(s_udp_payload_fifo_tvalid),
.s_axis_tready(s_udp_payload_fifo_tready),
.s_axis_tlast(s_udp_payload_fifo_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_udp_payload_fifo_tuser),
// AXI output
.m_axis_tdata(m_udp_payload_fifo_tdata),
.m_axis_tkeep(m_udp_payload_fifo_tkeep),
.m_axis_tvalid(m_udp_payload_fifo_tvalid),
.m_axis_tready(m_udp_payload_fifo_tready),
.m_axis_tlast(m_udp_payload_fifo_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_udp_payload_fifo_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
assign s_udp_payload_fifo_tdata = s_udp_payload_axis_tdata;
assign s_udp_payload_fifo_tkeep = s_udp_payload_axis_tkeep;
assign s_udp_payload_fifo_tvalid = s_udp_payload_axis_tvalid && shift_payload_in;
assign s_udp_payload_axis_tready = s_udp_payload_fifo_tready && shift_payload_in;
assign s_udp_payload_fifo_tlast = s_udp_payload_axis_tlast;
assign s_udp_payload_fifo_tuser = s_udp_payload_axis_tuser;
assign m_udp_payload_axis_tdata = m_udp_payload_fifo_tdata;
assign m_udp_payload_axis_tkeep = m_udp_payload_fifo_tkeep;
assign m_udp_payload_axis_tvalid = m_udp_payload_fifo_tvalid;
assign m_udp_payload_fifo_tready = m_udp_payload_axis_tready;
assign m_udp_payload_axis_tlast = m_udp_payload_fifo_tlast;
assign m_udp_payload_axis_tuser = m_udp_payload_fifo_tuser;
/*
* UDP Header FIFO
*/
reg [HEADER_FIFO_ADDR_WIDTH:0] header_fifo_wr_ptr_reg = {HEADER_FIFO_ADDR_WIDTH+1{1'b0}}, header_fifo_wr_ptr_next;
reg [HEADER_FIFO_ADDR_WIDTH:0] header_fifo_rd_ptr_reg = {HEADER_FIFO_ADDR_WIDTH+1{1'b0}}, header_fifo_rd_ptr_next;
reg [47:0] eth_dest_mac_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [47:0] eth_src_mac_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] eth_type_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [3:0] ip_version_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [3:0] ip_ihl_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [5:0] ip_dscp_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [1:0] ip_ecn_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] ip_identification_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [2:0] ip_flags_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [12:0] ip_fragment_offset_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [7:0] ip_ttl_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] ip_header_checksum_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [31:0] ip_source_ip_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [31:0] ip_dest_ip_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_source_port_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_dest_port_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_length_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_checksum_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg [15:0] m_udp_source_port_reg = 16'd0;
reg [15:0] m_udp_dest_port_reg = 16'd0;
reg [15:0] m_udp_length_reg = 16'd0;
reg [15:0] m_udp_checksum_reg = 16'd0;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
// full when first MSB different but rest same
wire header_fifo_full = ((header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH] != header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH]) &&
(header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0] == header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire header_fifo_empty = header_fifo_wr_ptr_reg == header_fifo_rd_ptr_reg;
// control signals
reg header_fifo_write;
reg header_fifo_read;
wire header_fifo_ready = !header_fifo_full;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_udp_length_reg + 16'd20;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = 8'h11;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
// Write logic
always @* begin
header_fifo_write = 1'b0;
header_fifo_wr_ptr_next = header_fifo_wr_ptr_reg;
if (hdr_valid_reg) begin
// input data valid
if (~header_fifo_full) begin
// not full, perform write
header_fifo_write = 1'b1;
header_fifo_wr_ptr_next = header_fifo_wr_ptr_reg + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
header_fifo_wr_ptr_reg <= {HEADER_FIFO_ADDR_WIDTH+1{1'b0}};
end else begin
header_fifo_wr_ptr_reg <= header_fifo_wr_ptr_next;
end
if (header_fifo_write) begin
eth_dest_mac_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= eth_dest_mac_reg;
eth_src_mac_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= eth_src_mac_reg;
eth_type_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= eth_type_reg;
ip_version_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_version_reg;
ip_ihl_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_ihl_reg;
ip_dscp_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_dscp_reg;
ip_ecn_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_ecn_reg;
ip_identification_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_identification_reg;
ip_flags_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_flags_reg;
ip_fragment_offset_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_fragment_offset_reg;
ip_ttl_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_ttl_reg;
ip_header_checksum_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_header_checksum_reg;
ip_source_ip_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_source_ip_reg;
ip_dest_ip_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_dest_ip_reg;
udp_source_port_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= udp_source_port_reg;
udp_dest_port_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= udp_dest_port_reg;
udp_length_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= frame_ptr_reg;
udp_checksum_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= checksum_reg[15:0];
end
end
// Read logic
always @* begin
header_fifo_read = 1'b0;
header_fifo_rd_ptr_next = header_fifo_rd_ptr_reg;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg;
if (m_udp_hdr_ready || !m_udp_hdr_valid) begin
// output data not valid OR currently being transferred
if (!header_fifo_empty) begin
// not empty, perform read
header_fifo_read = 1'b1;
m_udp_hdr_valid_next = 1'b1;
header_fifo_rd_ptr_next = header_fifo_rd_ptr_reg + 1;
end else begin
// empty, invalidate
m_udp_hdr_valid_next = 1'b0;
end
end
end
always @(posedge clk) begin
if (rst) begin
header_fifo_rd_ptr_reg <= {HEADER_FIFO_ADDR_WIDTH+1{1'b0}};
m_udp_hdr_valid_reg <= 1'b0;
end else begin
header_fifo_rd_ptr_reg <= header_fifo_rd_ptr_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
end
if (header_fifo_read) begin
m_eth_dest_mac_reg <= eth_dest_mac_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_eth_src_mac_reg <= eth_src_mac_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_eth_type_reg <= eth_type_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_version_reg <= ip_version_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_ihl_reg <= ip_ihl_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_dscp_reg <= ip_dscp_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_ecn_reg <= ip_ecn_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_identification_reg <= ip_identification_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_flags_reg <= ip_flags_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_fragment_offset_reg <= ip_fragment_offset_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_ttl_reg <= ip_ttl_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_header_checksum_reg <= ip_header_checksum_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_source_ip_reg <= ip_source_ip_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_dest_ip_reg <= ip_dest_ip_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_source_port_reg <= udp_source_port_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_dest_port_reg <= udp_dest_port_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_length_reg <= udp_length_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_checksum_reg <= udp_checksum_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
end
end
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign busy = busy_reg;
integer i, word_cnt;
always @* begin
state_next = STATE_IDLE;
s_udp_hdr_ready_next = 1'b0;
s_udp_payload_axis_tready_next = 1'b0;
store_udp_hdr = 1'b0;
shift_payload_in = 1'b0;
frame_ptr_next = frame_ptr_reg;
checksum_next = checksum_reg;
checksum_temp1_next = checksum_temp1_reg;
checksum_temp2_next = checksum_temp2_reg;
hdr_valid_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state
s_udp_hdr_ready_next = header_fifo_ready;
if (s_udp_hdr_ready && s_udp_hdr_valid) begin
store_udp_hdr = 1'b1;
frame_ptr_next = 0;
// 16'h0011 = zero padded type field
// 16'h0010 = header length times two
checksum_next = 16'h0011 + 16'h0010;
checksum_temp1_next = s_ip_source_ip[31:16];
checksum_temp2_next = s_ip_source_ip[15:0];
s_udp_hdr_ready_next = 1'b0;
state_next = STATE_SUM_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_SUM_HEADER: begin
// sum pseudo header and header
checksum_next = checksum_reg + checksum_temp1_reg + checksum_temp2_reg;
checksum_temp1_next = ip_dest_ip_reg[31:16] + ip_dest_ip_reg[15:0];
checksum_temp2_next = udp_source_port_reg + udp_dest_port_reg;
frame_ptr_next = 8;
state_next = STATE_SUM_PAYLOAD;
end
STATE_SUM_PAYLOAD: begin
// sum payload
shift_payload_in = 1'b1;
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
word_cnt = 1;
for (i = 1; i <= 8; i = i + 1) begin
if (s_udp_payload_axis_tkeep == 8'hff >> (8-i)) word_cnt = i;
end
checksum_temp1_next = 0;
checksum_temp2_next = 0;
for (i = 0; i < 4; i = i + 1) begin
if (s_udp_payload_axis_tkeep[i]) begin
if (i & 1) begin
checksum_temp1_next = checksum_temp1_next + {8'h00, s_udp_payload_axis_tdata[i*8 +: 8]};
end else begin
checksum_temp1_next = checksum_temp1_next + {s_udp_payload_axis_tdata[i*8 +: 8], 8'h00};
end
end
end
for (i = 4; i < 8; i = i + 1) begin
if (s_udp_payload_axis_tkeep[i]) begin
if (i & 1) begin
checksum_temp2_next = checksum_temp2_next + {8'h00, s_udp_payload_axis_tdata[i*8 +: 8]};
end else begin
checksum_temp2_next = checksum_temp2_next + {s_udp_payload_axis_tdata[i*8 +: 8], 8'h00};
end
end
end
// add length * 2 (two copies of length field in pseudo header)
checksum_next = checksum_reg + checksum_temp1_reg + checksum_temp2_reg + (word_cnt << 1);
frame_ptr_next = frame_ptr_reg + word_cnt;
if (s_udp_payload_axis_tlast) begin
state_next = STATE_FINISH_SUM_1;
end else begin
state_next = STATE_SUM_PAYLOAD;
end
end else begin
state_next = STATE_SUM_PAYLOAD;
end
end
STATE_FINISH_SUM_1: begin
// empty pipeline
checksum_next = checksum_reg + checksum_temp1_reg + checksum_temp2_reg;
state_next = STATE_FINISH_SUM_2;
end
STATE_FINISH_SUM_2: begin
// add MSW (twice!) for proper ones complement sum
checksum_part = checksum_reg[15:0] + checksum_reg[31:16];
checksum_next = ~(checksum_part[15:0] + checksum_part[16]);
hdr_valid_next = 1;
state_next = STATE_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_udp_hdr_ready_reg <= 1'b0;
s_udp_payload_axis_tready_reg <= 1'b0;
hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
s_udp_payload_axis_tready_reg <= s_udp_payload_axis_tready_next;
hdr_valid_reg <= hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
end
frame_ptr_reg <= frame_ptr_next;
checksum_reg <= checksum_next;
checksum_temp1_reg <= checksum_temp1_next;
checksum_temp2_reg <= checksum_temp2_next;
// datapath
if (store_udp_hdr) begin
eth_dest_mac_reg <= s_eth_dest_mac;
eth_src_mac_reg <= s_eth_src_mac;
eth_type_reg <= s_eth_type;
ip_version_reg <= s_ip_version;
ip_ihl_reg <= s_ip_ihl;
ip_dscp_reg <= s_ip_dscp;
ip_ecn_reg <= s_ip_ecn;
ip_identification_reg <= s_ip_identification;
ip_flags_reg <= s_ip_flags;
ip_fragment_offset_reg <= s_ip_fragment_offset;
ip_ttl_reg <= s_ip_ttl;
ip_header_checksum_reg <= s_ip_header_checksum;
ip_source_ip_reg <= s_ip_source_ip;
ip_dest_ip_reg <= s_ip_dest_ip;
udp_source_port_reg <= s_udp_source_port;
udp_dest_port_reg <= s_udp_dest_port;
end
end
endmodule
`resetall

661
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/udp_complete_64.v Executable file
View File

@@ -0,0 +1,661 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IPv4 and ARP block with UDP support, ethernet frame interface (64 bit datapath)
*/
module udp_complete_64 #(
parameter ARP_CACHE_ADDR_WIDTH = 9,
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2,
parameter ARP_REQUEST_TIMEOUT = 125000000*30,
parameter UDP_CHECKSUM_GEN_ENABLE = 1,
parameter UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048,
parameter UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* UDP input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [5:0] s_udp_ip_dscp,
input wire [1:0] s_udp_ip_ecn,
input wire [7:0] s_udp_ip_ttl,
input wire [31:0] s_udp_ip_source_ip,
input wire [31:0] s_udp_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [63:0] s_udp_payload_axis_tdata,
input wire [7:0] s_udp_payload_axis_tkeep,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* UDP output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_udp_eth_dest_mac,
output wire [47:0] m_udp_eth_src_mac,
output wire [15:0] m_udp_eth_type,
output wire [3:0] m_udp_ip_version,
output wire [3:0] m_udp_ip_ihl,
output wire [5:0] m_udp_ip_dscp,
output wire [1:0] m_udp_ip_ecn,
output wire [15:0] m_udp_ip_length,
output wire [15:0] m_udp_ip_identification,
output wire [2:0] m_udp_ip_flags,
output wire [12:0] m_udp_ip_fragment_offset,
output wire [7:0] m_udp_ip_ttl,
output wire [7:0] m_udp_ip_protocol,
output wire [15:0] m_udp_ip_header_checksum,
output wire [31:0] m_udp_ip_source_ip,
output wire [31:0] m_udp_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status
*/
output wire ip_rx_busy,
output wire ip_tx_busy,
output wire udp_rx_busy,
output wire udp_tx_busy,
output wire ip_rx_error_header_early_termination,
output wire ip_rx_error_payload_early_termination,
output wire ip_rx_error_invalid_header,
output wire ip_rx_error_invalid_checksum,
output wire ip_tx_error_payload_early_termination,
output wire ip_tx_error_arp_failed,
output wire udp_rx_error_header_early_termination,
output wire udp_rx_error_payload_early_termination,
output wire udp_tx_error_payload_early_termination,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_arp_cache
);
wire ip_rx_ip_hdr_valid;
wire ip_rx_ip_hdr_ready;
wire [47:0] ip_rx_ip_eth_dest_mac;
wire [47:0] ip_rx_ip_eth_src_mac;
wire [15:0] ip_rx_ip_eth_type;
wire [3:0] ip_rx_ip_version;
wire [3:0] ip_rx_ip_ihl;
wire [5:0] ip_rx_ip_dscp;
wire [1:0] ip_rx_ip_ecn;
wire [15:0] ip_rx_ip_length;
wire [15:0] ip_rx_ip_identification;
wire [2:0] ip_rx_ip_flags;
wire [12:0] ip_rx_ip_fragment_offset;
wire [7:0] ip_rx_ip_ttl;
wire [7:0] ip_rx_ip_protocol;
wire [15:0] ip_rx_ip_header_checksum;
wire [31:0] ip_rx_ip_source_ip;
wire [31:0] ip_rx_ip_dest_ip;
wire [63:0] ip_rx_ip_payload_axis_tdata;
wire [7:0] ip_rx_ip_payload_axis_tkeep;
wire ip_rx_ip_payload_axis_tvalid;
wire ip_rx_ip_payload_axis_tlast;
wire ip_rx_ip_payload_axis_tuser;
wire ip_rx_ip_payload_axis_tready;
wire ip_tx_ip_hdr_valid;
wire ip_tx_ip_hdr_ready;
wire [5:0] ip_tx_ip_dscp;
wire [1:0] ip_tx_ip_ecn;
wire [15:0] ip_tx_ip_length;
wire [7:0] ip_tx_ip_ttl;
wire [7:0] ip_tx_ip_protocol;
wire [31:0] ip_tx_ip_source_ip;
wire [31:0] ip_tx_ip_dest_ip;
wire [63:0] ip_tx_ip_payload_axis_tdata;
wire [7:0] ip_tx_ip_payload_axis_tkeep;
wire ip_tx_ip_payload_axis_tvalid;
wire ip_tx_ip_payload_axis_tlast;
wire ip_tx_ip_payload_axis_tuser;
wire ip_tx_ip_payload_axis_tready;
wire udp_rx_ip_hdr_valid;
wire udp_rx_ip_hdr_ready;
wire [47:0] udp_rx_ip_eth_dest_mac;
wire [47:0] udp_rx_ip_eth_src_mac;
wire [15:0] udp_rx_ip_eth_type;
wire [3:0] udp_rx_ip_version;
wire [3:0] udp_rx_ip_ihl;
wire [5:0] udp_rx_ip_dscp;
wire [1:0] udp_rx_ip_ecn;
wire [15:0] udp_rx_ip_length;
wire [15:0] udp_rx_ip_identification;
wire [2:0] udp_rx_ip_flags;
wire [12:0] udp_rx_ip_fragment_offset;
wire [7:0] udp_rx_ip_ttl;
wire [7:0] udp_rx_ip_protocol;
wire [15:0] udp_rx_ip_header_checksum;
wire [31:0] udp_rx_ip_source_ip;
wire [31:0] udp_rx_ip_dest_ip;
wire [63:0] udp_rx_ip_payload_axis_tdata;
wire [7:0] udp_rx_ip_payload_axis_tkeep;
wire udp_rx_ip_payload_axis_tvalid;
wire udp_rx_ip_payload_axis_tlast;
wire udp_rx_ip_payload_axis_tuser;
wire udp_rx_ip_payload_axis_tready;
wire udp_tx_ip_hdr_valid;
wire udp_tx_ip_hdr_ready;
wire [5:0] udp_tx_ip_dscp;
wire [1:0] udp_tx_ip_ecn;
wire [15:0] udp_tx_ip_length;
wire [7:0] udp_tx_ip_ttl;
wire [7:0] udp_tx_ip_protocol;
wire [31:0] udp_tx_ip_source_ip;
wire [31:0] udp_tx_ip_dest_ip;
wire [63:0] udp_tx_ip_payload_axis_tdata;
wire [7:0] udp_tx_ip_payload_axis_tkeep;
wire udp_tx_ip_payload_axis_tvalid;
wire udp_tx_ip_payload_axis_tlast;
wire udp_tx_ip_payload_axis_tuser;
wire udp_tx_ip_payload_axis_tready;
/*
* Input classifier (ip_protocol)
*/
wire s_select_udp = (ip_rx_ip_protocol == 8'h11);
wire s_select_ip = !s_select_udp;
reg s_select_udp_reg = 1'b0;
reg s_select_ip_reg = 1'b0;
always @(posedge clk) begin
if (rst) begin
s_select_udp_reg <= 1'b0;
s_select_ip_reg <= 1'b0;
end else begin
if (ip_rx_ip_payload_axis_tvalid) begin
if ((!s_select_udp_reg && !s_select_ip_reg) ||
(ip_rx_ip_payload_axis_tvalid && ip_rx_ip_payload_axis_tready && ip_rx_ip_payload_axis_tlast)) begin
s_select_udp_reg <= s_select_udp;
s_select_ip_reg <= s_select_ip;
end
end else begin
s_select_udp_reg <= 1'b0;
s_select_ip_reg <= 1'b0;
end
end
end
// IP frame to UDP module
assign udp_rx_ip_hdr_valid = s_select_udp && ip_rx_ip_hdr_valid;
assign udp_rx_ip_eth_dest_mac = ip_rx_ip_eth_dest_mac;
assign udp_rx_ip_eth_src_mac = ip_rx_ip_eth_src_mac;
assign udp_rx_ip_eth_type = ip_rx_ip_eth_type;
assign udp_rx_ip_version = ip_rx_ip_version;
assign udp_rx_ip_ihl = ip_rx_ip_ihl;
assign udp_rx_ip_dscp = ip_rx_ip_dscp;
assign udp_rx_ip_ecn = ip_rx_ip_ecn;
assign udp_rx_ip_length = ip_rx_ip_length;
assign udp_rx_ip_identification = ip_rx_ip_identification;
assign udp_rx_ip_flags = ip_rx_ip_flags;
assign udp_rx_ip_fragment_offset = ip_rx_ip_fragment_offset;
assign udp_rx_ip_ttl = ip_rx_ip_ttl;
assign udp_rx_ip_protocol = 8'h11;
assign udp_rx_ip_header_checksum = ip_rx_ip_header_checksum;
assign udp_rx_ip_source_ip = ip_rx_ip_source_ip;
assign udp_rx_ip_dest_ip = ip_rx_ip_dest_ip;
assign udp_rx_ip_payload_axis_tdata = ip_rx_ip_payload_axis_tdata;
assign udp_rx_ip_payload_axis_tkeep = ip_rx_ip_payload_axis_tkeep;
assign udp_rx_ip_payload_axis_tvalid = s_select_udp_reg && ip_rx_ip_payload_axis_tvalid;
assign udp_rx_ip_payload_axis_tlast = ip_rx_ip_payload_axis_tlast;
assign udp_rx_ip_payload_axis_tuser = ip_rx_ip_payload_axis_tuser;
// External IP frame output
assign m_ip_hdr_valid = s_select_ip && ip_rx_ip_hdr_valid;
assign m_ip_eth_dest_mac = ip_rx_ip_eth_dest_mac;
assign m_ip_eth_src_mac = ip_rx_ip_eth_src_mac;
assign m_ip_eth_type = ip_rx_ip_eth_type;
assign m_ip_version = ip_rx_ip_version;
assign m_ip_ihl = ip_rx_ip_ihl;
assign m_ip_dscp = ip_rx_ip_dscp;
assign m_ip_ecn = ip_rx_ip_ecn;
assign m_ip_length = ip_rx_ip_length;
assign m_ip_identification = ip_rx_ip_identification;
assign m_ip_flags = ip_rx_ip_flags;
assign m_ip_fragment_offset = ip_rx_ip_fragment_offset;
assign m_ip_ttl = ip_rx_ip_ttl;
assign m_ip_protocol = ip_rx_ip_protocol;
assign m_ip_header_checksum = ip_rx_ip_header_checksum;
assign m_ip_source_ip = ip_rx_ip_source_ip;
assign m_ip_dest_ip = ip_rx_ip_dest_ip;
assign m_ip_payload_axis_tdata = ip_rx_ip_payload_axis_tdata;
assign m_ip_payload_axis_tkeep = ip_rx_ip_payload_axis_tkeep;
assign m_ip_payload_axis_tvalid = s_select_ip_reg && ip_rx_ip_payload_axis_tvalid;
assign m_ip_payload_axis_tlast = ip_rx_ip_payload_axis_tlast;
assign m_ip_payload_axis_tuser = ip_rx_ip_payload_axis_tuser;
assign ip_rx_ip_hdr_ready = (s_select_udp && udp_rx_ip_hdr_ready) ||
(s_select_ip && m_ip_hdr_ready);
assign ip_rx_ip_payload_axis_tready = (s_select_udp_reg && udp_rx_ip_payload_axis_tready) ||
(s_select_ip_reg && m_ip_payload_axis_tready);
/*
* Output arbiter
*/
ip_arb_mux #(
.S_COUNT(2),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.ARB_TYPE_ROUND_ROBIN(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
ip_arb_mux_inst (
.clk(clk),
.rst(rst),
// IP frame inputs
.s_ip_hdr_valid({s_ip_hdr_valid, udp_tx_ip_hdr_valid}),
.s_ip_hdr_ready({s_ip_hdr_ready, udp_tx_ip_hdr_ready}),
.s_eth_dest_mac(0),
.s_eth_src_mac(0),
.s_eth_type(0),
.s_ip_version(0),
.s_ip_ihl(0),
.s_ip_dscp({s_ip_dscp, udp_tx_ip_dscp}),
.s_ip_ecn({s_ip_ecn, udp_tx_ip_ecn}),
.s_ip_length({s_ip_length, udp_tx_ip_length}),
.s_ip_identification(0),
.s_ip_flags(0),
.s_ip_fragment_offset(0),
.s_ip_ttl({s_ip_ttl, udp_tx_ip_ttl}),
.s_ip_protocol({s_ip_protocol, udp_tx_ip_protocol}),
.s_ip_header_checksum(0),
.s_ip_source_ip({s_ip_source_ip, udp_tx_ip_source_ip}),
.s_ip_dest_ip({s_ip_dest_ip, udp_tx_ip_dest_ip}),
.s_ip_payload_axis_tdata({s_ip_payload_axis_tdata, udp_tx_ip_payload_axis_tdata}),
.s_ip_payload_axis_tkeep({s_ip_payload_axis_tkeep, udp_tx_ip_payload_axis_tkeep}),
.s_ip_payload_axis_tvalid({s_ip_payload_axis_tvalid, udp_tx_ip_payload_axis_tvalid}),
.s_ip_payload_axis_tready({s_ip_payload_axis_tready, udp_tx_ip_payload_axis_tready}),
.s_ip_payload_axis_tlast({s_ip_payload_axis_tlast, udp_tx_ip_payload_axis_tlast}),
.s_ip_payload_axis_tid(0),
.s_ip_payload_axis_tdest(0),
.s_ip_payload_axis_tuser({s_ip_payload_axis_tuser, udp_tx_ip_payload_axis_tuser}),
// IP frame output
.m_ip_hdr_valid(ip_tx_ip_hdr_valid),
.m_ip_hdr_ready(ip_tx_ip_hdr_ready),
.m_eth_dest_mac(),
.m_eth_src_mac(),
.m_eth_type(),
.m_ip_version(),
.m_ip_ihl(),
.m_ip_dscp(ip_tx_ip_dscp),
.m_ip_ecn(ip_tx_ip_ecn),
.m_ip_length(ip_tx_ip_length),
.m_ip_identification(),
.m_ip_flags(),
.m_ip_fragment_offset(),
.m_ip_ttl(ip_tx_ip_ttl),
.m_ip_protocol(ip_tx_ip_protocol),
.m_ip_header_checksum(),
.m_ip_source_ip(ip_tx_ip_source_ip),
.m_ip_dest_ip(ip_tx_ip_dest_ip),
.m_ip_payload_axis_tdata(ip_tx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(ip_tx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(ip_tx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(ip_tx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(ip_tx_ip_payload_axis_tlast),
.m_ip_payload_axis_tid(),
.m_ip_payload_axis_tdest(),
.m_ip_payload_axis_tuser(ip_tx_ip_payload_axis_tuser)
);
/*
* IP stack
*/
ip_complete_64 #(
.ARP_CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT)
)
ip_complete_64_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(ip_tx_ip_hdr_valid),
.s_ip_hdr_ready(ip_tx_ip_hdr_ready),
.s_ip_dscp(ip_tx_ip_dscp),
.s_ip_ecn(ip_tx_ip_ecn),
.s_ip_length(ip_tx_ip_length),
.s_ip_ttl(ip_tx_ip_ttl),
.s_ip_protocol(ip_tx_ip_protocol),
.s_ip_source_ip(ip_tx_ip_source_ip),
.s_ip_dest_ip(ip_tx_ip_dest_ip),
.s_ip_payload_axis_tdata(ip_tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(ip_tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(ip_tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(ip_tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(ip_tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(ip_tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(ip_rx_ip_hdr_valid),
.m_ip_hdr_ready(ip_rx_ip_hdr_ready),
.m_ip_eth_dest_mac(ip_rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(ip_rx_ip_eth_src_mac),
.m_ip_eth_type(ip_rx_ip_eth_type),
.m_ip_version(ip_rx_ip_version),
.m_ip_ihl(ip_rx_ip_ihl),
.m_ip_dscp(ip_rx_ip_dscp),
.m_ip_ecn(ip_rx_ip_ecn),
.m_ip_length(ip_rx_ip_length),
.m_ip_identification(ip_rx_ip_identification),
.m_ip_flags(ip_rx_ip_flags),
.m_ip_fragment_offset(ip_rx_ip_fragment_offset),
.m_ip_ttl(ip_rx_ip_ttl),
.m_ip_protocol(ip_rx_ip_protocol),
.m_ip_header_checksum(ip_rx_ip_header_checksum),
.m_ip_source_ip(ip_rx_ip_source_ip),
.m_ip_dest_ip(ip_rx_ip_dest_ip),
.m_ip_payload_axis_tdata(ip_rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(ip_rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(ip_rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(ip_rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(ip_rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(ip_rx_ip_payload_axis_tuser),
// Status
.rx_busy(ip_rx_busy),
.tx_busy(ip_tx_busy),
.rx_error_header_early_termination(ip_rx_error_header_early_termination),
.rx_error_payload_early_termination(ip_rx_error_payload_early_termination),
.rx_error_invalid_header(ip_rx_error_invalid_header),
.rx_error_invalid_checksum(ip_rx_error_invalid_checksum),
.tx_error_payload_early_termination(ip_tx_error_payload_early_termination),
.tx_error_arp_failed(ip_tx_error_arp_failed),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(clear_arp_cache)
);
/*
* UDP interface
*/
udp_64 #(
.CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.CHECKSUM_PAYLOAD_FIFO_DEPTH(UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH),
.CHECKSUM_HEADER_FIFO_DEPTH(UDP_CHECKSUM_HEADER_FIFO_DEPTH)
)
udp_64_inst (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(udp_rx_ip_hdr_valid),
.s_ip_hdr_ready(udp_rx_ip_hdr_ready),
.s_ip_eth_dest_mac(udp_rx_ip_eth_dest_mac),
.s_ip_eth_src_mac(udp_rx_ip_eth_src_mac),
.s_ip_eth_type(udp_rx_ip_eth_type),
.s_ip_version(udp_rx_ip_version),
.s_ip_ihl(udp_rx_ip_ihl),
.s_ip_dscp(udp_rx_ip_dscp),
.s_ip_ecn(udp_rx_ip_ecn),
.s_ip_length(udp_rx_ip_length),
.s_ip_identification(udp_rx_ip_identification),
.s_ip_flags(udp_rx_ip_flags),
.s_ip_fragment_offset(udp_rx_ip_fragment_offset),
.s_ip_ttl(udp_rx_ip_ttl),
.s_ip_protocol(udp_rx_ip_protocol),
.s_ip_header_checksum(udp_rx_ip_header_checksum),
.s_ip_source_ip(udp_rx_ip_source_ip),
.s_ip_dest_ip(udp_rx_ip_dest_ip),
.s_ip_payload_axis_tdata(udp_rx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(udp_rx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(udp_rx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(udp_rx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(udp_rx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(udp_rx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(udp_tx_ip_hdr_valid),
.m_ip_hdr_ready(udp_tx_ip_hdr_ready),
.m_ip_eth_dest_mac(),
.m_ip_eth_src_mac(),
.m_ip_eth_type(),
.m_ip_version(),
.m_ip_ihl(),
.m_ip_dscp(udp_tx_ip_dscp),
.m_ip_ecn(udp_tx_ip_ecn),
.m_ip_length(udp_tx_ip_length),
.m_ip_identification(),
.m_ip_flags(),
.m_ip_fragment_offset(),
.m_ip_ttl(udp_tx_ip_ttl),
.m_ip_protocol(udp_tx_ip_protocol),
.m_ip_header_checksum(),
.m_ip_source_ip(udp_tx_ip_source_ip),
.m_ip_dest_ip(udp_tx_ip_dest_ip),
.m_ip_payload_axis_tdata(udp_tx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(udp_tx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(udp_tx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(udp_tx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(udp_tx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(udp_tx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_udp_eth_dest_mac(48'd0),
.s_udp_eth_src_mac(48'd0),
.s_udp_eth_type(16'd0),
.s_udp_ip_version(4'd0),
.s_udp_ip_ihl(4'd0),
.s_udp_ip_dscp(s_udp_ip_dscp),
.s_udp_ip_ecn(s_udp_ip_ecn),
.s_udp_ip_identification(16'd0),
.s_udp_ip_flags(3'd0),
.s_udp_ip_fragment_offset(13'd0),
.s_udp_ip_ttl(s_udp_ip_ttl),
.s_udp_ip_header_checksum(16'd0),
.s_udp_ip_source_ip(s_udp_ip_source_ip),
.s_udp_ip_dest_ip(s_udp_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_length(s_udp_length),
.s_udp_checksum(s_udp_checksum),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_udp_eth_dest_mac(m_udp_eth_dest_mac),
.m_udp_eth_src_mac(m_udp_eth_src_mac),
.m_udp_eth_type(m_udp_eth_type),
.m_udp_ip_version(m_udp_ip_version),
.m_udp_ip_ihl(m_udp_ip_ihl),
.m_udp_ip_dscp(m_udp_ip_dscp),
.m_udp_ip_ecn(m_udp_ip_ecn),
.m_udp_ip_length(m_udp_ip_length),
.m_udp_ip_identification(m_udp_ip_identification),
.m_udp_ip_flags(m_udp_ip_flags),
.m_udp_ip_fragment_offset(m_udp_ip_fragment_offset),
.m_udp_ip_ttl(m_udp_ip_ttl),
.m_udp_ip_protocol(m_udp_ip_protocol),
.m_udp_ip_header_checksum(m_udp_ip_header_checksum),
.m_udp_ip_source_ip(m_udp_ip_source_ip),
.m_udp_ip_dest_ip(m_udp_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
// Status
.rx_busy(udp_rx_busy),
.tx_busy(udp_tx_busy),
.rx_error_header_early_termination(udp_rx_error_header_early_termination),
.rx_error_payload_early_termination(udp_rx_error_payload_early_termination),
.tx_error_payload_early_termination(udp_tx_error_payload_early_termination)
);
endmodule
`resetall

564
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/udp_ip_rx_64.v Executable file
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@@ -0,0 +1,564 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* UDP ethernet frame receiver (IP frame in, UDP frame out, 64 bit datapath)
*/
module udp_ip_rx_64
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_payload_early_termination
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives an IP frame with header fields in parallel and payload on
an AXI stream interface, decodes and strips the UDP header fields, then
produces the header fields in parallel along with the UDP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_hdr_word_0;
reg store_last_word;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg [15:0] m_udp_source_port_reg = 16'd0;
reg [15:0] m_udp_dest_port_reg = 16'd0;
reg [15:0] m_udp_length_reg = 16'd0;
reg [15:0] m_udp_checksum_reg = 16'd0;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [63:0] m_udp_payload_axis_tdata_int;
reg [7:0] m_udp_payload_axis_tkeep_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
state_next = STATE_IDLE;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
store_ip_hdr = 1'b0;
store_hdr_word_0 = 1'b0;
store_last_word = 1'b0;
word_count_next = word_count_reg;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
m_udp_payload_axis_tdata_int = 64'd0;
m_udp_payload_axis_tkeep_int = 8'd0;
m_udp_payload_axis_tvalid_int = 1'b0;
m_udp_payload_axis_tlast_int = 1'b0;
m_udp_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b1;
store_ip_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
s_ip_payload_axis_tready_next = 1'b1;
word_count_next = {s_ip_payload_axis_tdata[39:32], s_ip_payload_axis_tdata[47:40]} - 16'd8;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer in - store it
state_next = STATE_READ_HEADER;
store_hdr_word_0 = 1'b1;
m_udp_hdr_valid_next = 1'b1;
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
state_next = STATE_READ_PAYLOAD;
if (s_ip_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
m_udp_hdr_valid_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = s_ip_payload_axis_tdata;
m_udp_payload_axis_tkeep_int = s_ip_payload_axis_tkeep;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
store_last_word = 1'b1;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
m_udp_payload_axis_tvalid_int = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_udp_payload_axis_tkeep_int = s_ip_payload_axis_tkeep & count2keep(word_count_reg);
if (s_ip_payload_axis_tlast) begin
if (keep2count(s_ip_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_udp_payload_axis_tuser_int = 1'b1;
end
s_ip_payload_axis_tready_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
m_udp_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
if (s_ip_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_udp_payload_axis_tuser_int = 1'b1;
s_ip_payload_axis_tready_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = last_word_data_reg;
m_udp_payload_axis_tkeep_int = last_word_keep_reg;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
m_udp_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
s_ip_payload_axis_tready_next = 1'b1;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_udp_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
busy_reg <= state_next != STATE_IDLE;
end
word_count_reg <= word_count_next;
// datapath
if (store_ip_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
m_ip_version_reg <= s_ip_version;
m_ip_ihl_reg <= s_ip_ihl;
m_ip_dscp_reg <= s_ip_dscp;
m_ip_ecn_reg <= s_ip_ecn;
m_ip_length_reg <= s_ip_length;
m_ip_identification_reg <= s_ip_identification;
m_ip_flags_reg <= s_ip_flags;
m_ip_fragment_offset_reg <= s_ip_fragment_offset;
m_ip_ttl_reg <= s_ip_ttl;
m_ip_protocol_reg <= s_ip_protocol;
m_ip_header_checksum_reg <= s_ip_header_checksum;
m_ip_source_ip_reg <= s_ip_source_ip;
m_ip_dest_ip_reg <= s_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= m_udp_payload_axis_tdata_int;
last_word_keep_reg <= m_udp_payload_axis_tkeep_int;
end
if (store_hdr_word_0) begin
m_udp_source_port_reg[15: 8] <= s_ip_payload_axis_tdata[ 7: 0];
m_udp_source_port_reg[ 7: 0] <= s_ip_payload_axis_tdata[15: 8];
m_udp_dest_port_reg[15: 8] <= s_ip_payload_axis_tdata[23:16];
m_udp_dest_port_reg[ 7: 0] <= s_ip_payload_axis_tdata[31:24];
m_udp_length_reg[15: 8] <= s_ip_payload_axis_tdata[39:32];
m_udp_length_reg[ 7: 0] <= s_ip_payload_axis_tdata[47:40];
m_udp_checksum_reg[15: 8] <= s_ip_payload_axis_tdata[55:48];
m_udp_checksum_reg[ 7: 0] <= s_ip_payload_axis_tdata[63:56];
end
end
// output datapath logic
reg [63:0] m_udp_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_udp_payload_axis_tkeep_reg = 8'd0;
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg m_udp_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_udp_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_udp_payload_axis_tkeep_reg = 8'd0;
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg temp_m_udp_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_udp_payload_int_to_output;
reg store_udp_payload_int_to_temp;
reg store_udp_payload_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tkeep = m_udp_payload_axis_tkeep_reg;
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_udp_payload_int_to_output = 1'b0;
store_udp_payload_int_to_temp = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
// datapath
if (store_udp_payload_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_udp_payload_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tkeep_reg <= temp_m_udp_payload_axis_tkeep_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_udp_payload_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/udp_ip_tx_64.v Executable file
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* UDP ethernet frame transmitter (UDP frame in, IP frame out, 64-bit datapath)
*/
module udp_ip_tx_64
(
input wire clk,
input wire rst,
/*
* UDP frame input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [63:0] s_udp_payload_axis_tdata,
input wire [7:0] s_udp_payload_axis_tkeep,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_payload_early_termination
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives a UDP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the IP headers, and transmits the complete IP payload on an AXI interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_PAYLOAD = 3'd2,
STATE_WRITE_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_udp_hdr;
reg store_last_word;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg [15:0] udp_source_port_reg = 16'd0;
reg [15:0] udp_dest_port_reg = 16'd0;
reg [15:0] udp_length_reg = 16'd0;
reg [15:0] udp_checksum_reg = 16'd0;
reg s_udp_hdr_ready_reg = 1'b0, s_udp_hdr_ready_next;
reg s_udp_payload_axis_tready_reg = 1'b0, s_udp_payload_axis_tready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg busy_reg = 1'b0;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [63:0] m_ip_payload_axis_tdata_int;
reg [7:0] m_ip_payload_axis_tkeep_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign s_udp_payload_axis_tready = s_udp_payload_axis_tready_reg;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
state_next = STATE_IDLE;
s_udp_hdr_ready_next = 1'b0;
s_udp_payload_axis_tready_next = 1'b0;
store_udp_hdr = 1'b0;
store_last_word = 1'b0;
word_count_next = word_count_reg;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
error_payload_early_termination_next = 1'b0;
m_ip_payload_axis_tdata_int = 64'd0;
m_ip_payload_axis_tkeep_int = 8'd0;
m_ip_payload_axis_tvalid_int = 1'b0;
m_ip_payload_axis_tlast_int = 1'b0;
m_ip_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
word_count_next = s_udp_length - 16'd8;
if (s_udp_hdr_ready && s_udp_hdr_valid) begin
store_udp_hdr = 1'b1;
s_udp_hdr_ready_next = 1'b0;
m_ip_hdr_valid_next = 1'b1;
state_next = STATE_WRITE_HEADER;
if (m_ip_payload_axis_tready_int_reg) begin
m_ip_payload_axis_tvalid_int = 1'b1;
m_ip_payload_axis_tdata_int[ 7: 0] = s_udp_source_port[15: 8];
m_ip_payload_axis_tdata_int[15: 8] = s_udp_source_port[ 7: 0];
m_ip_payload_axis_tdata_int[23:16] = s_udp_dest_port[15: 8];
m_ip_payload_axis_tdata_int[31:24] = s_udp_dest_port[ 7: 0];
m_ip_payload_axis_tdata_int[39:32] = s_udp_length[15: 8];
m_ip_payload_axis_tdata_int[47:40] = s_udp_length[ 7: 0];
m_ip_payload_axis_tdata_int[55:48] = s_udp_checksum[15: 8];
m_ip_payload_axis_tdata_int[63:56] = s_udp_checksum[ 7: 0];
m_ip_payload_axis_tkeep_int = 8'hff;
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// write header state
if (m_ip_payload_axis_tready_int_reg) begin
// word transfer out
m_ip_payload_axis_tvalid_int = 1'b1;
m_ip_payload_axis_tdata_int[ 7: 0] = udp_source_port_reg[15: 8];
m_ip_payload_axis_tdata_int[15: 8] = udp_source_port_reg[ 7: 0];
m_ip_payload_axis_tdata_int[23:16] = udp_dest_port_reg[15: 8];
m_ip_payload_axis_tdata_int[31:24] = udp_dest_port_reg[ 7: 0];
m_ip_payload_axis_tdata_int[39:32] = udp_length_reg[15: 8];
m_ip_payload_axis_tdata_int[47:40] = udp_length_reg[ 7: 0];
m_ip_payload_axis_tdata_int[55:48] = udp_checksum_reg[15: 8];
m_ip_payload_axis_tdata_int[63:56] = udp_checksum_reg[ 7: 0];
m_ip_payload_axis_tkeep_int = 8'hff;
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_PAYLOAD: begin
// write payload
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
m_ip_payload_axis_tdata_int = s_udp_payload_axis_tdata;
m_ip_payload_axis_tkeep_int = s_udp_payload_axis_tkeep;
m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast;
m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser;
store_last_word = 1'b1;
if (m_ip_payload_axis_tready_int_reg && s_udp_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
m_ip_payload_axis_tvalid_int = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_ip_payload_axis_tkeep_int = count2keep(word_count_reg);
if (s_udp_payload_axis_tlast) begin
if (keep2count(s_udp_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
end
s_udp_payload_axis_tready_next = 1'b0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
m_ip_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
if (s_udp_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
s_udp_payload_axis_tready_next = 1'b0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
m_ip_payload_axis_tdata_int = last_word_data_reg;
m_ip_payload_axis_tkeep_int = last_word_keep_reg;
m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast;
m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser;
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
m_ip_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
s_udp_payload_axis_tready_next = 1'b1;
if (s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_udp_hdr_ready_reg <= 1'b0;
s_udp_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
s_udp_payload_axis_tready_reg <= s_udp_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
error_payload_early_termination_reg <= error_payload_early_termination_next;
end
word_count_reg <= word_count_next;
// datapath
if (store_udp_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
m_ip_version_reg <= s_ip_version;
m_ip_ihl_reg <= s_ip_ihl;
m_ip_dscp_reg <= s_ip_dscp;
m_ip_ecn_reg <= s_ip_ecn;
m_ip_length_reg <= s_udp_length + 20;
m_ip_identification_reg <= s_ip_identification;
m_ip_flags_reg <= s_ip_flags;
m_ip_fragment_offset_reg <= s_ip_fragment_offset;
m_ip_ttl_reg <= s_ip_ttl;
m_ip_protocol_reg <= s_ip_protocol;
m_ip_header_checksum_reg <= s_ip_header_checksum;
m_ip_source_ip_reg <= s_ip_source_ip;
m_ip_dest_ip_reg <= s_ip_dest_ip;
udp_source_port_reg <= s_udp_source_port;
udp_dest_port_reg <= s_udp_dest_port;
udp_length_reg <= s_udp_length;
udp_checksum_reg <= s_udp_checksum;
end
if (store_last_word) begin
last_word_data_reg <= m_ip_payload_axis_tdata_int;
last_word_keep_reg <= m_ip_payload_axis_tkeep_int;
end
end
// output datapath logic
reg [63:0] m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_ip_payload_axis_tkeep_reg = 8'd0;
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg m_ip_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_ip_payload_axis_tkeep_reg = 8'd0;
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg temp_m_ip_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_ip_payload_int_to_output;
reg store_ip_payload_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tkeep = m_ip_payload_axis_tkeep_reg;
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_ip_payload_int_to_output = 1'b0;
store_ip_payload_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
// datapath
if (store_ip_payload_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_ip_payload_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/xgmii_baser_dec_64.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XGMII 10GBASE-R decoder
*/
module xgmii_baser_dec_64 #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded input
*/
input wire [DATA_WIDTH-1:0] encoded_rx_data,
input wire [HDR_WIDTH-1:0] encoded_rx_hdr,
/*
* XGMII interface
*/
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* Status
*/
output wire rx_bad_block,
output wire rx_sequence_error
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
reg [DATA_WIDTH-1:0] decoded_ctrl;
reg [CTRL_WIDTH-1:0] decode_err;
reg [DATA_WIDTH-1:0] xgmii_rxd_reg = {DATA_WIDTH{1'b0}}, xgmii_rxd_next;
reg [CTRL_WIDTH-1:0] xgmii_rxc_reg = {CTRL_WIDTH{1'b0}}, xgmii_rxc_next;
reg rx_bad_block_reg = 1'b0, rx_bad_block_next;
reg rx_sequence_error_reg = 1'b0, rx_sequence_error_next;
reg frame_reg = 1'b0, frame_next;
assign xgmii_rxd = xgmii_rxd_reg;
assign xgmii_rxc = xgmii_rxc_reg;
assign rx_bad_block = rx_bad_block_reg;
assign rx_sequence_error = rx_sequence_error_reg;
integer i;
always @* begin
xgmii_rxd_next = {8{XGMII_ERROR}};
xgmii_rxc_next = 8'hff;
rx_bad_block_next = 1'b0;
rx_sequence_error_next = 1'b0;
frame_next = frame_reg;
for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
case (encoded_rx_data[7*i+8 +: 7])
CTRL_IDLE: begin
decoded_ctrl[8*i +: 8] = XGMII_IDLE;
decode_err[i] = 1'b0;
end
CTRL_LPI: begin
decoded_ctrl[8*i +: 8] = XGMII_LPI;
decode_err[i] = 1'b0;
end
CTRL_ERROR: begin
decoded_ctrl[8*i +: 8] = XGMII_ERROR;
decode_err[i] = 1'b0;
end
CTRL_RES_0: begin
decoded_ctrl[8*i +: 8] = XGMII_RES_0;
decode_err[i] = 1'b0;
end
CTRL_RES_1: begin
decoded_ctrl[8*i +: 8] = XGMII_RES_1;
decode_err[i] = 1'b0;
end
CTRL_RES_2: begin
decoded_ctrl[8*i +: 8] = XGMII_RES_2;
decode_err[i] = 1'b0;
end
CTRL_RES_3: begin
decoded_ctrl[8*i +: 8] = XGMII_RES_3;
decode_err[i] = 1'b0;
end
CTRL_RES_4: begin
decoded_ctrl[8*i +: 8] = XGMII_RES_4;
decode_err[i] = 1'b0;
end
CTRL_RES_5: begin
decoded_ctrl[8*i +: 8] = XGMII_RES_5;
decode_err[i] = 1'b0;
end
default: begin
decoded_ctrl[8*i +: 8] = XGMII_ERROR;
decode_err[i] = 1'b1;
end
endcase
end
// use only four bits of block type for reduced fanin
if (encoded_rx_hdr[0] == 0) begin
xgmii_rxd_next = encoded_rx_data;
xgmii_rxc_next = 8'h00;
rx_bad_block_next = 1'b0;
end else begin
case (encoded_rx_data[7:4])
BLOCK_TYPE_CTRL[7:4]: begin
// C7 C6 C5 C4 C3 C2 C1 C0 BT
xgmii_rxd_next = decoded_ctrl;
xgmii_rxc_next = 8'hff;
rx_bad_block_next = decode_err != 0;
end
BLOCK_TYPE_OS_4[7:4]: begin
// D7 D6 D5 O4 C3 C2 C1 C0 BT
xgmii_rxd_next[31:0] = decoded_ctrl[31:0];
xgmii_rxc_next[3:0] = 4'hf;
xgmii_rxd_next[63:40] = encoded_rx_data[63:40];
xgmii_rxc_next[7:4] = 4'h1;
if (encoded_rx_data[39:36] == O_SEQ_OS) begin
xgmii_rxd_next[39:32] = XGMII_SEQ_OS;
rx_bad_block_next = decode_err[3:0] != 0;
end else begin
xgmii_rxd_next[39:32] = XGMII_ERROR;
rx_bad_block_next = 1'b1;
end
end
BLOCK_TYPE_START_4[7:4]: begin
// D7 D6 D5 C3 C2 C1 C0 BT
xgmii_rxd_next = {encoded_rx_data[63:40], XGMII_START, decoded_ctrl[31:0]};
xgmii_rxc_next = 8'h1f;
rx_bad_block_next = decode_err[3:0] != 0;
rx_sequence_error_next = frame_reg;
frame_next = 1'b1;
end
BLOCK_TYPE_OS_START[7:4]: begin
// D7 D6 D5 O0 D3 D2 D1 BT
xgmii_rxd_next[31:8] = encoded_rx_data[31:8];
xgmii_rxc_next[3:0] = 4'hf;
if (encoded_rx_data[35:32] == O_SEQ_OS) begin
xgmii_rxd_next[7:0] = XGMII_SEQ_OS;
rx_bad_block_next = 1'b0;
end else begin
xgmii_rxd_next[7:0] = XGMII_ERROR;
rx_bad_block_next = 1'b1;
end
xgmii_rxd_next[63:32] = {encoded_rx_data[63:40], XGMII_START};
xgmii_rxc_next[7:4] = 4'h1;
rx_sequence_error_next = frame_reg;
frame_next = 1'b1;
end
BLOCK_TYPE_OS_04[7:4]: begin
// D7 D6 D5 O4 O0 D3 D2 D1 BT
rx_bad_block_next = 1'b0;
xgmii_rxd_next[31:8] = encoded_rx_data[31:8];
xgmii_rxc_next[3:0] = 4'h1;
if (encoded_rx_data[35:32] == O_SEQ_OS) begin
xgmii_rxd_next[7:0] = XGMII_SEQ_OS;
end else begin
xgmii_rxd_next[7:0] = XGMII_ERROR;
rx_bad_block_next = 1'b1;
end
xgmii_rxd_next[63:40] = encoded_rx_data[63:40];
xgmii_rxc_next[7:4] = 4'h1;
if (encoded_rx_data[39:36] == O_SEQ_OS) begin
xgmii_rxd_next[39:32] = XGMII_SEQ_OS;
end else begin
xgmii_rxd_next[39:32] = XGMII_ERROR;
rx_bad_block_next = 1'b1;
end
end
BLOCK_TYPE_START_0[7:4]: begin
// D7 D6 D5 D4 D3 D2 D1 BT
xgmii_rxd_next = {encoded_rx_data[63:8], XGMII_START};
xgmii_rxc_next = 8'h01;
rx_bad_block_next = 1'b0;
rx_sequence_error_next = frame_reg;
frame_next = 1'b1;
end
BLOCK_TYPE_OS_0[7:4]: begin
// C7 C6 C5 C4 O0 D3 D2 D1 BT
xgmii_rxd_next[31:8] = encoded_rx_data[31:8];
xgmii_rxc_next[3:0] = 4'h1;
if (encoded_rx_data[35:32] == O_SEQ_OS) begin
xgmii_rxd_next[7:0] = XGMII_SEQ_OS;
rx_bad_block_next = decode_err[7:4] != 0;
end else begin
xgmii_rxd_next[7:0] = XGMII_ERROR;
rx_bad_block_next = 1'b1;
end
xgmii_rxd_next[63:32] = decoded_ctrl[63:32];
xgmii_rxc_next[7:4] = 4'hf;
end
BLOCK_TYPE_TERM_0[7:4]: begin
// C7 C6 C5 C4 C3 C2 C1 BT
xgmii_rxd_next = {decoded_ctrl[63:8], XGMII_TERM};
xgmii_rxc_next = 8'hff;
rx_bad_block_next = decode_err[7:1] != 0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
BLOCK_TYPE_TERM_1[7:4]: begin
// C7 C6 C5 C4 C3 C2 D0 BT
xgmii_rxd_next = {decoded_ctrl[63:16], XGMII_TERM, encoded_rx_data[15:8]};
xgmii_rxc_next = 8'hfe;
rx_bad_block_next = decode_err[7:2] != 0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
BLOCK_TYPE_TERM_2[7:4]: begin
// C7 C6 C5 C4 C3 D1 D0 BT
xgmii_rxd_next = {decoded_ctrl[63:24], XGMII_TERM, encoded_rx_data[23:8]};
xgmii_rxc_next = 8'hfc;
rx_bad_block_next = decode_err[7:3] != 0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
BLOCK_TYPE_TERM_3[7:4]: begin
// C7 C6 C5 C4 D2 D1 D0 BT
xgmii_rxd_next = {decoded_ctrl[63:32], XGMII_TERM, encoded_rx_data[31:8]};
xgmii_rxc_next = 8'hf8;
rx_bad_block_next = decode_err[7:4] != 0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
BLOCK_TYPE_TERM_4[7:4]: begin
// C7 C6 C5 D3 D2 D1 D0 BT
xgmii_rxd_next = {decoded_ctrl[63:40], XGMII_TERM, encoded_rx_data[39:8]};
xgmii_rxc_next = 8'hf0;
rx_bad_block_next = decode_err[7:5] != 0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
BLOCK_TYPE_TERM_5[7:4]: begin
// C7 C6 D4 D3 D2 D1 D0 BT
xgmii_rxd_next = {decoded_ctrl[63:48], XGMII_TERM, encoded_rx_data[47:8]};
xgmii_rxc_next = 8'he0;
rx_bad_block_next = decode_err[7:6] != 0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
BLOCK_TYPE_TERM_6[7:4]: begin
// C7 D5 D4 D3 D2 D1 D0 BT
xgmii_rxd_next = {decoded_ctrl[63:56], XGMII_TERM, encoded_rx_data[55:8]};
xgmii_rxc_next = 8'hc0;
rx_bad_block_next = decode_err[7] != 0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
BLOCK_TYPE_TERM_7[7:4]: begin
// D6 D5 D4 D3 D2 D1 D0 BT
xgmii_rxd_next = {XGMII_TERM, encoded_rx_data[63:8]};
xgmii_rxc_next = 8'h80;
rx_bad_block_next = 1'b0;
rx_sequence_error_next = !frame_reg;
frame_next = 1'b0;
end
default: begin
// invalid block type
xgmii_rxd_next = {8{XGMII_ERROR}};
xgmii_rxc_next = 8'hff;
rx_bad_block_next = 1'b1;
end
endcase
end
// check all block type bits to detect bad encodings
if (encoded_rx_hdr == SYNC_DATA) begin
end else if (encoded_rx_hdr == SYNC_CTRL) begin
case (encoded_rx_data[7:0])
BLOCK_TYPE_CTRL: begin end
BLOCK_TYPE_OS_4: begin end
BLOCK_TYPE_START_4: begin end
BLOCK_TYPE_OS_START: begin end
BLOCK_TYPE_OS_04: begin end
BLOCK_TYPE_START_0: begin end
BLOCK_TYPE_OS_0: begin end
BLOCK_TYPE_TERM_0: begin end
BLOCK_TYPE_TERM_1: begin end
BLOCK_TYPE_TERM_2: begin end
BLOCK_TYPE_TERM_3: begin end
BLOCK_TYPE_TERM_4: begin end
BLOCK_TYPE_TERM_5: begin end
BLOCK_TYPE_TERM_6: begin end
BLOCK_TYPE_TERM_7: begin end
default: begin
// invalid block type
xgmii_rxd_next = {8{XGMII_ERROR}};
xgmii_rxc_next = 8'hff;
rx_bad_block_next = 1'b1;
end
endcase
end else begin
// invalid header
xgmii_rxd_next = {8{XGMII_ERROR}};
xgmii_rxc_next = 8'hff;
rx_bad_block_next = 1'b1;
end
end
always @(posedge clk) begin
xgmii_rxd_reg <= xgmii_rxd_next;
xgmii_rxc_reg <= xgmii_rxc_next;
rx_bad_block_reg <= rx_bad_block_next;
rx_sequence_error_reg <= rx_sequence_error_next;
frame_reg <= frame_next;
if (rst) begin
frame_reg <= 1'b0;
end
end
endmodule
`resetall

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radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/xgmii_baser_enc_64.v Executable file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XGMII 10GBASE-R encoder
*/
module xgmii_baser_enc_64 #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_tx_data,
output wire [HDR_WIDTH-1:0] encoded_tx_hdr,
/*
* Status
*/
output wire tx_bad_block
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
reg [DATA_WIDTH*7/8-1:0] encoded_ctrl;
reg [CTRL_WIDTH-1:0] encode_err;
reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {DATA_WIDTH{1'b0}}, encoded_tx_data_next;
reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = {HDR_WIDTH{1'b0}}, encoded_tx_hdr_next;
reg tx_bad_block_reg = 1'b0, tx_bad_block_next;
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign tx_bad_block = tx_bad_block_reg;
integer i;
always @* begin
tx_bad_block_next = 1'b0;
for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
if (xgmii_txc[i]) begin
// control
case (xgmii_txd[8*i +: 8])
XGMII_IDLE: begin
encoded_ctrl[7*i +: 7] = CTRL_IDLE;
encode_err[i] = 1'b0;
end
XGMII_LPI: begin
encoded_ctrl[7*i +: 7] = CTRL_LPI;
encode_err[i] = 1'b0;
end
XGMII_ERROR: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b0;
end
XGMII_RES_0: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_0;
encode_err[i] = 1'b0;
end
XGMII_RES_1: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_1;
encode_err[i] = 1'b0;
end
XGMII_RES_2: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_2;
encode_err[i] = 1'b0;
end
XGMII_RES_3: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_3;
encode_err[i] = 1'b0;
end
XGMII_RES_4: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_4;
encode_err[i] = 1'b0;
end
XGMII_RES_5: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_5;
encode_err[i] = 1'b0;
end
default: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
endcase
end else begin
// data (always invalid as control)
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
end
if (xgmii_txc == 8'h00) begin
encoded_tx_data_next = xgmii_txd;
encoded_tx_hdr_next = SYNC_DATA;
tx_bad_block_next = 1'b0;
end else begin
if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_SEQ_OS) begin
// ordered set in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, encoded_ctrl[27:0], BLOCK_TYPE_OS_4};
tx_bad_block_next = encode_err[3:0] != 0;
end else if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_START) begin
// start in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, encoded_ctrl[27:0], BLOCK_TYPE_START_4};
tx_bad_block_next = encode_err[3:0] != 0;
end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_START) begin
// ordered set in lane 0, start in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_START};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_SEQ_OS) begin
// ordered set in lane 0 and lane 4
encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_04};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'h01 && xgmii_txd[7:0] == XGMII_START) begin
// start in lane 0
encoded_tx_data_next = {xgmii_txd[63:8], BLOCK_TYPE_START_0};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'hf1 && xgmii_txd[7:0] == XGMII_SEQ_OS) begin
// ordered set in lane 0
encoded_tx_data_next = {encoded_ctrl[55:28], O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_0};
tx_bad_block_next = encode_err[7:4] != 0;
end else if (xgmii_txc == 8'hff && xgmii_txd[7:0] == XGMII_TERM) begin
// terminate in lane 0
encoded_tx_data_next = {encoded_ctrl[55:7], 7'd0, BLOCK_TYPE_TERM_0};
tx_bad_block_next = encode_err[7:1] != 0;
end else if (xgmii_txc == 8'hfe && xgmii_txd[15:8] == XGMII_TERM) begin
// terminate in lane 1
encoded_tx_data_next = {encoded_ctrl[55:14], 6'd0, xgmii_txd[7:0], BLOCK_TYPE_TERM_1};
tx_bad_block_next = encode_err[7:2] != 0;
end else if (xgmii_txc == 8'hfc && xgmii_txd[23:16] == XGMII_TERM) begin
// terminate in lane 2
encoded_tx_data_next = {encoded_ctrl[55:21], 5'd0, xgmii_txd[15:0], BLOCK_TYPE_TERM_2};
tx_bad_block_next = encode_err[7:3] != 0;
end else if (xgmii_txc == 8'hf8 && xgmii_txd[31:24] == XGMII_TERM) begin
// terminate in lane 3
encoded_tx_data_next = {encoded_ctrl[55:28], 4'd0, xgmii_txd[23:0], BLOCK_TYPE_TERM_3};
tx_bad_block_next = encode_err[7:4] != 0;
end else if (xgmii_txc == 8'hf0 && xgmii_txd[39:32] == XGMII_TERM) begin
// terminate in lane 4
encoded_tx_data_next = {encoded_ctrl[55:35], 3'd0, xgmii_txd[31:0], BLOCK_TYPE_TERM_4};
tx_bad_block_next = encode_err[7:5] != 0;
end else if (xgmii_txc == 8'he0 && xgmii_txd[47:40] == XGMII_TERM) begin
// terminate in lane 5
encoded_tx_data_next = {encoded_ctrl[55:42], 2'd0, xgmii_txd[39:0], BLOCK_TYPE_TERM_5};
tx_bad_block_next = encode_err[7:6] != 0;
end else if (xgmii_txc == 8'hc0 && xgmii_txd[55:48] == XGMII_TERM) begin
// terminate in lane 6
encoded_tx_data_next = {encoded_ctrl[55:49], 1'd0, xgmii_txd[47:0], BLOCK_TYPE_TERM_6};
tx_bad_block_next = encode_err[7] != 0;
end else if (xgmii_txc == 8'h80 && xgmii_txd[63:56] == XGMII_TERM) begin
// terminate in lane 7
encoded_tx_data_next = {xgmii_txd[55:0], BLOCK_TYPE_TERM_7};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'hff) begin
// all control
encoded_tx_data_next = {encoded_ctrl, BLOCK_TYPE_CTRL};
tx_bad_block_next = encode_err != 0;
end else begin
// no corresponding block format
encoded_tx_data_next = {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
tx_bad_block_next = 1'b1;
end
encoded_tx_hdr_next = SYNC_CTRL;
end
end
always @(posedge clk) begin
encoded_tx_data_reg <= encoded_tx_data_next;
encoded_tx_hdr_reg <= encoded_tx_hdr_next;
tx_bad_block_reg <= tx_bad_block_next;
end
endmodule
`resetall

367
radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v Executable file
View File

@@ -0,0 +1,367 @@
`resetall
`timescale 1ns / 1ps
`default_nettype none
module waveform_gen #
(
parameter CTRL_REG_ADDR = 32'h00000000,
parameter NUM_SAMPLES_REG_ADDR = 32'h00000004,
parameter START_SAMPLE_REG_ADDR = 32'h00000008,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
)
(
input wire clk,
// AXI4L Config Interface
axi4l_intf.slave ctrl_if,
input wire start_of_pulse,
input wire [14:0] dac0_wf_bram_addr,
input wire dac0_wf_bram_clk,
input wire [31:0] dac0_wf_bram_din,
output wire [31:0] dac0_wf_bram_dout,
input wire dac0_wf_bram_en,
input wire dac0_wf_bram_rst,
input wire [3:0] dac0_wf_bram_we,
input wire [14:0] dac1_wf_bram_addr,
input wire dac1_wf_bram_clk,
input wire [31:0] dac1_wf_bram_din,
output wire [31:0] dac1_wf_bram_dout,
input wire dac1_wf_bram_en,
input wire dac1_wf_bram_rst,
input wire [3:0] dac1_wf_bram_we,
input wire [14:0] dac2_wf_bram_addr,
input wire dac2_wf_bram_clk,
input wire [31:0] dac2_wf_bram_din,
output wire [31:0] dac2_wf_bram_dout,
input wire dac2_wf_bram_en,
input wire dac2_wf_bram_rst,
input wire [3:0] dac2_wf_bram_we,
input wire [14:0] dac3_wf_bram_addr,
input wire dac3_wf_bram_clk,
input wire [31:0] dac3_wf_bram_din,
output wire [31:0] dac3_wf_bram_dout,
input wire dac3_wf_bram_en,
input wire dac3_wf_bram_rst,
input wire [3:0] dac3_wf_bram_we,
output wire [511:0] jesd_tx
);
reg [15:0] dac0_bram_addr;
wire [127:0] dac0_bram_dout;
reg [15:0] dac1_bram_addr;
wire [127:0] dac1_bram_dout;
reg [15:0] dac2_bram_addr;
wire [127:0] dac2_bram_dout;
reg [15:0] dac3_bram_addr;
wire [127:0] dac3_bram_dout;
// ------------------------------
// AXIL Decode
// ------------------------------
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
wire rden;
wire wren;
wire [AXI_DATA_WIDTH-1 : 0] wdata;
reg [AXI_DATA_WIDTH-1 : 0] rdata;
axil_slave
# (
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH)
) axil_slave_i
(
// AXIL Slave
.S_AXI_ACLK(ctrl_if.clk),
.S_AXI_ARESETN(ctrl_if.resetn),
.S_AXI_AWADDR(ctrl_if.awaddr),
.S_AXI_AWPROT(ctrl_if.awprot),
.S_AXI_AWVALID(ctrl_if.awvalid),
.S_AXI_AWREADY(ctrl_if.awready),
.S_AXI_WDATA(ctrl_if.wdata),
.S_AXI_WSTRB(ctrl_if.wstrb),
.S_AXI_WVALID(ctrl_if.wvalid),
.S_AXI_WREADY(ctrl_if.wready),
.S_AXI_BRESP(ctrl_if.bresp),
.S_AXI_BVALID(ctrl_if.bvalid),
.S_AXI_BREADY(ctrl_if.bready),
.S_AXI_ARADDR(ctrl_if.araddr),
.S_AXI_ARPROT(ctrl_if.arprot),
.S_AXI_ARVALID(ctrl_if.arvalid),
.S_AXI_ARREADY(ctrl_if.arready),
.S_AXI_RDATA(ctrl_if.rdata),
.S_AXI_RRESP(ctrl_if.rresp),
.S_AXI_RVALID(ctrl_if.rvalid),
.S_AXI_RREADY(ctrl_if.rready),
.raddr(raddr),
.waddr(waddr),
.wren(wren),
.rden(rden),
.wdata(wdata),
.rdata(rdata)
);
// ------------------------------
// Config Registers
// ------------------------------
wire reset;
reg [31:0] reg_ctrl;
reg [15:0] reg_num_samples;
reg [27:0] reg_start_sample;
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_ctrl <= 0;
end else if (wren && waddr[11:0] == CTRL_REG_ADDR) begin
reg_ctrl <= wdata[15:0];
end
end
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_num_samples <= 0;
end else if (wren && waddr[11:0] == NUM_SAMPLES_REG_ADDR) begin
reg_num_samples <= wdata[15:0];
end
end
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_start_sample <= 0;
end else if (wren && waddr[11:0] == START_SAMPLE_REG_ADDR) begin
reg_start_sample <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (rden) begin
if ( raddr[11:0] == CTRL_REG_ADDR )
rdata <= reg_ctrl;
if ( raddr[11:0] == NUM_SAMPLES_REG_ADDR )
rdata <= reg_num_samples;
if ( raddr[11:0] == START_SAMPLE_REG_ADDR )
rdata <= reg_start_sample;
end
end
assign reset = reg_ctrl[0];
// ------------------------------
// Sample gating
// ------------------------------
reg [16:0] sample_cnt;
reg pulse_active;
reg pulse_active_q;
reg pulse_active_q2;
// Delay event pulse by start sample
reg [27:0] start_sample_cnt;
reg [27:0] start_sample_this_pulse;
reg delay_active;
reg delay_active_q;
reg delay_active_fed;
reg [255:0] jesd_out_reg;
reg [255:0] all_brams_out;
always @ (posedge clk) begin
if (reset == 1'b1) begin
start_sample_cnt <= 0;
delay_active <= 0;
end else begin
delay_active_q <= delay_active;
delay_active_fed <= ~delay_active && delay_active_q;
if (start_of_pulse) begin
start_sample_cnt <= reg_start_sample;
start_sample_this_pulse <= reg_start_sample;
delay_active <= 1;
end
if (delay_active) begin
start_sample_cnt <= start_sample_cnt - 1;
if (start_sample_cnt == 0) begin
delay_active <= 0;
end
end
end
end
always @ (posedge clk) begin
if (reset == 1'b1) begin
sample_cnt <= 0;
pulse_active <= 0;
pulse_active_q <= 0;
pulse_active_q2 <= 0;
end else begin
pulse_active_q <= pulse_active;
pulse_active_q2 <= pulse_active_q;
if (delay_active_fed) begin
sample_cnt <= 0;
pulse_active <= 1;
end;
if (pulse_active) begin
sample_cnt <= sample_cnt + 1;
if (sample_cnt == reg_num_samples-1) begin
sample_cnt <= 0;
pulse_active <= 0;
end
end
if (pulse_active_q2) begin
jesd_out_reg <= all_brams_out;
end else begin
jesd_out_reg <= 0;
end
end
end
always @ (posedge clk) begin
if (pulse_active) begin
dac0_bram_addr <= dac0_bram_addr + 1;
end else begin
dac0_bram_addr <= 0;
end
end
//assign all_brams_out[16*0+15 + 384 : 16*0 + 384] = dac3_bram_dout[16*6+15:16*6];
//assign all_brams_out[16*1+15 + 384 : 16*1 + 384] = dac3_bram_dout[16*4+15:16*4];
//assign all_brams_out[16*2+15 + 384 : 16*2 + 384] = dac3_bram_dout[16*2+15:16*2];
//assign all_brams_out[16*3+15 + 384 : 16*3 + 384] = dac3_bram_dout[16*0+15:16*0];
//assign all_brams_out[16*4+15 + 384 : 16*4 + 384] = dac3_bram_dout[16*7+15:16*7];
//assign all_brams_out[16*5+15 + 384 : 16*5 + 384] = dac3_bram_dout[16*5+15:16*5];
//assign all_brams_out[16*6+15 + 384 : 16*6 + 384] = dac3_bram_dout[16*3+15:16*3];
//assign all_brams_out[16*7+15 + 384 : 16*7 + 384] = dac3_bram_dout[16*1+15:16*1];
//assign all_brams_out[16*0+15 + 256 : 16*0 + 256] = dac2_bram_dout[16*6+15:16*6];
//assign all_brams_out[16*1+15 + 256 : 16*1 + 256] = dac2_bram_dout[16*4+15:16*4];
//assign all_brams_out[16*2+15 + 256 : 16*2 + 256] = dac2_bram_dout[16*2+15:16*2];
//assign all_brams_out[16*3+15 + 256 : 16*3 + 256] = dac2_bram_dout[16*0+15:16*0];
//assign all_brams_out[16*4+15 + 256 : 16*4 + 256] = dac2_bram_dout[16*7+15:16*7];
//assign all_brams_out[16*5+15 + 256 : 16*5 + 256] = dac2_bram_dout[16*5+15:16*5];
//assign all_brams_out[16*6+15 + 256 : 16*6 + 256] = dac2_bram_dout[16*3+15:16*3];
//assign all_brams_out[16*7+15 + 256 : 16*7 + 256] = dac2_bram_dout[16*1+15:16*1];
assign all_brams_out[16*0+15 + 128 : 16*0 + 128] = dac1_bram_dout[16*6+15:16*6];
assign all_brams_out[16*1+15 + 128 : 16*1 + 128] = dac1_bram_dout[16*4+15:16*4];
assign all_brams_out[16*2+15 + 128 : 16*2 + 128] = dac1_bram_dout[16*2+15:16*2];
assign all_brams_out[16*3+15 + 128 : 16*3 + 128] = dac1_bram_dout[16*0+15:16*0];
assign all_brams_out[16*4+15 + 128 : 16*4 + 128] = dac1_bram_dout[16*7+15:16*7];
assign all_brams_out[16*5+15 + 128 : 16*5 + 128] = dac1_bram_dout[16*5+15:16*5];
assign all_brams_out[16*6+15 + 128 : 16*6 + 128] = dac1_bram_dout[16*3+15:16*3];
assign all_brams_out[16*7+15 + 128 : 16*7 + 128] = dac1_bram_dout[16*1+15:16*1];
assign all_brams_out[16*0+15 + 0 : 16*0 + 0] = dac0_bram_dout[16*6+15:16*6];
assign all_brams_out[16*1+15 + 0 : 16*1 + 0] = dac0_bram_dout[16*4+15:16*4];
assign all_brams_out[16*2+15 + 0 : 16*2 + 0] = dac0_bram_dout[16*2+15:16*2];
assign all_brams_out[16*3+15 + 0 : 16*3 + 0] = dac0_bram_dout[16*0+15:16*0];
assign all_brams_out[16*4+15 + 0 : 16*4 + 0] = dac0_bram_dout[16*7+15:16*7];
assign all_brams_out[16*5+15 + 0 : 16*5 + 0] = dac0_bram_dout[16*5+15:16*5];
assign all_brams_out[16*6+15 + 0 : 16*6 + 0] = dac0_bram_dout[16*3+15:16*3];
assign all_brams_out[16*7+15 + 0 : 16*7 + 0] = dac0_bram_dout[16*1+15:16*1];
assign dac1_bram_addr = dac0_bram_addr;
//assign dac2_bram_addr = dac0_bram_addr;
//assign dac3_bram_addr = dac0_bram_addr;
// dac2 and dac3 are used for LOs, so just need a constant 1 + j0 output. The NCO
// inside the AD9081 will be used to turn this into a tone
assign jesd_tx[511:384] = {16'h0000, 16'h0000, 16'h0000, 16'h0000, 16'h7FFF, 16'h7FFF, 16'h7FFF, 16'h7FFF};
assign jesd_tx[383:256] = {16'h0000, 16'h0000, 16'h0000, 16'h0000, 16'h7FFF, 16'h7FFF, 16'h7FFF, 16'h7FFF};
assign jesd_tx[255:0] = jesd_out_reg;
wf_memory dac0_wf_mem (
.clka(dac0_wf_bram_clk),
.ena(dac0_wf_bram_en),
.wea(dac0_wf_bram_we),
.addra(dac0_wf_bram_addr[14:2]),
.dina(dac0_wf_bram_din),
.douta(dac0_wf_bram_dout),
.clkb(clk),
.enb(1'b1),
.web(1'b0),
.addrb(dac0_bram_addr),
.dinb(0),
.doutb(dac0_bram_dout)
);
wf_memory dac1_wf_mem (
.clka(dac1_wf_bram_clk),
.ena(dac1_wf_bram_en),
.wea(dac1_wf_bram_we),
.addra(dac1_wf_bram_addr[14:2]),
.dina(dac1_wf_bram_din),
.douta(dac1_wf_bram_dout),
.clkb(clk),
.enb(1'b1),
.web(1'b0),
.addrb(dac1_bram_addr),
.dinb(0),
.doutb(dac1_bram_dout)
);
//wf_memory dac2_wf_mem (
// .clka(dac2_wf_bram_clk),
// .ena(dac2_wf_bram_en),
// .wea(dac2_wf_bram_we),
// .addra(dac2_wf_bram_addr[14:2]),
// .dina(dac2_wf_bram_din),
// .douta(dac2_wf_bram_dout),
// .clkb(clk),
// .enb(1'b1),
// .web(1'b0),
// .addrb(dac2_bram_addr),
// .dinb(0),
// .doutb(dac2_bram_dout)
//);
//wf_memory dac3_wf_mem (
// .clka(dac3_wf_bram_clk),
// .ena(dac3_wf_bram_en),
// .wea(dac3_wf_bram_we),
// .addra(dac3_wf_bram_addr[14:2]),
// .dina(dac3_wf_bram_din),
// .douta(dac3_wf_bram_dout),
// .clkb(clk),
// .enb(1'b1),
// .web(1'b0),
// .addrb(dac3_bram_addr),
// .dinb(0),
// .doutb(dac3_bram_dout)
//);
endmodule
`resetall

507
radar_alinx_kintex.srcs/sources_1/ip/axis_switch_0/axis_switch_0.xci Executable file
View File

@@ -0,0 +1,507 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axis_switch_0",
"component_reference": "xilinx.com:ip:axis_switch:1.1",
"ip_revision": "27",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/axis_switch_0",
"parameters": {
"component_parameters": {
"NUM_SI": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_MI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ROUTING_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ARB_ON_MAX_XFERS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ARB_ON_NUM_CYCLES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ARB_ON_TLAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ARB_ALGORITHM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DECODER_REG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OUTPUT_REG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"COMMON_CLOCK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_AXIS_BASETDEST": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M01_AXIS_BASETDEST": [ { "value": "0x00000001", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M02_AXIS_BASETDEST": [ { "value": "0x00000002", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M03_AXIS_BASETDEST": [ { "value": "0x00000003", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M04_AXIS_BASETDEST": [ { "value": "0x00000004", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M05_AXIS_BASETDEST": [ { "value": "0x00000005", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M06_AXIS_BASETDEST": [ { "value": "0x00000006", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M07_AXIS_BASETDEST": [ { "value": "0x00000007", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M08_AXIS_BASETDEST": [ { "value": "0x00000008", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M09_AXIS_BASETDEST": [ { "value": "0x00000009", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M10_AXIS_BASETDEST": [ { "value": "0x0000000a", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M11_AXIS_BASETDEST": [ { "value": "0x0000000b", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M12_AXIS_BASETDEST": [ { "value": "0x0000000c", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M13_AXIS_BASETDEST": [ { "value": "0x0000000d", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M14_AXIS_BASETDEST": [ { "value": "0x0000000e", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M15_AXIS_BASETDEST": [ { "value": "0x0000000f", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M00_AXIS_HIGHTDEST": [ { "value": "0x0000000F", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M01_AXIS_HIGHTDEST": [ { "value": "0x00000001", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M02_AXIS_HIGHTDEST": [ { "value": "0x00000002", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M03_AXIS_HIGHTDEST": [ { "value": "0x00000003", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M04_AXIS_HIGHTDEST": [ { "value": "0x00000004", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M05_AXIS_HIGHTDEST": [ { "value": "0x00000005", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M06_AXIS_HIGHTDEST": [ { "value": "0x00000006", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M07_AXIS_HIGHTDEST": [ { "value": "0x00000007", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M08_AXIS_HIGHTDEST": [ { "value": "0x00000008", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M09_AXIS_HIGHTDEST": [ { "value": "0x00000009", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M10_AXIS_HIGHTDEST": [ { "value": "0x0000000a", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M11_AXIS_HIGHTDEST": [ { "value": "0x0000000b", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M12_AXIS_HIGHTDEST": [ { "value": "0x0000000c", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M13_AXIS_HIGHTDEST": [ { "value": "0x0000000d", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M14_AXIS_HIGHTDEST": [ { "value": "0x0000000e", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M15_AXIS_HIGHTDEST": [ { "value": "0x0000000f", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M00_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M00_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M01_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M05_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M06_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M07_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M08_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M09_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M10_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M11_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M12_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M13_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M14_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S00_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S01_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S02_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S03_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S04_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S05_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S06_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S07_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S08_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S09_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S10_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S11_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S12_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S13_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S14_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M15_S15_CONNECTIVITY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "axis_switch_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_NUM_SI_SLOTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOG_SI_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_MI_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000011010011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_ARB_ON_MAX_XFERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ARB_ON_NUM_CYCLES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ARB_ON_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INCLUDE_ARBITER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ARB_ALGORITHM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DECODER_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_CONNECTIVITY_ARRAY": [ { "value": "\"11\"", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
"C_M_AXIS_BASETDEST_ARRAY": [ { "value": "0b0000", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
"C_M_AXIS_HIGHTDEST_ARRAY": [ { "value": "0b1111", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ],
"C_ROUTING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "27" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/axis_switch_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axis_tvalid": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
"s_axis_tlast": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x3" } ],
"s_axis_tdest": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
"s_axis_tuser": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
"m_axis_tvalid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
"m_axis_tready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
"m_axis_tlast": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
"m_axis_tdest": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
"m_axis_tuser": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
"s_req_suppress": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"s_decode_err": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
},
"interfaces": {
"S00_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid", "physical_left": "0", "physical_right": "0" } ],
"TREADY": [ { "physical_name": "s_axis_tready", "physical_left": "0", "physical_right": "0" } ],
"TDATA": [ { "physical_name": "s_axis_tdata", "physical_left": "63", "physical_right": "0" } ],
"TLAST": [ { "physical_name": "s_axis_tlast", "physical_left": "0", "physical_right": "0" } ],
"TDEST": [ { "physical_name": "s_axis_tdest", "physical_left": "3", "physical_right": "0" } ],
"TUSER": [ { "physical_name": "s_axis_tuser", "physical_left": "15", "physical_right": "0" } ]
}
},
"M00_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid", "physical_left": "0", "physical_right": "0" } ],
"TREADY": [ { "physical_name": "m_axis_tready", "physical_left": "0", "physical_right": "0" } ],
"TDATA": [ { "physical_name": "m_axis_tdata", "physical_left": "63", "physical_right": "0" } ],
"TLAST": [ { "physical_name": "m_axis_tlast", "physical_left": "0", "physical_right": "0" } ],
"TDEST": [ { "physical_name": "m_axis_tdest", "physical_left": "3", "physical_right": "0" } ],
"TUSER": [ { "physical_name": "m_axis_tuser", "physical_left": "15", "physical_right": "0" } ]
}
},
"S01_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid", "physical_left": "1", "physical_right": "1" } ],
"TREADY": [ { "physical_name": "s_axis_tready", "physical_left": "1", "physical_right": "1" } ],
"TDATA": [ { "physical_name": "s_axis_tdata", "physical_left": "127", "physical_right": "64" } ],
"TLAST": [ { "physical_name": "s_axis_tlast", "physical_left": "1", "physical_right": "1" } ],
"TDEST": [ { "physical_name": "s_axis_tdest", "physical_left": "7", "physical_right": "4" } ],
"TUSER": [ { "physical_name": "s_axis_tuser", "physical_left": "31", "physical_right": "16" } ]
}
},
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}

189
radar_alinx_kintex.srcs/sources_1/ip/clock_converter/clock_converter.xci Executable file
View File

@@ -0,0 +1,189 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "clock_converter",
"component_reference": "xilinx.com:ip:axis_clock_converter:1.1",
"ip_revision": "28",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/clock_converter",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLK_RATIO": [ { "value": "1:2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "clock_converter", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "28" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/clock_converter" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"M_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "m_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
},
"M_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "m_axis_aclk" } ]
}
}
}
}
}
}

175
radar_alinx_kintex.srcs/sources_1/ip/data_fifo/data_fifo.xci Executable file
View File

@@ -0,0 +1,175 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "data_fifo",
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
"ip_revision": "9",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/data_fifo",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_DEPTH": [ { "value": "512", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "data_fifo", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "9" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/data_fifo" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
}
}
}
}
}

197
radar_alinx_kintex.srcs/sources_1/ip/dig_rx_clock_converter/dig_rx_clock_converter.xci Executable file
View File

@@ -0,0 +1,197 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "dig_rx_clock_converter",
"component_reference": "xilinx.com:ip:axis_clock_converter:1.1",
"ip_revision": "28",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/dig_rx_clock_converter",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLK_RATIO": [ { "value": "1:2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "dig_rx_clock_converter", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000010010011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "28" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/dig_rx_clock_converter" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0x0000000000000000" } ],
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_tuser": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
"m_axis_tlast": [ { "direction": "out" } ],
"m_axis_tuser": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
"TUSER": [ { "physical_name": "s_axis_tuser" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
"TUSER": [ { "physical_name": "m_axis_tuser" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"M_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "m_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
},
"M_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "m_axis_aclk" } ]
}
}
}
}
}
}

162
radar_alinx_kintex.srcs/sources_1/ip/dig_rx_dwidth_converter/dig_rx_dwidth_converter.xci Executable file
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@@ -0,0 +1,162 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "dig_rx_dwidth_converter",
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
"ip_revision": "26",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/dig_rx_dwidth_converter",
"parameters": {
"component_parameters": {
"S_TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_BITS_PER_BYTE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "dig_rx_dwidth_converter", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_S_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_TUSER_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TUSER_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000010010011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "26" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/dig_rx_dwidth_converter" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_tuser": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
"m_axis_tlast": [ { "direction": "out" } ],
"m_axis_tuser": [ { "direction": "out", "size_left": "7", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
"TUSER": [ { "physical_name": "s_axis_tuser" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
"TUSER": [ { "physical_name": "m_axis_tuser" } ]
}
},
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}

898
radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_channel/eth_xcvr_gt_channel.xci Executable file
View File

@@ -0,0 +1,898 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "eth_xcvr_gt_channel",
"component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7",
"ip_revision": "14",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/eth_xcvr_gt_channel",
"parameters": {
"component_parameters": {
"GT_TYPE": [ { "value": "GTH", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_GT_PRIM_TYPE": [ { "value": "gthe3", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"GT_REV": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"GT_DIRECTION": [ { "value": "BOTH", "resolve_type": "user", "usage": "all" } ],
"RX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"TX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"CHANNEL_ENABLE": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
"TX_MASTER_CHANNEL": [ { "value": "X0Y0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_MASTER_CHANNEL": [ { "value": "X0Y0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_COMMONS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"LOCATE_COMMON": [ { "value": "EXAMPLE_DESIGN", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_NUM_COMMONS_CORE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
"RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
"RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
"RX_TERMINATION_PROG_VALUE": [ { "value": "800", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_COUPLING": [ { "value": "AC", "resolve_type": "user", "usage": "all" } ],
"RX_BUFFER_BYPASS_MODE": [ { "value": "MULTI", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_CB_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_COMMAALIGN": [ { "value": "DISABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "usage": "all" } ],
"TX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "usage": "all" } ],
"RESET_SEQUENCE_INTERVAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_COMMA_PRESET": [ { "value": "NONE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_VALID_ONLY": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_COMMA_P_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_M_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_DOUBLE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_P_VAL": [ { "value": "0101111100", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_M_VAL": [ { "value": "1010000011", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_MASK": [ { "value": "0000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_ALIGN_WORD": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_SLIDE_MODE": [ { "value": "OFF", "resolve_type": "user", "usage": "all" } ],
"RX_CB_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MAX_SKEW": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MAX_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MASK": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_VAL": [ { "value": "00000000000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_K": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_DISP": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_KEEP_IDLE": [ { "value": "DISABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_PRECEDENCE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_REPEAT_WAIT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_MASK": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_VAL": [ { "value": "00000000000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "user", "usage": "all" } ],
"RX_CC_K": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_DISP": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"ENABLE_OPTIONAL_PORTS": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_SOURCE": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_SOURCE": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"LOCATE_RESET_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"LOCATE_TX_BUFFER_BYPASS_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"LOCATE_RX_BUFFER_BYPASS_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"LOCATE_IN_SYSTEM_IBERT_CORE": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
"LOCATE_TX_USER_CLOCKING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"LOCATE_RX_USER_CLOCKING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_UPDATE_IP_SYMBOL_drpclk_in": [ { "value": "false", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"SECONDARY_QPLL_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SECONDARY_QPLL_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SECONDARY_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ENABLE_COMMON_USRCLK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PCIE_64BIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PCIE_GEN4_EIOS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGBYPASSB_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGMONITORENB_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGPDB_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGRCALOVRD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTGREFCLK0_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTGREFCLK1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK00_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK01_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK10_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK11_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVD0_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVD1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0PD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1PD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD2_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD3_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD4_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RCALENB_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0DATA_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0WIDTH_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1DATA_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1WIDTH_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONGPI_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONPOWERUP_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDO_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDRDY_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBENABLE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBGPI_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBINTR_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBIOLMBRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMBRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMREGEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMTCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMTDI_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONGPO_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDADDR_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDEN_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDI_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDWE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMTDO_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBTXUART_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CDRSTEPSX_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CFGRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CLKRSVD0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CLKRSVD1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONFIFORESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONITORCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPADDR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDI_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPWE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_FREQOS_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTGREFCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHRXN_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHRXP_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRESETSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRSVD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRXRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTTXRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_INCPCTRL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYRXN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYRXP_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LOOPBACK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LOOPRSVD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCSRSVDIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVDIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0CLK_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1CLK_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RESETOVRD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RSTCLKENTX_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RX8B10BEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBUFRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDI_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCKCALRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCKCALSTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMMADETEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEAGCCTRL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDCCFORCESTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEAGCHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEAGCOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKFCNUM_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKFEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKFPULSE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKHOLD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKOVREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEKHHOLD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEKHOVRDEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFELFHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFELFOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFELPMRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP10HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP10OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP11HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP11OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP12HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP12OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP13HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP13OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP14HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP14OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP15HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP15OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP2HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP2OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP3HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP3OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP4HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP4OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP5HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP5OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP6HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP6OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP7HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP7OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP8HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP8OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP9HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP9OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEUTHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEUTOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEVPHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEVSEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXEQTRAINING_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXGEARBOXSLIP_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLATCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMGCHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMGCOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMHFHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMHFOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMLFHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMLFKLOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXMONITORSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOOBRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSCALRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTCFG_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPCSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHDLYPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPMARESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPOLARITY_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXQPIEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRATE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRATEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIDE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPPMA_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXTERMINATION_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXUSERRDY_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXUSRCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXUSRCLK2_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TSTIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TX8B10BEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMINIT_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMSAS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMWAKE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCTRL0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCTRL1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCTRL2_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDATA_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDCCRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDEEMPH_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDETECTRX_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDIFFPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXELECIDLE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXELFORCESTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXHEADER_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXINHIBIT_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLATCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMARGIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXONESZEROS_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPCSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHALIGN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHDLYPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHINIT_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPISOPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPMARESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPOLARITY_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRBSSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRECURSOR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRATE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRATEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSEQUENCE_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSWING_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXUSERRDY_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXUSRCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXUSRCLK2_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTCE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTDIV_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTRESET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLLOCK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONITOROUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDO_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPRDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHTXN_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHTXP_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYTXN_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYTXP_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PHYSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_POWERPRESENT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDO_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMMADET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL0_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL1_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL2_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL3_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDATA_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDATAVALID_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXELECIDLE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXHEADER_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSERR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXQPISENN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXQPISENP_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRATEDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXVALID_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDCCDONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPISENN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPISENP_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRATEDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"Component_Name": [ { "value": "eth_xcvr_gt_channel", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_CHANNEL_ENABLE": [ { "value": "\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_PCIE_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CPLL_VCO_FREQUENCY": [ { "value": "2578.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_GT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_GT_REV": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_COMMON_USRCLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USER_GTPOWERGOOD_DELAY_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_COMMON": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_RESET_CONTROLLER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_IN_SYSTEM_IBERT_CORE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_RX_USER_CLOCKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_TX_USER_CLOCKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RESET_CONTROLLER_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_BUFFBYPASS_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_BUFFER_BYPASS_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_DISP": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CB_K": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CB_MAX_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_LEN_SEQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_NUM_SEQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_VAL": [ { "value": "\"00000000000000000000000000000000000000000000000000000000000000000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CC_DISP": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CC_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RESET_SEQUENCE_INTERVAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_K": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CC_LEN_SEQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_NUM_SEQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_VAL": [ { "value": "\"00000000000000000000000000000000000000000000000000000000000000000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_COMMA_M_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_COMMA_M_VAL": [ { "value": "\"1010000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_COMMA_P_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_COMMA_P_VAL": [ { "value": "\"0101111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_DATA_DECODING": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_MASTER_CHANNEL_IDX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_OUTCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_PLL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_RECCLK_OUTPUT": [ { "value": "0x000000000000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_SLIDE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_USRCLK2_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_SECONDARY_QPLL_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TOTAL_NUM_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TOTAL_NUM_COMMONS_EXAMPLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TXPROGDIV_FREQ_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TXPROGDIV_FREQ_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_BUFFBYPASS_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_BUFFER_BYPASS_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_DATA_ENCODING": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_MASTER_CHANNEL_IDX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_PLL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USRCLK2_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "14" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/eth_xcvr_gt_channel" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"gtwiz_userclk_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_clk_freerun_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_all_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_qpll0lock_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_cdr_stable_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_qpll0reset_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gthrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gthrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxgearboxslip_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txheader_in": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"txsequence_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
"gthtxn_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gthtxp_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtpowergood_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxdatavalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxheader_out": [ { "direction": "out", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"rxheadervalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxstartofseq_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"txpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
}
}
}
}

896
radar_alinx_kintex.srcs/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.xci Executable file
View File

@@ -0,0 +1,896 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "eth_xcvr_gt_full",
"component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7",
"ip_revision": "14",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/eth_xcvr_gt_full",
"parameters": {
"component_parameters": {
"GT_TYPE": [ { "value": "GTH", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_GT_PRIM_TYPE": [ { "value": "gthe3", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"GT_REV": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"GT_DIRECTION": [ { "value": "BOTH", "resolve_type": "user", "usage": "all" } ],
"RX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"TX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"CHANNEL_ENABLE": [ { "value": "X0Y3", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_MASTER_CHANNEL": [ { "value": "X0Y3", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_MASTER_CHANNEL": [ { "value": "X0Y3", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_COMMONS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"LOCATE_COMMON": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_NUM_COMMONS_CORE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
"RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_PLL_TYPE": [ { "value": "QPLL0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "resolve_type": "user", "usage": "all" } ],
"RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
"RX_JTOL_FC": [ { "value": "6.1862627", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "resolve_type": "user", "usage": "all" } ],
"SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
"RX_TERMINATION_PROG_VALUE": [ { "value": "800", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_COUPLING": [ { "value": "AC", "resolve_type": "user", "usage": "all" } ],
"RX_BUFFER_BYPASS_MODE": [ { "value": "MULTI", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_CB_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_COMMAALIGN": [ { "value": "DISABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "usage": "all" } ],
"TX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "usage": "all" } ],
"RESET_SEQUENCE_INTERVAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_COMMA_PRESET": [ { "value": "NONE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_VALID_ONLY": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_COMMA_P_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_M_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_DOUBLE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_P_VAL": [ { "value": "0101111100", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_M_VAL": [ { "value": "1010000011", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_MASK": [ { "value": "0000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_ALIGN_WORD": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_SLIDE_MODE": [ { "value": "OFF", "resolve_type": "user", "usage": "all" } ],
"RX_CB_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MAX_SKEW": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MAX_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MASK": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_VAL": [ { "value": "00000000000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_K": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_DISP": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_KEEP_IDLE": [ { "value": "DISABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_PRECEDENCE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_REPEAT_WAIT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_MASK": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_VAL": [ { "value": "00000000000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "user", "usage": "all" } ],
"RX_CC_K": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_DISP": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"ENABLE_OPTIONAL_PORTS": [ { "value": "qpll0lock_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_SOURCE": [ { "value": "X0Y3 clk1+2", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_SOURCE": [ { "value": "X0Y3 clk1+2", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"LOCATE_RESET_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"LOCATE_TX_BUFFER_BYPASS_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"LOCATE_RX_BUFFER_BYPASS_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"LOCATE_IN_SYSTEM_IBERT_CORE": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
"LOCATE_TX_USER_CLOCKING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"LOCATE_RX_USER_CLOCKING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRESET": [ { "value": "GTH-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "14", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_UPDATE_IP_SYMBOL_drpclk_in": [ { "value": "false", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"SECONDARY_QPLL_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SECONDARY_QPLL_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SECONDARY_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"TXPROGDIV_FREQ_SOURCE": [ { "value": "QPLL0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ENABLE_COMMON_USRCLK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PCIE_64BIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PCIE_GEN4_EIOS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGBYPASSB_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGMONITORENB_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGPDB_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGRCALOVRD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTGREFCLK0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTGREFCLK1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK00_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK01_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK10_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK11_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVD0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVD1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0PD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1PD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1RESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD2_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD3_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLRSVD4_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RCALENB_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0DATA_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0WIDTH_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1DATA_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1RESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1WIDTH_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONGPI_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONPOWERUP_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDO_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDRDY_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBENABLE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBGPI_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBINTR_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBIOLMBRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMBRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMREGEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMTCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMTDI_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONGPO_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDADDR_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDEN_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDI_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBDWE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBMDMTDO_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_UBTXUART_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CDRSTEPSX_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CFGRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CLKRSVD0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CLKRSVD1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONFIFORESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONITORCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPADDR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDI_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPRST_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPWE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_FREQOS_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTGREFCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHRXN_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHRXP_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLK1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRESETSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRSVD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRXRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTTXRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_INCPCTRL_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYRXN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYRXP_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LOOPBACK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LOOPRSVD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCSRSVDIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PMARSVDIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0CLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1CLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RESETOVRD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RSTCLKENTX_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RX8B10BEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBUFRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDI_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCKCALRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCKCALSTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMMADETEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEAGCCTRL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDCCFORCESTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEAGCHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEAGCOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKFCNUM_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKFEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKFPULSE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKHOLD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFECFOKOVREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEKHHOLD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEKHOVRDEN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFELFHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFELFOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFELPMRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP10HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP10OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP11HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP11OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP12HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP12OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP13HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP13OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP14HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP14OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP15HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP15OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP2HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP2OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP3HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP3OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP4HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP4OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP5HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP5OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP6HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP6OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP7HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP7OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP8HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP8OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP9HOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFETAP9OVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEUTHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEUTOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEVPHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEVSEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXEQTRAINING_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXGEARBOXSLIP_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLATCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMGCHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMGCOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMHFHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMHFOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMLFHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMLFKLOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXMONITORSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOOBRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSCALRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTCFG_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPCSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHDLYPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPMARESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPOLARITY_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXQPIEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRATE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRATEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIDE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPPMA_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXTERMINATION_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXUSERRDY_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXUSRCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXUSRCLK2_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TSTIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TX8B10BEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMINIT_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMSAS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMWAKE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCTRL0_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCTRL1_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCTRL2_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDATA_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDCCRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDEEMPH_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDETECTRX_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDIFFPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYHOLD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXELECIDLE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXELFORCESTART_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXHEADER_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXINHIBIT_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLATCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMARGIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXONESZEROS_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPCSRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHALIGN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHDLYPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHINIT_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPISOPD_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPMARESET_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPOLARITY_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRBSSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRECURSOR_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRATE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRATEMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSEQUENCE_IN": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSWING_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCIN_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCMODE_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXUSERRDY_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXUSRCLK_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXUSRCLK2_IN": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTCE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTDIV_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTRESET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLLOCK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONITOROUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPDO_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_DRPRDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHTXN_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTHTXP_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYTXN_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_GTYTXP_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PHYSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_POWERPRESENT_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCHBONDO_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMMADET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL0_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL1_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL2_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXCTRL3_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDATA_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDATAVALID_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXELECIDLE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXHEADER_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSERR_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXQPISENN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXQPISENP_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRATEDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_RXVALID_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDCCDONE_OUT": [ { "value": "-1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLK_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPISENN_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXQPISENP_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRATEDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXRESETDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"Component_Name": [ { "value": "eth_xcvr_gt_full", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_CHANNEL_ENABLE": [ { "value": "\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_PCIE_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CPLL_VCO_FREQUENCY": [ { "value": "2578.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_GT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_GT_REV": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_COMMON_USRCLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USER_GTPOWERGOOD_DELAY_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_COMMON": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_RESET_CONTROLLER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_IN_SYSTEM_IBERT_CORE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_RX_USER_CLOCKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOCATE_TX_USER_CLOCKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RESET_CONTROLLER_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_BUFFBYPASS_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_BUFFER_BYPASS_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_DISP": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CB_K": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CB_MAX_LEVEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_LEN_SEQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_NUM_SEQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CB_VAL": [ { "value": "\"00000000000000000000000000000000000000000000000000000000000000000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CC_DISP": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CC_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RESET_SEQUENCE_INTERVAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_K": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_CC_LEN_SEQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_NUM_SEQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_CC_VAL": [ { "value": "\"00000000000000000000000000000000000000000000000000000000000000000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_COMMA_M_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_COMMA_M_VAL": [ { "value": "\"1010000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_COMMA_P_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_COMMA_P_VAL": [ { "value": "\"0101111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_DATA_DECODING": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_MASTER_CHANNEL_IDX": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_OUTCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_PLL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_RECCLK_OUTPUT": [ { "value": "0x000000000000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_RX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_SLIDE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USER_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_USRCLK2_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_SECONDARY_QPLL_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TOTAL_NUM_COMMONS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TOTAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TXPROGDIV_FREQ_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TXPROGDIV_FREQ_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TXPROGDIV_FREQ_VAL": [ { "value": "312.5", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_BUFFBYPASS_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_BUFFER_BYPASS_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_DATA_ENCODING": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_INT_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_LINE_RATE": [ { "value": "10.3125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_MASTER_CHANNEL_IDX": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_PLL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USRCLK_FREQUENCY": [ { "value": "312.5000000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USRCLK2_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "14" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/eth_xcvr_gt_full" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"gtwiz_userclk_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_clk_freerun_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_all_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_cdr_stable_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtrefclk00_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0lock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0outclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0outrefclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gthrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gthrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxgearboxslip_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txheader_in": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"txsequence_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
"gthtxn_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gthtxp_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtpowergood_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxdatavalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxheader_out": [ { "direction": "out", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"rxheadervalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxstartofseq_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"txpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
}
}
}
}

179
radar_alinx_kintex.srcs/sources_1/ip/hdr_fifo/hdr_fifo.xci Executable file
View File

@@ -0,0 +1,179 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "hdr_fifo",
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
"ip_revision": "9",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/hdr_fifo",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_DEPTH": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "hdr_fifo", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000010011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "9" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/hdr_fifo" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0x0000000000000000" } ],
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
"m_axis_tlast": [ { "direction": "out" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
}
}
}
}
}

281
radar_alinx_kintex.srcs/sources_1/ip/hdr_mem/hdr_mem.xci Executable file
View File

@@ -0,0 +1,281 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "hdr_mem",
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
"ip_revision": "5",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/hdr_mem",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "hdr_mem", "resolve_type": "user", "usage": "all" } ],
"Interface_Type": [ { "value": "Native", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ],
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Operating_Mode_A": [ { "value": "NO_CHANGE", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
"Write_Width_B": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "64", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
"C_INIT_FILE": [ { "value": "hdr_mem.mem", "resolve_type": "generated", "usage": "all" } ],
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BYTE_WEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WEA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_MODE_A": [ { "value": "NO_CHANGE", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_A": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BYTE_WEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_B": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_B": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRB_WIDTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.153512 mW", "resolve_type": "generated", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "5" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/hdr_mem" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"clka": [ { "direction": "in", "driver_value": "0" } ],
"ena": [ { "direction": "in", "driver_value": "0" } ],
"wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
"dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"clkb": [ { "direction": "in", "driver_value": "0" } ],
"enb": [ { "direction": "in", "driver_value": "0" } ],
"addrb": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
"doutb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ]
},
"interfaces": {
"CLK.ACLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"RST.ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"BRAM_PORTA": {
"vlnv": "xilinx.com:interface:bram:1.0",
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
"mode": "slave",
"parameters": {
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "addra" } ],
"CLK": [ { "physical_name": "clka" } ],
"DIN": [ { "physical_name": "dina" } ],
"EN": [ { "physical_name": "ena" } ],
"WE": [ { "physical_name": "wea" } ]
}
},
"BRAM_PORTB": {
"vlnv": "xilinx.com:interface:bram:1.0",
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
"mode": "slave",
"parameters": {
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "addrb" } ],
"CLK": [ { "physical_name": "clkb" } ],
"DOUT": [ { "physical_name": "doutb" } ],
"EN": [ { "physical_name": "enb" } ]
}
}
},
"memory_maps": {
"S_1": {
"address_blocks": {
"Mem0": {
"base_address": "0",
"range": "4096",
"usage": "memory",
"access": "read-write",
"parameters": {
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
}
}
}
}
}
}
}
}

183
radar_alinx_kintex.srcs/sources_1/ip/pulse_buffer_fifo/pulse_buffer_fifo.xci Executable file
View File

@@ -0,0 +1,183 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "pulse_buffer_fifo",
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
"ip_revision": "9",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/pulse_buffer_fifo",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "pulse_buffer_fifo", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000010010011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "9" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/pulse_buffer_fifo" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_tuser": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
"m_axis_tlast": [ { "direction": "out" } ],
"m_axis_tuser": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TUSER": [ { "physical_name": "s_axis_tuser" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TUSER": [ { "physical_name": "m_axis_tuser" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
}
}
}
}
}

287
radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci Executable file
View File

@@ -0,0 +1,287 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "wf_memory",
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
"ip_revision": "5",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/wf_memory",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "wf_memory", "resolve_type": "user", "usage": "all" } ],
"Interface_Type": [ { "value": "Native", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_Byte_Write_Enable": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Byte_Size": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
"Write_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Read_Width_B": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_B": [ { "value": "Use_ENB_Pin", "resolve_type": "user", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
"MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
"CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MEM_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_BYTE_SIZE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
"C_INIT_FILE": [ { "value": "wf_memory.mem", "resolve_type": "generated", "usage": "all" } ],
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WEA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRA_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WEB_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRB_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
"C_COMMON_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 4.152427 mW", "resolve_type": "generated", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "5" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/wf_memory" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"clka": [ { "direction": "in", "driver_value": "0" } ],
"ena": [ { "direction": "in", "driver_value": "0" } ],
"wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"addra": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
"dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"clkb": [ { "direction": "in", "driver_value": "0" } ],
"enb": [ { "direction": "in", "driver_value": "0" } ],
"web": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"addrb": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
"dinb": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
"doutb": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
},
"interfaces": {
"CLK.ACLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"RST.ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"BRAM_PORTA": {
"vlnv": "xilinx.com:interface:bram:1.0",
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
"mode": "slave",
"parameters": {
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "addra" } ],
"CLK": [ { "physical_name": "clka" } ],
"DIN": [ { "physical_name": "dina" } ],
"DOUT": [ { "physical_name": "douta" } ],
"EN": [ { "physical_name": "ena" } ],
"WE": [ { "physical_name": "wea" } ]
}
},
"BRAM_PORTB": {
"vlnv": "xilinx.com:interface:bram:1.0",
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
"mode": "slave",
"parameters": {
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "addrb" } ],
"CLK": [ { "physical_name": "clkb" } ],
"DIN": [ { "physical_name": "dinb" } ],
"DOUT": [ { "physical_name": "doutb" } ],
"EN": [ { "physical_name": "enb" } ],
"WE": [ { "physical_name": "web" } ]
}
}
},
"memory_maps": {
"S_1": {
"address_blocks": {
"Mem0": {
"base_address": "0",
"range": "4096",
"usage": "memory",
"access": "read-write",
"parameters": {
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
}
}
}
}
}
}
}
}

154
radar_alinx_kintex.srcs/sources_1/ip/width_converter/width_converter.xci Executable file
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "width_converter",
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
"ip_revision": "26",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/width_converter",
"parameters": {
"component_parameters": {
"S_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TDATA_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "width_converter", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_S_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "26" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/width_converter" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
}
},
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}

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radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp Executable file
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radar_alinx_kintex.xpr Executable file
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4
vitis/.gitignore vendored Normal file
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RemoteSystemsTempFiles
.metadata
*.log
.analytics

476
vitis/bootloader/.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="xilinx.gnu.mb.exe.debug.787148227">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.debug.787148227" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.mb.exe.debug.787148227" name="Debug" parent="xilinx.gnu.mb.exe.debug">
<folderInfo id="xilinx.gnu.mb.exe.debug.787148227." name="/" resourcePath="">
<toolChain id="xilinx.gnu.mb.exe.debug.toolchain.966694998" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.debug.toolchain">
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.debug.415755652" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.debug"/>
<builder buildPath="${workspace_loc:/bootloader}/Debug" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.debug.1737839447" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.mb.toolchain.builder.debug"/>
<tool id="xilinx.gnu.mb.c.toolchain.assembler.debug.1388621966" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.debug">
<option id="xilinx.gnu.mb.assembler.usele.735244737" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>
<inputType id="xilinx.gnu.assembler.input.64142705" superClass="xilinx.gnu.assembler.input"/>
</tool>
<tool id="xilinx.gnu.mb.c.toolchain.compiler.debug.776270743" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1066972995" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.1669005533" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.1164323226" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.1405857167" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.893069048" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.831207257" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1645871610" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1265612557" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usediv.850348855" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.fpu.2018499045" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.692323687" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.642806493" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspInclude}"/>
</option>
<inputType id="xilinx.gnu.compiler.input.359278436" name="C source files" superClass="xilinx.gnu.compiler.input"/>
</tool>
<tool id="xilinx.gnu.mb.cxx.toolchain.compiler.debug.645805051" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.272680176" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.2058355711" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.685400822" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.36663381" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.2145736941" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.502807478" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1371860711" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1781486245" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usediv.2027319371" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.fpu.2117027224" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.713055314" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1906149567" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspInclude}"/>
</option>
</tool>
<tool id="xilinx.gnu.mb.toolchain.archiver.1377463170" name="MicroBlaze archiver" superClass="xilinx.gnu.mb.toolchain.archiver"/>
<tool id="xilinx.gnu.mb.c.toolchain.linker.debug.1015034700" name="MicroBlaze gcc linker" superClass="xilinx.gnu.mb.c.toolchain.linker.debug">
<option id="xilinx.gnu.mb.linker.inferred.mbversion.1310310286" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.linker.inferred.norelax.967549118" superClass="xilinx.gnu.mb.linker.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.garbage.1008740776" superClass="xilinx.gnu.mb.linker.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usele.813310563" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usebarrel.249266266" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.1074211010" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usediv.181913254" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.fpu.66007638" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1141562976" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1501608344" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.314140228" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.1915898335" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
<inputType id="xilinx.gnu.linker.input.177269354" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
<inputType id="xilinx.gnu.linker.input.lscript.1358038365" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
<tool id="xilinx.gnu.mb.cxx.toolchain.linker.debug.104037971" name="MicroBlaze g++ linker" superClass="xilinx.gnu.mb.cxx.toolchain.linker.debug">
<option id="xilinx.gnu.mb.linker.inferred.mbversion.1106548916" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.linker.inferred.norelax.1346508353" superClass="xilinx.gnu.mb.linker.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.garbage.623930981" superClass="xilinx.gnu.mb.linker.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usele.878740057" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usebarrel.1153727488" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.1393443009" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usediv.1724752848" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.fpu.62238292" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.456529428" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.2097513689" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.848637791" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.1204220918" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
<tool id="xilinx.gnu.mb.size.debug.2090451817" name="MicroBlaze Print Size" superClass="xilinx.gnu.mb.size.debug"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="_ide" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="xilinx.gnu.mb.exe.release.408304434">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.release.408304434" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="xilinx.gnu.mb.exe.release.408304434" name="Release" parent="xilinx.gnu.mb.exe.release">
<folderInfo id="xilinx.gnu.mb.exe.release.408304434." name="/" resourcePath="">
<toolChain id="xilinx.gnu.mb.exe.release.toolchain.1724115306" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.release.toolchain">
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.release.834753559" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.release"/>
<builder buildPath="${workspace_loc:/bootloader}/Release" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.release.312320268" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.mb.toolchain.builder.release"/>
<tool id="xilinx.gnu.mb.c.toolchain.assembler.release.351712782" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.release">
<option id="xilinx.gnu.mb.assembler.usele.514181513" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>
<inputType id="xilinx.gnu.assembler.input.1089355912" superClass="xilinx.gnu.assembler.input"/>
</tool>
<tool id="xilinx.gnu.mb.c.toolchain.compiler.release.218609145" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.release">
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1918000656" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.1757777751" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.587772732" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.1422909417" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.301172250" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.835711007" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usebarrel.2050922871" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.2077945380" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usediv.2117224822" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.fpu.1948509195" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.331676528" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.610045271" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspInclude}"/>
</option>
<inputType id="xilinx.gnu.compiler.input.88842988" name="C source files" superClass="xilinx.gnu.compiler.input"/>
</tool>
<tool id="xilinx.gnu.mb.cxx.toolchain.compiler.release.233554043" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.release">
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1071676241" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.142972768" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.1469893295" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.190812498" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.82656265" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.1293985221" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usebarrel.557344692" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1584776451" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usediv.885761566" superClass="xilinx.gnu.mb.compiler.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.fpu.250999897" superClass="xilinx.gnu.mb.compiler.inferred.fpu" value="xilinx.gnu.mb.compiler.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.1901622397" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.787908182" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspInclude}"/>
</option>
</tool>
<tool id="xilinx.gnu.mb.toolchain.archiver.2101089573" name="MicroBlaze archiver" superClass="xilinx.gnu.mb.toolchain.archiver"/>
<tool id="xilinx.gnu.mb.c.toolchain.linker.release.1112198995" name="MicroBlaze gcc linker" superClass="xilinx.gnu.mb.c.toolchain.linker.release">
<option id="xilinx.gnu.mb.linker.inferred.mbversion.1560456653" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.linker.inferred.norelax.922620880" superClass="xilinx.gnu.mb.linker.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.garbage.1024317549" superClass="xilinx.gnu.mb.linker.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usele.986405362" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usebarrel.2054791336" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.176558075" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usediv.997551390" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.fpu.771924786" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1801825914" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.2032442504" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.145142568" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.301496449" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
<inputType id="xilinx.gnu.linker.input.2118718020" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
<inputType id="xilinx.gnu.linker.input.lscript.325304645" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
<tool id="xilinx.gnu.mb.cxx.toolchain.linker.release.108220038" name="MicroBlaze g++ linker" superClass="xilinx.gnu.mb.cxx.toolchain.linker.release">
<option id="xilinx.gnu.mb.linker.inferred.mbversion.1354177354" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.linker.inferred.norelax.2120048058" superClass="xilinx.gnu.mb.linker.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.garbage.1568018689" superClass="xilinx.gnu.mb.linker.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usele.1120071086" superClass="xilinx.gnu.mb.linker.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usebarrel.1341801441" superClass="xilinx.gnu.mb.linker.inferred.usebarrel" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.1718590776" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.usediv.317272787" superClass="xilinx.gnu.mb.linker.inferred.usediv" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.fpu.428463190" superClass="xilinx.gnu.mb.linker.inferred.fpu" value="xilinx.gnu.mb.linker.inferred.fpu.basic" valueType="enumerated"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.442677204" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1295304772" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=bootloader,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.1391446590" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.197421543" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
<tool id="xilinx.gnu.mb.size.release.1226510156" name="MicroBlaze Print Size" superClass="xilinx.gnu.mb.size.release"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="_ide" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="bootloader.xilinx.gnu.mb.exe.516922112" name="Xilinx MicroBlaze Executable" projectType="xilinx.gnu.mb.exe"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.408304434;xilinx.gnu.mb.exe.release.408304434.">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.787148227;xilinx.gnu.mb.exe.debug.787148227.">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.408304434;xilinx.gnu.mb.exe.release.408304434.;xilinx.gnu.mb.c.toolchain.compiler.release.218609145;xilinx.gnu.compiler.input.88842988">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.debug.787148227;xilinx.gnu.mb.exe.debug.787148227.;xilinx.gnu.mb.c.toolchain.compiler.debug.776270743;xilinx.gnu.compiler.input.359278436">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.MBGCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="refreshScope"/>
</cproject>

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vitis/bootloader/.gitignore vendored Normal file
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/Debug/
/Release/

27
vitis/bootloader/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>bootloader</name>
<comment>Created by Vitis v2022.2</comment>
<projects>
<project>top</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdx.sdk.core.SdkProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2022.2 (64-bit) -->
<!-- SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Oct 14 2022 -->
<!-- -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file. -->
<MemInfo Version="1" Minor="9">
<Processor Endianness="Little" InstPath="microblaze_bd_i/microblaze_0">
<AddressSpace Name="microblaze_bd_i_microblaze_0.microblaze_bd_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="32767">
<AddressSpaceRange Name="microblaze_bd_i_microblaze_0.microblaze_bd_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="32767" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
<BusBlock>
<BitLane MemType="RAMB36" Placement="X5Y36" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="7" LSB="4"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X5Y35" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="3" LSB="0"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y36" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="15" LSB="12"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y35" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="11" LSB="8"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y40" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="23" LSB="20"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y39" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="19" LSB="16"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y38" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="31" LSB="28"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X6Y37" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="27" LSB="24"/>
<AddressRange Begin="0" End="8191"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
</BusBlock>
</AddressSpaceRange>
</AddressSpace>
</Processor>
<Processor Endianness="Little" InstPath="microblaze_bd_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I">
<AddressSpace Name="microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_microblaze_I.microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_dlmb_cntlr" Begin="0" End="65535">
<AddressSpaceRange Name="microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_microblaze_I.microblaze_bd_i_ddr4_0_inst_u_ddr4_mem_intfc_u_ddr_cal_riu_mcs0_inst_dlmb_cntlr" Begin="0" End="65535" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
<BusBlock>
<BitLane MemType="RAMB36" Placement="X0Y8" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="7" LSB="6"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y9" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="5" LSB="4"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y7" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="3" LSB="2"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y10" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="1" LSB="0"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y20" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="15" LSB="14"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="13" LSB="12"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X2Y20" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="11" LSB="10"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y21" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="9" LSB="8"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y4" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="23" LSB="22"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y23" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="21" LSB="20"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y24" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="19" LSB="18"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y25" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="17" LSB="16"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y22" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="31" LSB="30"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X1Y22" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="29" LSB="28"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y5" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="27" LSB="26"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
<BitLane MemType="RAMB36" Placement="X0Y6" Read_Width="0" SLR_INDEX="-1">
<DataWidth MSB="25" LSB="24"/>
<AddressRange Begin="0" End="16383"/>
<BitLayout pattern=""/>
<Parity ON="false" NumBits="0"/>
</BitLane>
</BusBlock>
</AddressSpaceRange>
</AddressSpace>
</Processor>
<Config>
<Option Name="Part" Val="xcku040-ffva1156-2-i"/>
</Config>
<DRC>
<Rule Name="RDADDRCHANGE" Val="false"/>
</DRC>
</MemInfo>

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308456516

72
vitis/bootloader/_ide/launch/Debugger_bootloader-Default.launch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="com.xilinx.sdx.sdsoc.debug.launch.SdsTcfLaunchDelegate">
<booleanAttribute key="com.xilinx.sdk.tcf.debug.ui.breakpoint.main" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.ui.exec.script" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.ui.exec.script.location" value=""/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.ui.fsbl_exit_function" value="XFsbl_Exit"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.ui.fsbl_flow" value="true"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.ui.fsbl_path" value="${sdxTcfLaunchFile:project=bootloader;fileType=fsbl;}"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.ui.fsbl_run" value="true"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.ui.skip.fpga.revision.check" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiapplication.path" value="Debug/bootloader.elf"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uicrosstrigger.bpcontainer" value="{&quot;arch&quot;:&quot;non_zynq&quot;,&quot;isSelected&quot;:false,&quot;breakPoints&quot;:[]}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uidebug.type" value="STANDALONE_DEBUG"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uienable.crosstrigger" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uifpga.device" value="Auto Detect"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.bit.file" value=""/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uihw.init.tcl" value=""/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uipl.powerup" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.appl.map" value="{&quot;microblaze_0&quot;:{&quot;xilinx.tcf.application&quot;:&quot;Debug/bootloader.elf&quot;,&quot;xilinx.tcf.datafiles&quot;:&quot;&quot;,&quot;xilinx.tcf.no_download&quot;:false,&quot;xilinx.tcf.profile_enabled&quot;:false,&quot;xilinx.tcf.profile_frequency&quot;:&quot;10000&quot;,&quot;xilinx.tcf.profile_non_int_frequency&quot;:&quot;150000000&quot;,&quot;xilinx.tcf.profile_non_int_high_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_low_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.profile_non_int_use_count_instr&quot;:false,&quot;xilinx.tcf.profile_non_int_use_cumulate&quot;:false,&quot;xilinx.tcf.profile_non_intrusive_support&quot;:false,&quot;xilinx.tcf.profile_store_address&quot;:&quot;0x0&quot;,&quot;xilinx.tcf.profile_use_intrusive&quot;:false,&quot;xilinx.tcf.project&quot;:&quot;bootloader&quot;,&quot;xilinx.tcf.relocate&quot;:false,&quot;xilinx.tcf.relocate_addr&quot;:&quot;&quot;,&quot;xilinx.tcf.reset&quot;:false,&quot;xilinx.tcf.stop_at_entry&quot;:false}}"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproc.selection" value="microblaze_0"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uiprogram.fpga" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uiproject.name" value="bootloader"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uips.device" value="Auto Detect"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uips7.init" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uips7.post" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.apu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.lock.step" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.rpu" value="false"/>
<booleanAttribute key="com.xilinx.sdk.tcf.debug.uireset.system" value="false"/>
<stringAttribute key="com.xilinx.sdk.tcf.debug.uitarget.peer" value="Local"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.active.build.config" value="Debug"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.application.type" value=""/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.build.disabled" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.custom.launch.storage" value=""/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.data.files" value=""/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.debug.target" value=""/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.eclipse.portable.path" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.edge.kernel.function.names" value=""/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.edge.kernel.start" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.emulation" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.estimate" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.hw_spec.path" value="${sdxTcfLaunchFile:project=bootloader;fileType=hw;}"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.ingore.peer.conflict" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.launch.work.dir" value=""/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.performance.analysis" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.performance.analysis.linux.hw.target" value="Local"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.sdsoc.project" value="bootloader"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.secure.debug" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.secure.debug.image" value=""/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.system.launch" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.trace" value="false"/>
<stringAttribute key="com.xilinx.sdx.sdsoc.debug.ui.versal.system.emulation" value="false"/>
<stringAttribute key="ide.launch.pdi.path" value=""/>
<stringAttribute key="ide.launch.program.device" value="false"/>
<stringAttribute key="launch.version" value="2022.2"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/bootloader"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<booleanAttribute key="org.eclipse.tcf.debug.AttachChildren" value="true"/>
<booleanAttribute key="org.eclipse.tcf.debug.DisconnectOnCtxExit" value="false"/>
<booleanAttribute key="org.eclipse.tcf.debug.StopAtEntry" value="false"/>
<booleanAttribute key="org.eclipse.tcf.debug.StopAtMain" value="true"/>
<booleanAttribute key="org.eclipse.tcf.debug.UseContextFilter" value="false"/>
<booleanAttribute key="org.eclipse.tcf.debug.UseTerminal" value="false"/>
<stringAttribute key="profile.data.transfer.trace" value="coarse"/>
<stringAttribute key="profile.enable" value="true"/>
<stringAttribute key="profile.mode" value="default"/>
<stringAttribute key="profile.stall.trace" value="off"/>
</launchConfiguration>

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vitis/bootloader/bootloader.prj Normal file
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<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="bootloader" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/bootloader" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="bootloader_system" sysConfig="top" runtime="cpp" cpu="standalone_microblaze_0" cpuInstance="microblaze_0" os="standalone" mssSignature="5cf4b93eb4839ad64096fe0b93be55b5">
<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.787148227">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<configuration name="Release" id="xilinx.gnu.mb.exe.release.408304434" dirty="true">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<template appTemplateName="srec_spi_bootloader" hasBspSettings="true"/>
</sdkproject:SdkProject>

7
vitis/bootloader/src/blconfig.h Normal file
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/******************************************************************************
* Copyright (C) 2004 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#warning "Please provide the correct address value for the definition FLASH_IMAGE_BASEADDR. Please give the flash offset @ which SREC application is programmed"
#define FLASH_IMAGE_BASEADDR 0xd00000

545
vitis/bootloader/src/bootloader.c Normal file
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/******************************************************************************
* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/*
* Simple SREC Bootloader
* It is capable of booting an SREC format image file (Mototorola S-record format),
* given the location of the image in memory.
* In particular, this bootloader is designed for images stored in non-volatile flash
* memory that is addressable from the processor.
*
* Please modify the define "FLASH_IMAGE_BASEADDR" in the blconfig.h header file
* to point to the memory location from which the bootloader has to pick up the
* flash image from.
*
* You can include these sources in your software application project and build
* the project for the processor for which you want the bootload to happen.
* You can also subsequently modify these sources to adapt the bootloader for any
* specific scenario that you might require it for.
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "blconfig.h"
#include "portab.h"
#include "errors.h"
#include "srec.h"
#include "xparameters.h"
#include "xspi.h"
/* Defines */
#define CR 13
#define RECORD_TYPE 2
#define BYTE_COUNT 2
#define RECORD_TERMINATOR 2
/* Comment the following line, if you want a smaller and faster bootloader which will be silent */
#define VERBOSE
/* Declarations */
static void display_progress (uint32_t lines);
static uint8_t load_exec ();
static uint8_t flash_get_srec_line (uint8_t *buf);
extern void init_stdout();
uint8 grab_hex_byte (uint8 *buf);
/*
* The following constant defines the slave select signal that is used to
* to select the Flash device on the SPI bus, this signal is typically
* connected to the chip select of the device.
*/
#define SPI_SELECT 0x01
/*
* Number of bytes per page in the flash device.
*/
#define PAGE_SIZE 256
/*
* Byte Positions.
*/
#define BYTE1 0 /* Byte 1 position */
#define BYTE2 1 /* Byte 2 position */
#define BYTE3 2 /* Byte 3 position */
#define BYTE4 3 /* Byte 4 position */
#define BYTE5 4 /* Byte 5 position */
#define READ_WRITE_EXTRA_BYTES 4 /* Read/Write extra bytes */
#define READ_WRITE_EXTRA_BYTES_4BYTE_MODE 5 /**< Command extra bytes */
#define RD_ID_SIZE 4
#define ISSI_ID_BYTE0 0x9D
#define MICRON_ID_BYTE0 0x20
#define ENTER_4B_ADDR_MODE 0xb7 /* Enter 4Byte Mode command */
#define EXIT_4B_ADDR_MODE 0xe9 /* Exit 4Byte Mode command */
#define EXIT_4B_ADDR_MODE_ISSI 0x29
#define WRITE_ENABLE 0x06 /* Write Enable command */
#define ENTER_4B 1
#define EXIT_4B 0
#define FLASH_16_MB 0x18
#define FLASH_MAKE 0
#define FLASH_SIZE 2
#define READ_CMD 0x03
/* Declarations */
static void display_progress (uint32_t lines);
static uint8_t load_exec ();
static uint8_t flash_get_srec_line (uint8_t *buf);
extern void init_stdout();
uint8 grab_hex_byte (uint8 *buf);
int FlashReadID(void);
#define SPI_DEVICE_ID XPAR_SPI_2_DEVICE_ID
/*
* The instances to support the device drivers are global such that they
* are initialized to zero each time the program runs. They could be local
* but should at least be static so they are zeroed.
*/
static XSpi Spi;
int mode = READ_WRITE_EXTRA_BYTES;
u8 WriteBuffer[PAGE_SIZE + READ_WRITE_EXTRA_BYTES];
/*
* Buffer used during Read transactions.
*/
u8 ReadBuffer[PAGE_SIZE + READ_WRITE_EXTRA_BYTES];
u8 FlashID[3];
extern int srec_line;
#ifdef __cplusplus
extern "C" {
#endif
extern void outbyte(char c);
#ifdef __cplusplus
}
#endif
/* Data structures */
static srec_info_t srinfo;
static uint8_t sr_buf[SREC_MAX_BYTES];
static uint8_t sr_data_buf[SREC_DATA_MAX_BYTES];
u32 flbuf;
#ifdef VERBOSE
static int8_t *errors[] = {
"",
"Error while copying executable image into RAM",
"Error while reading an SREC line from flash",
"SREC line is corrupted",
"SREC has invalid checksum."
};
#endif
/* We don't use interrupts/exceptions.
Dummy definitions to reduce code size on MicroBlaze */
#ifdef __MICROBLAZE__
void _interrupt_handler () {}
void _exception_handler () {}
void _hw_exception_handler () {}
#endif
int main()
{
int Status;
uint8_t ret;
#ifdef VERBOSE
print ("\r\nSREC SPI Bootloader\r\n");
#endif
sleep(3);
// Reset QSPI
Xil_Out32(0x40050008, (1 << 10));
sleep(1);
Xil_Out32(0x40050008, 0);
sleep(1);
/*
* Initialize the SPI driver so that it's ready to use,
* specify the device ID that is generated in xparameters.h.
*/
Status = XSpi_Initialize(&Spi, SPI_DEVICE_ID);
if(Status != XST_SUCCESS) {
print("init fail");
return XST_FAILURE;
}
/*
* Set the SPI device as a master and in manual slave select mode such
* that the slave select signal does not toggle for every byte of a
* transfer, this must be done before the slave select is set.
*/
Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION |
XSP_MANUAL_SSELECT_OPTION);
if(Status != XST_SUCCESS) {
print("options fail");
return XST_FAILURE;
}
/*
* Select the flash device on the SPI bus, so that it can be
* read and written using the SPI bus.
*/
Status = XSpi_SetSlaveSelect(&Spi, SPI_SELECT);
if(Status != XST_SUCCESS) {
print("slave select fail");
return XST_FAILURE;
}
/*
* Start the SPI driver so that interrupts and the device are enabled.
*/
XSpi_Start(&Spi);
XSpi_IntrGlobalDisable(&Spi);
init_stdout();
sleep(1);
print ("Read Flash ID");
Status = FlashReadID( );
if(Status != XST_SUCCESS) {
print("flash read id fail");
return XST_FAILURE;
}
print ("Read Flash ID");
Status = FlashReadID( );
if(Status != XST_SUCCESS) {
print("flash read id fail");
return XST_FAILURE;
}
print ("Read Flash ID");
Status = FlashReadID( );
if(Status != XST_SUCCESS) {
print("flash read id fail");
return XST_FAILURE;
}
#ifdef VERBOSE
print ("Loading SREC image from flash @ address: ");
putnum (FLASH_IMAGE_BASEADDR);
print ("\r\n");
#endif
sleep(1);
print ("After Sleep");
flbuf = (u32)FLASH_IMAGE_BASEADDR;
ret = load_exec ();
/* If we reach here, we are in error */
#ifdef VERBOSE
if (ret > LD_SREC_LINE_ERROR) {
print ("ERROR in SREC line: ");
putnum (srec_line);
print (errors[ret]);
} else {
print ("ERROR: ");
print (errors[ret]);
}
#endif
return ret;
}
/*****************************************************************************/
/**
*
* This function enables writes to the Serial Flash memory.
*
* @param Spi is a pointer to the instance of the Spi device.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None
*
******************************************************************************/
int FlashWriteEnable(XSpi *Spi)
{
int Status;
u8 *NULLPtr = NULL;
/*
* Prepare the WriteBuffer.
*/
WriteBuffer[BYTE1] = WRITE_ENABLE;
Status = XSpi_Transfer(Spi, WriteBuffer, NULLPtr, 1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* @brief
* This API enters the flash device into 4 bytes addressing mode.
*
* @param Spi is a pointer to the instance of the Spi device.
* @param Enable is a either 1 or 0 if 1 then enters 4 byte if 0 exits.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if it fails.
*
*
******************************************************************************/
int FlashEnterExit4BAddMode(XSpi *Spi, unsigned int Enable)
{
int Status;
u8 *NULLPtr = NULL;
if((FlashID[FLASH_MAKE] == MICRON_ID_BYTE0) ||
(FlashID[FLASH_MAKE] == ISSI_ID_BYTE0)) {
Status = FlashWriteEnable(Spi);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
if (Enable) {
WriteBuffer[BYTE1] = ENTER_4B_ADDR_MODE;
} else {
if (FlashID[FLASH_MAKE] == ISSI_ID_BYTE0)
WriteBuffer[BYTE1] = EXIT_4B_ADDR_MODE_ISSI;
else
WriteBuffer[BYTE1] = EXIT_4B_ADDR_MODE;
}
Status = XSpi_Transfer(Spi, WriteBuffer, NULLPtr, 1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function reads serial FLASH ID connected to the SPI interface.
*
* @param None.
*
* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
int FlashReadID(void)
{
int Status;
int i;
/* Read ID in Auto mode.*/
WriteBuffer[BYTE1] = 0x9f;
WriteBuffer[BYTE2] = 0xff; /* 4 dummy bytes */
WriteBuffer[BYTE3] = 0xff;
WriteBuffer[BYTE4] = 0xff;
WriteBuffer[BYTE5] = 0xff;
Status = XSpi_Transfer(&Spi, WriteBuffer, ReadBuffer, 5);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
for(i = 0; i < 3; i++)
FlashID[i] = ReadBuffer[i + 1];
#ifdef VERBOSE
xil_printf("FlashID=0x%x 0x%x 0x%x\n\r", ReadBuffer[1], ReadBuffer[2],
ReadBuffer[3]);
#endif
return XST_SUCCESS;
}
#ifdef VERBOSE
static void display_progress (uint32_t count)
{
/* Send carriage return */
outbyte (CR);
print ("Bootloader: Processed (0x)");
putnum (count);
print (" S-records");
}
#endif
static uint8_t load_exec ()
{
uint8_t ret;
void (*laddr)();
int8_t done = 0;
int Status;
srinfo.sr_data = sr_data_buf;
if(FlashID[FLASH_SIZE] > FLASH_16_MB) {
Status = FlashEnterExit4BAddMode(&Spi, ENTER_4B);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
mode = READ_WRITE_EXTRA_BYTES_4BYTE_MODE;
}
while (!done) {
if ((ret = flash_get_srec_line (sr_buf)) != 0)
return ret;
if ((ret = decode_srec_line (sr_buf, &srinfo)) != 0)
return ret;
#ifdef VERBOSE
if (srec_line % 16 == 0) {
// Don't print every line because it takes forever over UART
display_progress (srec_line);
}
#endif
switch (srinfo.type) {
case SREC_TYPE_0:
break;
case SREC_TYPE_1:
case SREC_TYPE_2:
case SREC_TYPE_3:
memcpy ((void*)srinfo.addr, (void*)srinfo.sr_data, srinfo.dlen);
break;
case SREC_TYPE_5:
break;
case SREC_TYPE_7:
case SREC_TYPE_8:
case SREC_TYPE_9:
laddr = (void (*)())srinfo.addr;
done = 1;
ret = 0;
break;
}
}
if(FlashID[FLASH_SIZE] > FLASH_16_MB) {
Status = FlashEnterExit4BAddMode(&Spi, EXIT_4B);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
mode = READ_WRITE_EXTRA_BYTES;
}
#ifdef VERBOSE
print ("\r\nExecuting program starting at address: ");
putnum ((uint32_t)laddr);
print ("\r\n");
#endif
(*laddr)();
/* We will be dead at this point */
return 0;
}
static uint8_t flash_get_srec_line (uint8_t *buf)
{
int Status;
int i;
int len;
u8 ReadCmd = READ_CMD;
/*
* Read 1st 4bytes of a record. Its contains the information about
* the type of the record and number of bytes that follow in the
* rest of the record (address + data + checksum).
*/
if(mode == READ_WRITE_EXTRA_BYTES) {
WriteBuffer[BYTE1] = ReadCmd;
WriteBuffer[BYTE2] = (u8) (flbuf >> 16);
WriteBuffer[BYTE3] = (u8) (flbuf >> 8);
WriteBuffer[BYTE4] = (u8) flbuf;
} else {
WriteBuffer[BYTE1] = ReadCmd;
WriteBuffer[BYTE2] = (u8) (flbuf >> 24);
WriteBuffer[BYTE3] = (u8) (flbuf >> 16);
WriteBuffer[BYTE4] = (u8) (flbuf >> 8);
WriteBuffer[BYTE5] = (u8) flbuf;
}
Status = XSpi_Transfer(&Spi, WriteBuffer, ReadBuffer,
(RECORD_TYPE + BYTE_COUNT + mode));
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
flbuf += RECORD_TYPE + BYTE_COUNT;
/*
* Get the number of bytes (address + data + checksum) in a record.
*/
len = grab_hex_byte((ReadBuffer + mode + RECORD_TYPE)) * 2;
for(i = 0; i < (RECORD_TYPE + BYTE_COUNT); i++)
*buf++ = ReadBuffer[mode + i];
/*
* Read address + data + checksum from the record.
*/
if(mode == READ_WRITE_EXTRA_BYTES) {
WriteBuffer[BYTE1] = ReadCmd;
WriteBuffer[BYTE2] = (u8) (flbuf >> 16);
WriteBuffer[BYTE3] = (u8) (flbuf >> 8);
WriteBuffer[BYTE4] = (u8) flbuf;
} else {
WriteBuffer[BYTE1] = ReadCmd;
WriteBuffer[BYTE2] = (u8) (flbuf >> 24);
WriteBuffer[BYTE3] = (u8) (flbuf >> 16);
WriteBuffer[BYTE4] = (u8) (flbuf >> 8);
WriteBuffer[BYTE5] = (u8) flbuf;
}
Status = XSpi_Transfer(&Spi, WriteBuffer, ReadBuffer, (len + mode));
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
flbuf += (len + RECORD_TERMINATOR);
for(i = 0; i < len; i++)
*buf++ = ReadBuffer[mode + i];
if ((RECORD_TYPE + BYTE_COUNT + len) > SREC_MAX_BYTES)
return LD_SREC_LINE_ERROR;
return 0;
}
#ifdef __PPC__
#include <unistd.h>
/* Save some code and data space on PowerPC
by defining a minimal exit */
void exit (int ret):
{
_exit (ret);
}
#endif

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vitis/bootloader/src/errors.h Normal file
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/******************************************************************************
* Copyright (C) 2004 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef BL_ERRORS_H
#define BL_ERRORS_H
#define LD_MEM_WRITE_ERROR 1
#define LD_SREC_LINE_ERROR 2
#define SREC_PARSE_ERROR 3
#define SREC_CKSUM_ERROR 4
#endif /* BL_ERRORS_H */

221
vitis/bootloader/src/lscript.ld Normal file
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/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: 2018.3 */
/* */
/* Copyright (c) 2010-2019 Xilinx, Inc. All rights reserved. */
/* */
/* Description : MicroBlaze Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0;
/* Define Memories in the system */
MEMORY
{
microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem : ORIGIN = 0x50, LENGTH = 0x7FB0
ddr4_0_C0_DDR4_MEMORY_MAP_BASEADDR_C0_DDR4_ADDRESS_BLOCK : ORIGIN = 0x80000000, LENGTH = 0x80000000
axi_bram_ctrl_0_Mem0 : ORIGIN = 0x10000, LENGTH = 0x8000
axi_bram_ctrl_1_Mem0 : ORIGIN = 0x20000, LENGTH = 0x8000
axi_bram_ctrl_2_Mem0 : ORIGIN = 0x30000, LENGTH = 0x8000
axi_bram_ctrl_3_Mem0 : ORIGIN = 0x40000, LENGTH = 0x8000
}
/* Specify the default entry point to the program */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.vectors.reset 0x0 : {
KEEP (*(.vectors.reset))
}
.vectors.sw_exception 0x8 : {
KEEP (*(.vectors.sw_exception))
}
.vectors.interrupt 0x10 : {
KEEP (*(.vectors.interrupt))
}
.vectors.hw_exception 0x20 : {
KEEP (*(.vectors.hw_exception))
}
.text : {
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.note.gnu.build-id : {
KEEP (*(.note.gnu.build-id))
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.init : {
KEEP (*(.init))
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.fini : {
KEEP (*(.fini))
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
PROVIDE(__DTOR_END__ = .);
PROVIDE(___DTORS_END___ = .);
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.sdata2 : {
. = ALIGN(8);
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
. = ALIGN(8);
__sdata2_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.data : {
. = ALIGN(4);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
__data_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.got : {
*(.got)
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.got1 : {
*(.got1)
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.got2 : {
*(.got2)
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.eh_frame : {
*(.eh_frame)
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.jcr : {
*(.jcr)
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.gcc_except_table : {
*(.gcc_except_table)
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.sdata : {
. = ALIGN(8);
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.sbss (NOLOAD) : {
. = ALIGN(4);
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
. = ALIGN(8);
__sbss_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.bss (NOLOAD) : {
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(8);
_heap = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
.stack (NOLOAD) : {
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem
_end = .;
}

20
vitis/bootloader/src/platform.c Normal file
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/******************************************************************************
* Copyright (C) 2004 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xparameters.h"
#include "platform_config.h"
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
#endif
void
init_stdout()
{
/* if we have a uart 16550, then that needs to be initialized */
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
}

4
vitis/bootloader/src/platform_config.h Normal file
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#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#endif

33
vitis/bootloader/src/portab.h Normal file
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/******************************************************************************
* Copyright (C) 2004 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef BL_PORTAB_H
#define BL_PORTAB_H
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned int uint32;
typedef char int8;
typedef short int16;
typedef int int32;
/* An anonymous union allows the compiler to report typedef errors automatically */
/* Does not work with gcc. Might work only for g++ */
/* static union */
/* { */
/* char int8_incorrect [sizeof( int8) == 1]; */
/* char uint8_incorrect [sizeof( uint8) == 1]; */
/* char int16_incorrect [sizeof( int16) == 2]; */
/* char uint16_incorrect [sizeof(uint16) == 2]; */
/* char int32_incorrect [sizeof( int32) == 4]; */
/* char uint32_incorrect [sizeof(uint32) == 4]; */
/* }; */
#endif /* BL_PORTTAB_H */

153
vitis/bootloader/src/srec.c Normal file
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/******************************************************************************
* Copyright (C) 2004 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "portab.h"
#include "srec.h"
#include "errors.h"
uint8 grab_hex_byte (uint8 *buf);
uint16 grab_hex_word (uint8 *buf);
uint32 grab_hex_dword (uint8 *buf);
uint32 grab_hex_word24 (uint8 *buf);
int srec_line = 0;
uint8 nybble_to_val (char x)
{
if (x >= '0' && x <= '9')
return (uint8)(x-'0');
return (uint8)((x-'A') + 10);
}
uint8 grab_hex_byte (uint8 *buf)
{
return (uint8)((nybble_to_val ((char)buf[0]) << 4) +
nybble_to_val ((char)buf[1]));
}
uint16 grab_hex_word (uint8 *buf)
{
return (uint16)(((uint16)grab_hex_byte (buf) << 8) +
grab_hex_byte ((uint8*)((int)buf+2)));
}
uint32 grab_hex_word24 (uint8 *buf)
{
return (uint32)(((uint32)grab_hex_byte (buf) << 16) +
grab_hex_word ((uint8*)((int)buf+2)));
}
uint32 grab_hex_dword (uint8 *buf)
{
return (uint32)(((uint32)grab_hex_word (buf) << 16) +
grab_hex_word ((uint8*)((int)buf+4)));
}
uint8 decode_srec_data (uint8 *bufs, uint8 *bufd, uint8 count, uint8 skip)
{
uint8 cksum = 0, cbyte;
int i;
/* Parse remaining character pairs */
for (i=0; i < count; i++) {
cbyte = grab_hex_byte (bufs);
if ((i >= skip - 1) && (i != count-1)) /* Copy over only data bytes */
*bufd++ = cbyte;
bufs += 2;
cksum += cbyte;
}
return cksum;
}
uint8 eatup_srec_line (uint8 *bufs, uint8 count)
{
int i;
uint8 cksum = 0;
for (i=0; i < count; i++) {
cksum += grab_hex_byte(bufs);
bufs += 2;
}
return cksum;
}
uint8 decode_srec_line (uint8 *sr_buf, srec_info_t *info)
{
uint8 count;
uint8 *bufs;
uint8 cksum = 0, skip;
int type;
bufs = sr_buf;
srec_line++; /* for debug purposes on errors */
if ( *bufs != 'S') {
return SREC_PARSE_ERROR;
}
type = *++bufs - '0';
count = grab_hex_byte (++bufs);
bufs += 2;
cksum = count;
switch (type) {
case 0:
info->type = SREC_TYPE_0;
info->dlen = count;
cksum += eatup_srec_line (bufs, count);
break;
case 1:
info->type = SREC_TYPE_1;
skip = 3;
info->addr = (uint8*)(uint32)grab_hex_word (bufs);
info->dlen = count - skip;
cksum += decode_srec_data (bufs, info->sr_data, count, skip);
break;
case 2:
info->type = SREC_TYPE_2;
skip = 4;
info->addr = (uint8*)(uint32)grab_hex_word24 (bufs);
info->dlen = count - skip;
cksum += decode_srec_data (bufs, info->sr_data, count, skip);
break;
case 3:
info->type = SREC_TYPE_3;
skip = 5;
info->addr = (uint8*)(uint32)grab_hex_dword (bufs);
info->dlen = count - skip;
cksum += decode_srec_data (bufs, info->sr_data, count, skip);
break;
case 5:
info->type = SREC_TYPE_5;
info->addr = (uint8*)(uint32)grab_hex_word (bufs);
cksum += eatup_srec_line (bufs, count);
break;
case 7:
info->type = SREC_TYPE_7;
info->addr = (uint8*)(uint32)grab_hex_dword (bufs);
cksum += eatup_srec_line (bufs, count);
break;
case 8:
info->type = SREC_TYPE_8;
info->addr = (uint8*)(uint32)grab_hex_word24 (bufs);
cksum += eatup_srec_line (bufs, count);
break;
case 9:
info->type = SREC_TYPE_9;
info->addr = (uint8*)(uint32)grab_hex_word (bufs);
cksum += eatup_srec_line (bufs, count);
break;
default:
return SREC_PARSE_ERROR;
}
if (++cksum) {
return SREC_CKSUM_ERROR;
}
return 0;
}

38
vitis/bootloader/src/srec.h Normal file
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/******************************************************************************
* Copyright (C) 2004 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/* Note: This file depends on the following files having been included prior to self being included.
1. portab.h
*/
#ifndef BL_SREC_H
#define BL_SREC_H
#define SREC_MAX_BYTES 255 /* Maximum record length */
#define SREC_DATA_MAX_BYTES 123 /* Maximum of 123 data bytes */
#define SREC_TYPE_0 0
#define SREC_TYPE_1 1
#define SREC_TYPE_2 2
#define SREC_TYPE_3 3
#define SREC_TYPE_5 5
#define SREC_TYPE_7 7
#define SREC_TYPE_8 8
#define SREC_TYPE_9 9
typedef struct srec_info_s {
int8 type;
uint8* addr;
uint8* sr_data;
uint8 dlen;
} srec_info_t;
uint8 decode_srec_line (uint8 *sr_buf, srec_info_t *info);
#endif /* BL_SREC_H */

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