bkiedinger/castelion_radar_alinx_kintex
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version number and reverified data recording rate

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This commit is contained in:
bkiedinger@gmail.com
2025-06-08 16:34:22 -05:00
parent 68a4ed1428
commit 316ae900ae
11 changed files with 85 additions and 20 deletions
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1
cpp/data_recorder.cpp
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@@ -185,6 +185,7 @@ void DataRecorder::write_data() {
// A chunk is ready write it out
int cnt = write(out_fd, &(data_buffer[buffer_ind]), WRITE_CHUNK_SIZE);
total_bytes += cnt;
if (cnt < 0)
{
printf("File write error!\n");

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cpp/test_data_recorder
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13
python/radar_manager.py
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@@ -10,6 +10,7 @@ import numpy as np
import data_structures as msg_types
from data_structures import CpiHeader
UTIL_REG_ADDR = 0x40050000
TIMING_ENGINE_ADDR = 0x40051000
DIG_RX_ADDR = 0x20000000
DIG_RX_STRIDE = 0x10000
@@ -66,6 +67,7 @@ class RadarManager:
self.CONNECTED = False
self.connect()
self.get_fpga_datecode()
# Update UDP packet size
self.packet_size = 4096
@@ -259,6 +261,17 @@ class RadarManager:
return
def update_ip_address(self, ip, mask, gw, port):
ip = ipaddress.IPv4Address(ip)
mask = ipaddress.IPv4Address(mask)
gw = ipaddress.IPv4Address(gw)
data = bytes(np.array([ip, mask, gw, port], dtype=np.uint32))
self.config_flash_write(0xf00000, data)
def get_fpga_datecode(self):
datecode = self.axi_read_register(UTIL_REG_ADDR + 0x114)
timecode = self.axi_read_register(UTIL_REG_ADDR + 0x118)
print('FPGA Datestamp %x_%x' % (datecode, timecode))
def load_waveform(self, ch, amp, bw, pw):
# addr = 0x0010000 + 0x0010000 * ch

16
python/test_cpi.py
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@@ -14,7 +14,7 @@ from data_recorder import DataRecorder
# Note that increases the size of rmem_max in the linux kernel improves performance for data recording
# this can be done witht the following terminal command
# sudo sysctl -w net.core.rmem_max=1048576
# sudo sysctl -w net.core.rmem_max=41918464
def db20(x):
return 20*np.log10(np.abs(x))
@@ -29,7 +29,7 @@ def db20n(x):
def main():
print('Hello')
radar = radar_manager.RadarManager(host='192.168.1.201', port=5002)
radar = radar_manager.RadarManager(host='192.168.1.200', port=5001)
clk = radar_manager.TIMING_ENGINE_FREQ
@@ -42,15 +42,6 @@ def main():
radar.ad9081_write_reg(0x0A0A, 0x60)
print(hex(radar.ad9081_read_reg(0x0A0A)))
# Program Config Flash IP Address
ip = ipaddress.IPv4Address('192.168.1.201')
mask = ipaddress.IPv4Address('255.255.255.0')
gw = ipaddress.IPv4Address('192.168.1.1')
port = 5002
data = bytes(np.array([ip, mask, gw, port], dtype=np.uint32))
radar.config_flash_write(0xf00000, data)
# CPI Parameters (timing values are in clk ticks)
num_pulses = 128
# Should be multiple of udp packet size, currently 4096 bytes, or 1024 samples
@@ -66,6 +57,7 @@ def main():
inter_cpi = 20000
tx_lo_offset = 10e6
rx_lo_offset = 0
test_duration = 60
pri_float = pri / clk
@@ -85,7 +77,7 @@ def main():
print('Start Running')
radar.start_running()
# Let it run for a bit
time.sleep(60)
time.sleep(test_duration)
# Stop running
radar.stop_running()
# Stop the data recorder

25
python/update_ip.py Executable file
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@@ -0,0 +1,25 @@
import numpy as np
import ipaddress
import radar_manager
# This scrip updates the IP address stored in the configuration flash chip on the FPGA board
# After running this script the FPGA must be power cycled for the new IP to take effect
def main():
print('Updating IP Address')
radar = radar_manager.RadarManager(host='192.168.1.200', port=5001)
# Program Config Flash IP Address
ip = '192.168.1.200'
mask = '255.255.255.0'
gw = '192.168.1.1'
port = 5001
radar.update_ip_address(ip, mask, gw, port)
print('Updating IP Address Complete')
if __name__ == '__main__':
main()

7
radar_alinx_kintex.srcs/sources_1/hdl/top.v
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@@ -132,6 +132,11 @@ module top #
output wire resetb
);
parameter DATE_CODE = 32'h0000_0000;
parameter TIME_CODE = 32'h0000_0000;
wire mdio_mdio_i;
wire mdio_mdio_o;
wire mdio_mdio_t;
@@ -753,6 +758,8 @@ module top #
.gpi(gpi),
.packet_size(packet_size),
.fan_pwm(fan_pwm),
.datecode(DATE_CODE),
.timecode(TIME_CODE),
.tx0_rf_attn_sin(tx0_rf_attn_sin),
.tx0_rf_attn_clk(tx0_rf_attn_clk),

8
radar_alinx_kintex.srcs/sources_1/hdl/util_reg.v
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@@ -15,6 +15,8 @@ module util_reg #
input wire [31:0] gpi,
output wire [15:0] packet_size,
output wire fan_pwm,
input wire [31:0] datecode,
input wire [31:0] timecode,
output wire tx0_rf_attn_sin, //ADRF5730
output wire tx0_rf_attn_clk, //ADRF5730
@@ -203,7 +205,11 @@ always @ (posedge ctrl_if.clk) begin
if (raddr[11:0] == 'h10C)
rdata <= reg_spi_clk_div;
if (raddr[11:0] == 'h110)
rdata <= {28'b0000000, 2'b00, spi_active, le_active};
rdata <= {28'b0000000, 2'b00, spi_active, le_active};
if (raddr[11:0] == 'h114)
rdata <= datecode;
if (raddr[11:0] == 'h118)
rdata <= timecode;
end
end

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radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
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18
radar_alinx_kintex.xpr
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@@ -564,6 +564,14 @@
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/set_build_date.tcl">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
<Attr Name="UsedInSteps" Val="synth_1;SYNTH_DESIGN;TCL.PRE"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@@ -763,8 +771,10 @@
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design" PreStepTclHook="$PSRCDIR/set_build_date.tcl"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
@@ -893,7 +903,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>

15
vitis/radar/src/ad9081_hal_functions.c
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@@ -70,18 +70,27 @@ int32_t ad9081_hal_log_write(void *user_data, int32_t log_type, const char *comm
char log_msg[MAX_LOG_LINE_LENGTH] = {0};
const char *log_type_str;
int enable_log = 0;
log_type_str = "MESSAGE:";
if ((log_type & ADI_CMS_LOG_WARN) > 0)
if ((log_type & ADI_CMS_LOG_WARN) > 0) {
enable_log = 1;
log_type_str = "WARNING:";
if ((log_type & ADI_CMS_LOG_ERR) > 0)
}
if ((log_type & ADI_CMS_LOG_ERR) > 0) {
enable_log = 1;
log_type_str = "ERROR :";
}
err = snprintf(log_msg + strlen(log_msg), MAX_LOG_LINE_LENGTH, "%s ", log_type_str);
if (err < 0)
return API_CMS_ERROR_LOG_WRITE;
if (vsprintf(log_msg + strlen(log_msg), comment, argp) < 0)
return API_CMS_ERROR_LOG_WRITE;
xil_printf("%s\r\n", log_msg);
if (enable_log) {
xil_printf("%s\r\n", log_msg);
}
// if (fprintf(g_log_fd, "%s\n", log_msg) < 0)
// return API_CMS_ERROR_LOG_WRITE;

2
vitis/radar/src/main.c
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@@ -112,7 +112,7 @@ void main_task( void *pvParameters ) {
xPortInstallInterruptHandler(XPAR_MICROBLAZE_0_AXI_INTC_SYSTEM_PPS_INTR, (XInterruptHandler) pps_irq_handler, (void *)0);
vPortEnableInterrupt(XPAR_MICROBLAZE_0_AXI_INTC_SYSTEM_PPS_INTR);
// setup_data_converter();
setup_data_converter();
// config_flash_sector_erase(CONFIG_BASE_ADDRESS);