version number and reverified data recording rate

This commit is contained in:
2025-06-08 16:34:22 -05:00
parent 68a4ed1428
commit 316ae900ae
11 changed files with 85 additions and 20 deletions

View File

@@ -10,6 +10,7 @@ import numpy as np
import data_structures as msg_types
from data_structures import CpiHeader
UTIL_REG_ADDR = 0x40050000
TIMING_ENGINE_ADDR = 0x40051000
DIG_RX_ADDR = 0x20000000
DIG_RX_STRIDE = 0x10000
@@ -66,6 +67,7 @@ class RadarManager:
self.CONNECTED = False
self.connect()
self.get_fpga_datecode()
# Update UDP packet size
self.packet_size = 4096
@@ -259,6 +261,17 @@ class RadarManager:
return
def update_ip_address(self, ip, mask, gw, port):
ip = ipaddress.IPv4Address(ip)
mask = ipaddress.IPv4Address(mask)
gw = ipaddress.IPv4Address(gw)
data = bytes(np.array([ip, mask, gw, port], dtype=np.uint32))
self.config_flash_write(0xf00000, data)
def get_fpga_datecode(self):
datecode = self.axi_read_register(UTIL_REG_ADDR + 0x114)
timecode = self.axi_read_register(UTIL_REG_ADDR + 0x118)
print('FPGA Datestamp %x_%x' % (datecode, timecode))
def load_waveform(self, ch, amp, bw, pw):
# addr = 0x0010000 + 0x0010000 * ch