support for multiple waveforms

2025-06-29 20:18:52 -05:00
parent d60c55f292
commit 6dfee38d7c
9 changed files with 116 additions and 57 deletions
--- a/python/radar_manager.py
+++ b/python/radar_manager.py
@@ -6,6 +6,7 @@ import struct
 import time

 import numpy as np
+from matplotlib import pyplot as plt

 import data_structures as msg_types
 from data_structures import CpiHeader
@@ -273,32 +274,36 @@ class RadarManager:
        timecode = self.axi_read_register(UTIL_REG_ADDR + 0x118)
        print('FPGA Datestamp %x_%x' % (datecode, timecode))

-    def load_waveform(self, ch, amp, bw, pw):
-        # addr = 0x0010000 + 0x0010000 * ch
+    def load_waveform(self, ch, amp, bw, pw, num_wf=1):
        addr = 0x0020000 + 0x0020000 * ch
        print('Load', hex(addr))
        num_samples = pw
-        wf = form_chirp(pw, bw, 1)
-        wf = wf * amp

-        bram_address = addr
+        waveforms = np.empty(num_wf*num_samples, dtype=np.complex64)
+        for wf_ind in range(num_wf):
+            wf = form_chirp(pw, bw, 1)
+            wf = wf * amp / (wf_ind + 1)
+            waveforms[(wf_ind * num_samples):(wf_ind * num_samples + num_samples)] = wf

-        iq = wf * 0x7FFF
+        # plt.plot(waveforms.real)
+        # plt.show()
+
+        iq = waveforms * 0x7FFF
        iq_real = iq.real.astype(np.uint16)
        iq_imag = iq.imag.astype(np.uint16)
        iq_real = iq_real.astype(np.uint32)
        iq_imag = iq_imag.astype(np.uint32)
        data = iq_real | (iq_imag << 16)

-        num_bursts = num_samples / msg_types.MAX_BURST_LENGTH
+        num_bursts = len(waveforms) / msg_types.MAX_BURST_LENGTH
        num_bursts = int(np.ceil(num_bursts))

        for i in range(num_bursts):
            start_ind = i * msg_types.MAX_BURST_LENGTH
            stop_ind = start_ind + msg_types.MAX_BURST_LENGTH
-            stop_ind = min(stop_ind, num_samples)
+            stop_ind = min(stop_ind, num_wf*num_samples)
            burst_data = data[start_ind:stop_ind]
-            self.axi_write_register_burst(bram_address + i * 4 * msg_types.MAX_BURST_LENGTH, burst_data)
+            self.axi_write_register_burst(addr + i * 4 * msg_types.MAX_BURST_LENGTH, burst_data)

    def reset_10g_udp(self):
        val = self.axi_read_register(0x40050008)
@@ -348,7 +353,7 @@ class RadarManager:
            # Just force the enable high all the time before we start running
            self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, 0x1FFFFFFF)

-    def setup_tx(self, num_samples, start_sample):
+    def setup_tx(self, num_samples, start_sample, num_wf):
        if JESD204B:
            self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 1)
            self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 1)
@@ -356,6 +361,8 @@ class RadarManager:
            self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 2)
            self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 2)

+        self.axi_write_register(WAVEFORM_GEN_ADDR + 0xC, num_wf)
+
        # Setup TX Strobe
        # self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample >> 2)
        # self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples >> 2)
@@ -389,8 +396,11 @@ class RadarManager:

    def configure_cpi(self, pri, inter_cpi, num_pulses, num_samples, start_sample,
                      tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset, dec_rate):
-        self.load_waveform(0, 1, 0.05, tx_num_samples)
-        self.load_waveform(1, 1, 0.05, tx_num_samples)
+
+        num_wf = 4
+
+        self.load_waveform(0, 1, 0.05, tx_num_samples, num_wf)
+        self.load_waveform(1, 1, 0.05, tx_num_samples, num_wf)

        num_samples_quant = int(self.packet_size / 4)
        if num_samples % num_samples_quant > 0:
@@ -421,6 +431,6 @@ class RadarManager:

        self.setup_timing_engine(pri, num_pulses, inter_cpi)
        self.setup_rx(num_samples, start_sample, dec_rate)
-        self.setup_tx(tx_num_samples, tx_start_sample)
+        self.setup_tx(tx_num_samples, tx_start_sample, num_wf)
        self.setup_cpi_header(pri, inter_cpi, num_pulses, num_samples, start_sample,
                      tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset)
--- a/python/read_data_file.py
+++ b/python/read_data_file.py
@@ -92,10 +92,16 @@ def main():
    # # plt.ylim([0, .04])

    plt.figure()
-    plt.plot(iq.T.real, '.-')
-    plt.plot(iq.T.imag, '--.')
+    plt.plot(iq[0:4, :].T.real, '.-')
+    # plt.plot(iq[0:4, :].T.imag, '--.')
    plt.grid()

+    plt.figure()
+    plt.plot(np.mean(iq, axis=0).real, '.-')
+    plt.plot(np.mean(iq, axis=0).imag, '--.')
+    plt.grid()
+
+
    plt.figure()
    plt.imshow(db20n(iq), aspect='auto', interpolation='nearest', vmin=vmin, vmax=vmax)
    plt.ylabel('Pulse Count')
--- a/python/test_cpi.py
+++ b/python/test_cpi.py
@@ -45,11 +45,11 @@ def main():
    # CPI Parameters (timing values are in clk ticks)
    num_pulses = 128
    # Should be multiple of udp packet size, currently 4096 bytes, or 1024 samples
-    num_samples = 4096
+    num_samples = 8192
    start_sample = 2000
    tx_num_samples = 4096
    tx_start_sample = start_sample
-    prf = 8000
+    prf = 1000
    pri = int(1/prf * clk)
    pri -= (pri % 3)
    # pri = int(.0001 * clk)
@@ -57,7 +57,7 @@ def main():
    inter_cpi = 20000
    tx_lo_offset = 10e6
    rx_lo_offset = 0
-    dec_rate = 16
+    dec_rate = 1
    test_duration = 2

    pri_float = pri / clk
--- a/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ui/bd_37ca4332.ui
+++ b/radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ui/bd_37ca4332.ui
@@ -1,7 +1,7 @@
 {
   "ActiveEmotionalView":"Default View",
-   "Default View_ScaleFactor":"1.0",
-   "Default View_TopLeft":"-400,-66",
+   "Default View_ScaleFactor":"2.10612",
+   "Default View_TopLeft":"55,0",
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
 #  -string -flagsOSRD
@@ -23,25 +23,25 @@ preplace inst axis_broadcaster_2 -pg 1 -lvl 6 -x 1620 -y 350 -defaultsOSRD
 preplace inst dec_4_width -pg 1 -lvl 8 -x 2200 -y 80 -defaultsOSRD
 preplace inst dec_16_width -pg 1 -lvl 8 -x 2200 -y 400 -defaultsOSRD
 preplace inst dec_8_width -pg 1 -lvl 8 -x 2200 -y 540 -defaultsOSRD
-preplace netloc Net 1 0 8 -70 270 210 300 540 190 830 220 1160 410 1460 430 1790 460 2080
-preplace netloc Net1 1 0 8 -80 280 220 290 520 180 840 380 1170 420 1470 440 1780 470 2090
-preplace netloc dec_2_fir_M_AXIS_DATA 1 1 1 N 190
-preplace netloc axis_broadcaster_0_M01_AXIS 1 2 1 530 220n
-preplace netloc dec_4_fir_M_AXIS_DATA 1 3 1 N 280
-preplace netloc axis_broadcaster_1_M01_AXIS 1 4 1 N 310
-preplace netloc dec_8_fir_M_AXIS_DATA 1 5 1 N 330
-preplace netloc axis_broadcaster_2_M01_AXIS 1 6 1 N 360
+preplace netloc Net 1 0 8 -70 270 200 300 540 190 820 220 1160 410 1450 430 1790 460 2070
+preplace netloc Net1 1 0 8 -80 280 210 290 520 180 830 380 1170 420 1460 440 1780 470 2080
 preplace netloc axis_broadcaster_0_M00_AXIS 1 2 6 N 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ
+preplace netloc axis_broadcaster_0_M01_AXIS 1 2 1 530 220n
 preplace netloc axis_broadcaster_1_M00_AXIS 1 4 4 1150 60 NJ 60 NJ 60 NJ
+preplace netloc axis_broadcaster_1_M01_AXIS 1 4 1 N 310
 preplace netloc axis_broadcaster_2_M00_AXIS 1 6 2 1770 520 NJ
+preplace netloc axis_broadcaster_2_M01_AXIS 1 6 1 N 360
 preplace netloc dec_16_fir_M_AXIS_DATA 1 7 1 N 380
-preplace netloc dec_2_width_M_AXIS 1 8 1 NJ 220
-preplace netloc dec_4_width_M_AXIS 1 8 1 NJ 80
-preplace netloc dec_8_width_M_AXIS 1 8 1 NJ 540
 preplace netloc dec_16_width_M_AXIS 1 8 1 NJ 400
+preplace netloc dec_2_fir_M_AXIS_DATA 1 1 1 N 190
+preplace netloc dec_2_width_M_AXIS 1 8 1 NJ 220
+preplace netloc dec_4_fir_M_AXIS_DATA 1 3 1 N 280
+preplace netloc dec_4_width_M_AXIS 1 8 1 NJ 80
+preplace netloc dec_8_fir_M_AXIS_DATA 1 5 1 N 330
+preplace netloc dec_8_width_M_AXIS 1 8 1 NJ 540
 preplace netloc in_i_1 1 0 1 NJ 170
 levelinfo -pg 1 -100 70 370 690 1000 1320 1620 1940 2200 2330
 pagesize -pg 1 -db -bbox -sgen -180 0 2450 620
 "
 }
-
+0
--- a/radar_alinx_kintex.srcs/sources_1/hdl/top.v
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/top.v
@@ -202,7 +202,7 @@ module top #
    wire jesd_core_clk_in;
    wire jesd_core_clk2_in;
  
-    wire [14:0] dac0_wf_bram_addr;
+    wire [31:0] dac0_wf_bram_addr;
    wire        dac0_wf_bram_clk;
    wire [31:0] dac0_wf_bram_din;
    wire [31:0] dac0_wf_bram_dout;
@@ -210,7 +210,7 @@ module top #
    wire        dac0_wf_bram_rst;
    wire [3:0]  dac0_wf_bram_we;    
    
-    wire [14:0] dac1_wf_bram_addr;
+    wire [31:0] dac1_wf_bram_addr;
    wire        dac1_wf_bram_clk;
    wire [31:0] dac1_wf_bram_din;
    wire [31:0] dac1_wf_bram_dout;
@@ -218,7 +218,7 @@ module top #
    wire        dac1_wf_bram_rst;
    wire [3:0]  dac1_wf_bram_we;  

-    wire [14:0] dac2_wf_bram_addr;
+    wire [31:0] dac2_wf_bram_addr;
    wire        dac2_wf_bram_clk;
    wire [31:0] dac2_wf_bram_din;
    wire [31:0] dac2_wf_bram_dout;
@@ -226,7 +226,7 @@ module top #
    wire        dac2_wf_bram_rst;
    wire [3:0]  dac2_wf_bram_we;  
    
-    wire [14:0] dac3_wf_bram_addr;
+    wire [31:0] dac3_wf_bram_addr;
    wire        dac3_wf_bram_clk;
    wire [31:0] dac3_wf_bram_din;
    wire [31:0] dac3_wf_bram_dout;
--- a/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v
+++ b/radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v
@@ -7,6 +7,7 @@ module waveform_gen #
    parameter CTRL_REG_ADDR = 32'h00000000,
    parameter NUM_SAMPLES_REG_ADDR = 32'h00000004,
    parameter START_SAMPLE_REG_ADDR = 32'h00000008,
+    parameter NUM_WFS_REG_ADDR = 32'h0000000C,
    
    parameter integer AXI_ADDR_WIDTH	= 32,
    parameter integer AXI_DATA_WIDTH	= 32    
@@ -122,6 +123,7 @@ axil_slave
 wire reset;
 reg [31:0]  reg_ctrl;
 reg [15:0]  reg_num_samples;
+reg [15:0]  reg_num_wfs;
 reg [27:0]  reg_start_sample;

 always @ (posedge ctrl_if.clk) begin
@@ -148,6 +150,13 @@ always @ (posedge ctrl_if.clk) begin
    end
 end

+always @ (posedge ctrl_if.clk) begin
+    if (~ctrl_if.resetn) begin
+        reg_num_wfs <= 0;
+    end else if (wren && waddr[11:0] == NUM_WFS_REG_ADDR) begin
+        reg_num_wfs <= wdata;
+    end
+end
 always @ (posedge ctrl_if.clk) begin
    if (rden) begin
        if ( raddr[11:0] == CTRL_REG_ADDR ) 
@@ -156,6 +165,8 @@ always @ (posedge ctrl_if.clk) begin
            rdata <= reg_num_samples;   
        if ( raddr[11:0] == START_SAMPLE_REG_ADDR ) 
            rdata <= reg_start_sample;   
+        if ( raddr[11:0] == NUM_WFS_REG_ADDR ) 
+            rdata <= reg_num_wfs;               
    end      
 end

@@ -165,6 +176,7 @@ assign reset = reg_ctrl[0];
 // Sample gating
 // ------------------------------
 reg [16:0] sample_cnt;
+reg [16:0] wf_ind;
 reg pulse_active;
 reg pulse_active_q;
 reg pulse_active_q2;
@@ -183,6 +195,8 @@ reg [255:0] all_brams_out;
 //reg [127:0] jesd_out_reg;
 //reg [127:0] all_brams_out;

+reg reset_bram_addr;
+

 always @ (posedge clk) begin
    if (reset == 1'b1) begin
@@ -215,6 +229,9 @@ always @ (posedge clk) begin
        pulse_active <= 0;
        pulse_active_q <= 0;
        pulse_active_q2 <= 0;
+        wf_ind <= 0;
+        reset_bram_addr <= 0;
+        dac0_bram_addr <= 0;
        
    end else begin
       
@@ -231,27 +248,32 @@ always @ (posedge clk) begin
            if (sample_cnt == reg_num_samples-1) begin
                sample_cnt <= 0;
                pulse_active <= 0;
+                wf_ind <= wf_ind + 1;
            end
        end
+        
+        if (wf_ind == reg_num_wfs) begin
+            reset_bram_addr <= 1;
+            wf_ind <= 0;
+        end else begin
+            reset_bram_addr <= 0;
+        end

        if (pulse_active_q2) begin
            jesd_out_reg <= all_brams_out;
        end else begin
            jesd_out_reg <= 0;            
        end
+        
+        if (pulse_active) begin
+            dac0_bram_addr <= dac0_bram_addr + 1;
+        end else if (reset_bram_addr) begin
+            dac0_bram_addr <= 0;
+        end        

    end
 end

-always @ (posedge clk) begin
-    if (pulse_active) begin
-        dac0_bram_addr <= dac0_bram_addr + 1;
-    end else begin
-        dac0_bram_addr <= 0;
-    end
-end
-
-

 assign dac1_bram_addr = dac0_bram_addr;

--- a/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
+++ b/radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
--- a/radar_alinx_kintex.xpr
+++ b/radar_alinx_kintex.xpr
@@ -785,9 +785,7 @@
  <Runs Version="1" Minor="19">
    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
        <Step Id="synth_design" PreStepTclHook="$PSRCDIR/set_build_date.tcl"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -917,9 +915,7 @@
    </Run>
    <Run Id="decimation_bd_synth_1" Type="Ft3:Synth" SrcSet="decimation_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="decimation_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/decimation_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -929,9 +925,7 @@
    </Run>
    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
@@ -1153,9 +1147,7 @@
    </Run>
    <Run Id="decimation_bd_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="decimation_bd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="decimation_bd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/decimation_bd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/decimation_bd_impl_1">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
--- a/vitis/top/platform.tcl
+++ b/vitis/top/platform.tcl
@@ -128,3 +128,32 @@ bsp write
 bsp reload
 catch {bsp regenerate}
 platform generate -domains freertos10_xilinx_microblaze_0 
+platform active {top}
+bsp reload
+bsp config stdin "mdm_1"
+bsp config stdin "mdm_1"
+bsp config stdout "mdm_1"
+bsp write
+bsp reload
+catch {bsp regenerate}
+platform generate
+bsp config stdin "axi_uartlite_0"
+bsp config stdin "axi_uartlite_0"
+bsp config stdout "mdm_1"
+bsp config stdout "axi_uartlite_0"
+bsp write
+bsp reload
+catch {bsp regenerate}
+platform generate -domains freertos10_xilinx_microblaze_0 
+bsp config stdin "mdm_1"
+bsp config stdout "mdm_1"
+bsp write
+bsp reload
+catch {bsp regenerate}
+platform generate -domains freertos10_xilinx_microblaze_0 
+bsp config stdin "axi_uartlite_0"
+bsp config stdout "axi_uartlite_0"
+bsp write
+bsp reload
+catch {bsp regenerate}
+platform generate -domains freertos10_xilinx_microblaze_0