support for multiple waveforms

radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ui/bd_37ca4332.ui

@@ -1,7 +1,7 @@
 {
    "ActiveEmotionalView":"Default View",
-   "Default View_ScaleFactor":"1.0",
-   "Default View_TopLeft":"-400,-66",
+   "Default View_ScaleFactor":"2.10612",
+   "Default View_TopLeft":"55,0",
    "ExpandedHierarchyInLayout":"",
    "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
 #  -string -flagsOSRD
@@ -23,25 +23,25 @@ preplace inst axis_broadcaster_2 -pg 1 -lvl 6 -x 1620 -y 350 -defaultsOSRD
 preplace inst dec_4_width -pg 1 -lvl 8 -x 2200 -y 80 -defaultsOSRD
 preplace inst dec_16_width -pg 1 -lvl 8 -x 2200 -y 400 -defaultsOSRD
 preplace inst dec_8_width -pg 1 -lvl 8 -x 2200 -y 540 -defaultsOSRD
-preplace netloc Net 1 0 8 -70 270 210 300 540 190 830 220 1160 410 1460 430 1790 460 2080
-preplace netloc Net1 1 0 8 -80 280 220 290 520 180 840 380 1170 420 1470 440 1780 470 2090
-preplace netloc dec_2_fir_M_AXIS_DATA 1 1 1 N 190
-preplace netloc axis_broadcaster_0_M01_AXIS 1 2 1 530 220n
-preplace netloc dec_4_fir_M_AXIS_DATA 1 3 1 N 280
-preplace netloc axis_broadcaster_1_M01_AXIS 1 4 1 N 310
-preplace netloc dec_8_fir_M_AXIS_DATA 1 5 1 N 330
-preplace netloc axis_broadcaster_2_M01_AXIS 1 6 1 N 360
+preplace netloc Net 1 0 8 -70 270 200 300 540 190 820 220 1160 410 1450 430 1790 460 2070
+preplace netloc Net1 1 0 8 -80 280 210 290 520 180 830 380 1170 420 1460 440 1780 470 2080
 preplace netloc axis_broadcaster_0_M00_AXIS 1 2 6 N 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ
+preplace netloc axis_broadcaster_0_M01_AXIS 1 2 1 530 220n
 preplace netloc axis_broadcaster_1_M00_AXIS 1 4 4 1150 60 NJ 60 NJ 60 NJ
+preplace netloc axis_broadcaster_1_M01_AXIS 1 4 1 N 310
 preplace netloc axis_broadcaster_2_M00_AXIS 1 6 2 1770 520 NJ
+preplace netloc axis_broadcaster_2_M01_AXIS 1 6 1 N 360
 preplace netloc dec_16_fir_M_AXIS_DATA 1 7 1 N 380
-preplace netloc dec_2_width_M_AXIS 1 8 1 NJ 220
-preplace netloc dec_4_width_M_AXIS 1 8 1 NJ 80
-preplace netloc dec_8_width_M_AXIS 1 8 1 NJ 540
 preplace netloc dec_16_width_M_AXIS 1 8 1 NJ 400
+preplace netloc dec_2_fir_M_AXIS_DATA 1 1 1 N 190
+preplace netloc dec_2_width_M_AXIS 1 8 1 NJ 220
+preplace netloc dec_4_fir_M_AXIS_DATA 1 3 1 N 280
+preplace netloc dec_4_width_M_AXIS 1 8 1 NJ 80
+preplace netloc dec_8_fir_M_AXIS_DATA 1 5 1 N 330
+preplace netloc dec_8_width_M_AXIS 1 8 1 NJ 540
 preplace netloc in_i_1 1 0 1 NJ 170
 levelinfo -pg 1 -100 70 370 690 1000 1320 1620 1940 2200 2330
 pagesize -pg 1 -db -bbox -sgen -180 0 2450 620
 "
 }
-
+0

radar_alinx_kintex.srcs/sources_1/hdl/top.v

@@ -202,7 +202,7 @@ module top #
     wire jesd_core_clk_in;
     wire jesd_core_clk2_in;
   
-    wire [14:0] dac0_wf_bram_addr;
+    wire [31:0] dac0_wf_bram_addr;
     wire        dac0_wf_bram_clk;
     wire [31:0] dac0_wf_bram_din;
     wire [31:0] dac0_wf_bram_dout;
@@ -210,7 +210,7 @@ module top #
     wire        dac0_wf_bram_rst;
     wire [3:0]  dac0_wf_bram_we;    
     
-    wire [14:0] dac1_wf_bram_addr;
+    wire [31:0] dac1_wf_bram_addr;
     wire        dac1_wf_bram_clk;
     wire [31:0] dac1_wf_bram_din;
     wire [31:0] dac1_wf_bram_dout;
@@ -218,7 +218,7 @@ module top #
     wire        dac1_wf_bram_rst;
     wire [3:0]  dac1_wf_bram_we;  
 
-    wire [14:0] dac2_wf_bram_addr;
+    wire [31:0] dac2_wf_bram_addr;
     wire        dac2_wf_bram_clk;
     wire [31:0] dac2_wf_bram_din;
     wire [31:0] dac2_wf_bram_dout;
@@ -226,7 +226,7 @@ module top #
     wire        dac2_wf_bram_rst;
     wire [3:0]  dac2_wf_bram_we;  
     
-    wire [14:0] dac3_wf_bram_addr;
+    wire [31:0] dac3_wf_bram_addr;
     wire        dac3_wf_bram_clk;
     wire [31:0] dac3_wf_bram_din;
     wire [31:0] dac3_wf_bram_dout;

radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v

@@ -7,6 +7,7 @@ module waveform_gen #
     parameter CTRL_REG_ADDR = 32'h00000000,
     parameter NUM_SAMPLES_REG_ADDR = 32'h00000004,
     parameter START_SAMPLE_REG_ADDR = 32'h00000008,
+    parameter NUM_WFS_REG_ADDR = 32'h0000000C,
     
     parameter integer AXI_ADDR_WIDTH	= 32,
     parameter integer AXI_DATA_WIDTH	= 32    
@@ -122,6 +123,7 @@ axil_slave
 wire reset;
 reg [31:0]  reg_ctrl;
 reg [15:0]  reg_num_samples;
+reg [15:0]  reg_num_wfs;
 reg [27:0]  reg_start_sample;
 
 always @ (posedge ctrl_if.clk) begin
@@ -148,6 +150,13 @@ always @ (posedge ctrl_if.clk) begin
     end
 end
 
+always @ (posedge ctrl_if.clk) begin
+    if (~ctrl_if.resetn) begin
+        reg_num_wfs <= 0;
+    end else if (wren && waddr[11:0] == NUM_WFS_REG_ADDR) begin
+        reg_num_wfs <= wdata;
+    end
+end
 always @ (posedge ctrl_if.clk) begin
     if (rden) begin
         if ( raddr[11:0] == CTRL_REG_ADDR ) 
@@ -156,6 +165,8 @@ always @ (posedge ctrl_if.clk) begin
             rdata <= reg_num_samples;   
         if ( raddr[11:0] == START_SAMPLE_REG_ADDR ) 
             rdata <= reg_start_sample;   
+        if ( raddr[11:0] == NUM_WFS_REG_ADDR ) 
+            rdata <= reg_num_wfs;               
     end      
 end
 
@@ -165,6 +176,7 @@ assign reset = reg_ctrl[0];
 // Sample gating
 // ------------------------------
 reg [16:0] sample_cnt;
+reg [16:0] wf_ind;
 reg pulse_active;
 reg pulse_active_q;
 reg pulse_active_q2;
@@ -183,6 +195,8 @@ reg [255:0] all_brams_out;
 //reg [127:0] jesd_out_reg;
 //reg [127:0] all_brams_out;
 
+reg reset_bram_addr;
+
 
 always @ (posedge clk) begin
     if (reset == 1'b1) begin
@@ -215,6 +229,9 @@ always @ (posedge clk) begin
         pulse_active <= 0;
         pulse_active_q <= 0;
         pulse_active_q2 <= 0;
+        wf_ind <= 0;
+        reset_bram_addr <= 0;
+        dac0_bram_addr <= 0;
         
     end else begin
        
@@ -231,27 +248,32 @@ always @ (posedge clk) begin
             if (sample_cnt == reg_num_samples-1) begin
                 sample_cnt <= 0;
                 pulse_active <= 0;
+                wf_ind <= wf_ind + 1;
             end
         end
+        
+        if (wf_ind == reg_num_wfs) begin
+            reset_bram_addr <= 1;
+            wf_ind <= 0;
+        end else begin
+            reset_bram_addr <= 0;
+        end
 
         if (pulse_active_q2) begin
             jesd_out_reg <= all_brams_out;
         end else begin
             jesd_out_reg <= 0;            
         end
+        
+        if (pulse_active) begin
+            dac0_bram_addr <= dac0_bram_addr + 1;
+        end else if (reset_bram_addr) begin
+            dac0_bram_addr <= 0;
+        end        
 
     end
 end
 
-always @ (posedge clk) begin
-    if (pulse_active) begin
-        dac0_bram_addr <= dac0_bram_addr + 1;
-    end else begin
-        dac0_bram_addr <= 0;
-    end
-end
-
-
 
 assign dac1_bram_addr = dac0_bram_addr;