support for multiple waveforms

This commit is contained in:
2025-06-29 20:18:52 -05:00
parent d60c55f292
commit 6dfee38d7c
9 changed files with 116 additions and 57 deletions

View File

@@ -202,7 +202,7 @@ module top #
wire jesd_core_clk_in;
wire jesd_core_clk2_in;
wire [14:0] dac0_wf_bram_addr;
wire [31:0] dac0_wf_bram_addr;
wire dac0_wf_bram_clk;
wire [31:0] dac0_wf_bram_din;
wire [31:0] dac0_wf_bram_dout;
@@ -210,7 +210,7 @@ module top #
wire dac0_wf_bram_rst;
wire [3:0] dac0_wf_bram_we;
wire [14:0] dac1_wf_bram_addr;
wire [31:0] dac1_wf_bram_addr;
wire dac1_wf_bram_clk;
wire [31:0] dac1_wf_bram_din;
wire [31:0] dac1_wf_bram_dout;
@@ -218,7 +218,7 @@ module top #
wire dac1_wf_bram_rst;
wire [3:0] dac1_wf_bram_we;
wire [14:0] dac2_wf_bram_addr;
wire [31:0] dac2_wf_bram_addr;
wire dac2_wf_bram_clk;
wire [31:0] dac2_wf_bram_din;
wire [31:0] dac2_wf_bram_dout;
@@ -226,7 +226,7 @@ module top #
wire dac2_wf_bram_rst;
wire [3:0] dac2_wf_bram_we;
wire [14:0] dac3_wf_bram_addr;
wire [31:0] dac3_wf_bram_addr;
wire dac3_wf_bram_clk;
wire [31:0] dac3_wf_bram_din;
wire [31:0] dac3_wf_bram_dout;

View File

@@ -7,6 +7,7 @@ module waveform_gen #
parameter CTRL_REG_ADDR = 32'h00000000,
parameter NUM_SAMPLES_REG_ADDR = 32'h00000004,
parameter START_SAMPLE_REG_ADDR = 32'h00000008,
parameter NUM_WFS_REG_ADDR = 32'h0000000C,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
@@ -122,6 +123,7 @@ axil_slave
wire reset;
reg [31:0] reg_ctrl;
reg [15:0] reg_num_samples;
reg [15:0] reg_num_wfs;
reg [27:0] reg_start_sample;
always @ (posedge ctrl_if.clk) begin
@@ -148,6 +150,13 @@ always @ (posedge ctrl_if.clk) begin
end
end
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_num_wfs <= 0;
end else if (wren && waddr[11:0] == NUM_WFS_REG_ADDR) begin
reg_num_wfs <= wdata;
end
end
always @ (posedge ctrl_if.clk) begin
if (rden) begin
if ( raddr[11:0] == CTRL_REG_ADDR )
@@ -156,6 +165,8 @@ always @ (posedge ctrl_if.clk) begin
rdata <= reg_num_samples;
if ( raddr[11:0] == START_SAMPLE_REG_ADDR )
rdata <= reg_start_sample;
if ( raddr[11:0] == NUM_WFS_REG_ADDR )
rdata <= reg_num_wfs;
end
end
@@ -165,6 +176,7 @@ assign reset = reg_ctrl[0];
// Sample gating
// ------------------------------
reg [16:0] sample_cnt;
reg [16:0] wf_ind;
reg pulse_active;
reg pulse_active_q;
reg pulse_active_q2;
@@ -183,6 +195,8 @@ reg [255:0] all_brams_out;
//reg [127:0] jesd_out_reg;
//reg [127:0] all_brams_out;
reg reset_bram_addr;
always @ (posedge clk) begin
if (reset == 1'b1) begin
@@ -215,6 +229,9 @@ always @ (posedge clk) begin
pulse_active <= 0;
pulse_active_q <= 0;
pulse_active_q2 <= 0;
wf_ind <= 0;
reset_bram_addr <= 0;
dac0_bram_addr <= 0;
end else begin
@@ -231,27 +248,32 @@ always @ (posedge clk) begin
if (sample_cnt == reg_num_samples-1) begin
sample_cnt <= 0;
pulse_active <= 0;
wf_ind <= wf_ind + 1;
end
end
if (wf_ind == reg_num_wfs) begin
reset_bram_addr <= 1;
wf_ind <= 0;
end else begin
reset_bram_addr <= 0;
end
if (pulse_active_q2) begin
jesd_out_reg <= all_brams_out;
end else begin
jesd_out_reg <= 0;
end
if (pulse_active) begin
dac0_bram_addr <= dac0_bram_addr + 1;
end else if (reset_bram_addr) begin
dac0_bram_addr <= 0;
end
end
end
always @ (posedge clk) begin
if (pulse_active) begin
dac0_bram_addr <= dac0_bram_addr + 1;
end else begin
dac0_bram_addr <= 0;
end
end
assign dac1_bram_addr = dac0_bram_addr;