bkiedinger/castelion_radar_alinx_kintex
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last update to chris

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This commit is contained in:
bkiedinger@gmail.com
2025-05-29 20:47:32 -05:00
parent 7f2dd0103e
commit 6e4aa1230a
19 changed files with 96 additions and 84 deletions
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BIN
cpp/test.bin
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Binary file not shown.

3
python/radar_manager.py
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@@ -246,7 +246,8 @@ class RadarManager:
def load_waveform(self, ch, amp, bw, pw):
addr = 0x0010000 + 0x0010000 * ch
# addr = 0x0010000 + 0x0010000 * ch
addr = 0x0020000 + 0x0020000 * ch
print('Load', hex(addr))
num_samples = pw
wf = form_chirp(pw, bw, 1)

2
python/read_data_file.py
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@@ -25,7 +25,7 @@ def main():
headers = []
offset = 0
file = 'test0.bin'
file = 'test1.bin'
fid = open(file, 'rb')
# Find header, recording buffer could have wrapped depending on data rate and how long we ran for

10
python/test_cpi.py
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@@ -54,7 +54,7 @@ def main():
pri -= (pri % 3)
# pri = int(.0001 * clk)
print(pri)
inter_cpi = 2000
inter_cpi = 20000
tx_lo_offset = 10e6
rx_lo_offset = 0
@@ -66,9 +66,9 @@ def main():
recorder0 = DataRecorder("192.168.2.128", 1234, packet_size=radar.packet_size)
# recorder1 = DataRecorder("192.168.3.128", 1235, packet_size=radar.packet_size)
recorder1 = DataRecorder("192.168.3.128", 1235, packet_size=radar.packet_size)
recorder0.start_recording('test0.bin', True)
# recorder1.start_recording('test1.bin', True)
recorder1.start_recording('test1.bin', True)
radar.configure_cpi(pri, inter_cpi, num_pulses, num_samples, start_sample,
tx_num_samples, tx_start_sample, rx_lo_offset, tx_lo_offset)
@@ -81,8 +81,8 @@ def main():
radar.stop_running()
# Stop the data recorder
recorder0.stop_recording()
# recorder1.stop_recording()
#
recorder1.stop_recording()
# # Parse some data
#
# # Find header, recording buffer could have wrapped depending on data rate and how long we ran for

27
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
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@@ -122,7 +122,10 @@ set_property IOSTANDARD LVCMOS18 [get_ports rx1_lna_en]
#-------------------------------------------
# PPS
#-------------------------------------------
set_property PACKAGE_PIN H24 [get_ports pps]
# FMC2
#set_property PACKAGE_PIN H24 [get_ports pps]
# FMC1
set_property PACKAGE_PIN AF27 [get_ports pps]
set_property IOSTANDARD LVCMOS18 [get_ports pps]
#-------------------------------------------
@@ -280,21 +283,21 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
# Works with the board at my house
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
# Works with the board Chris has
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
#create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]
# Works with the board Chris has
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
##create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
#set_property PACKAGE_PIN H2 [get_ports {jesd_rxp_in[1]}]

34
radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd
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@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0xD9A446DC95B09871",
"boundary_crc": "0x3EB2241EA722D10B",
"device": "xcku040-ffva1156-2-i",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/bd/microblaze_bd",
"name": "microblaze_bd",
@@ -1064,7 +1064,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1083,7 +1083,7 @@
"ADDR": {
"physical_name": "dac0_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -1131,7 +1131,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1150,7 +1150,7 @@
"ADDR": {
"physical_name": "dac1_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -1198,7 +1198,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1217,7 +1217,7 @@
"ADDR": {
"physical_name": "dac2_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -1265,7 +1265,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1284,7 +1284,7 @@
"ADDR": {
"physical_name": "dac3_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -9290,23 +9290,23 @@
"segments": {
"SEG_axi_bram_ctrl_0_Mem0": {
"address_block": "/axi_bram_ctrl_0/S_AXI/Mem0",
"offset": "0x00010000",
"range": "32K"
"offset": "0x00020000",
"range": "128K"
},
"SEG_axi_bram_ctrl_1_Mem0": {
"address_block": "/axi_bram_ctrl_1/S_AXI/Mem0",
"offset": "0x00020000",
"range": "32K"
"offset": "0x00040000",
"range": "128K"
},
"SEG_axi_bram_ctrl_2_Mem0": {
"address_block": "/axi_bram_ctrl_2/S_AXI/Mem0",
"offset": "0x00030000",
"range": "32K"
"offset": "0x00060000",
"range": "128K"
},
"SEG_axi_bram_ctrl_3_Mem0": {
"address_block": "/axi_bram_ctrl_3/S_AXI/Mem0",
"offset": "0x00040000",
"range": "32K"
"offset": "0x00080000",
"range": "128K"
},
"SEG_axi_ethernet_0_Reg0": {
"address_block": "/axi_ethernet_0/s_axi/Reg0",

12
radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v
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@@ -19,7 +19,7 @@ module waveform_gen #
input wire start_of_pulse,
input wire [14:0] dac0_wf_bram_addr,
input wire [16:0] dac0_wf_bram_addr,
input wire dac0_wf_bram_clk,
input wire [31:0] dac0_wf_bram_din,
output wire [31:0] dac0_wf_bram_dout,
@@ -27,7 +27,7 @@ module waveform_gen #
input wire dac0_wf_bram_rst,
input wire [3:0] dac0_wf_bram_we,
input wire [14:0] dac1_wf_bram_addr,
input wire [16:0] dac1_wf_bram_addr,
input wire dac1_wf_bram_clk,
input wire [31:0] dac1_wf_bram_din,
output wire [31:0] dac1_wf_bram_dout,
@@ -35,7 +35,7 @@ module waveform_gen #
input wire dac1_wf_bram_rst,
input wire [3:0] dac1_wf_bram_we,
input wire [14:0] dac2_wf_bram_addr,
input wire [16:0] dac2_wf_bram_addr,
input wire dac2_wf_bram_clk,
input wire [31:0] dac2_wf_bram_din,
output wire [31:0] dac2_wf_bram_dout,
@@ -43,7 +43,7 @@ module waveform_gen #
input wire dac2_wf_bram_rst,
input wire [3:0] dac2_wf_bram_we,
input wire [14:0] dac3_wf_bram_addr,
input wire [16:0] dac3_wf_bram_addr,
input wire dac3_wf_bram_clk,
input wire [31:0] dac3_wf_bram_din,
output wire [31:0] dac3_wf_bram_dout,
@@ -304,7 +304,7 @@ wf_memory dac0_wf_mem (
.clka(dac0_wf_bram_clk),
.ena(dac0_wf_bram_en),
.wea(dac0_wf_bram_we),
.addra(dac0_wf_bram_addr[14:2]),
.addra(dac0_wf_bram_addr[16:2]),
.dina(dac0_wf_bram_din),
.douta(dac0_wf_bram_dout),
@@ -320,7 +320,7 @@ wf_memory dac1_wf_mem (
.clka(dac1_wf_bram_clk),
.ena(dac1_wf_bram_en),
.wea(dac1_wf_bram_we),
.addra(dac1_wf_bram_addr[14:2]),
.addra(dac1_wf_bram_addr[16:2]),
.dina(dac1_wf_bram_din),
.douta(dac1_wf_bram_dout),

24
radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci
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@@ -14,7 +14,7 @@
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -33,7 +33,7 @@
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "32768", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
@@ -112,9 +112,9 @@
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRA_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_A": [ { "value": "32768", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_A": [ { "value": "32768", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRA_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -126,9 +126,9 @@
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRB_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRB_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -153,9 +153,9 @@
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "32", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 4.152427 mW", "resolve_type": "generated", "usage": "all" } ]
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 10.681069 mW", "resolve_type": "generated", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
@@ -188,13 +188,13 @@
"clka": [ { "direction": "in", "driver_value": "0" } ],
"ena": [ { "direction": "in", "driver_value": "0" } ],
"wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"addra": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
"addra": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
"dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"clkb": [ { "direction": "in", "driver_value": "0" } ],
"enb": [ { "direction": "in", "driver_value": "0" } ],
"web": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"addrb": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
"addrb": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
"dinb": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
"doutb": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
},

BIN
radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
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Binary file not shown.

12
radar_alinx_kintex.xpr
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@@ -63,13 +63,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="47"/>
<Option Name="WTModelSimExportSim" Val="47"/>
<Option Name="WTQuestaExportSim" Val="47"/>
<Option Name="WTXSimExportSim" Val="48"/>
<Option Name="WTModelSimExportSim" Val="48"/>
<Option Name="WTQuestaExportSim" Val="48"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="47"/>
<Option Name="WTRivieraExportSim" Val="47"/>
<Option Name="WTActivehdlExportSim" Val="47"/>
<Option Name="WTVcsExportSim" Val="48"/>
<Option Name="WTRivieraExportSim" Val="48"/>
<Option Name="WTActivehdlExportSim" Val="48"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>

2
vitis/radar/radar.prj
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="31c4a066f121f9dfdf4b2a6e46d178c9">
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="b81ac1744f29e93881cfaa8e8b019a98">
<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.245787499">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>

32
vitis/radar/src/data_converter_setup.c
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@@ -525,23 +525,23 @@ void setup_data_converter() {
#ifndef IBERT_TESTING
// Update FPGA TX Transceiver settings
set_lane_cal(0, 0, 0, 11);
set_lane_cal(1, 10, 5, 11);
set_lane_cal(2, 5, 0, 11);
set_lane_cal(3, 0, 0, 11);
set_lane_cal(4, 0, 0, 11);
set_lane_cal(5, 0, 0, 11);
set_lane_cal(6, 12, 0, 11);
set_lane_cal(7, 0, 0, 11);
// set_lane_cal(0, 0, 0, 11);
// set_lane_cal(1, 10, 5, 11);
// set_lane_cal(2, 5, 0, 11);
// set_lane_cal(3, 0, 0, 11);
// set_lane_cal(4, 0, 0, 11);
// set_lane_cal(5, 0, 0, 11);
// set_lane_cal(6, 12, 0, 11);
// set_lane_cal(7, 0, 0, 11);
// set_lane_cal(0, 9, 0, 7);
// set_lane_cal(1, 9, 0, 7);
// set_lane_cal(2, 9, 0, 7);
// set_lane_cal(3, 9, 0, 7);
// set_lane_cal(4, 9, 0, 7);
// set_lane_cal(5, 9, 0, 7);
// set_lane_cal(6, 9, 0, 7);
// set_lane_cal(7, 9, 0, 7);
set_lane_cal(0, 9, 0, 7);
set_lane_cal(1, 9, 0, 7);
set_lane_cal(2, 9, 0, 7);
set_lane_cal(3, 9, 0, 7);
set_lane_cal(4, 9, 0, 7);
set_lane_cal(5, 9, 0, 7);
set_lane_cal(6, 9, 0, 7);
set_lane_cal(7, 9, 0, 7);
vTaskDelay(100);
int subclass = jtx_param[uc][0].jesd_subclass;

4
vitis/radar_system/_ide/flash/radar.elf.srec
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@@ -15980,7 +15980,7 @@ S3158003E650FFFF00B024E4F4B95400C03001006030F9
S3158003E660068000B03C6560F870FF10B80000731038
S3158003E670068000B000306030000000B0FFFFA5A424
S3158003E680000083E400288488080004BC000060102E
S3158003E69008000FB6000000800000C510404100B09E
S3158003E69008000FB6000000800000C510004000B0DF
S3158003E6A00000A030FCFF21300000E1F9000000B03B
S3158003E6B01400F4B9000000800000E1E908000FB6F9
S3158003E6C00400213008008530000064E8080063A454
@@ -23759,7 +23759,7 @@ S3158005CC8000000080ECFF25BE0000008008000FB67E
S3158005CC9000000080068000B0303160E802006364E1
S3158005CCA0FFFFA5300018E000FFFFE730FCFF27BE39
S3158005CCB000000080ECFF25BE0000008008000FB64E
S3158005CCC000000080404100B00000A030FCFF21300C
S3158005CCC000000080004000B00000A030FCFF21304D
S3158005CCD00000E1F9FEFF00B00C1AF4B900000080EF
S3118005CCE00000E1E908000FB604002130D1
S3158005CCECF0FF21300008E0D9FFFF603102C80B94B4

4
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h
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@@ -496,8 +496,8 @@
#define PLATFORM_MB
/******************************************************************/
#define STDIN_BASEADDRESS 0x41400000
#define STDOUT_BASEADDRESS 0x41400000
#define STDIN_BASEADDRESS 0x40000000
#define STDOUT_BASEADDRESS 0x40000000
/******************************************************************/

BIN
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a
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BIN
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a
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4
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss
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@@ -6,8 +6,8 @@ BEGIN OS
PARAMETER OS_NAME = freertos10_xilinx
PARAMETER OS_VER = 1.12
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdin = mdm_1
PARAMETER stdout = mdm_1
PARAMETER stdin = axi_uartlite_0
PARAMETER stdout = axi_uartlite_0
PARAMETER total_heap_size = 2097152
END

2
vitis/top/platform.spr
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@@ -1 +1 @@
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}

8
vitis/top/platform.tcl
View File

@@ -90,3 +90,11 @@ bsp write
bsp reload
catch {bsp regenerate}
platform generate -domains freertos10_xilinx_microblaze_0
platform active {top}
bsp reload
bsp config stdin "axi_uartlite_0"
bsp config stdout "axi_uartlite_0"
bsp write
bsp reload
catch {bsp regenerate}
platform generate