bkiedinger/castelion_radar_alinx_kintex
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last update to chris

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bkiedinger@gmail.com
2025-05-29 20:47:32 -05:00
parent 7f2dd0103e
commit 6e4aa1230a
19 changed files with 96 additions and 84 deletions
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27
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
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@@ -122,7 +122,10 @@ set_property IOSTANDARD LVCMOS18 [get_ports rx1_lna_en]
#-------------------------------------------
# PPS
#-------------------------------------------
set_property PACKAGE_PIN H24 [get_ports pps]
# FMC2
#set_property PACKAGE_PIN H24 [get_ports pps]
# FMC1
set_property PACKAGE_PIN AF27 [get_ports pps]
set_property IOSTANDARD LVCMOS18 [get_ports pps]
#-------------------------------------------
@@ -280,21 +283,21 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
# Works with the board at my house
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
# Works with the board Chris has
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
#create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]
# Works with the board Chris has
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
##create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
#set_property PACKAGE_PIN H2 [get_ports {jesd_rxp_in[1]}]

34
radar_alinx_kintex.srcs/sources_1/bd/microblaze_bd/microblaze_bd.bd
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@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0xD9A446DC95B09871",
"boundary_crc": "0x3EB2241EA722D10B",
"device": "xcku040-ffva1156-2-i",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/bd/microblaze_bd",
"name": "microblaze_bd",
@@ -1064,7 +1064,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1083,7 +1083,7 @@
"ADDR": {
"physical_name": "dac0_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -1131,7 +1131,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1150,7 +1150,7 @@
"ADDR": {
"physical_name": "dac1_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -1198,7 +1198,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1217,7 +1217,7 @@
"ADDR": {
"physical_name": "dac2_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -1265,7 +1265,7 @@
"value_src": "user_prop"
},
"MEM_SIZE": {
"value": "32768",
"value": "131072",
"value_src": "ip_prop"
},
"MEM_WIDTH": {
@@ -1284,7 +1284,7 @@
"ADDR": {
"physical_name": "dac3_wf_bram_addr",
"direction": "O",
"left": "14",
"left": "16",
"right": "0"
},
"CLK": {
@@ -9290,23 +9290,23 @@
"segments": {
"SEG_axi_bram_ctrl_0_Mem0": {
"address_block": "/axi_bram_ctrl_0/S_AXI/Mem0",
"offset": "0x00010000",
"range": "32K"
"offset": "0x00020000",
"range": "128K"
},
"SEG_axi_bram_ctrl_1_Mem0": {
"address_block": "/axi_bram_ctrl_1/S_AXI/Mem0",
"offset": "0x00020000",
"range": "32K"
"offset": "0x00040000",
"range": "128K"
},
"SEG_axi_bram_ctrl_2_Mem0": {
"address_block": "/axi_bram_ctrl_2/S_AXI/Mem0",
"offset": "0x00030000",
"range": "32K"
"offset": "0x00060000",
"range": "128K"
},
"SEG_axi_bram_ctrl_3_Mem0": {
"address_block": "/axi_bram_ctrl_3/S_AXI/Mem0",
"offset": "0x00040000",
"range": "32K"
"offset": "0x00080000",
"range": "128K"
},
"SEG_axi_ethernet_0_Reg0": {
"address_block": "/axi_ethernet_0/s_axi/Reg0",

12
radar_alinx_kintex.srcs/sources_1/hdl/waveform_gen.v
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@@ -19,7 +19,7 @@ module waveform_gen #
input wire start_of_pulse,
input wire [14:0] dac0_wf_bram_addr,
input wire [16:0] dac0_wf_bram_addr,
input wire dac0_wf_bram_clk,
input wire [31:0] dac0_wf_bram_din,
output wire [31:0] dac0_wf_bram_dout,
@@ -27,7 +27,7 @@ module waveform_gen #
input wire dac0_wf_bram_rst,
input wire [3:0] dac0_wf_bram_we,
input wire [14:0] dac1_wf_bram_addr,
input wire [16:0] dac1_wf_bram_addr,
input wire dac1_wf_bram_clk,
input wire [31:0] dac1_wf_bram_din,
output wire [31:0] dac1_wf_bram_dout,
@@ -35,7 +35,7 @@ module waveform_gen #
input wire dac1_wf_bram_rst,
input wire [3:0] dac1_wf_bram_we,
input wire [14:0] dac2_wf_bram_addr,
input wire [16:0] dac2_wf_bram_addr,
input wire dac2_wf_bram_clk,
input wire [31:0] dac2_wf_bram_din,
output wire [31:0] dac2_wf_bram_dout,
@@ -43,7 +43,7 @@ module waveform_gen #
input wire dac2_wf_bram_rst,
input wire [3:0] dac2_wf_bram_we,
input wire [14:0] dac3_wf_bram_addr,
input wire [16:0] dac3_wf_bram_addr,
input wire dac3_wf_bram_clk,
input wire [31:0] dac3_wf_bram_din,
output wire [31:0] dac3_wf_bram_dout,
@@ -304,7 +304,7 @@ wf_memory dac0_wf_mem (
.clka(dac0_wf_bram_clk),
.ena(dac0_wf_bram_en),
.wea(dac0_wf_bram_we),
.addra(dac0_wf_bram_addr[14:2]),
.addra(dac0_wf_bram_addr[16:2]),
.dina(dac0_wf_bram_din),
.douta(dac0_wf_bram_dout),
@@ -320,7 +320,7 @@ wf_memory dac1_wf_mem (
.clka(dac1_wf_bram_clk),
.ena(dac1_wf_bram_en),
.wea(dac1_wf_bram_we),
.addra(dac1_wf_bram_addr[14:2]),
.addra(dac1_wf_bram_addr[16:2]),
.dina(dac1_wf_bram_din),
.douta(dac1_wf_bram_dout),

24
radar_alinx_kintex.srcs/sources_1/ip/wf_memory/wf_memory.xci
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@@ -14,7 +14,7 @@
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
@@ -33,7 +33,7 @@
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Write_Depth_A": [ { "value": "32768", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ],
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
@@ -112,9 +112,9 @@
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_A": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRA_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_A": [ { "value": "32768", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_A": [ { "value": "32768", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRA_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -126,9 +126,9 @@
"C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
"C_WRITE_WIDTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_WIDTH_B": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRB_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_WRITE_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_READ_DEPTH_B": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ADDRB_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -153,9 +153,9 @@
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "8", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "32", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 4.152427 mW", "resolve_type": "generated", "usage": "all" } ]
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 10.681069 mW", "resolve_type": "generated", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
@@ -188,13 +188,13 @@
"clka": [ { "direction": "in", "driver_value": "0" } ],
"ena": [ { "direction": "in", "driver_value": "0" } ],
"wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"addra": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
"addra": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
"dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"clkb": [ { "direction": "in", "driver_value": "0" } ],
"enb": [ { "direction": "in", "driver_value": "0" } ],
"web": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"addrb": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
"addrb": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ],
"dinb": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
"doutb": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
},

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radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
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