bkiedinger/castelion_radar_alinx_kintex
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last update to chris

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bkiedinger@gmail.com
2025-05-29 20:47:32 -05:00
parent 7f2dd0103e
commit 6e4aa1230a
19 changed files with 96 additions and 84 deletions
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27
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
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@@ -122,7 +122,10 @@ set_property IOSTANDARD LVCMOS18 [get_ports rx1_lna_en]
#-------------------------------------------
# PPS
#-------------------------------------------
set_property PACKAGE_PIN H24 [get_ports pps]
# FMC2
#set_property PACKAGE_PIN H24 [get_ports pps]
# FMC1
set_property PACKAGE_PIN AF27 [get_ports pps]
set_property IOSTANDARD LVCMOS18 [get_ports pps]
#-------------------------------------------
@@ -280,21 +283,21 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
# Works with the board at my house
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
# Works with the board Chris has
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
#create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]
# Works with the board Chris has
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
#set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
#set_property DQS_BIAS TRUE [get_ports jesd_core_clk_n]
#create_clock -period 5.333 -name jesd_core_clk [get_ports jesd_core_clk_p]
##create_clock -period 4.0 -name jesd_core_clk [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F2 [get_ports {jesd_rxp_in[0]}]
#set_property PACKAGE_PIN H2 [get_ports {jesd_rxp_in[1]}]