bkiedinger/castelion_radar_alinx_kintex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

Browse Source
This commit is contained in:
bkiedinger@gmail.com
2025-07-15 22:40:15 -05:00
parent 1ee9b4db20
commit 707e9f82a4
19 changed files with 12405 additions and 12283 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
python/radar_manager.py
View File

@@ -71,7 +71,8 @@ class RadarManager:
self.get_fpga_datecode()
# Update UDP packet size
self.packet_size = 4096
# self.packet_size = 4096
self.packet_size = 16
self.axi_write_register(0x4005001C, self.packet_size)
self.reset_10g_udp()

12
python/test_cpi.py
View File

@@ -45,11 +45,12 @@ def main():
# CPI Parameters (timing values are in clk ticks)
num_pulses = 128
# Should be multiple of udp packet size, currently 4096 bytes, or 1024 samples
num_samples = 8192
# num_samples = 8192
num_samples = 8100
start_sample = 2000
tx_num_samples = 4096
tx_start_sample = start_sample
prf = 1000
prf = 10000
pri = int(1/prf * clk)
pri -= (pri % 3)
# pri = int(.0001 * clk)
@@ -58,7 +59,12 @@ def main():
tx_lo_offset = 10e6
rx_lo_offset = 0
dec_rate = 1
test_duration = 2
test_duration = 60
# TESTING
total_bytes_cpi = num_pulses * num_samples * 4
radar.axi_write_register(0x4005001C, total_bytes_cpi)
# TESTING
pri_float = pri / clk

78
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
View File

@@ -123,9 +123,9 @@ set_property IOSTANDARD LVCMOS18 [get_ports rx1_lna_en]
# PPS
#-------------------------------------------
# FMC2
#set_property PACKAGE_PIN H24 [get_ports pps]
#set_property PACKAGE_PIN H24 [get_ports pps]
# FMC1
set_property PACKAGE_PIN AF27 [get_ports pps]
set_property PACKAGE_PIN AF27 [get_ports pps]
set_property IOSTANDARD LVCMOS18 [get_ports pps]
#-------------------------------------------
@@ -234,17 +234,17 @@ set_property PACKAGE_PIN A25 [get_ports fmc_spi0_miso]
set_property PACKAGE_PIN B27 [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN B25 [get_ports fmc_spi0_ss]
set_property PULLUP TRUE [get_ports fmc_spi0_mosi]
set_property PULLUP TRUE [get_ports fmc_spi0_miso]
set_property PULLUP TRUE [get_ports fmc_spi0_sck]
set_property PULLUP true [get_ports fmc_spi0_mosi]
set_property PULLUP true [get_ports fmc_spi0_miso]
set_property PULLUP true [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN C22 [get_ports fmc_spi1_mosi]
set_property PACKAGE_PIN D20 [get_ports fmc_spi1_sck]
set_property PACKAGE_PIN C21 [get_ports fmc_spi1_ss]
set_property PACKAGE_PIN F27 [get_ports resetb]
set_property PULLUP TRUE [get_ports fmc_spi1_mosi]
set_property PULLUP TRUE [get_ports fmc_spi1_sck]
set_property PULLUP true [get_ports fmc_spi1_mosi]
set_property PULLUP true [get_ports fmc_spi1_sck]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_miso]
@@ -283,11 +283,11 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
# Works with the board at my house
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
# Works with the board Chris has (broken USB UART)
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
@@ -448,3 +448,59 @@ set_property PACKAGE_PIN AE23 [get_ports {ddr_dq[7]}]
connect_debug_port u_ila_0/probe6 [get_nets [list {tx_udp_switch_out\\.tlast}]]
connect_debug_port u_ila_0/probe4 [get_nets [list ethernet_top_i/tx_udp_hdr_ready]]
connect_debug_port u_ila_0/probe6 [get_nets [list ethernet_top_i/core_inst_0/tx_udp_hdr_valid]]
connect_debug_port u_ila_0/probe7 [get_nets [list ethernet_top_i/core_inst_0/tx_udp_hdr_valid_reg_n_0]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list {ethernet_top_i/sfp_phy_inst/phy1.eth_xcvr_phy_1/xcvr.eth_xcvr_gt_full_inst/inst/gen_gtwizard_gthe3_top.eth_xcvr_gt_full_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_user_clocking_internal.gen_single_instance.gtwiz_userclk_tx_inst/gtwiz_userclk_tx_usrclk2_out[0]}]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 28 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[3]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[4]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[5]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[6]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[7]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[8]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[10]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[11]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[12]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[13]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[14]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[15]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[16]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[17]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[18]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[19]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[20]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[21]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[22]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[23]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[24]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[25]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[26]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[27]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[28]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[29]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[30]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {tx_udp_switch_out\\.tdest[0]} {tx_udp_switch_out\\.tdest[1]} {tx_udp_switch_out\\.tdest[2]} {tx_udp_switch_out\\.tdest[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {ethernet_top_i/core_inst_0/tlast_cnt_reg[0]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[1]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[2]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[3]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[4]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[5]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[6]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[7]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[8]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[9]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[10]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[11]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[12]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[13]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[14]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list ethernet_top_i/core_inst_0/tlast_udp]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list ethernet_top_i/core_inst_0/udp_complete_inst/udp_64_inst/tx_udp_hdr_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {tx_udp_switch_out\\.tready}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {tx_udp_switch_out\\.tvalid}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list ethernet_top_i/core_inst_0/tx_udp_hdr_valid]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

2
radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.v
View File

@@ -17,7 +17,7 @@ module ethernet_top #
output wire [3:0] eth_clk,
output wire [3:0] eth_resetn,
input wire [15:0] packet_size,
input wire [31:0] packet_size,
axi4s_intf.master rx_udp_0,
axi4s_intf.slave tx_udp_0,

7
radar_alinx_kintex.srcs/sources_1/hdl/top.v
View File

@@ -447,6 +447,7 @@ module top #
reg pps_q;
reg pps_q2;
reg pps_red;
reg pps_fed;
always @ (posedge mb_axi_clk) begin
pps_pipe <= {pps_pipe[14:0], pps};
@@ -454,6 +455,7 @@ module top #
pps_q <= pps_debounce;
pps_q2 <= pps_q;
pps_red <= !pps_q2 & pps_q;
pps_fed <= pps_q2 & !pps_q;
end
microblaze_bd microblaze_bd_i
@@ -478,7 +480,8 @@ module top #
.qspi_flash_aresetn(qspi_flash_aresetn),
.pps(pps_red),
// .pps(pps_red),
.pps(pps_fed),
.clk_200_in_clk_n(clk_200_n),
.clk_200_in_clk_p(clk_200_p),
@@ -725,7 +728,7 @@ module top #
wire [31:0] gpi;
wire [31:0] gpo;
wire [15:0] packet_size;
wire [31:0] packet_size;
wire eth_reset;

4
radar_alinx_kintex.srcs/sources_1/hdl/util_reg.v
View File

@@ -13,7 +13,7 @@ module util_reg #
output wire [31:0] gpo,
input wire [31:0] gpi,
output wire [15:0] packet_size,
output wire [31:0] packet_size,
output wire fan_pwm,
input wire [31:0] datecode,
input wire [31:0] timecode,
@@ -97,7 +97,7 @@ reg [31:0] scratch;
reg [31:0] reg_gpo;
reg [24:0] pwm_period;
reg [24:0] pwm_pulsewidth;
reg [15:0] reg_packet_size;
reg [31:0] reg_packet_size;
reg [7:0] reg_num_bits;
reg [15:0] reg_dev_sel;
reg [31:0] reg_spi_data;

75
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/fpga_core.v
View File

@@ -44,7 +44,7 @@ module fpga_core #
*/
input wire clk,
input wire rst,
input wire [15:0] packet_size,
input wire [31:0] packet_size,
output wire [63:0] rx_fifo_udp_payload_axis_tdata,
output wire [7:0] rx_fifo_udp_payload_axis_tkeep,
@@ -283,13 +283,18 @@ assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast || tlast_udp; // what happens if tlast comes before payload length ends
//assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast || tlast_udp; // what happens if tlast comes before payload length ends
assign tx_udp_payload_axis_tlast = tlast_udp; // what happens if tlast comes before payload length ends
// assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign tx_udp_payload_axis_tuser = 0;
reg [12:0] packet_size_div_8;
// assign packet_size_div_8 = packet_size[15:3];
reg [31:0] bytes_left_cpi;
// Need to inject additional TLAST signals on UDP packet boundaries, incoming data from
// DMA will only have TLAST at very end
reg [15:0] tlast_cnt;
@@ -299,7 +304,6 @@ always @(posedge clk) begin
tlast_cnt <= 0;
tlast_udp <= 0;
tx_udp_hdr_valid <= 0;
// next_packet_ready <= 1;
tx_udp_length <= 1024;
packet_size_div_8 <= 128;
end else begin
@@ -310,19 +314,55 @@ always @(posedge clk) begin
end else if (tlast_cnt == (packet_size_div_8-1)) begin
tlast_udp <= 0;
tlast_cnt <= 0;
// next_packet_ready <= 1;
end else begin
tlast_cnt <= tlast_cnt + 1;
tlast_udp <= 0;
end
end else if (tx_fifo_udp_payload_axis_tready && tx_fifo_udp_payload_axis_tlast) begin
tlast_cnt <= 0;
// end else if (tx_fifo_udp_payload_axis_tready && tx_fifo_udp_payload_axis_tlast) begin
// tlast_cnt <= 0;
end
if (tx_udp_hdr_ready) begin
if (tx_fifo_udp_payload_axis_tvalid) begin
// if (tx_udp_hdr_ready) begin
// if (tx_fifo_udp_payload_axis_tvalid) begin
// tx_udp_hdr_valid <= 1;
// if (tx_fifo_udp_payload_axis_tdest == 15) begin
// // Control Traffic
// tx_udp_dest_port <= control_port;
// tx_udp_length <= control_packet_size+8;
// packet_size_div_8 <= (control_packet_size >> 3);
// end else if (tx_fifo_udp_payload_axis_tdest == 0) begin
// // Header Packet
// tx_udp_dest_port <= port;
// tx_udp_length <= 1024+8;
// packet_size_div_8 <= (1024 >> 3);
// bytes_left_cpi <= packet_size;
// end else begin
// // Data Traffic
// tx_udp_dest_port <= port;
//// tx_udp_length <= packet_size+8;
//// packet_size_div_8 <= (packet_size >> 3);
// if (bytes_left_cpi > 4096) begin
// tx_udp_length <= 4096+8;
// packet_size_div_8 <= 512;
// end else begin
// tx_udp_length <= bytes_left_cpi+8;
// packet_size_div_8 <= (bytes_left_cpi >> 3);
// end
// bytes_left_cpi = bytes_left_cpi - 4096;
// end
// end
// end else begin
// tx_udp_hdr_valid = 0;
// end
if (tx_fifo_udp_payload_axis_tvalid && tx_udp_hdr_ready) begin
if (tx_udp_hdr_valid && tx_udp_hdr_ready) begin
tx_udp_hdr_valid <= 0;
end else begin
tx_udp_hdr_valid <= 1;
// next_packet_ready <= 0;
if (tx_fifo_udp_payload_axis_tdest == 15) begin
// Control Traffic
tx_udp_dest_port <= control_port;
@@ -333,17 +373,28 @@ always @(posedge clk) begin
tx_udp_dest_port <= port;
tx_udp_length <= 1024+8;
packet_size_div_8 <= (1024 >> 3);
bytes_left_cpi <= packet_size;
end else begin
// Data Traffic
tx_udp_dest_port <= port;
tx_udp_length <= packet_size+8;
packet_size_div_8 <= (packet_size >> 3);
// tx_udp_length <= packet_size+8;
// packet_size_div_8 <= (packet_size >> 3);
if (bytes_left_cpi > 4096) begin
tx_udp_length <= 4096+8;
packet_size_div_8 <= 512;
end else begin
tx_udp_length <= bytes_left_cpi+8;
packet_size_div_8 <= (bytes_left_cpi >> 3);
end
bytes_left_cpi = bytes_left_cpi - 4096;
end
end
end else begin
tx_udp_hdr_valid = 0;
end
end
end

BIN
radar_alinx_kintex.srcs/utils_1/imports/synth_1/top.dcp
View File

Binary file not shown.

2
vitis/radar/radar.prj
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="b81ac1744f29e93881cfaa8e8b019a98">
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="31c4a066f121f9dfdf4b2a6e46d178c9">
<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.245787499">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>

32
vitis/radar/src/data_converter_setup.c
View File

@@ -525,23 +525,23 @@ void setup_data_converter() {
#ifndef IBERT_TESTING
// Update FPGA TX Transceiver settings
// set_lane_cal(0, 0, 0, 11);
// set_lane_cal(1, 10, 5, 11);
// set_lane_cal(2, 5, 0, 11);
// set_lane_cal(3, 0, 0, 11);
// set_lane_cal(4, 0, 0, 11);
// set_lane_cal(5, 0, 0, 11);
// set_lane_cal(6, 12, 0, 11);
// set_lane_cal(7, 0, 0, 11);
set_lane_cal(0, 0, 0, 11);
set_lane_cal(1, 10, 5, 11);
set_lane_cal(2, 5, 0, 11);
set_lane_cal(3, 0, 0, 11);
set_lane_cal(4, 0, 0, 11);
set_lane_cal(5, 0, 0, 11);
set_lane_cal(6, 12, 0, 11);
set_lane_cal(7, 0, 0, 11);
set_lane_cal(0, 9, 0, 7);
set_lane_cal(1, 9, 0, 7);
set_lane_cal(2, 9, 0, 7);
set_lane_cal(3, 9, 0, 7);
set_lane_cal(4, 9, 0, 7);
set_lane_cal(5, 9, 0, 7);
set_lane_cal(6, 9, 0, 7);
set_lane_cal(7, 9, 0, 7);
// set_lane_cal(0, 9, 0, 7);
// set_lane_cal(1, 9, 0, 7);
// set_lane_cal(2, 9, 0, 7);
// set_lane_cal(3, 9, 0, 7);
// set_lane_cal(4, 9, 0, 7);
// set_lane_cal(5, 9, 0, 7);
// set_lane_cal(6, 9, 0, 7);
// set_lane_cal(7, 9, 0, 7);
vTaskDelay(100);
int subclass = jtx_param[uc][0].jesd_subclass;

8
vitis/radar/src/main.c
View File

@@ -103,8 +103,12 @@ void status_task( void *pvParameters ) {
}
static void pps_irq_handler(u32 context) {
xil_printf("pps irq %lu\r\n", utc_time);
Xil_Out32(TIMING_ENGINE_ADDR + 0x14, utc_time + 1);
uint32_t current_seconds = Xil_In32(TIMING_ENGINE_ADDR + 0x14);
uint32_t new_time = utc_time + 1;
if (current_seconds != new_time) {
Xil_Out32(TIMING_ENGINE_ADDR + 0x14, new_time);
xil_printf("pps irq %lu, %lu\r\n", current_seconds, new_time);
}
}
void main_task( void *pvParameters ) {

6
vitis/radar/src/novatel.c
View File

@@ -97,9 +97,9 @@ void novatel_task()
utc_time = utc_sec;
xil_printf("gps_week %lu\r\n", msg->hdr.week);
xil_printf("gps_ms %lu\r\n", msg->hdr.ms);
xil_printf("utc_time %lu\r\n", utc_sec);
// xil_printf("gps_week %lu\r\n", msg->hdr.week);
// xil_printf("gps_ms %lu\r\n", msg->hdr.ms);
// xil_printf("utc_time %lu\r\n", utc_sec);
}
break;

24438
vitis/radar_system/_ide/flash/radar.elf.srec
View File

File diff suppressed because it is too large Load Diff

4
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/include/xparameters.h
View File

@@ -496,8 +496,8 @@
#define PLATFORM_MB
/******************************************************************/
#define STDIN_BASEADDRESS 0x40000000
#define STDOUT_BASEADDRESS 0x40000000
#define STDIN_BASEADDRESS 0x41400000
#define STDOUT_BASEADDRESS 0x41400000
/******************************************************************/

BIN
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libfreertos.a
View File

Binary file not shown.

BIN
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/microblaze_0/lib/libxil.a
View File

Binary file not shown.

4
vitis/top/microblaze_0/freertos10_xilinx_microblaze_0/bsp/system.mss
View File

@@ -6,8 +6,8 @@ BEGIN OS
PARAMETER OS_NAME = freertos10_xilinx
PARAMETER OS_VER = 1.12
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdin = axi_uartlite_0
PARAMETER stdout = axi_uartlite_0
PARAMETER stdin = mdm_1
PARAMETER stdout = mdm_1
PARAMETER total_heap_size = 2097152
END

2
vitis/top/platform.spr
View File

@@ -1 +1 @@
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}

11
vitis/top/platform.tcl
View File

@@ -175,3 +175,14 @@ bsp write
bsp reload
catch {bsp regenerate}
platform generate -domains freertos10_xilinx_microblaze_0
platform active {top}
bsp reload
bsp reload
platform active {top}
bsp reload
bsp config stdin "mdm_1"
bsp config stdout "mdm_1"
bsp write
bsp reload
catch {bsp regenerate}
platform generate