bkiedinger/castelion_radar_alinx_kintex
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updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

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bkiedinger@gmail.com
2025-07-15 22:40:15 -05:00
parent 1ee9b4db20
commit 707e9f82a4
19 changed files with 12405 additions and 12283 deletions
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78
radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc
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@@ -123,9 +123,9 @@ set_property IOSTANDARD LVCMOS18 [get_ports rx1_lna_en]
# PPS
#-------------------------------------------
# FMC2
#set_property PACKAGE_PIN H24 [get_ports pps]
#set_property PACKAGE_PIN H24 [get_ports pps]
# FMC1
set_property PACKAGE_PIN AF27 [get_ports pps]
set_property PACKAGE_PIN AF27 [get_ports pps]
set_property IOSTANDARD LVCMOS18 [get_ports pps]
#-------------------------------------------
@@ -234,17 +234,17 @@ set_property PACKAGE_PIN A25 [get_ports fmc_spi0_miso]
set_property PACKAGE_PIN B27 [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN B25 [get_ports fmc_spi0_ss]
set_property PULLUP TRUE [get_ports fmc_spi0_mosi]
set_property PULLUP TRUE [get_ports fmc_spi0_miso]
set_property PULLUP TRUE [get_ports fmc_spi0_sck]
set_property PULLUP true [get_ports fmc_spi0_mosi]
set_property PULLUP true [get_ports fmc_spi0_miso]
set_property PULLUP true [get_ports fmc_spi0_sck]
set_property PACKAGE_PIN C22 [get_ports fmc_spi1_mosi]
set_property PACKAGE_PIN D20 [get_ports fmc_spi1_sck]
set_property PACKAGE_PIN C21 [get_ports fmc_spi1_ss]
set_property PACKAGE_PIN F27 [get_ports resetb]
set_property PULLUP TRUE [get_ports fmc_spi1_mosi]
set_property PULLUP TRUE [get_ports fmc_spi1_sck]
set_property PULLUP true [get_ports fmc_spi1_mosi]
set_property PULLUP true [get_ports fmc_spi1_sck]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_mosi]
set_property IOSTANDARD LVCMOS18 [get_ports fmc_spi0_miso]
@@ -283,11 +283,11 @@ create_clock -period 5.333 -name jesd_qpll_refclk [get_ports jesd_qpll0_refclk_p
#set_property PACKAGE_PIN P6 [get_ports jesd_qpll0_refclk_p]
# Works with the board at my house
set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
#set_property PACKAGE_PIN G10 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN F10 [get_ports jesd_core_clk_n]
# Works with the board Chris has (broken USB UART)
#set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
#set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property PACKAGE_PIN D24 [get_ports jesd_core_clk_p]
set_property PACKAGE_PIN C24 [get_ports jesd_core_clk_n]
set_property IOSTANDARD LVDS [get_ports jesd_core_clk_p]
set_property DQS_BIAS TRUE [get_ports jesd_core_clk_p]
@@ -448,3 +448,59 @@ set_property PACKAGE_PIN AE23 [get_ports {ddr_dq[7]}]
connect_debug_port u_ila_0/probe6 [get_nets [list {tx_udp_switch_out\\.tlast}]]
connect_debug_port u_ila_0/probe4 [get_nets [list ethernet_top_i/tx_udp_hdr_ready]]
connect_debug_port u_ila_0/probe6 [get_nets [list ethernet_top_i/core_inst_0/tx_udp_hdr_valid]]
connect_debug_port u_ila_0/probe7 [get_nets [list ethernet_top_i/core_inst_0/tx_udp_hdr_valid_reg_n_0]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list {ethernet_top_i/sfp_phy_inst/phy1.eth_xcvr_phy_1/xcvr.eth_xcvr_gt_full_inst/inst/gen_gtwizard_gthe3_top.eth_xcvr_gt_full_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_user_clocking_internal.gen_single_instance.gtwiz_userclk_tx_inst/gtwiz_userclk_tx_usrclk2_out[0]}]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 28 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[3]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[4]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[5]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[6]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[7]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[8]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[10]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[11]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[12]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[13]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[14]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[15]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[16]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[17]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[18]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[19]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[20]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[21]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[22]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[23]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[24]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[25]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[26]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[27]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[28]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[29]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[30]} {ethernet_top_i/core_inst_0/bytes_left_cpi_reg[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {tx_udp_switch_out\\.tdest[0]} {tx_udp_switch_out\\.tdest[1]} {tx_udp_switch_out\\.tdest[2]} {tx_udp_switch_out\\.tdest[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {ethernet_top_i/core_inst_0/tlast_cnt_reg[0]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[1]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[2]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[3]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[4]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[5]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[6]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[7]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[8]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[9]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[10]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[11]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[12]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[13]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[14]} {ethernet_top_i/core_inst_0/tlast_cnt_reg[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list ethernet_top_i/core_inst_0/tlast_udp]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list ethernet_top_i/core_inst_0/udp_complete_inst/udp_64_inst/tx_udp_hdr_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {tx_udp_switch_out\\.tready}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {tx_udp_switch_out\\.tvalid}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list ethernet_top_i/core_inst_0/tx_udp_hdr_valid]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]