bkiedinger/castelion_radar_alinx_kintex
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updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size

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This commit is contained in:
bkiedinger@gmail.com
2025-07-15 22:40:15 -05:00
parent 1ee9b4db20
commit 707e9f82a4
19 changed files with 12405 additions and 12283 deletions
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2
radar_alinx_kintex.srcs/sources_1/hdl/ethernet_top.v
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@@ -17,7 +17,7 @@ module ethernet_top #
output wire [3:0] eth_clk,
output wire [3:0] eth_resetn,
input wire [15:0] packet_size,
input wire [31:0] packet_size,
axi4s_intf.master rx_udp_0,
axi4s_intf.slave tx_udp_0,

7
radar_alinx_kintex.srcs/sources_1/hdl/top.v
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@@ -447,6 +447,7 @@ module top #
reg pps_q;
reg pps_q2;
reg pps_red;
reg pps_fed;
always @ (posedge mb_axi_clk) begin
pps_pipe <= {pps_pipe[14:0], pps};
@@ -454,6 +455,7 @@ module top #
pps_q <= pps_debounce;
pps_q2 <= pps_q;
pps_red <= !pps_q2 & pps_q;
pps_fed <= pps_q2 & !pps_q;
end
microblaze_bd microblaze_bd_i
@@ -478,7 +480,8 @@ module top #
.qspi_flash_aresetn(qspi_flash_aresetn),
.pps(pps_red),
// .pps(pps_red),
.pps(pps_fed),
.clk_200_in_clk_n(clk_200_n),
.clk_200_in_clk_p(clk_200_p),
@@ -725,7 +728,7 @@ module top #
wire [31:0] gpi;
wire [31:0] gpo;
wire [15:0] packet_size;
wire [31:0] packet_size;
wire eth_reset;

4
radar_alinx_kintex.srcs/sources_1/hdl/util_reg.v
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@@ -13,7 +13,7 @@ module util_reg #
output wire [31:0] gpo,
input wire [31:0] gpi,
output wire [15:0] packet_size,
output wire [31:0] packet_size,
output wire fan_pwm,
input wire [31:0] datecode,
input wire [31:0] timecode,
@@ -97,7 +97,7 @@ reg [31:0] scratch;
reg [31:0] reg_gpo;
reg [24:0] pwm_period;
reg [24:0] pwm_pulsewidth;
reg [15:0] reg_packet_size;
reg [31:0] reg_packet_size;
reg [7:0] reg_num_bits;
reg [15:0] reg_dev_sel;
reg [31:0] reg_spi_data;

75
radar_alinx_kintex.srcs/sources_1/hdl/verilog_ethernet/fpga_core.v
View File

@@ -44,7 +44,7 @@ module fpga_core #
*/
input wire clk,
input wire rst,
input wire [15:0] packet_size,
input wire [31:0] packet_size,
output wire [63:0] rx_fifo_udp_payload_axis_tdata,
output wire [7:0] rx_fifo_udp_payload_axis_tkeep,
@@ -283,13 +283,18 @@ assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast || tlast_udp; // what happens if tlast comes before payload length ends
//assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast || tlast_udp; // what happens if tlast comes before payload length ends
assign tx_udp_payload_axis_tlast = tlast_udp; // what happens if tlast comes before payload length ends
// assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign tx_udp_payload_axis_tuser = 0;
reg [12:0] packet_size_div_8;
// assign packet_size_div_8 = packet_size[15:3];
reg [31:0] bytes_left_cpi;
// Need to inject additional TLAST signals on UDP packet boundaries, incoming data from
// DMA will only have TLAST at very end
reg [15:0] tlast_cnt;
@@ -299,7 +304,6 @@ always @(posedge clk) begin
tlast_cnt <= 0;
tlast_udp <= 0;
tx_udp_hdr_valid <= 0;
// next_packet_ready <= 1;
tx_udp_length <= 1024;
packet_size_div_8 <= 128;
end else begin
@@ -310,19 +314,55 @@ always @(posedge clk) begin
end else if (tlast_cnt == (packet_size_div_8-1)) begin
tlast_udp <= 0;
tlast_cnt <= 0;
// next_packet_ready <= 1;
end else begin
tlast_cnt <= tlast_cnt + 1;
tlast_udp <= 0;
end
end else if (tx_fifo_udp_payload_axis_tready && tx_fifo_udp_payload_axis_tlast) begin
tlast_cnt <= 0;
// end else if (tx_fifo_udp_payload_axis_tready && tx_fifo_udp_payload_axis_tlast) begin
// tlast_cnt <= 0;
end
if (tx_udp_hdr_ready) begin
if (tx_fifo_udp_payload_axis_tvalid) begin
// if (tx_udp_hdr_ready) begin
// if (tx_fifo_udp_payload_axis_tvalid) begin
// tx_udp_hdr_valid <= 1;
// if (tx_fifo_udp_payload_axis_tdest == 15) begin
// // Control Traffic
// tx_udp_dest_port <= control_port;
// tx_udp_length <= control_packet_size+8;
// packet_size_div_8 <= (control_packet_size >> 3);
// end else if (tx_fifo_udp_payload_axis_tdest == 0) begin
// // Header Packet
// tx_udp_dest_port <= port;
// tx_udp_length <= 1024+8;
// packet_size_div_8 <= (1024 >> 3);
// bytes_left_cpi <= packet_size;
// end else begin
// // Data Traffic
// tx_udp_dest_port <= port;
//// tx_udp_length <= packet_size+8;
//// packet_size_div_8 <= (packet_size >> 3);
// if (bytes_left_cpi > 4096) begin
// tx_udp_length <= 4096+8;
// packet_size_div_8 <= 512;
// end else begin
// tx_udp_length <= bytes_left_cpi+8;
// packet_size_div_8 <= (bytes_left_cpi >> 3);
// end
// bytes_left_cpi = bytes_left_cpi - 4096;
// end
// end
// end else begin
// tx_udp_hdr_valid = 0;
// end
if (tx_fifo_udp_payload_axis_tvalid && tx_udp_hdr_ready) begin
if (tx_udp_hdr_valid && tx_udp_hdr_ready) begin
tx_udp_hdr_valid <= 0;
end else begin
tx_udp_hdr_valid <= 1;
// next_packet_ready <= 0;
if (tx_fifo_udp_payload_axis_tdest == 15) begin
// Control Traffic
tx_udp_dest_port <= control_port;
@@ -333,17 +373,28 @@ always @(posedge clk) begin
tx_udp_dest_port <= port;
tx_udp_length <= 1024+8;
packet_size_div_8 <= (1024 >> 3);
bytes_left_cpi <= packet_size;
end else begin
// Data Traffic
tx_udp_dest_port <= port;
tx_udp_length <= packet_size+8;
packet_size_div_8 <= (packet_size >> 3);
// tx_udp_length <= packet_size+8;
// packet_size_div_8 <= (packet_size >> 3);
if (bytes_left_cpi > 4096) begin
tx_udp_length <= 4096+8;
packet_size_div_8 <= 512;
end else begin
tx_udp_length <= bytes_left_cpi+8;
packet_size_div_8 <= (bytes_left_cpi >> 3);
end
bytes_left_cpi = bytes_left_cpi - 4096;
end
end
end else begin
tx_udp_hdr_valid = 0;
end
end
end