updated udp packet fragmentation so that we don't have to restrict number of samples to be a multiple of a fixed udp packet size
This commit is contained in:
@@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="ASCII"?>
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<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="b81ac1744f29e93881cfaa8e8b019a98">
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<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="radar" location="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar" platform="/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/top/export/top/top.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="radar_system" sysConfig="top" runtime="C/C++" cpu="freertos10_xilinx_microblaze_0" cpuInstance="microblaze_0" os="freertos10_xilinx" mssSignature="31c4a066f121f9dfdf4b2a6e46d178c9">
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<configuration name="Debug" id="xilinx.gnu.mb.exe.debug.245787499">
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<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
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<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
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@@ -525,23 +525,23 @@ void setup_data_converter() {
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#ifndef IBERT_TESTING
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// Update FPGA TX Transceiver settings
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// set_lane_cal(0, 0, 0, 11);
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// set_lane_cal(1, 10, 5, 11);
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// set_lane_cal(2, 5, 0, 11);
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// set_lane_cal(3, 0, 0, 11);
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// set_lane_cal(4, 0, 0, 11);
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// set_lane_cal(5, 0, 0, 11);
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// set_lane_cal(6, 12, 0, 11);
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// set_lane_cal(7, 0, 0, 11);
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set_lane_cal(0, 0, 0, 11);
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set_lane_cal(1, 10, 5, 11);
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set_lane_cal(2, 5, 0, 11);
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set_lane_cal(3, 0, 0, 11);
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set_lane_cal(4, 0, 0, 11);
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set_lane_cal(5, 0, 0, 11);
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set_lane_cal(6, 12, 0, 11);
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set_lane_cal(7, 0, 0, 11);
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set_lane_cal(0, 9, 0, 7);
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set_lane_cal(1, 9, 0, 7);
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set_lane_cal(2, 9, 0, 7);
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set_lane_cal(3, 9, 0, 7);
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set_lane_cal(4, 9, 0, 7);
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set_lane_cal(5, 9, 0, 7);
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set_lane_cal(6, 9, 0, 7);
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set_lane_cal(7, 9, 0, 7);
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// set_lane_cal(0, 9, 0, 7);
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// set_lane_cal(1, 9, 0, 7);
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// set_lane_cal(2, 9, 0, 7);
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// set_lane_cal(3, 9, 0, 7);
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// set_lane_cal(4, 9, 0, 7);
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// set_lane_cal(5, 9, 0, 7);
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// set_lane_cal(6, 9, 0, 7);
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// set_lane_cal(7, 9, 0, 7);
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vTaskDelay(100);
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int subclass = jtx_param[uc][0].jesd_subclass;
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@@ -103,8 +103,12 @@ void status_task( void *pvParameters ) {
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}
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static void pps_irq_handler(u32 context) {
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xil_printf("pps irq %lu\r\n", utc_time);
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Xil_Out32(TIMING_ENGINE_ADDR + 0x14, utc_time + 1);
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uint32_t current_seconds = Xil_In32(TIMING_ENGINE_ADDR + 0x14);
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uint32_t new_time = utc_time + 1;
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if (current_seconds != new_time) {
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Xil_Out32(TIMING_ENGINE_ADDR + 0x14, new_time);
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xil_printf("pps irq %lu, %lu\r\n", current_seconds, new_time);
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}
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}
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void main_task( void *pvParameters ) {
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@@ -97,9 +97,9 @@ void novatel_task()
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utc_time = utc_sec;
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xil_printf("gps_week %lu\r\n", msg->hdr.week);
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xil_printf("gps_ms %lu\r\n", msg->hdr.ms);
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xil_printf("utc_time %lu\r\n", utc_sec);
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// xil_printf("gps_week %lu\r\n", msg->hdr.week);
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// xil_printf("gps_ms %lu\r\n", msg->hdr.ms);
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// xil_printf("utc_time %lu\r\n", utc_sec);
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}
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break;
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File diff suppressed because it is too large
Load Diff
@@ -496,8 +496,8 @@
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#define PLATFORM_MB
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/******************************************************************/
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#define STDIN_BASEADDRESS 0x40000000
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#define STDOUT_BASEADDRESS 0x40000000
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#define STDIN_BASEADDRESS 0x41400000
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#define STDOUT_BASEADDRESS 0x41400000
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/******************************************************************/
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@@ -6,8 +6,8 @@ BEGIN OS
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PARAMETER OS_NAME = freertos10_xilinx
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PARAMETER OS_VER = 1.12
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PARAMETER PROC_INSTANCE = microblaze_0
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PARAMETER stdin = axi_uartlite_0
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PARAMETER stdout = axi_uartlite_0
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PARAMETER stdin = mdm_1
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PARAMETER stdout = mdm_1
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PARAMETER total_heap_size = 2097152
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END
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@@ -1 +1 @@
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{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"4c4ac3edab33e057a6d0ea5f5fe6bbb4","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"total_heap_size":"2097152","libOptionNames":["total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
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{"platformName":"top","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"top","platHandOff":"/home/bkiedinger/projects/castelion/radar_alinx_kintex/top.xsa","platIntHandOff":"<platformDir>/hw/top.xsa","deviceType":"FPGA","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"top","systems":[{"systemName":"top","systemDesc":"top","sysIsBootAutoGen":"true","systemDispName":"top","sysActiveDom":"freertos10_xilinx_microblaze_0","sysDefaultDom":"standalone_microblaze_0","domains":[{"domainName":"freertos10_xilinx_microblaze_0","domainDispName":"freertos10_xilinx_microblaze_0","domainDesc":"freertos10_xilinx_microblaze_0","processors":"microblaze_0","os":"freertos10_xilinx","sdxOs":"freertos10_xilinx","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"1.12","mssFile":"","md5Digest":"b936724655c64fcfe17fbda77eb413eb","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip211:1.8"],"libOptions":{"freertos10_xilinx":{"stdin":"mdm_1","stdout":"mdm_1","total_heap_size":"2097152","libOptionNames":["stdin","stdout","total_heap_size"]},"lwip211":{"api_mode":"SOCKET_API","default_tcp_recvmbox_size":"4096","dhcp_does_arp_check":"true","lwip_dhcp":"true","lwip_tcpip_core_locking_input":"true","mem_size":"524288","memp_n_pbuf":"1024","memp_n_tcp_seg":"1024","memp_num_netbuf":"4096","n_rx_descriptors":"512","n_tx_descriptors":"512","pbuf_pool_size":"16384","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","tcpip_mbox_size":"4096","libOptionNames":["api_mode","default_tcp_recvmbox_size","dhcp_does_arp_check","lwip_dhcp","lwip_tcpip_core_locking_input","mem_size","memp_n_pbuf","memp_n_tcp_seg","memp_num_netbuf","n_rx_descriptors","n_tx_descriptors","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd","tcpip_mbox_size"]},"libsContainingOptions":["freertos10_xilinx","lwip211"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_microblaze_0","domainDispName":"standalone_microblaze_0","domainDesc":"standalone_microblaze_0","processors":"microblaze_0","os":"standalone","sdxOs":"standalone","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"8.0","mssFile":"","md5Digest":"c7a3ff64e4f9fb39fec5475cd7ffa1a7","compatibleApp":"","domType":"mssDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
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@@ -175,3 +175,14 @@ bsp write
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bsp reload
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catch {bsp regenerate}
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platform generate -domains freertos10_xilinx_microblaze_0
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platform active {top}
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bsp reload
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bsp reload
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platform active {top}
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bsp reload
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bsp config stdin "mdm_1"
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bsp config stdout "mdm_1"
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bsp write
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bsp reload
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catch {bsp regenerate}
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platform generate
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