fixed pinout, made some updates for discrete timing pulses, needs to be tested

python/radar_manager.py

@@ -17,6 +17,10 @@ WAVEFORM_GEN_ADDR = 0x40053000
 
 NUM_RX = 2
 
+
+ADC_SAMPLE_RATE = 187.5e6
+DAC_SAMPLE_RATE = 187.5e6
+
 def form_chirp(pulsewidth, bw, sample_rate, win=None, ):
 
     n = int(np.round(pulsewidth * sample_rate))
@@ -248,10 +252,18 @@ class RadarManager:
             self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x4, num_samples >> 2)
             self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x8, start_sample >> 2)
 
+            # Setup RX Strobe
+            self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample)
+            self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples)
+
     def setup_tx(self, num_samples, start_sample):
         self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 2)
         self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 2)
 
+        # Setup TX Strobe
+        self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample)
+        self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples)
+
     def start_running(self):
         for i in range(NUM_RX):
             self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x0, 0)  # RX Reset
@@ -285,7 +297,6 @@ class RadarManager:
 
         # DAC at 5.25 GHz is in second nyquist
         # ADC would be in 3rd nyquist
-        lo = 5.25e9
         f_dac = 9e9
         f_adc = 3e9
         tx_lo = 5.25e9 % f_dac

radar_alinx_kintex.srcs/constrs_1/new/constraints.xdc

@@ -35,7 +35,7 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_200_n]
 #-------------------------------------------
 # RF Attenautors
 #-------------------------------------------
-set_property PACKAGE_PIN G26 [get_ports tx0_rf_attn_sin]
+set_property PACKAGE_PIN G25 [get_ports tx0_rf_attn_sin]
 set_property PACKAGE_PIN H26 [get_ports tx0_rf_attn_clk]
 set_property PACKAGE_PIN J26 [get_ports tx0_rf_attn_le]
 set_property PACKAGE_PIN L25 [get_ports tx1_rf_attn_sin]

radar_alinx_kintex.srcs/sources_1/hdl/timing_engine.v

@@ -6,7 +6,8 @@ module timing_engine #
 (
     parameter integer AXI_ADDR_WIDTH	= 32,
     parameter integer AXI_DATA_WIDTH	= 32,    
-    parameter NUM_RX	= 2    
+    parameter NUM_RX	= 2,
+    parameter NUM_TIMING_PULSES	= 8     
 )
 (
     input  wire         clk,
@@ -18,6 +19,8 @@ module timing_engine #
 
     output wire         start_of_cpi,
     output wire         start_of_pulse,
+    
+    output wire [NUM_TIMING_PULSES-1:0]   timing_pulses,
 
     axi4s_intf.master   hdr_out[NUM_RX]
 );
@@ -76,13 +79,16 @@ axil_slave
 wire reset;
 assign reset = ~ctrl_if.resetn;
 reg [31:0] reg_ctrl;
-reg [31:0] reg_pri;
-reg [31:0] reg_num_pulses; 
-reg [31:0] reg_inter_cpi; 
-reg [64:0] system_time;
-reg [64:0] pps_frac_sec;
-reg [32:0] pps_sec;
-reg [32:0] reg_pps_sec_set;
+reg [27:0] reg_pri;
+reg [27:0] reg_num_pulses; 
+reg [27:0] reg_inter_cpi; 
+reg [31:0] reg_pps_sec_set;
+reg [31:0] reg_pulse_width [NUM_TIMING_PULSES-1:0];
+reg [31:0] reg_pulse_start [NUM_TIMING_PULSES-1:0];
+
+reg [63:0] system_time;
+reg [63:0] pps_frac_sec;
+reg [31:0] pps_sec;
 reg reg_pps_set;
 reg hdr_bram_we;
 
@@ -130,6 +136,30 @@ always @ (posedge ctrl_if.clk) begin
     end
 end
 
+genvar gen_reg;
+generate
+    for (gen_reg = 0; gen_reg < NUM_TIMING_PULSES; gen_reg = gen_reg + 1) begin
+        always @ (posedge ctrl_if.clk) begin
+            if (reset) begin
+                reg_pulse_start[gen_reg] <= 0;
+            end else if (wren && waddr[11:0] == ('h080 + gen_reg*8)) begin
+                reg_pulse_start[gen_reg] <= wdata;
+            end
+        end
+        
+        always @ (posedge ctrl_if.clk) begin
+            if (reset) begin
+                reg_pulse_width[gen_reg] <= 0;
+            end else if (wren && waddr[11:0] == ('h080 + gen_reg*8 + 4)) begin
+                reg_pulse_width[gen_reg] <= wdata;
+            end
+        end
+                
+    end
+endgenerate        
+
+
+
 always @ (posedge ctrl_if.clk) begin
     if (wren && waddr[11:10] == 2'b11) begin
         hdr_bram_we <= 1;
@@ -154,9 +184,9 @@ end
 // ------------------------------
 // Timestamping
 // ------------------------------
-reg [64:0] system_time_start_of_cpi;
-reg [64:0] pps_sec_start_of_cpi;
-reg [64:0] pps_frac_sec_start_of_cpi;
+reg [63:0] system_time_start_of_cpi;
+reg [63:0] pps_sec_start_of_cpi;
+reg [63:0] pps_frac_sec_start_of_cpi;
 
 
 reg [15:0] pps_pipe;
@@ -303,33 +333,14 @@ generate
     end
 endgenerate
 
-// hdr_fifo hdr_fifo_i (
-//   .s_axis_aresetn(rstn), 
-//   .s_axis_aclk(hdr_out.clk),       
-
-//   .s_axis_tvalid(hdr_active_q3),   
-//   .s_axis_tready(),   
-//   .s_axis_tdata(hdr_data),     
-//   .s_axis_tlast(hdr_tlast_q3),     
-
-//   .m_axis_tvalid(hdr_out.tvalid),   
-//   .m_axis_tready(hdr_out.tready),   
-//   .m_axis_tdata(hdr_out.tdata),     
-//   .m_axis_tlast(hdr_out.tlast)      
-// );
-
-// assign hdr_out.tkeep = '1;
-// assign hdr_out.tuser = 64;
-// assign hdr_out.tdest = 0;
-
 // ------------------------------
 // Timing
 // ------------------------------
 wire rst;
 wire rstn;
 
-reg [31:0]  pri_cnt;
-reg [31:0]  pulse_cnt;
+reg [27:0]  pri_cnt;
+reg [27:0]  pulse_cnt;
 wire inter_cpi_active;
 reg start_of_pulse_reg;
 reg start_of_cpi_reg;
@@ -382,6 +393,33 @@ always @ (posedge clk) begin
     end
 end
 
+// ------------------------------
+// Pulse Generators
+// ------------------------------
+reg [NUM_TIMING_PULSES-1:0] pulse_start; 
+
+genvar j;
+generate
+    for (j = 0; j < NUM_TIMING_PULSES; j = j + 1) begin
+    
+        always @ (posedge clk) begin
+            if (pri_cnt == reg_pulse_start[j]) begin
+                pulse_start[j] <= 1;
+            end else begin  
+                pulse_start[j] <= 0;
+            end
+        end
+    
+        pulse_generator (
+            .clk(clk),
+            .rst(rst),
+            .pulse_length(reg_pulse_width[j]),
+            .start_of_pulse(pulse_start[j]),
+            .pulse_out(timing_pulses[j])
+        );
+
+    end
+endgenerate
 
 endmodule
 

radar_alinx_kintex.srcs/sources_1/hdl/top.v

@@ -807,7 +807,13 @@ module top #
 
     // ------------------------------
     // Timing Engine
-    // ------------------------------   
+    // ------------------------------
+    wire [7:0]   timing_pulses;
+    
+    assign txlo_drv_en = timing_pulses[0];
+    assign rx0_lna_en = timing_pulses[1];
+    assign rx1_lna_en = timing_pulses[2];
+       
     timing_engine timing_engine_i
     (
         .clk(jesd_core_clk),    
@@ -817,12 +823,11 @@ module top #
         
         .start_of_cpi(start_of_cpi),
         .start_of_pulse(start_of_pulse),
+        .timing_pulses(timing_pulses),
 
         .hdr_out(hdr_out)
     );  
 
-
-
     // ------------------------------
     // TX Chain
     // ------------------------------  

radar_alinx_kintex.xpr

@@ -381,6 +381,13 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/hdl/pulse_generator.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/hdl/verilog_ethernet/sync_reset.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>

vitis/radar_system/_ide/flash/bootimage.bif

@@ -1,5 +1,5 @@
 the_ROM_image:
 {
-/home/bkiedinger/projects/castelion/radar_alinx_kintex/radar_alinx_kintex.runs/impl_1/download.bit
+/home/bkiedinger/projects/castelion/radar_alinx_kintex/vitis/radar_system/_ide/flash/radar.elf.srec
 }