fixed pinout, made some updates for discrete timing pulses, needs to be tested

This commit is contained in:
2025-04-14 08:17:28 -05:00
parent a404c3b146
commit 729d034a13
9 changed files with 25092 additions and 24800 deletions

View File

@@ -17,6 +17,10 @@ WAVEFORM_GEN_ADDR = 0x40053000
NUM_RX = 2
ADC_SAMPLE_RATE = 187.5e6
DAC_SAMPLE_RATE = 187.5e6
def form_chirp(pulsewidth, bw, sample_rate, win=None, ):
n = int(np.round(pulsewidth * sample_rate))
@@ -248,10 +252,18 @@ class RadarManager:
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x4, num_samples >> 2)
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x8, start_sample >> 2)
# Setup RX Strobe
self.axi_write_register(TIMING_ENGINE_ADDR + 0x88 + i * 8, start_sample)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x8C + i * 8, num_samples)
def setup_tx(self, num_samples, start_sample):
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x4, num_samples >> 2)
self.axi_write_register(WAVEFORM_GEN_ADDR + 0x8, start_sample >> 2)
# Setup TX Strobe
self.axi_write_register(TIMING_ENGINE_ADDR + 0x80, start_sample)
self.axi_write_register(TIMING_ENGINE_ADDR + 0x84, num_samples)
def start_running(self):
for i in range(NUM_RX):
self.axi_write_register(DIG_RX_ADDR + i*DIG_RX_STRIDE + 0x0, 0) # RX Reset
@@ -285,7 +297,6 @@ class RadarManager:
# DAC at 5.25 GHz is in second nyquist
# ADC would be in 3rd nyquist
lo = 5.25e9
f_dac = 9e9
f_adc = 3e9
tx_lo = 5.25e9 % f_dac