fixed pinout, made some updates for discrete timing pulses, needs to be tested

2025-04-14 08:17:28 -05:00
parent a404c3b146
commit 729d034a13
9 changed files with 25092 additions and 24800 deletions
--- a/radar_alinx_kintex.xpr
+++ b/radar_alinx_kintex.xpr
@@ -381,6 +381,13 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
+      <File Path="$PSRCDIR/sources_1/hdl/pulse_generator.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
      <File Path="$PSRCDIR/sources_1/hdl/verilog_ethernet/sync_reset.v">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>