added latency to freq mult to improve timing, had to delete and remake the IP core for some reason

radar_alinx_kintex.srcs/sources_1/hdl/delay_shift_reg.sv

@@ -3,22 +3,41 @@
 `default_nettype none
 
 module delay_shift_register #(
-  parameter DELAY_CYCLES = 4 
+  parameter DELAY_CYCLES = 4 ,
+  parameter DATA_WIDTH = 1
 ) (
   input  wire clk,
   input  wire reset, 
-  input  wire data_in,
-  output wire data_out
+  input  wire [DATA_WIDTH-1:0] data_in,
+  output wire [DATA_WIDTH-1:0] data_out
 );
 
+  // // Declare a register to hold the shifted data
+  // reg [DELAY_CYCLES-1:0] shift_reg;
+
+  // always @ (posedge clk) begin
+  //   if (reset) begin
+  //     shift_reg <= '0;
+  //   end else begin
+  //     shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in};
+  //   end
+  // end
+
+  // assign data_out = shift_reg[DELAY_CYCLES-1];
+
   // Declare a register to hold the shifted data
-  reg [DELAY_CYCLES-1:0] shift_reg;
+  reg [DATA_WIDTH-1:0] shift_reg [DELAY_CYCLES];
 
   always @ (posedge clk) begin
     if (reset) begin
-      shift_reg <= '0;
+        for (int i = 0; i < DELAY_CYCLES; i = i + 1) begin
+            shift_reg[i] <= 0;
+        end
     end else begin
-      shift_reg <= {shift_reg[DELAY_CYCLES-2:0], data_in};
+        for (int i = DELAY_CYCLES-1; i > 0; i = i - 1) begin
+            shift_reg[i] <= shift_reg[i-1]; // Shift right
+        end
+        shift_reg[0] <= data_in;
     end
   end
 

radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv

@@ -321,7 +321,7 @@ end
 
 wire [47:0] mult_out;
 wire [31:0] chip_delta_freq;
-ofdm_freq_mult freq_mult (
+freq_mult freq_mult (
   .CLK(clk), 
   .A(reg_delta_freq),  
   .B(read_sequence),
@@ -340,9 +340,20 @@ end
 
 assign set_phase = (chip_cnt == 0) ? pulse_active : 1'b0;
 
+wire [15:0] read_phase_delayed;
+delay_shift_register # (
+    .DELAY_CYCLES(6),
+    .DATA_WIDTH(16)
+) delay_phase (
+  .clk(clk), 
+  .reset(reset),
+  .data_in(read_phase),    
+  .data_out(read_phase_delayed)
+);
+
 wire pulse_active_delayed;
 delay_shift_register # (
-    .DELAY_CYCLES(4)
+    .DELAY_CYCLES(8)
 ) delay_valid (
   .clk(clk), 
   .reset(reset),
@@ -352,7 +363,7 @@ delay_shift_register # (
 
 wire set_phase_delayed;
 delay_shift_register # (
-    .DELAY_CYCLES(4)
+    .DELAY_CYCLES(8)
 ) delay_set_phase (
   .clk(clk), 
   .reset(reset),
@@ -366,7 +377,8 @@ gen_sine gen_sine_i (
     .reset(reset),  
     .set_phase(set_phase_delayed),  
 	.valid(pulse_active_delayed),
-    .phase({read_phase_q2, 16'h0000}),
+    // .phase({read_phase_q2, 16'h0000}),
+    .phase({read_phase_delayed, 16'h0000}),
     .frequency(chip_freq),
     .iq_out(iq_out),
 	.iq_out_valid(iq_out_valid)