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fix multidriver net issue in real build that worked fine in simulation

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This commit is contained in:
bkiedinger@gmail.com
2025-11-12 08:52:44 -06:00
parent 522bd9e8c9
commit ea0785e7d3
5 changed files with 126 additions and 94 deletions
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14
radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/decimation_bd.bda
View File

@@ -23,20 +23,20 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VM">decimation_bd</data>
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="VH">2</data>
<data key="VM">decimation_bd</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">decimation_bd</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0"/>
<edge id="e1" source="n0" target="n1"/>
<edge id="e0" source="n0" target="n1"/>
<edge id="e1" source="n1" target="n2"/>
</graph>
</graphml>

4
radar_alinx_kintex.srcs/sources_1/bd/decimation_bd/ip/decimation_bd_axis_broadcaster_0_0/decimation_bd_axis_broadcaster_0_0.xci
View File

@@ -187,7 +187,7 @@ imum {}} value data_valid} enabled {attribs {resolve_type generated dependency d
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
@@ -206,7 +206,7 @@ imum {}} value data_valid} enabled {attribs {resolve_type generated dependency d
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]

91
radar_alinx_kintex.srcs/sources_1/hdl/top.v
View File

@@ -945,47 +945,62 @@ module top #
assign jesd_axis_tx_cmd_tdata = 0;
assign jesd_axis_tx_cmd_tvalid = 1'b1;
waveform_gen waveform_gen_i (
.clk(jesd_core_clk),
wire [127:0] iq_out;
wire iq_out_valid;
gen_ofdm dut (
.clk(jesd_core_clk),
.reset(1'b0),
.ctrl_if(wf_gen_if),
.start_pulse(start_of_pulse),
.iq_out(iq_out),
.iq_out_valid(iq_out_valid)
);
.start_of_pulse(start_of_pulse),
.dac0_wf_bram_addr(dac0_wf_bram_addr),
.dac0_wf_bram_clk(dac0_wf_bram_clk),
.dac0_wf_bram_din(dac0_wf_bram_din),
.dac0_wf_bram_dout(dac0_wf_bram_dout),
.dac0_wf_bram_en(dac0_wf_bram_en),
.dac0_wf_bram_rst(dac0_wf_bram_rst),
.dac0_wf_bram_we(dac0_wf_bram_we),
.dac1_wf_bram_addr(dac1_wf_bram_addr),
.dac1_wf_bram_clk(dac1_wf_bram_clk),
.dac1_wf_bram_din(dac1_wf_bram_din),
.dac1_wf_bram_dout(dac1_wf_bram_dout),
.dac1_wf_bram_en(dac1_wf_bram_en),
.dac1_wf_bram_rst(dac1_wf_bram_rst),
.dac1_wf_bram_we(dac1_wf_bram_we),
.dac2_wf_bram_addr(dac2_wf_bram_addr),
.dac2_wf_bram_clk(dac2_wf_bram_clk),
.dac2_wf_bram_din(dac2_wf_bram_din),
.dac2_wf_bram_dout(dac2_wf_bram_dout),
.dac2_wf_bram_en(dac2_wf_bram_en),
.dac2_wf_bram_rst(dac2_wf_bram_rst),
.dac2_wf_bram_we(dac2_wf_bram_we),
.dac3_wf_bram_addr(dac3_wf_bram_addr),
.dac3_wf_bram_clk(dac3_wf_bram_clk),
.dac3_wf_bram_din(dac3_wf_bram_din),
.dac3_wf_bram_dout(dac3_wf_bram_dout),
.dac3_wf_bram_en(dac3_wf_bram_en),
.dac3_wf_bram_rst(dac3_wf_bram_rst),
.dac3_wf_bram_we(dac3_wf_bram_we),
assign jesd_axis_tx_tdata = {iq_out, iq_out, iq_out, iq_out};
.jesd_tx(jesd_axis_tx_tdata)
);
// waveform_gen waveform_gen_i (
// .clk(jesd_core_clk),
// .ctrl_if(wf_gen_if),
// .start_of_pulse(start_of_pulse),
// .dac0_wf_bram_addr(dac0_wf_bram_addr),
// .dac0_wf_bram_clk(dac0_wf_bram_clk),
// .dac0_wf_bram_din(dac0_wf_bram_din),
// .dac0_wf_bram_dout(dac0_wf_bram_dout),
// .dac0_wf_bram_en(dac0_wf_bram_en),
// .dac0_wf_bram_rst(dac0_wf_bram_rst),
// .dac0_wf_bram_we(dac0_wf_bram_we),
// .dac1_wf_bram_addr(dac1_wf_bram_addr),
// .dac1_wf_bram_clk(dac1_wf_bram_clk),
// .dac1_wf_bram_din(dac1_wf_bram_din),
// .dac1_wf_bram_dout(dac1_wf_bram_dout),
// .dac1_wf_bram_en(dac1_wf_bram_en),
// .dac1_wf_bram_rst(dac1_wf_bram_rst),
// .dac1_wf_bram_we(dac1_wf_bram_we),
// .dac2_wf_bram_addr(dac2_wf_bram_addr),
// .dac2_wf_bram_clk(dac2_wf_bram_clk),
// .dac2_wf_bram_din(dac2_wf_bram_din),
// .dac2_wf_bram_dout(dac2_wf_bram_dout),
// .dac2_wf_bram_en(dac2_wf_bram_en),
// .dac2_wf_bram_rst(dac2_wf_bram_rst),
// .dac2_wf_bram_we(dac2_wf_bram_we),
// .dac3_wf_bram_addr(dac3_wf_bram_addr),
// .dac3_wf_bram_clk(dac3_wf_bram_clk),
// .dac3_wf_bram_din(dac3_wf_bram_din),
// .dac3_wf_bram_dout(dac3_wf_bram_dout),
// .dac3_wf_bram_en(dac3_wf_bram_en),
// .dac3_wf_bram_rst(dac3_wf_bram_rst),
// .dac3_wf_bram_we(dac3_wf_bram_we),
// .jesd_tx(jesd_axis_tx_tdata)
// );
endmodule

4
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv
View File

@@ -24,6 +24,7 @@ reg valid_q2;
reg [31:0] phase_q;
reg [31:0] frequency_q;
reg [127:0] iq_out_i;
wire [3:0] iq_out_valid_i;
always @ (posedge clk) begin
set_phase_q <= set_phase;
@@ -58,7 +59,7 @@ generate
.aclk(clk),
.s_axis_phase_tvalid(valid_q2),
.s_axis_phase_tdata(cordic_phase_in),
.m_axis_dout_tvalid(iq_out_valid),
.m_axis_dout_tvalid(iq_out_valid_i[i]),
.m_axis_dout_tdata(iq_out_i[i*32+31:i*32])
);
@@ -66,6 +67,7 @@ generate
endgenerate
assign iq_out = iq_out_i;
assign iq_out_valid = &iq_out_valid_i;
endmodule
`resetall

107
radar_alinx_kintex.xpr
View File

@@ -451,6 +451,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/delay_shift_reg.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/digital_rx_chain.v">
<FileInfo SFType="SVerilog">
<Attr Name="UsedIn" Val="synthesis"/>
@@ -465,6 +472,20 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_ofdm.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_sine.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/timing_engine.v">
<FileInfo SFType="SVerilog">
<Attr Name="UsedIn" Val="synthesis"/>
@@ -479,15 +500,16 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/waveform_gen.v">
<File Path="$PSRCDIR/sources_1/hdl/top.v">
<FileInfo SFType="SVerilog">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/top.v">
<File Path="$PSRCDIR/sources_1/hdl/waveform_gen.v">
<FileInfo SFType="SVerilog">
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -517,30 +539,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_sine.sv">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_ofdm.sv">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/delay_shift_reg.sv">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
@@ -699,6 +697,7 @@
<FileSet Name="wf_memory" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wf_memory" RelGenDir="$PGENDIR/wf_memory">
<File Path="$PSRCDIR/sources_1/ip/wf_memory/wf_memory.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -785,7 +784,6 @@
<FileSet Name="wfg_cordic" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wfg_cordic" RelGenDir="$PGENDIR/wfg_cordic">
<File Path="$PSRCDIR/sources_1/ip/wfg_cordic/wfg_cordic.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -815,7 +813,6 @@
<FileSet Name="ofdm_sequence_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ofdm_sequence_ram" RelGenDir="$PGENDIR/ofdm_sequence_ram">
<File Path="$PSRCDIR/sources_1/ip/ofdm_sequence_ram/ofdm_sequence_ram.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -830,7 +827,6 @@
<FileSet Name="ofdm_freq_mult" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ofdm_freq_mult" RelGenDir="$PGENDIR/ofdm_freq_mult">
<File Path="$PSRCDIR/sources_1/ip/ofdm_freq_mult/ofdm_freq_mult.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -865,74 +861,84 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="19">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design" PreStepTclHook="$PSRCDIR/set_build_date.tcl"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Run Id="axis_switch_0_synth_1" Type="Ft3:Synth" SrcSet="axis_switch_0" Part="xcku040-ffva1156-2-i" ConstrsSet="axis_switch_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_switch_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_switch_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Run Id="hdr_mem_synth_1" Type="Ft3:Synth" SrcSet="hdr_mem" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_mem" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_mem_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_mem_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Run Id="dig_rx_clock_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_clock_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_clock_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_clock_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_clock_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Run Id="dig_rx_dwidth_converter_synth_1" Type="Ft3:Synth" SrcSet="dig_rx_dwidth_converter" Part="xcku040-ffva1156-2-i" ConstrsSet="dig_rx_dwidth_converter" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dig_rx_dwidth_converter_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dig_rx_dwidth_converter_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Run Id="pulse_buffer_fifo_synth_1" Type="Ft3:Synth" SrcSet="pulse_buffer_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="pulse_buffer_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pulse_buffer_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/pulse_buffer_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Run Id="eth_xcvr_gt_channel_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_channel" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_channel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_channel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_channel_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Run Id="eth_xcvr_gt_full_synth_1" Type="Ft3:Synth" SrcSet="eth_xcvr_gt_full" Part="xcku040-ffva1156-2-i" ConstrsSet="eth_xcvr_gt_full" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/eth_xcvr_gt_full_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/eth_xcvr_gt_full_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
@@ -946,11 +952,12 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Run Id="hdr_fifo_synth_1" Type="Ft3:Synth" SrcSet="hdr_fifo" Part="xcku040-ffva1156-2-i" ConstrsSet="hdr_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hdr_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hdr_fifo_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
@@ -964,11 +971,12 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Run Id="microblaze_bd_synth_1" Type="Ft3:Synth" SrcSet="microblaze_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="microblaze_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/microblaze_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/microblaze_bd_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
@@ -982,20 +990,22 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="decimation_bd_synth_1" Type="Ft3:Synth" SrcSet="decimation_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="decimation_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1">
<Run Id="decimation_bd_synth_1" Type="Ft3:Synth" SrcSet="decimation_bd" Part="xcku040-ffva1156-2-i" ConstrsSet="decimation_bd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/decimation_bd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/decimation_bd_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wfg_cordic_synth_1" Type="Ft3:Synth" SrcSet="wfg_cordic" Part="xcku040-ffva1156-2-i" ConstrsSet="wfg_cordic" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1">
<Run Id="wfg_cordic_synth_1" Type="Ft3:Synth" SrcSet="wfg_cordic" Part="xcku040-ffva1156-2-i" ConstrsSet="wfg_cordic" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wfg_cordic_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
@@ -1009,27 +1019,31 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="ofdm_sequence_ram_synth_1" Type="Ft3:Synth" SrcSet="ofdm_sequence_ram" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_sequence_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1">
<Run Id="ofdm_sequence_ram_synth_1" Type="Ft3:Synth" SrcSet="ofdm_sequence_ram" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_sequence_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ofdm_sequence_ram_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_sequence_ram_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="ofdm_freq_mult_synth_1" Type="Ft3:Synth" SrcSet="ofdm_freq_mult" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_freq_mult" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_synth_1">
<Run Id="ofdm_freq_mult_synth_1" Type="Ft3:Synth" SrcSet="ofdm_freq_mult" Part="xcku040-ffva1156-2-i" ConstrsSet="ofdm_freq_mult" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ofdm_freq_mult_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ofdm_freq_mult_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -1040,6 +1054,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>