bkiedinger/castelion_radar_alinx_kintex
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fix multidriver net issue in real build that worked fine in simulation

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This commit is contained in:
bkiedinger@gmail.com
2025-11-12 08:52:44 -06:00
parent 522bd9e8c9
commit ea0785e7d3
5 changed files with 126 additions and 94 deletions
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91
radar_alinx_kintex.srcs/sources_1/hdl/top.v
View File

@@ -945,47 +945,62 @@ module top #
assign jesd_axis_tx_cmd_tdata = 0;
assign jesd_axis_tx_cmd_tvalid = 1'b1;
waveform_gen waveform_gen_i (
.clk(jesd_core_clk),
wire [127:0] iq_out;
wire iq_out_valid;
gen_ofdm dut (
.clk(jesd_core_clk),
.reset(1'b0),
.ctrl_if(wf_gen_if),
.start_pulse(start_of_pulse),
.iq_out(iq_out),
.iq_out_valid(iq_out_valid)
);
.start_of_pulse(start_of_pulse),
.dac0_wf_bram_addr(dac0_wf_bram_addr),
.dac0_wf_bram_clk(dac0_wf_bram_clk),
.dac0_wf_bram_din(dac0_wf_bram_din),
.dac0_wf_bram_dout(dac0_wf_bram_dout),
.dac0_wf_bram_en(dac0_wf_bram_en),
.dac0_wf_bram_rst(dac0_wf_bram_rst),
.dac0_wf_bram_we(dac0_wf_bram_we),
.dac1_wf_bram_addr(dac1_wf_bram_addr),
.dac1_wf_bram_clk(dac1_wf_bram_clk),
.dac1_wf_bram_din(dac1_wf_bram_din),
.dac1_wf_bram_dout(dac1_wf_bram_dout),
.dac1_wf_bram_en(dac1_wf_bram_en),
.dac1_wf_bram_rst(dac1_wf_bram_rst),
.dac1_wf_bram_we(dac1_wf_bram_we),
.dac2_wf_bram_addr(dac2_wf_bram_addr),
.dac2_wf_bram_clk(dac2_wf_bram_clk),
.dac2_wf_bram_din(dac2_wf_bram_din),
.dac2_wf_bram_dout(dac2_wf_bram_dout),
.dac2_wf_bram_en(dac2_wf_bram_en),
.dac2_wf_bram_rst(dac2_wf_bram_rst),
.dac2_wf_bram_we(dac2_wf_bram_we),
.dac3_wf_bram_addr(dac3_wf_bram_addr),
.dac3_wf_bram_clk(dac3_wf_bram_clk),
.dac3_wf_bram_din(dac3_wf_bram_din),
.dac3_wf_bram_dout(dac3_wf_bram_dout),
.dac3_wf_bram_en(dac3_wf_bram_en),
.dac3_wf_bram_rst(dac3_wf_bram_rst),
.dac3_wf_bram_we(dac3_wf_bram_we),
assign jesd_axis_tx_tdata = {iq_out, iq_out, iq_out, iq_out};
.jesd_tx(jesd_axis_tx_tdata)
);
// waveform_gen waveform_gen_i (
// .clk(jesd_core_clk),
// .ctrl_if(wf_gen_if),
// .start_of_pulse(start_of_pulse),
// .dac0_wf_bram_addr(dac0_wf_bram_addr),
// .dac0_wf_bram_clk(dac0_wf_bram_clk),
// .dac0_wf_bram_din(dac0_wf_bram_din),
// .dac0_wf_bram_dout(dac0_wf_bram_dout),
// .dac0_wf_bram_en(dac0_wf_bram_en),
// .dac0_wf_bram_rst(dac0_wf_bram_rst),
// .dac0_wf_bram_we(dac0_wf_bram_we),
// .dac1_wf_bram_addr(dac1_wf_bram_addr),
// .dac1_wf_bram_clk(dac1_wf_bram_clk),
// .dac1_wf_bram_din(dac1_wf_bram_din),
// .dac1_wf_bram_dout(dac1_wf_bram_dout),
// .dac1_wf_bram_en(dac1_wf_bram_en),
// .dac1_wf_bram_rst(dac1_wf_bram_rst),
// .dac1_wf_bram_we(dac1_wf_bram_we),
// .dac2_wf_bram_addr(dac2_wf_bram_addr),
// .dac2_wf_bram_clk(dac2_wf_bram_clk),
// .dac2_wf_bram_din(dac2_wf_bram_din),
// .dac2_wf_bram_dout(dac2_wf_bram_dout),
// .dac2_wf_bram_en(dac2_wf_bram_en),
// .dac2_wf_bram_rst(dac2_wf_bram_rst),
// .dac2_wf_bram_we(dac2_wf_bram_we),
// .dac3_wf_bram_addr(dac3_wf_bram_addr),
// .dac3_wf_bram_clk(dac3_wf_bram_clk),
// .dac3_wf_bram_din(dac3_wf_bram_din),
// .dac3_wf_bram_dout(dac3_wf_bram_dout),
// .dac3_wf_bram_en(dac3_wf_bram_en),
// .dac3_wf_bram_rst(dac3_wf_bram_rst),
// .dac3_wf_bram_we(dac3_wf_bram_we),
// .jesd_tx(jesd_axis_tx_tdata)
// );
endmodule

4
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv
View File

@@ -24,6 +24,7 @@ reg valid_q2;
reg [31:0] phase_q;
reg [31:0] frequency_q;
reg [127:0] iq_out_i;
wire [3:0] iq_out_valid_i;
always @ (posedge clk) begin
set_phase_q <= set_phase;
@@ -58,7 +59,7 @@ generate
.aclk(clk),
.s_axis_phase_tvalid(valid_q2),
.s_axis_phase_tdata(cordic_phase_in),
.m_axis_dout_tvalid(iq_out_valid),
.m_axis_dout_tvalid(iq_out_valid_i[i]),
.m_axis_dout_tdata(iq_out_i[i*32+31:i*32])
);
@@ -66,6 +67,7 @@ generate
endgenerate
assign iq_out = iq_out_i;
assign iq_out_valid = &iq_out_valid_i;
endmodule
`resetall