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@@ -1,489 +0,0 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////
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//
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// Author : Torry Akins
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// Creation Date : 06/04/2024
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// File Name : dma_engine_256.sv
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// Tool Version : 2021.2
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// Description : DMA Engine (256 bits wide)
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//
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// Copyright (c) 2024 Wide Swath Research, LLC.
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// This design is confidential and is the proprietary property
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// of Wide Swath Research, LLC.
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//
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// Design licensed for use by Aloft Sensing, Inc.
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//
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//////////////////////////////////////////////////////////////////////////////
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module dma_engine_256 (
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axi4l_intf.slave axi,
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axi4s_intf.slave axis,
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axi4_intf.master axim
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);
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// incoming pipeline of write address
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reg awaddr_valid;
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reg [axi.AXI_ADDR_WIDTH-1:0] awaddr;
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// incoming pipeline of write data
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reg wdata_valid;
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reg [((axi.AXI_DATA_WIDTH/8)-1):0] wstrb;
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reg [axi.AXI_DATA_WIDTH-1:0] wdata;
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// incoming pipeline of read address
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reg araddr_valid;
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reg [axi.AXI_ADDR_WIDTH:0] araddr;
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// outgoing pipeline of read data
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reg rvalid;
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reg [axi.AXI_DATA_WIDTH-1:0] rdata;
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integer byte_index;
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reg [axi.AXI_DATA_WIDTH-1:0] ctrl_reg[3:0];
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wire [axi.AXI_DATA_WIDTH-1:0] status_reg[4:0];
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reg ctrl_fifo_wren;
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reg [127:0] ctrl_fifo_din;
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wire dma_rst;
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wire dma_enable;
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wire ctrl_fifo_rst;
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reg ctrl_fifo_rden;
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wire [71:0] ctrl_fifo_dout;
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wire ctrl_fifo_full;
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wire ctrl_fifo_empty;
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wire [9:0] ctrl_fifo_count;
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wire stat_fifo_rst;
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reg stat_fifo_wren;
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reg [71:0] stat_fifo_din;
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reg stat_fifo_rden;
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wire [71:0] stat_fifo_dout;
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wire stat_fifo_full;
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wire stat_fifo_empty;
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wire [9:0] stat_fifo_count;
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reg [1:0] state;
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reg [71:0] active_buf;
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reg [22:0] remaining_len;
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reg [22:0] bytes_written;
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wire s_axis_s2mm_cmd_tvalid;
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wire s_axis_s2mm_cmd_tready;
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reg [79:0] s_axis_s2mm_cmd_tdata;
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wire m_axis_s2mm_sts_tvalid;
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wire m_axis_s2mm_sts_tready;
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wire [7:0] m_axis_s2mm_sts_tdata;
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// ready while data hasn't been latched and still waiting
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// for acknowledgement to our response
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assign axi.awready = !awaddr_valid && !axi.bvalid && axi.resetn;
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assign axi.wready = !wdata_valid && !axi.bvalid && axi.resetn;
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always @( posedge axi.clk )
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begin
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if ( axi.resetn == 1'b0 ) begin
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awaddr_valid <= 1'b0;
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awaddr <= 'b0;
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wdata_valid <= 1'b0;
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wstrb <= 'b0;
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wdata <= 'b0;
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axi.bvalid <= 1'b0;
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axi.bresp <= 2'b0;
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end
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else begin
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// latch awaddr and valid signal
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if (axi.awready && axi.awvalid) begin
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awaddr_valid <= 1'b1;
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awaddr <= axi.awaddr;
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end
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// latch wirte data and valid signal
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if (axi.wready && axi.wvalid) begin
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wdata_valid <= 1'b1;
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wstrb <= axi.wstrb;
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wdata <= axi.wdata;
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end
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// clear valids when both high;
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// data needs to be consumed on this same condition
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if (awaddr_valid && wdata_valid && !axi.bvalid) begin
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awaddr_valid <= 1'b0;
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wdata_valid <= 1'b0;
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axi.bvalid <= 1'b1;
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axi.bresp <= 2'b0; // 'OKAY' response
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end
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// clear bvalid when it has been acknowledged
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if (axi.bvalid && axi.bready) begin
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axi.bvalid <= 1'b0;
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end
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end
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end
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// ready while data hasn't been latched and still waiting
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// for acknowledgement to our response
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assign axi.arready = !araddr_valid && !axi.rvalid && axi.resetn;
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always @( posedge axi.clk )
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begin
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if ( axi.resetn == 1'b0 ) begin
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araddr_valid <= 1'b0;
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araddr <= 'b0;
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axi.rvalid <= 1'b0;
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axi.rresp <= 2'b0;
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axi.rdata <= 'b0;
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end
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else begin
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// latch araddr and valid signal
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if (axi.arready && axi.arvalid) begin
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araddr_valid <= 1'b1;
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araddr <= axi.araddr;
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end
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// if address is valid and rdata has been latched;
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// set axi bus rdata and valid signal
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if (araddr_valid && rvalid && !axi.rvalid) begin
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araddr_valid <= 1'b0;
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axi.rvalid <= 1'b1;
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axi.rresp <= 2'b0; // 'OKAY' response
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axi.rdata <= rdata;
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end
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// clear rvalid when it has been acknowledged
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if (axi.rvalid && axi.rready) begin
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axi.rvalid <= 1'b0;
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end
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end
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end
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always @( posedge axi.clk )
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begin
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if ( axi.resetn == 1'b0 ) begin
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ctrl_reg[0] <= 'b111;
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ctrl_reg[1] <= 'b0;
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ctrl_reg[2] <= 'b0;
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ctrl_reg[3] <= 'b0;
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ctrl_fifo_wren <= 'b0;
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ctrl_fifo_din <= 'b0;
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stat_fifo_rden <= 1'b0;
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rvalid <= 1'b0;
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rdata <= 'b0;
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end
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else begin
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ctrl_fifo_wren <= 'b0;
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// everything is valid; latch data to the correct location
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if (awaddr_valid && wdata_valid) begin
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for ( byte_index = 0; byte_index <= (axi.AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) begin
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if ( wstrb[byte_index] == 1 ) begin
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if ( awaddr[7:0] == 'h00 )
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ctrl_reg[0][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
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if ( awaddr[7:0] == 'h04 )
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ctrl_reg[1][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
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if ( awaddr[7:0] == 'h08 )
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ctrl_reg[2][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
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if ( awaddr[7:0] == 'h0C )
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ctrl_reg[3][(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
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if ( awaddr[7:0] == 'h20 )
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ctrl_fifo_din[(byte_index*8) +: 8] <= wdata[(byte_index*8) +: 8];
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if ( awaddr[7:0] == 'h24 )
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ctrl_fifo_din[(byte_index*8)+32 +: 8] <= wdata[(byte_index*8) +: 8];
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if ( awaddr[7:0] == 'h28 ) begin
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ctrl_fifo_din[(byte_index*8)+64 +: 8] <= wdata[(byte_index*8) +: 8];
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if (byte_index == 0) ctrl_fifo_wren <= 1'b1;
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end
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end
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end
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end
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stat_fifo_rden <= 1'b0;
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// by default rvalid is low; unless read address is valid;
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// latch appropriate data and set valid signal
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rvalid <= 1'b0;
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if (araddr_valid && !rvalid) begin
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if ( araddr[7:0] == 'h0 )
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rdata <= ctrl_reg[0];
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if ( araddr[7:0] == 'h4 )
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rdata <= ctrl_reg[1];
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if ( araddr[7:0] == 'h8 )
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rdata <= ctrl_reg[2];
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if ( araddr[7:0] == 'hC )
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rdata <= ctrl_reg[3];
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if ( araddr[7:0] == 'h10 )
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rdata <= status_reg[0];
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if ( araddr[7:0] == 'h14 )
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rdata <= status_reg[1];
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if ( araddr[7:0] == 'h18 )
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rdata <= status_reg[2];
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if ( araddr[7:0] == 'h1C )
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rdata <= status_reg[3];
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if ( araddr[7:0] == 'h20 )
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rdata <= stat_fifo_dout[31:0];
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if ( araddr[7:0] == 'h24 ) begin
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rdata <= stat_fifo_dout[63:32];
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end
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if ( araddr[7:0] == 'h28 ) begin
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rdata <= {24'b0, stat_fifo_dout[71:64]};
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stat_fifo_rden <= 1'b1;
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end
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if ( araddr[7:0] == 'h2C) begin
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rdata <= status_reg[4];
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end
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rvalid <= 1'b1;
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end
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end
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end
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assign ctrl_fifo_rst = ctrl_reg[0][0];
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assign stat_fifo_rst = ctrl_reg[0][1];
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assign dma_rst = ctrl_reg[0][2];
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assign dma_enable = ctrl_reg[0][8];
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assign status_reg[0] = {30'h00, state};
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assign status_reg[1] = {16'h00, 8'd23, 8'd9};
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assign status_reg[2] = {6'b0, ctrl_fifo_count, 15'b0, ctrl_fifo_full};
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assign status_reg[3] = {6'b0, stat_fifo_count, 15'b0, stat_fifo_empty};
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assign status_reg[4] = 32'hBEEF_BEEF;
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// State Machines
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parameter DMA_IDLE = 0;
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parameter DMA_START = 1;
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parameter DMA_ACTIVE = 2;
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parameter DMA_COMP = 3;
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axi4s_intf # (
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.AXI_DATA_WIDTH(axis.AXI_DATA_WIDTH)
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)
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axis_gated(
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.clk(axis.clk)
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);
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always @( posedge axi.clk )
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begin
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ctrl_fifo_rden <= 1'b0;
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stat_fifo_wren <= 1'b0;
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if ( dma_rst == 1'b1 ) begin
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state <= DMA_IDLE;
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end
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else begin
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case (state)
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DMA_IDLE: begin
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s_axis_s2mm_cmd_tdata <= 'b0;
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s_axis_s2mm_cmd_tdata[71:32] <= ctrl_fifo_dout[71:32];
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s_axis_s2mm_cmd_tdata[30] <= 1'b1;
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s_axis_s2mm_cmd_tdata[23] <= 1'b1;
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s_axis_s2mm_cmd_tdata[22:0] <= ctrl_fifo_dout[31:9];
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active_buf <= ctrl_fifo_dout;
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remaining_len <= ctrl_fifo_dout[31:9];
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bytes_written <= 'b0;
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if ((ctrl_fifo_empty == 1'b0) && ( dma_enable == 1'b1 )) begin
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ctrl_fifo_rden <= 1'b1;
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state <= DMA_START;
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end
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end
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DMA_START : begin
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if (s_axis_s2mm_cmd_tready == 1'b1) begin
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state <= DMA_ACTIVE;
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end
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end
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DMA_ACTIVE : begin
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if ((axis_gated.tready == 1'b1) && (axis_gated.tvalid == 1'b1)) begin
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if ( dma_enable == 1'b1 ) begin
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remaining_len <= remaining_len - (axis.AXI_DATA_WIDTH/8);
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bytes_written <= bytes_written + (axis.AXI_DATA_WIDTH/8);
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if (remaining_len == (axis.AXI_DATA_WIDTH/8)) begin
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state <= DMA_COMP;
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end
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end
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else begin
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state <= DMA_COMP;
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end
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end
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end
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DMA_COMP: begin
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if (m_axis_s2mm_sts_tvalid == 1'b1) begin //TODO: this is a bug
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stat_fifo_wren <= 1'b1;
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stat_fifo_din <= active_buf;
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stat_fifo_din[31:9] <= bytes_written;
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state <= DMA_IDLE;
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end
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end
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default : begin
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state <= DMA_IDLE;
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end
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endcase
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end
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end
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assign s_axis_s2mm_cmd_tvalid = (state == DMA_START) ? 1'b1 : 1'b0;
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assign axis_gated.tdata = axis.tdata;
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assign axis_gated.tkeep = axis.tkeep;
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assign axis_gated.tlast = ((remaining_len == (axis.AXI_DATA_WIDTH/8)) || ( dma_enable == 1'b0 )) ? 1'b1 : 1'b0;
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assign axis_gated.tvalid = (state == DMA_ACTIVE) ? (( dma_enable == 1'b0 ) ? 1'b1 : axis.tvalid) : 1'b0;
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assign axis.tready = (state == DMA_ACTIVE) ? axis_gated.tready : (( dma_enable == 1'b0 ) ? 1'b1 : 1'b0);
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// This can be removed and changed back to just 1'b0;
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assign m_axis_s2mm_sts_tready = (state == DMA_COMP) ? 1'b1 : 1'b0;
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// basic idea behind datamover control;
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// control fifo allows dma driver to allocate PS DDR buffer and load the physical address
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// into the fifo; once the transfer is complete the result fifo will be loaded with completion result
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// that will also contain the physical DDR buffer address
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dma_ctrl_status_fifo_0 ctrl_fifo_i (
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.clk( axi.clk ), // : IN STD_LOGIC;
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.srst( ctrl_fifo_rst ), // : IN STD_LOGIC;
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.din( ctrl_fifo_din[71:0] ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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.wr_en( ctrl_fifo_wren ), // : IN STD_LOGIC;
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.rd_en( ctrl_fifo_rden ), // : IN STD_LOGIC;
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.dout( ctrl_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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.full( ctrl_fifo_full ), // : OUT STD_LOGIC;
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.empty( ctrl_fifo_empty ), // : OUT STD_LOGIC;
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.data_count( ctrl_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
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.wr_rst_busy( ),
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.rd_rst_busy( )
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);
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dma_ctrl_status_fifo_0 stat_fifo_i (
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.clk( axi.clk ), // : IN STD_LOGIC;
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.srst( stat_fifo_rst ), // : IN STD_LOGIC;
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.din( stat_fifo_din ), // : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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.wr_en( stat_fifo_wren ), // : IN STD_LOGIC;
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.rd_en( stat_fifo_rden ), // : IN STD_LOGIC;
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.dout( stat_fifo_dout ), // : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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.full( stat_fifo_full ), // : OUT STD_LOGIC;
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.empty( stat_fifo_empty ), // : OUT STD_LOGIC;
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.data_count( stat_fifo_count ), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
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.wr_rst_busy( ),
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.rd_rst_busy( )
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);
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// Do a soft shutdown of the datamover on a reset request. This should ensure the AXI bus does not get hung mid burst
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// and allow the datamover to be instantiated without using store-forward. This will save blockrams, and is OK because we already
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// have buffering in the receive path
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logic s2mm_err;
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logic s2mm_halt;
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logic s2mm_halt_cmplt;
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logic datamover_rst;
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logic dma_rst_q;
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logic dma_rst_q2;
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logic dma_rst_red;
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always @ (posedge axim.clk) begin
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dma_rst_q <= dma_rst;
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dma_rst_q2 <= dma_rst_q;
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dma_rst_red <= dma_rst_q & ~dma_rst_q;
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s2mm_halt <= dma_rst;
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// Clear the datamover reset when the dma reset clears
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if (dma_rst == 1'b0) begin
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datamover_rst <= 1'b0;
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// s2mm_halt <= 1'b0;
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end
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// else if (dma_rst_red == 1'b1) begin
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// // Trigger soft shutdown when the dma reset signal goes high
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// s2mm_halt <= 1;
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// end
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else if (s2mm_halt_cmplt == 1'b1) begin
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// Wait for halt complete to trigger datamover reset
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datamover_rst <= 1'b1;
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end
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end
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axi_datamover_256_0 axi_datamover_0_i (
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.m_axi_s2mm_aclk( axim.clk ), //
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// .m_axi_s2mm_aresetn( ~dma_rst ), // : IN STD_LOGIC;
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||||
.m_axi_s2mm_aresetn( ~datamover_rst ), // : IN STD_LOGIC;
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.s2mm_halt(s2mm_halt), // input wire s2mm_halt
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.s2mm_halt_cmplt(s2mm_halt_cmplt), // output wire s2mm_halt_cmplt
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|
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.s2mm_allow_addr_req(1'b1), // input wire s2mm_allow_addr_req
|
||||
.s2mm_addr_req_posted(), // output wire s2mm_addr_req_posted
|
||||
.s2mm_wr_xfer_cmplt(), // output wire s2mm_wr_xfer_cmplt
|
||||
.s2mm_ld_nxt_len(), // output wire s2mm_ld_nxt_len
|
||||
.s2mm_wr_len(), // output wire [7 : 0] s2mm_wr_len
|
||||
|
||||
.s2mm_err(s2mm_err), // : OUT STD_LOGIC;
|
||||
|
||||
.m_axis_s2mm_cmdsts_awclk( axi.clk ), // : IN STD_LOGIC;
|
||||
.m_axis_s2mm_cmdsts_aresetn( ~dma_rst ), // : IN STD_LOGIC;
|
||||
.s_axis_s2mm_cmd_tvalid( s_axis_s2mm_cmd_tvalid ), // : IN STD_LOGIC;
|
||||
.s_axis_s2mm_cmd_tready( s_axis_s2mm_cmd_tready ), // : OUT STD_LOGIC;
|
||||
.s_axis_s2mm_cmd_tdata( s_axis_s2mm_cmd_tdata), // : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
|
||||
.m_axis_s2mm_sts_tvalid( m_axis_s2mm_sts_tvalid ), // : OUT STD_LOGIC;
|
||||
.m_axis_s2mm_sts_tready( m_axis_s2mm_sts_tready), // : IN STD_LOGIC;
|
||||
.m_axis_s2mm_sts_tdata( m_axis_s2mm_sts_tdata ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
.m_axis_s2mm_sts_tkeep( ), // : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
.m_axis_s2mm_sts_tlast( ), // : OUT STD_LOGIC;
|
||||
|
||||
.m_axi_s2mm_awaddr( axim.awaddr ), // : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
.m_axi_s2mm_awlen( axim.awlen ), // : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
.m_axi_s2mm_awsize( axim.awsize ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
.m_axi_s2mm_awburst( axim.awburst ), // : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
.m_axi_s2mm_awprot( axim.awprot ), // : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
.m_axi_s2mm_awcache( axim.awcache ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
.m_axi_s2mm_awuser( ), // : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
.m_axi_s2mm_awvalid( axim.awvalid ), // : OUT STD_LOGIC;
|
||||
.m_axi_s2mm_awready( axim.awready ), // : IN STD_LOGIC;
|
||||
.m_axi_s2mm_wdata( axim.wdata ), // : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
.m_axi_s2mm_wstrb( axim.wstrb ), // : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
.m_axi_s2mm_wlast( axim.wlast ), // : OUT STD_LOGIC;
|
||||
.m_axi_s2mm_wvalid( axim.wvalid ), // : OUT STD_LOGIC;
|
||||
.m_axi_s2mm_wready( axim.wready ), // : IN STD_LOGIC;
|
||||
.m_axi_s2mm_bresp( axim.bresp ), // : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
.m_axi_s2mm_bvalid( axim.bvalid ), // : IN STD_LOGIC;
|
||||
.m_axi_s2mm_bready( axim.bready ), // : OUT STD_LOGIC;
|
||||
|
||||
.s_axis_s2mm_tdata( axis_gated.tdata ), // : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
.s_axis_s2mm_tkeep( axis_gated.tkeep ), // : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
.s_axis_s2mm_tlast( axis_gated.tlast ), // : IN STD_LOGIC;
|
||||
.s_axis_s2mm_tvalid( axis_gated.tvalid ), // : IN STD_LOGIC;
|
||||
.s_axis_s2mm_tready( axis_gated.tready ) // : OUT STD_LOGIC
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user