4 rx channels and 16 lane PCIe working on drex card

This commit is contained in:
2026-06-11 23:19:03 -05:00
parent b6da08b40e
commit b23f7fe4a6
51 changed files with 49090 additions and 7043 deletions

View File

@@ -8,9 +8,13 @@
#include <string>
#include <queue>
#define UTIL_REG_BASE 0x100000
#define TIMING_REG_BASE 0x110000
#define DATA_GEN_REG_BASE 0x120000
// #define UTIL_REG_BASE 0x100000
// #define TIMING_REG_BASE 0x110000
// #define DATA_GEN_REG_BASE 0x120000
#define UTIL_REG_BASE 0x10000
#define TIMING_REG_BASE 0x20000
#define DATA_GEN_REG_BASE 0x30000
#define WSRDMA_DMA_INIT 0
#define WSRDMA_DMA_CLEAR 1

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@@ -20,8 +20,8 @@ int main() {
// Setup Timing Engine and data generator to test
uint32_t n_pulses = 128;
float inter_cpi = 100e-6;
float pri = 84e-6;
uint32_t n_samples = 8192;
float pri = 70e-6;
uint32_t n_samples = 16384;
// float pri = 40e-6;
// uint32_t n_samples = 4096;