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4 rx channels and 16 lane PCIe working on drex card

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bkiedinger@gmail.com
2026-06-11 23:19:03 -05:00
parent b6da08b40e
commit b23f7fe4a6
51 changed files with 49090 additions and 7043 deletions
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195
project_1.srcs/constrs_1/constraints.xdc
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@@ -1,50 +1,181 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property PACKAGE_PIN M9 [get_ports {leds[0]}]
set_property PACKAGE_PIN K8 [get_ports {leds[1]}]
set_property PACKAGE_PIN L8 [get_ports {leds[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
#set_property PACKAGE_PIN M9 [get_ports {leds[0]}]
#set_property PACKAGE_PIN K8 [get_ports {leds[1]}]
#set_property PACKAGE_PIN L8 [get_ports {leds[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
set_property PACKAGE_PIN N8 [get_ports uart_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd]
#set_property PACKAGE_PIN N8 [get_ports uart_rxd]
#set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd]
set_property PACKAGE_PIN N9 [get_ports uart_txd]
set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
#set_property PACKAGE_PIN N9 [get_ports uart_txd]
#set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
set_property PACKAGE_PIN AJ9 [get_ports sys_clk_p]
set_property PACKAGE_PIN AK9 [get_ports sys_clk_n]
set_property PACKAGE_PIN AP19 [get_ports sys_clk_p]
set_property PACKAGE_PIN AR19 [get_ports sys_clk_n]
set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n]
create_clock -period 5.000 -name sys_clk_clk_p [get_ports sys_clk_p]
create_clock -period 10.000 -name sys_clk_clk_p [get_ports sys_clk_p]
set_property PACKAGE_PIN M8 [get_ports fan_pwm]
set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm]
#set_property PACKAGE_PIN M8 [get_ports fan_pwm]
#set_property IOSTANDARD LVCMOS33 [get_ports fan_pwm]
#-------------------------------------------
# PCIE
#-------------------------------------------
set_property PACKAGE_PIN AD8 [get_ports pcie_ref_clk_p]
set_property PACKAGE_PIN AB27 [get_ports pcie_ref_clk_p]
create_clock -period 10.000 -name pcie_ref_clk_p -waveform {0.000 5.000} [get_ports pcie_ref_clk_p]
set_property PACKAGE_PIN AP4 [get_ports {pcie_mgt_rxp[0]}]
set_property PACKAGE_PIN AN2 [get_ports {pcie_mgt_rxp[1]}]
set_property PACKAGE_PIN AL2 [get_ports {pcie_mgt_rxp[2]}]
set_property PACKAGE_PIN AK4 [get_ports {pcie_mgt_rxp[3]}]
set_property PACKAGE_PIN AJ2 [get_ports {pcie_mgt_rxp[4]}]
set_property PACKAGE_PIN AG2 [get_ports {pcie_mgt_rxp[5]}]
set_property PACKAGE_PIN AF4 [get_ports {pcie_mgt_rxp[6]}]
set_property PACKAGE_PIN AE2 [get_ports {pcie_mgt_rxp[7]}]
set_property PACKAGE_PIN AA38 [get_ports {pcie_mgt_rxp[8]}]
set_property PACKAGE_PIN AB36 [get_ports {pcie_mgt_rxp[9]}]
set_property PACKAGE_PIN AC38 [get_ports {pcie_mgt_rxp[10]}]
set_property PACKAGE_PIN AD36 [get_ports {pcie_mgt_rxp[11]}]
set_property PACKAGE_PIN AE38 [get_ports {pcie_mgt_rxp[12]}]
set_property PACKAGE_PIN AF36 [get_ports {pcie_mgt_rxp[13]}]
set_property PACKAGE_PIN AG38 [get_ports {pcie_mgt_rxp[14]}]
set_property PACKAGE_PIN AH36 [get_ports {pcie_mgt_rxp[15]}]
set_property PACKAGE_PIN AN6 [get_ports {pcie_mgt_txp[0]}]
set_property PACKAGE_PIN AM4 [get_ports {pcie_mgt_txp[1]}]
set_property PACKAGE_PIN AL6 [get_ports {pcie_mgt_txp[2]}]
set_property PACKAGE_PIN AJ6 [get_ports {pcie_mgt_txp[3]}]
set_property PACKAGE_PIN AH4 [get_ports {pcie_mgt_txp[4]}]
set_property PACKAGE_PIN AG6 [get_ports {pcie_mgt_txp[5]}]
set_property PACKAGE_PIN AE6 [get_ports {pcie_mgt_txp[6]}]
set_property PACKAGE_PIN AD4 [get_ports {pcie_mgt_txp[7]}]
set_property PACKAGE_PIN N38 [get_ports {pcie_mgt_rxp[0]}]
set_property PACKAGE_PIN L33 [get_ports {pcie_mgt_txp[0]}]
set_property PACKAGE_PIN P36 [get_ports {pcie_mgt_rxp[1]}]
set_property PACKAGE_PIN M31 [get_ports {pcie_mgt_txp[1]}]
set_property PACKAGE_PIN R38 [get_ports {pcie_mgt_rxp[2]}]
set_property PACKAGE_PIN N33 [get_ports {pcie_mgt_txp[2]}]
set_property PACKAGE_PIN T36 [get_ports {pcie_mgt_rxp[3]}]
set_property PACKAGE_PIN P31 [get_ports {pcie_mgt_txp[3]}]
set_property PACKAGE_PIN U38 [get_ports {pcie_mgt_rxp[4]}]
set_property PACKAGE_PIN R33 [get_ports {pcie_mgt_txp[4]}]
set_property PACKAGE_PIN V36 [get_ports {pcie_mgt_rxp[5]}]
set_property PACKAGE_PIN T31 [get_ports {pcie_mgt_txp[5]}]
set_property PACKAGE_PIN W38 [get_ports {pcie_mgt_rxp[6]}]
set_property PACKAGE_PIN U33 [get_ports {pcie_mgt_txp[6]}]
set_property PACKAGE_PIN Y36 [get_ports {pcie_mgt_rxp[7]}]
set_property PACKAGE_PIN V31 [get_ports {pcie_mgt_txp[7]}]
set_property PACKAGE_PIN W33 [get_ports {pcie_mgt_txp[8]}]
set_property PACKAGE_PIN AB36 [get_ports {pcie_mgt_txp[9]}]
set_property PACKAGE_PIN AA33 [get_ports {pcie_mgt_txp[10]}]
set_property PACKAGE_PIN AB31 [get_ports {pcie_mgt_txp[11]}]
set_property PACKAGE_PIN AC33 [get_ports {pcie_mgt_txp[12]}]
set_property PACKAGE_PIN AD31 [get_ports {pcie_mgt_txp[13]}]
set_property PACKAGE_PIN AE33 [get_ports {pcie_mgt_txp[14]}]
set_property PACKAGE_PIN AF31 [get_ports {pcie_mgt_txp[15]}]
set_property PACKAGE_PIN AA20 [get_ports pcie_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports pcie_rst_n]
set_property PACKAGE_PIN D13 [get_ports pcie_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports pcie_rst_n]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list design_1_i/xdma_0/inst/pcie4_ip_i/inst/design_1_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/CLK_USERCLK]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/pcie_m_axi1_bvalid[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/pcie_m_axi1_wvalid[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {design_1_i/pcie_m_axi1_awvalid[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {design_1_i/pcie_m_axi1_wready[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {design_1_i/pcie_m_axi1_bready[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {design_1_i/pcie_m_axi1_awready[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {design_1_i/pcie_m_axi0_wvalid[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {design_1_i/pcie_m_axi0_bvalid[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {design_1_i/pcie_m_axi0_wready[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {design_1_i/pcie_m_axi0_bready[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {design_1_i/pcie_m_axi0_awvalid[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {design_1_i/pcie_m_axi1_wlast[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {design_1_i/pcie_m_axi0_awready[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {design_1_i/pcie_m_axi0_wlast[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WVALID]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WREADY]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_WLAST]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_BVALID]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_BREADY]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_AWVALID]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list design_1_i/axi_interconnect_1_M00_AXI_AWREADY]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list start_of_pulse]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {pcie_dma_axis\\.tvalid}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {pcie_dma_axis\\.tready}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {pcie_dma_axis\\.tlast}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]