4 rx channels and 16 lane PCIe working on drex card
This commit is contained in:
118
project_1.xpr
118
project_1.xpr
@@ -7,7 +7,7 @@
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="5035618c223548df9c6d60447429821e"/>
|
||||
<Option Name="Part" Val="xczu7ev-ffvc1156-2-i"/>
|
||||
<Option Name="Part" Val="xcku15p-ffve1517-2-i"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
@@ -64,13 +64,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="19"/>
|
||||
<Option Name="WTModelSimExportSim" Val="19"/>
|
||||
<Option Name="WTQuestaExportSim" Val="19"/>
|
||||
<Option Name="WTXSimExportSim" Val="20"/>
|
||||
<Option Name="WTModelSimExportSim" Val="20"/>
|
||||
<Option Name="WTQuestaExportSim" Val="20"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="19"/>
|
||||
<Option Name="WTRivieraExportSim" Val="19"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="19"/>
|
||||
<Option Name="WTVcsExportSim" Val="20"/>
|
||||
<Option Name="WTRivieraExportSim" Val="20"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="20"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -159,6 +159,14 @@
|
||||
<Attr Name="IsVisible" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/axi_datamover_0_test/axi_datamover_0_test.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top"/>
|
||||
@@ -201,34 +209,6 @@
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="dma_ctrl_status_fifo_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dma_ctrl_status_fifo_0" RelGenDir="$PGENDIR/dma_ctrl_status_fifo_0">
|
||||
<File Path="$PSRCDIR/sources_1/ip/dma_ctrl_status_fifo_0/dma_ctrl_status_fifo_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="dma_ctrl_status_fifo_0"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_datamover_256_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_datamover_256_0" RelGenDir="$PGENDIR/axi_datamover_256_0">
|
||||
<File Path="$PSRCDIR/sources_1/ip/axi_datamover_256_0/axi_datamover_256_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_datamover_256_0"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1" RelGenDir="$PGENDIR/design_1">
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
@@ -257,17 +237,30 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_datamover_0_test" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_datamover_0_test" RelGenDir="$PGENDIR/axi_datamover_0_test">
|
||||
<File Path="$PSRCDIR/sources_1/ip/axi_datamover_0_test/axi_datamover_0_test.xci">
|
||||
<FileSet Name="dma_ctrl_status_fifo_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dma_ctrl_status_fifo_0" RelGenDir="$PGENDIR/dma_ctrl_status_fifo_0">
|
||||
<File Path="$PSRCDIR/sources_1/ip/dma_ctrl_status_fifo_0/dma_ctrl_status_fifo_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_datamover_0_test"/>
|
||||
<Option Name="TopModule" Val="dma_ctrl_status_fifo_0"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_datamover_256_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_datamover_256_0" RelGenDir="$PGENDIR/axi_datamover_256_0">
|
||||
<File Path="$PSRCDIR/sources_1/ip/axi_datamover_256_0/axi_datamover_256_0.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_datamover_256_0"/>
|
||||
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
@@ -295,7 +288,7 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="19">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku15p-ffve1517-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -305,7 +298,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="dma_ctrl_status_fifo_0_synth_1" Type="Ft3:Synth" SrcSet="dma_ctrl_status_fifo_0" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1">
|
||||
<Run Id="design_1_synth_1" Type="Ft3:Synth" SrcSet="design_1" Part="xcku15p-ffve1517-2-i" ConstrsSet="design_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -315,7 +308,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_datamover_256_0_synth_1" Type="Ft3:Synth" SrcSet="axi_datamover_256_0" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_256_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_datamover_256_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1">
|
||||
<Run Id="ch_data_buffer_synth_1" Type="Ft3:Synth" SrcSet="ch_data_buffer" Part="xcku15p-ffve1517-2-i" ConstrsSet="ch_data_buffer" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ch_data_buffer_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -325,7 +318,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_synth_1" Type="Ft3:Synth" SrcSet="design_1" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="design_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_synth_1">
|
||||
<Run Id="dma_ctrl_status_fifo_0_synth_1" Type="Ft3:Synth" SrcSet="dma_ctrl_status_fifo_0" Part="xcku15p-ffve1517-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -335,7 +328,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ch_data_buffer_synth_1" Type="Ft3:Synth" SrcSet="ch_data_buffer" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="ch_data_buffer" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ch_data_buffer_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_synth_1">
|
||||
<Run Id="axi_datamover_256_0_synth_1" Type="Ft3:Synth" SrcSet="axi_datamover_256_0" Part="xcku15p-ffve1517-2-i" ConstrsSet="axi_datamover_256_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_datamover_256_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -345,17 +338,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_datamover_0_test_synth_1" Type="Ft3:Synth" SrcSet="axi_datamover_0_test" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_0_test" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_datamover_0_test_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -373,7 +356,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="dma_ctrl_status_fifo_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1">
|
||||
<Run Id="design_1_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="design_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -390,7 +373,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_datamover_256_0_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_256_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_datamover_256_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1">
|
||||
<Run Id="ch_data_buffer_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="ch_data_buffer" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ch_data_buffer_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -407,7 +390,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="design_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_impl_1">
|
||||
<Run Id="dma_ctrl_status_fifo_0_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="dma_ctrl_status_fifo_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dma_ctrl_status_fifo_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dma_ctrl_status_fifo_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -424,24 +407,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="ch_data_buffer_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="ch_data_buffer" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ch_data_buffer_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ch_data_buffer_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_datamover_0_test_impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-i" ConstrsSet="axi_datamover_0_test" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_datamover_0_test_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_0_test_impl_1">
|
||||
<Run Id="axi_datamover_256_0_impl_1" Type="Ft2:EntireDesign" Part="xcku15p-ffve1517-2-i" ConstrsSet="axi_datamover_256_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_datamover_256_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_datamover_256_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||||
<Step Id="init_design"/>
|
||||
|
||||
Reference in New Issue
Block a user