bkiedinger/pcie_data_recorder
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bkiedinger 24aa6fb407 first commit
2026-05-25 22:36:52 -05:00
cpp
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2026-05-25 22:36:52 -05:00
top.xsa
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2026-05-25 22:36:52 -05:00
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15 MiB
Languages
VHDL 90.6%
Verilog 8.9%
SystemVerilog 0.4%