bkiedinger/pcie_data_recorder
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bkiedinger ffd3eab72d added file
2026-06-19 07:14:59 -05:00
cpp
added file
2026-06-19 07:14:59 -05:00
project_1.srcs
4 rx channels and 16 lane PCIe working on drex card
2026-06-11 23:19:03 -05:00
project_1.xpr
4 rx channels and 16 lane PCIe working on drex card
2026-06-11 23:19:03 -05:00
top.xsa
first commit
2026-05-25 22:36:52 -05:00
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15 MiB
Languages
VHDL 90.6%
Verilog 8.9%
SystemVerilog 0.4%