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bkiedinger@gmail.com
2025-09-28 08:55:19 -05:00
parent 498c02cf18
commit 086c5dd9f3
8 changed files with 920 additions and 9 deletions
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36
python/waveform_generator/hdl_sim_check_results.py Normal file
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from matplotlib import pyplot as plt
from ctypes import *
import numpy as np
def read_sim_output(filename, is_float=False):
fid = open(filename, "r")
lines = fid.readlines()
fid.close()
data = [int(line) for line in lines]
data = np.array(data)
if is_float:
as_floats = c_float * data.size
data = as_floats.from_buffer(data.astype(np.int32))
data = np.array(data)
return data
def main():
data = read_sim_output("sim_out.bin")
data[data >= 2**15] -= 2**16
data = data[0::2] + 1j * data[1::2]
plt.figure()
plt.plot(data.real)
plt.plot(data.imag)
plt.title('Sim Output')
plt.grid()
plt.show()
if __name__ == '__main__':
main()

14
python/waveform_generator/hdl_sim_config.py Normal file
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def main():
fs = 750e6
f = 10e6
n = 4096
freq = f/fs * 2**31
print(freq)
if __name__ == '__main__':
main()

159
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_ofdm.sv Normal file
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`resetall
`timescale 1ns / 1ps
`default_nettype none
module gen_ofdm # (
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 32
)
(
input wire clk,
input wire reset,
axi4l_intf.slave ctrl_if,
input wire start_pulse,
output wire [127:0] iq_out,
output wire iq_out_valid
);
// ------------------------------
// AXIL Decode
// ------------------------------
wire [AXI_ADDR_WIDTH-1 : 0] raddr;
wire [AXI_ADDR_WIDTH-1 : 0] waddr;
wire rden;
wire wren;
wire [AXI_DATA_WIDTH-1 : 0] wdata;
reg [AXI_DATA_WIDTH-1 : 0] rdata;
axil_slave
# (
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH)
) axil_slave_i
(
// AXIL Slave
.S_AXI_ACLK(ctrl_if.clk),
.S_AXI_ARESETN(ctrl_if.resetn),
.S_AXI_AWADDR(ctrl_if.awaddr),
.S_AXI_AWPROT(ctrl_if.awprot),
.S_AXI_AWVALID(ctrl_if.awvalid),
.S_AXI_AWREADY(ctrl_if.awready),
.S_AXI_WDATA(ctrl_if.wdata),
.S_AXI_WSTRB(ctrl_if.wstrb),
.S_AXI_WVALID(ctrl_if.wvalid),
.S_AXI_WREADY(ctrl_if.wready),
.S_AXI_BRESP(ctrl_if.bresp),
.S_AXI_BVALID(ctrl_if.bvalid),
.S_AXI_BREADY(ctrl_if.bready),
.S_AXI_ARADDR(ctrl_if.araddr),
.S_AXI_ARPROT(ctrl_if.arprot),
.S_AXI_ARVALID(ctrl_if.arvalid),
.S_AXI_ARREADY(ctrl_if.arready),
.S_AXI_RDATA(ctrl_if.rdata),
.S_AXI_RRESP(ctrl_if.rresp),
.S_AXI_RVALID(ctrl_if.rvalid),
.S_AXI_RREADY(ctrl_if.rready),
.raddr(raddr),
.waddr(waddr),
.wren(wren),
.rden(rden),
.wdata(wdata),
.rdata(rdata)
);
// ------------------------------
// Config Registers
// ------------------------------
reg [31:0] reg_ctrl;
reg [31:0] reg_freq;
reg [31:0] reg_phase;
reg [31:0] reg_chips;
always @ (posedge ctrl_if.clk) begin
if (~ctrl_if.resetn) begin
reg_ctrl <= 0;
reg_freq <= 0;
reg_phase <= 0;
end else begin
if (wren) begin
if (waddr[11:0] == 'h000) begin
reg_ctrl <= wdata;
end
if (waddr[11:0] == 'h004) begin
reg_freq <= wdata;
end
if (waddr[11:0] == 'h008) begin
reg_phase <= wdata;
end
if (waddr[11:0] == 'h00C) begin
reg_chips <= wdata;
end
// if (waddr[11:0] == 'h010) begin
// reg_phase <= wdata;
// end
end
end
end
wire [15:0] n_samp_chip = reg_chips[15:0];
wire [15:0] n_chip = reg_chips[31:16];
// ------------------------------
// Bla
// ------------------------------
reg [24:0] pulse_cnt;
reg [15:0] chip_cnt;
reg [15:0] chip_ind;
reg pulse_active;
reg start_of_pulse;
always @ (posedge clk) begin
if (reset) begin
chip_cnt <= 0;
chip_ind <= 0;
pulse_active <= 1'b0;
start_of_pulse <= 1'b0;
end else begin
start_of_pulse <= 1'b0;
if (start_pulse) begin
chip_cnt <= 0;
chip_ind <= 0;
pulse_active <= 1'b1;
start_of_pulse <= 1'b1;
end
if (pulse_active) begin
chip_cnt <= chip_cnt + 1;
if (chip_cnt == n_samp_chip - 1) begin
chip_cnt <= 0;
chip_ind <= chip_ind + 1;
if (chip_ind == n_chip - 1) begin
chip_ind <= 0;
pulse_active = 1'b0;
end
end
end
end
end
gen_sine gen_sine_i (
.clk(clk),
.reset(reset),
.set_phase(start_of_pulse),
.valid(pulse_active),
.phase(reg_phase),
.frequency(reg_freq),
.iq_out(iq_out),
.iq_out_valid(iq_out_valid)
);
endmodule
`resetall

72
radar_alinx_kintex.srcs/sources_1/hdl/wfg_ofdm/gen_sine.sv Normal file
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`resetall
`timescale 1ns / 1ps
`default_nettype none
// Generates 4 output samples in parallel
// Samples are 16 bit I and 16 bit Q, 32 bits per sample
module gen_sine
(
input wire clk,
input wire reset,
input wire set_phase,
input wire valid,
input wire [31:0] phase,
input wire [31:0] frequency,
output wire [127:0] iq_out,
output wire iq_out_valid
);
reg set_phase_q;
reg valid_q;
reg valid_q2;
reg [31:0] phase_q;
reg [31:0] frequency_q;
reg [127:0] iq_out_i;
always @ (posedge clk) begin
set_phase_q <= set_phase;
phase_q <= phase;
frequency_q <= frequency;
valid_q <= valid;
valid_q2 <= valid_q;
end
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin
reg [31:0] phase_accum;
always @ (posedge clk) begin
if (reset) begin
phase_accum <= 0;
end else if (valid_q) begin
if (set_phase_q) begin
phase_accum <= phase_q + i*frequency_q;
end else begin
phase_accum <= phase_accum + 4*frequency_q;
end
end
end
wire [39:0] cordic_phase_in = {{8{phase_accum[31]}}, phase_accum};
wfg_cordic wfg_cordic_i (
.aclk(clk),
.s_axis_phase_tvalid(valid_q2),
.s_axis_phase_tdata(cordic_phase_in),
.m_axis_dout_tvalid(iq_out_valid),
.m_axis_dout_tdata(iq_out_i[i*32+31:i*32])
);
end
endgenerate
assign iq_out = iq_out_i;
endmodule
`resetall

215
radar_alinx_kintex.srcs/sources_1/ip/axi_vip_0/axi_vip_0.xci Normal file
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axi_vip_0",
"component_reference": "xilinx.com:ip:axi_vip:1.1",
"ip_revision": "13",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/axi_vip_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "axi_vip_0", "resolve_type": "user", "usage": "all" } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
"INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"AWUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ARUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"WUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"BUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"SUPPORTS_NARROW": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_SIZE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_LOCK": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_CACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_REGION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_QOS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_PROT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_WSTRB": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_BRESP": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RRESP": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"VIP_PKG_NAME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_INTERFACE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_WID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_RID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SUPPORTS_NARROW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_LOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_CACHE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_REGION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_QOS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "13" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/axi_vip_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in", "driver_value": "0" } ],
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
"m_axi_awvalid": [ { "direction": "out" } ],
"m_axi_awready": [ { "direction": "in", "driver_value": "0" } ],
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
"m_axi_wvalid": [ { "direction": "out" } ],
"m_axi_wready": [ { "direction": "in", "driver_value": "0" } ],
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0" } ],
"m_axi_bready": [ { "direction": "out" } ],
"m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
"m_axi_arvalid": [ { "direction": "out" } ],
"m_axi_arready": [ { "direction": "in", "driver_value": "0" } ],
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0" } ],
"m_axi_rready": [ { "direction": "out" } ]
},
"interfaces": {
"M_AXI": {
"vlnv": "xilinx.com:interface:aximm:1.0",
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "master",
"address_space_ref": "Master_AXI",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
"BREADY": [ { "physical_name": "m_axi_bready" } ],
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
"RREADY": [ { "physical_name": "m_axi_rready" } ],
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
"WREADY": [ { "physical_name": "m_axi_wready" } ],
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
"WVALID": [ { "physical_name": "m_axi_wvalid" } ]
}
},
"RESET": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLOCK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXI", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
},
"address_spaces": {
"Master_AXI": {
"range": "4294967296",
"width": "32"
}
}
}
}
}

190
radar_alinx_kintex.srcs/sources_1/ip/wfg_cordic/wfg_cordic.xci Normal file
View File

@@ -0,0 +1,190 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "wfg_cordic",
"component_reference": "xilinx.com:ip:cordic:6.0",
"ip_revision": "18",
"gen_directory": "../../../../radar_alinx_kintex.gen/sources_1/ip/wfg_cordic",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "wfg_cordic", "resolve_type": "user", "usage": "all" } ],
"Functional_Selection": [ { "value": "Sin_and_Cos", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Architectural_Configuration": [ { "value": "Parallel", "resolve_type": "user", "usage": "all" } ],
"Pipelining_Mode": [ { "value": "Maximum", "resolve_type": "user", "usage": "all" } ],
"Data_Format": [ { "value": "SignedFraction", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Phase_Format": [ { "value": "Scaled_Radians", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Input_Width": [ { "value": "34", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Round_Mode": [ { "value": "Round_Pos_Inf", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Iterations": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Precision": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Coarse_Rotation": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Compensation_Scaling": [ { "value": "No_Scale_Compensation", "resolve_type": "user", "usage": "all" } ],
"cartesian_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"cartesian_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"cartesian_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"phase_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"phase_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"phase_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"flow_control": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
"optimize_goal": [ { "value": "Performance", "resolve_type": "user", "usage": "all" } ],
"out_tready": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"out_tlast_behv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
},
"model_parameters": {
"C_ARCHITECTURE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CORDIC_FUNCTION": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COARSE_ROTATE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_FORMAT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_XDEVICEFAMILY": [ { "value": "kintexu", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ACLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_CARTESIAN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_PHASE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INPUT_WIDTH": [ { "value": "34", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ITERATIONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_FORMAT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINE_MODE": [ { "value": "-2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRECISION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ROUND_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SCALE_COMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_PHASE_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_PHASE_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_PHASE_TDATA_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_CARTESIAN_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_AXIS_CARTESIAN_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_CARTESIAN_TDATA_WIDTH": [ { "value": "80", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_CARTESIAN_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexu" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku040" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "18" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../radar_alinx_kintex.gen/sources_1/ip/wfg_cordic" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_phase_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_phase_tdata": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0" } ],
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"aclk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "1000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"aresetn_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"aclken_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
}
},
"S_AXIS_PHASE": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "5", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
}
},
"M_AXIS_DOUT": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
}
}
}
}
}
}

119
radar_alinx_kintex.srcs/sources_1/sim/tb_gen_ofdm.sv Normal file
View File

@@ -0,0 +1,119 @@
`timescale 1ns / 1ps
import axi_vip_pkg::*;
import axi_vip_0_pkg::*;
module testbench();
reg clk;
reg reset;
reg resetn;
assign resetn = ~reset;
localparam T = 4;
always #(T/2) clk=~clk;
axi4l_intf # (
.AXI_ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32)
)
ctrl_if (
.clk(clk),
.resetn(resetn)
);
axi_vip_0_mst_t vip_mst;
xil_axi_resp_t resp;
axi_vip_0 axi_vip_inst (
.aclk(clk),
.aresetn(resetn),
.m_axi_awaddr( ctrl_if.awaddr ),
.m_axi_awprot( ctrl_if.awprot ),
.m_axi_awvalid( ctrl_if.awvalid ),
.m_axi_awready( ctrl_if.awready ),
.m_axi_wdata( ctrl_if.wdata ),
.m_axi_wstrb( ctrl_if.wstrb ),
.m_axi_wvalid( ctrl_if.wvalid ),
.m_axi_wready( ctrl_if.wready ),
.m_axi_bresp( ctrl_if.bresp ),
.m_axi_bvalid( ctrl_if.bvalid ),
.m_axi_bready( ctrl_if.bready ),
.m_axi_araddr( ctrl_if.araddr ),
.m_axi_arprot( ctrl_if.arprot ),
.m_axi_arvalid( ctrl_if.arvalid ),
.m_axi_arready( ctrl_if.arready ),
.m_axi_rdata( ctrl_if.rdata ),
.m_axi_rresp( ctrl_if.rresp ),
.m_axi_rvalid( ctrl_if.rvalid ),
.m_axi_rready( ctrl_if.rready )
);
initial begin
vip_mst = new("vip_mst", axi_vip_inst.inst.IF);
vip_mst.start_master();
end
wire [127:0] iq_out;
wire iq_out_valid;
reg start_pulse;
gen_ofdm dut (
.clk(clk),
.reset(reset),
.ctrl_if(ctrl_if),
.start_pulse(start_pulse),
.iq_out(iq_out),
.iq_out_valid(iq_out_valid)
);
int fid_out;
initial begin
reset = 1'b1;
clk = 1'b0;
start_pulse = 1'b0;
$display($time, " << Starting the Simulation >>");
// Open Output File
fid_out = $fopen("/home/bkiedinger/projects/castelion/radar_alinx_kintex/python/waveform_generator/sim_out.bin", "wb");
// Release Reset
repeat(25) @(posedge clk);
reset = 1'b0;
repeat(25) @(posedge clk);
// Set Control Regs
vip_mst.AXI4LITE_WRITE_BURST(16'h0000, 0, 0, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h0004, 0, 28633115, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h0008, 0, 0, resp);
vip_mst.AXI4LITE_WRITE_BURST(16'h000C, 0, ('h00010400), resp);
repeat(25) @(posedge clk);
start_pulse = 1'b1;
@(posedge clk);
start_pulse = 1'b0;
end
always @ (posedge clk) begin
if ( iq_out_valid == 1'b1 ) begin
$fwrite(fid_out, "%d\n", iq_out[15:0] );
$fwrite(fid_out, "%d\n", iq_out[31:16]);
$fwrite(fid_out, "%d\n", iq_out[47:32]);
$fwrite(fid_out, "%d\n", iq_out[63:48]);
$fwrite(fid_out, "%d\n", iq_out[79:64]);
$fwrite(fid_out, "%d\n", iq_out[95:80]);
$fwrite(fid_out, "%d\n", iq_out[111:96]);
$fwrite(fid_out, "%d\n", iq_out[127:112]);
end
end
endmodule
`resetall

124
radar_alinx_kintex.xpr
View File

@@ -56,20 +56,20 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTXSimLaunchSim" Val="34"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="50"/>
<Option Name="WTModelSimExportSim" Val="50"/>
<Option Name="WTQuestaExportSim" Val="50"/>
<Option Name="WTXSimExportSim" Val="53"/>
<Option Name="WTModelSimExportSim" Val="53"/>
<Option Name="WTQuestaExportSim" Val="53"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="50"/>
<Option Name="WTRivieraExportSim" Val="50"/>
<Option Name="WTActivehdlExportSim" Val="50"/>
<Option Name="WTVcsExportSim" Val="53"/>
<Option Name="WTRivieraExportSim" Val="53"/>
<Option Name="WTActivehdlExportSim" Val="53"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -517,6 +517,22 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_sine.sv">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/hdl/wfg_ofdm/gen_ofdm.sv">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
@@ -539,11 +555,17 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/sim/tb_gen_ofdm.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
<Option Name="TopModule" Val="testbench"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
@@ -760,6 +782,36 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="wfg_cordic" Type="BlockSrcs" RelSrcDir="$PSRCDIR/wfg_cordic" RelGenDir="$PGENDIR/wfg_cordic">
<File Path="$PSRCDIR/sources_1/ip/wfg_cordic/wfg_cordic.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="wfg_cordic"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axi_vip_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_vip_0" RelGenDir="$PGENDIR/axi_vip_0">
<File Path="$PSRCDIR/sources_1/ip/axi_vip_0/axi_vip_0.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="axi_vip_0"/>
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -923,6 +975,26 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wfg_cordic_synth_1" Type="Ft3:Synth" SrcSet="wfg_cordic" Part="xcku040-ffva1156-2-i" ConstrsSet="wfg_cordic" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/wfg_cordic_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wfg_cordic_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_vip_0_synth_1" Type="Ft3:Synth" SrcSet="axi_vip_0" Part="xcku040-ffva1156-2-i" ConstrsSet="axi_vip_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_vip_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_vip_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_vip_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
@@ -1162,6 +1234,40 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="wfg_cordic_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="wfg_cordic" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wfg_cordic_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wfg_cordic_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/wfg_cordic_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_vip_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-i" ConstrsSet="axi_vip_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_vip_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_vip_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_vip_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="0"/>